44 lines
1.3 KiB
Diff
44 lines
1.3 KiB
Diff
From 77c4cddca6aeb6e545e21f235e29323e05f5a3a3 Mon Sep 17 00:00:00 2001
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From: Richard Henderson <rth@redhat.com>
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Date: Tue, 21 Oct 2014 13:30:40 -0400
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Subject: [PATCH 055/415] aarch64: Simplify AARCH64_STACK_ALIGN
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The iOS abi doesn't require padding between arguments, but
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that's not what AARCH64_STACK_ALIGN meant. The hardware will
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in fact trap if the SP register is not 16 byte aligned.
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---
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src/aarch64/ffi.c | 10 +---------
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1 file changed, 1 insertion(+), 9 deletions(-)
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diff --git a/src/aarch64/ffi.c b/src/aarch64/ffi.c
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index f065be5..a6fcc11 100644
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--- a/src/aarch64/ffi.c
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+++ b/src/aarch64/ffi.c
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@@ -35,13 +35,6 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
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# define FFI_TYPE_LONGDOUBLE 4
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#endif
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-/* Stack alignment requirement in bytes */
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-#if defined (__APPLE__)
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-#define AARCH64_STACK_ALIGN 1
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-#else
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-#define AARCH64_STACK_ALIGN 16
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-#endif
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-
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#define N_X_ARG_REG 8
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#define N_V_ARG_REG 8
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@@ -799,8 +792,7 @@ ffi_status
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ffi_prep_cif_machdep (ffi_cif *cif)
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{
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/* Round the stack up to a multiple of the stack alignment requirement. */
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- cif->bytes =
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- (cif->bytes + (AARCH64_STACK_ALIGN - 1)) & ~ (AARCH64_STACK_ALIGN - 1);
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+ cif->bytes = ALIGN(cif->bytes, 16);
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/* Initialize our flags. We are interested if this CIF will touch a
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vector register, if so we will enable context save and load to
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--
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2.7.4.huawei.3
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