!8 添加sw架构
From: @wuzx065891 Reviewed-by: @liqingqing_1229 Signed-off-by: @liqingqing_1229
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118
libatomic_ops-7.6.12-sw.patch
Executable file
118
libatomic_ops-7.6.12-sw.patch
Executable file
@ -0,0 +1,118 @@
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diff -Naur libatomic_ops-7.6.12.org/src/Makefile.am libatomic_ops-7.6.12.sw/src/Makefile.am
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--- libatomic_ops-7.6.12.org/src/Makefile.am 2022-02-26 02:35:27.760000000 +0000
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+++ libatomic_ops-7.6.12.sw/src/Makefile.am 2022-02-26 02:38:49.230000000 +0000
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@@ -81,6 +81,7 @@
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\
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atomic_ops/sysdeps/gcc/aarch64.h \
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atomic_ops/sysdeps/gcc/alpha.h \
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+ atomic_ops/sysdeps/gcc/sw_64.h \
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atomic_ops/sysdeps/gcc/arm.h \
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atomic_ops/sysdeps/gcc/avr32.h \
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atomic_ops/sysdeps/gcc/cris.h \
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diff -Naur libatomic_ops-7.6.12.org/src/atomic_ops/sysdeps/gcc/sw_64.h libatomic_ops-7.6.12.sw/src/atomic_ops/sysdeps/gcc/sw_64.h
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--- libatomic_ops-7.6.12.org/src/atomic_ops/sysdeps/gcc/sw_64.h 1970-01-01 00:00:00.000000000 +0000
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+++ libatomic_ops-7.6.12.sw/src/atomic_ops/sysdeps/gcc/sw_64.h 2022-02-26 02:41:18.020000000 +0000
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@@ -0,0 +1,70 @@
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+/*
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+ * Copyright (c) 1991-1994 by Xerox Corporation. All rights reserved.
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+ * Copyright (c) 1996-1999 by Silicon Graphics. All rights reserved.
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+ * Copyright (c) 1999-2003 by Hewlett-Packard Company. All rights reserved.
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+ *
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+ *
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+ * THIS MATERIAL IS PROVIDED AS IS, WITH ABSOLUTELY NO WARRANTY EXPRESSED
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+ * OR IMPLIED. ANY USE IS AT YOUR OWN RISK.
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+ *
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+ * Permission is hereby granted to use or copy this program
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+ * for any purpose, provided the above notices are retained on all copies.
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+ * Permission to modify the code and to distribute modified code is granted,
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+ * provided the above notices are retained, and a notice that the code was
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+ * modified is included with the above copyright notice.
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+ *
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+ */
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+
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+#include "../loadstore/atomic_load.h"
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+#include "../loadstore/atomic_store.h"
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+
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+#include "../test_and_set_t_is_ao_t.h"
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+
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+#define AO_NO_DD_ORDERING
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+ /* Data dependence does not imply read ordering. */
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+
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+AO_INLINE void
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+AO_nop_full(void)
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+{
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+ __asm__ __volatile__("memb" : : : "memory");
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+}
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+#define AO_HAVE_nop_full
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+
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+AO_INLINE void
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+AO_nop_write(void)
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+{
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+ __asm__ __volatile__("memb" : : : "memory");
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+}
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+#define AO_HAVE_nop_write
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+
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+/* mb should be used for AO_nop_read(). That's the default. */
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+
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+/* TODO: implement AO_fetch_and_add explicitly. */
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+
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+/* We believe that ldq_l ... stq_c does not imply any memory barrier. */
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+AO_INLINE int
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+AO_compare_and_swap(volatile AO_t *addr,
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+ AO_t old, AO_t new_val)
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+{
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+ unsigned long was_equal;
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+ unsigned long temp;
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+
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+ __asm__ __volatile__(
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+ " ldi %3,%1\n"
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+ "1: lldl %0,0(%3)\n"
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+ " cmpeq %0,%5,%2\n"
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+ " wr_f %2\n"
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+ " mov %4,%0\n"
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+ " lstl %0,0(%3)\n"
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+ " rd_f %0\n"
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+ " beq %2,2f\n"
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+ " beq %0,1b\n"
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+ "2:\n"
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+ : "=&r" (temp), "+m" (*addr), "=&r" (was_equal),"=&r"(temp)
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+ : "r" (new_val), "Ir" (old)
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+ :"memory");
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+ return (int)was_equal;
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+}
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+#define AO_HAVE_compare_and_swap
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+
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+/* TODO: implement AO_fetch_compare_and_swap */
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diff -Naur libatomic_ops-7.6.12.org/src/atomic_ops.h libatomic_ops-7.6.12.sw/src/atomic_ops.h
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--- libatomic_ops-7.6.12.org/src/atomic_ops.h 2022-02-26 02:35:27.770000000 +0000
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+++ libatomic_ops-7.6.12.sw/src/atomic_ops.h 2022-02-26 02:36:05.400000000 +0000
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@@ -310,6 +310,8 @@
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# elif defined(__hppa__)
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# include "atomic_ops/sysdeps/gcc/hppa.h"
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# define AO_CAN_EMUL_CAS
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+# elif defined(__sw_64__)
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+# include "atomic_ops/sysdeps/gcc/sw_64.h"
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# elif defined(__alpha__)
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# include "atomic_ops/sysdeps/gcc/alpha.h"
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# define AO_GENERALIZE_TWICE
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diff -Naur libatomic_ops-7.6.12.org/src/atomic_ops_stack.c libatomic_ops-7.6.12.sw/src/atomic_ops_stack.c
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--- libatomic_ops-7.6.12.org/src/atomic_ops_stack.c 2022-02-26 02:35:27.760000000 +0000
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+++ libatomic_ops-7.6.12.sw/src/atomic_ops_stack.c 2022-02-26 02:38:24.530000000 +0000
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@@ -180,7 +180,7 @@
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/* We need to make sure that first is still the first entry on the */
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/* list. Otherwise it's possible that a reinsertion of it was */
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/* already started before we added the black list entry. */
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-# if defined(__alpha__) && (__GNUC__ == 4)
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+# if (defined(__alpha__) || defined(__sw_64__)) && (__GNUC__ == 4)
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if (first != AO_load_acquire(list))
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/* Workaround __builtin_expect bug found in */
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/* gcc-4.6.3/alpha causing test_stack failure. */
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@@ -196,7 +196,7 @@
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}
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first_ptr = AO_REAL_NEXT_PTR(first);
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next = AO_load_next(first_ptr);
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-# if defined(__alpha__) && (__GNUC__ == 4)
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+# if (defined(__alpha__) || defined(__sw_64__)) && (__GNUC__ == 4)
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if (!AO_compare_and_swap_release(list, first, next))
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# else
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if (AO_EXPECT_FALSE(!AO_compare_and_swap_release(list, first, next)))
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@ -1,10 +1,11 @@
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Name: libatomic_ops
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Version: 7.6.12
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Release: 1
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Release: 2
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Summary: Atomic memory update operations
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License: GPLv2
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URL: https://github.com/ivmai/libatomic_ops/
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Source0: http://github.com/ivmai/libatomic_ops/releases/download/v%{version}/libatomic_ops-%{version}.tar.gz
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Patch1: libatomic_ops-7.6.12-sw.patch
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BuildRequires: gcc
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@ -61,6 +62,9 @@ The devel for %{name}
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%doc AUTHORS ChangeLog README.md
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%changelog
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* Thu Jul 28 2022 wuzx<wuzx1226@qq.com> - 7.6.12-2
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- add sw64 patch
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* Tue Nov 30 2021 zhouwenpei <zhouwenpei1@huawei.com> - 7.6.12-1
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- Upgrade to 7.6.12
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