Mingzheng Xing 7ad266690d riscv: update to 6.6.0-28.0.0
Rebase riscv-kernel patch to 6.6.0-28.0.0, and fixed a merge conflicts from
the commit f1e873348141 ("LoongArch: limit min pci msi-x/msi vector number
when request more than 32 vectors")

Signed-off-by: Mingzheng Xing <xingmingzheng@iscas.ac.cn>
2024-05-26 20:10:47 +08:00
2019-12-25 17:15:27 +08:00
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2019-12-25 17:15:27 +08:00
2024-05-26 20:10:47 +08:00
2019-12-25 17:15:27 +08:00
2019-12-25 17:15:27 +08:00
2019-12-25 17:15:27 +08:00
2019-12-25 17:15:27 +08:00
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2019-12-25 17:15:27 +08:00
2024-05-26 10:09:42 +08:00
2020-06-15 18:18:15 +08:00

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