4 Commits

Author	SHA1	Message	Date
Mingzheng Xing	bb4da11934	riscv: update to 6.6.0-29.0.0 ... riscv-kernel patch update to 6.6.0-29.0.0 Fix QEMU UEFI boot panic. Deal with riscv th1520 SoC dtb search path. Signed-off-by: Mingzheng Xing <xingmingzheng@iscas.ac.cn>	2024-06-07 14:47:59 +08:00
Mingzheng Xing	7ad266690d	riscv: update to 6.6.0-28.0.0 ... Rebase riscv-kernel patch to 6.6.0-28.0.0, and fixed a merge conflicts from the commit f1e873348141 ("LoongArch: limit min pci msi-x/msi vector number when request more than 32 vectors") Signed-off-by: Mingzheng Xing <xingmingzheng@iscas.ac.cn>	2024-05-26 20:10:47 +08:00
Mingzheng Xing	03ec49e6b9	riscv: Update riscv-kernel patch ... Rebase 6.6.0-27.0.0 For sg2042, the following features have been added: - SPI Flash driver - kexec file raw image - HIGHMEM Build and boot testing passed. Signed-off-by: Mingzheng Xing <xingmingzheng@iscas.ac.cn>	2024-05-24 16:36:47 +08:00
Mingzheng Xing	b04eeb3465	riscv: Add riscv-kernel patch ... riscv-kernel[1] is to add support for multiple RISC-V SoCs on the basis of OLK-6.6 and enrich the openEuler riscv ecosystem. Currently, riscv-kernel has added support for sg2042[2] and th1520. After applying this patch, we can build the same kernel to start openEuler on qemu, sg2042, and th1520 platforms. Build and boot testing passed on qemu, Milk-V Pioneer[3] and Lpi4a[4]. Link: https://gitee.com/openeuler/riscv-kernel/tree/OLK-6.6 [1] Link: https://www.sophgo.com/product/introduce/sg2042.html [2] Link: https://milkv.io/zh/pioneer [3] Link: https://sipeed.com/licheepi4a [4] Signed-off-by: Mingzheng Xing <xingmingzheng@iscas.ac.cn>	2024-05-11 11:08:29 +08:00