From f0ddfbb0eb2731c03f8b06a0c3d8fb3072305221 Mon Sep 17 00:00:00 2001 From: Yafen Date: Wed, 15 May 2024 07:23:23 +0800 Subject: [PATCH] RPi: update kernel version to openEuler 6.6.0-26.0.0 --- 0000-raspberrypi-kernel.patch | 2543 +++++++++++++++++++++++---------- raspberrypi-kernel.spec | 12 +- 2 files changed, 1757 insertions(+), 798 deletions(-) diff --git a/0000-raspberrypi-kernel.patch b/0000-raspberrypi-kernel.patch index dc001f4..44d271c 100644 --- a/0000-raspberrypi-kernel.patch +++ b/0000-raspberrypi-kernel.patch @@ -1,7 +1,7 @@ -From cdb17cc37ef917eafea723f83212e58b4c824c13 Mon Sep 17 00:00:00 2001 +From 42a6a0e9bca5d03c3bbc4104eb93025153d4cfee Mon Sep 17 00:00:00 2001 From: Yafen -Date: Fri, 10 May 2024 08:18:47 +0800 -Subject: [PATCH] apply RPi patch of 6.6.26 (openEuler 6.6.0-25.0.0) +Date: Wed, 15 May 2024 06:23:21 +0800 +Subject: [PATCH] apply RPi patch of 6.6.30 (openEuler 6.6.0-26.0.0) --- .../admin-guide/media/bcm2835-isp.rst | 127 + @@ -73,30 +73,30 @@ Subject: [PATCH] apply RPi patch of 6.6.26 (openEuler 6.6.0-25.0.0) arch/arm/boot/dts/broadcom/bcm2708-rpi.dtsi | 57 + arch/arm/boot/dts/broadcom/bcm2708.dtsi | 19 + .../arm/boot/dts/broadcom/bcm2709-rpi-2-b.dts | 204 + - .../arm/boot/dts/broadcom/bcm2709-rpi-cm2.dts | 223 + + .../arm/boot/dts/broadcom/bcm2709-rpi-cm2.dts | 219 + arch/arm/boot/dts/broadcom/bcm2709-rpi.dtsi | 8 + arch/arm/boot/dts/broadcom/bcm2709.dtsi | 29 + - arch/arm/boot/dts/broadcom/bcm270x-rpi.dtsi | 186 + + arch/arm/boot/dts/broadcom/bcm270x-rpi.dtsi | 201 + arch/arm/boot/dts/broadcom/bcm270x.dtsi | 294 + .../arm/boot/dts/broadcom/bcm2710-rpi-2-b.dts | 204 + .../dts/broadcom/bcm2710-rpi-3-b-plus.dts | 299 + .../arm/boot/dts/broadcom/bcm2710-rpi-3-b.dts | 297 + - .../arm/boot/dts/broadcom/bcm2710-rpi-cm3.dts | 223 + + .../arm/boot/dts/broadcom/bcm2710-rpi-cm3.dts | 219 + .../dts/broadcom/bcm2710-rpi-zero-2-w.dts | 261 + .../boot/dts/broadcom/bcm2710-rpi-zero-2.dts | 1 + arch/arm/boot/dts/broadcom/bcm2710.dtsi | 32 + .../arm/boot/dts/broadcom/bcm2711-rpi-4-b.dts | 262 +- .../arm/boot/dts/broadcom/bcm2711-rpi-400.dts | 49 +- .../arm/boot/dts/broadcom/bcm2711-rpi-cm4.dts | 510 ++ - .../boot/dts/broadcom/bcm2711-rpi-cm4s.dts | 297 + + .../boot/dts/broadcom/bcm2711-rpi-cm4s.dts | 298 + .../arm/boot/dts/broadcom/bcm2711-rpi-ds.dtsi | 561 ++ arch/arm/boot/dts/broadcom/bcm2711-rpi.dtsi | 13 + arch/arm/boot/dts/broadcom/bcm2711.dtsi | 2 +- .../arm/boot/dts/broadcom/bcm2712-rpi-5-b.dts | 863 ++ .../dts/broadcom/bcm2712-rpi-cm5-cm4io.dts | 20 + .../dts/broadcom/bcm2712-rpi-cm5-cm5io.dts | 10 + - .../boot/dts/broadcom/bcm2712-rpi-cm5.dtsi | 860 ++ - arch/arm/boot/dts/broadcom/bcm2712-rpi.dtsi | 336 + + .../boot/dts/broadcom/bcm2712-rpi-cm5.dtsi | 888 ++ + arch/arm/boot/dts/broadcom/bcm2712-rpi.dtsi | 337 + arch/arm/boot/dts/broadcom/bcm2712.dtsi | 1304 +++ .../boot/dts/broadcom/bcm2712d0-rpi-5-b.dts | 107 + .../arm/boot/dts/broadcom/bcm271x-rpi-bt.dtsi | 38 + @@ -105,10 +105,10 @@ Subject: [PATCH] apply RPi patch of 6.6.26 (openEuler 6.6.0-25.0.0) .../dts/broadcom/bcm283x-rpi-csi1-4lane.dtsi | 4 + .../broadcom/bcm283x-rpi-i2c0mux_0_28.dtsi | 4 + .../broadcom/bcm283x-rpi-i2c0mux_0_44.dtsi | 4 + - arch/arm/boot/dts/broadcom/bcm283x.dtsi | 2 +- - arch/arm/boot/dts/broadcom/rp1.dtsi | 1306 +++ - arch/arm/boot/dts/overlays/Makefile | 333 + - arch/arm/boot/dts/overlays/README | 5346 ++++++++++++ + arch/arm/boot/dts/broadcom/bcm283x.dtsi | 4 +- + arch/arm/boot/dts/broadcom/rp1.dtsi | 1307 +++ + arch/arm/boot/dts/overlays/Makefile | 336 + + arch/arm/boot/dts/overlays/README | 5389 +++++++++++++ .../arm/boot/dts/overlays/act-led-overlay.dts | 28 + .../dts/overlays/adafruit-st7735r-overlay.dts | 83 + .../boot/dts/overlays/adafruit18-overlay.dts | 55 + @@ -142,8 +142,8 @@ Subject: [PATCH] apply RPi patch of 6.6.26 (openEuler 6.6.0-25.0.0) .../boot/dts/overlays/audremap-overlay.dts | 38 + .../boot/dts/overlays/balena-fin-overlay.dts | 125 + .../boot/dts/overlays/bcm2712d0-overlay.dts | 75 + - .../dts/overlays/camera-mux-2port-overlay.dts | 545 ++ - .../dts/overlays/camera-mux-4port-overlay.dts | 952 +++ + .../dts/overlays/camera-mux-2port-overlay.dts | 547 ++ + .../dts/overlays/camera-mux-4port-overlay.dts | 956 +++ .../arm/boot/dts/overlays/cap1106-overlay.dts | 52 + .../boot/dts/overlays/chipdip-dac-overlay.dts | 46 + .../dts/overlays/cirrus-wm5102-overlay.dts | 172 + @@ -221,7 +221,7 @@ Subject: [PATCH] apply RPi patch of 6.6.26 (openEuler 6.6.0-25.0.0) .../arm/boot/dts/overlays/i2c-rtc-common.dtsi | 367 + .../dts/overlays/i2c-rtc-gpio-overlay.dts | 31 + .../arm/boot/dts/overlays/i2c-rtc-overlay.dts | 42 + - .../boot/dts/overlays/i2c-sensor-common.dtsi | 578 ++ + .../boot/dts/overlays/i2c-sensor-common.dtsi | 597 ++ .../boot/dts/overlays/i2c-sensor-overlay.dts | 42 + arch/arm/boot/dts/overlays/i2c0-overlay.dts | 83 + .../boot/dts/overlays/i2c0-pi5-overlay.dts | 34 + @@ -300,7 +300,7 @@ Subject: [PATCH] apply RPi patch of 6.6.26 (openEuler 6.6.0-25.0.0) .../arm/boot/dts/overlays/mz61581-overlay.dts | 117 + arch/arm/boot/dts/overlays/ov2311-overlay.dts | 77 + arch/arm/boot/dts/overlays/ov2311.dtsi | 26 + - arch/arm/boot/dts/overlays/ov5647-overlay.dts | 93 + + arch/arm/boot/dts/overlays/ov5647-overlay.dts | 94 + arch/arm/boot/dts/overlays/ov5647.dtsi | 25 + .../arm/boot/dts/overlays/ov64a40-overlay.dts | 91 + arch/arm/boot/dts/overlays/ov64a40.dtsi | 34 + @@ -321,6 +321,7 @@ Subject: [PATCH] apply RPi patch of 6.6.26 (openEuler 6.6.0-25.0.0) .../dts/overlays/pifi-dac-zero-overlay.dts | 49 + .../dts/overlays/pifi-mini-210-overlay.dts | 42 + arch/arm/boot/dts/overlays/piglow-overlay.dts | 97 + + .../overlays/pineboards-hat-ai-overlay.dts | 18 + .../boot/dts/overlays/piscreen-overlay.dts | 107 + .../boot/dts/overlays/piscreen2r-overlay.dts | 106 + .../arm/boot/dts/overlays/pisound-overlay.dts | 118 + @@ -353,10 +354,11 @@ Subject: [PATCH] apply RPi patch of 6.6.26 (openEuler 6.6.0-25.0.0) arch/arm/boot/dts/overlays/rpi-tv-overlay.dts | 34 + .../rra-digidac1-wm8741-audio-overlay.dts | 49 + .../boot/dts/overlays/sainsmart18-overlay.dts | 52 + - .../dts/overlays/sc16is750-i2c-overlay.dts | 43 + - .../dts/overlays/sc16is752-i2c-overlay.dts | 43 + - .../dts/overlays/sc16is752-spi0-overlay.dts | 49 + - .../dts/overlays/sc16is752-spi1-overlay.dts | 67 + + .../dts/overlays/sc16is750-i2c-overlay.dts | 57 + + .../dts/overlays/sc16is750-spi0-overlay.dts | 63 + + .../dts/overlays/sc16is752-i2c-overlay.dts | 57 + + .../dts/overlays/sc16is752-spi0-overlay.dts | 63 + + .../dts/overlays/sc16is752-spi1-overlay.dts | 76 + arch/arm/boot/dts/overlays/sdhost-overlay.dts | 38 + arch/arm/boot/dts/overlays/sdio-overlay.dts | 77 + .../boot/dts/overlays/sdio-pi5-overlay.dts | 24 + @@ -397,6 +399,7 @@ Subject: [PATCH] apply RPi patch of 6.6.26 (openEuler 6.6.0-25.0.0) .../boot/dts/overlays/ssd1306-spi-overlay.dts | 85 + .../boot/dts/overlays/ssd1331-spi-overlay.dts | 83 + .../boot/dts/overlays/ssd1351-spi-overlay.dts | 83 + + .../overlays/sunfounder-pironman5-overlay.dts | 51 + .../dts/overlays/superaudioboard-overlay.dts | 73 + arch/arm/boot/dts/overlays/sx150x-overlay.dts | 1706 ++++ .../dts/overlays/tc358743-audio-overlay.dts | 52 + @@ -452,9 +455,9 @@ Subject: [PATCH] apply RPi patch of 6.6.26 (openEuler 6.6.0-25.0.0) .../waveshare-can-fd-hat-mode-b-overlay.dts | 103 + .../arm/boot/dts/overlays/wittypi-overlay.dts | 44 + .../dts/overlays/wm8960-soundcard-overlay.dts | 82 + - arch/arm/configs/bcm2709_defconfig | 1583 ++++ - arch/arm/configs/bcm2711_defconfig | 1610 ++++ - arch/arm/configs/bcmrpi_defconfig | 1576 ++++ + arch/arm/configs/bcm2709_defconfig | 1585 ++++ + arch/arm/configs/bcm2711_defconfig | 1615 ++++ + arch/arm/configs/bcmrpi_defconfig | 1578 ++++ arch/arm/include/asm/cacheflush.h | 21 + arch/arm/include/asm/glue-cache.h | 2 + arch/arm/include/asm/irqflags.h | 16 +- @@ -500,9 +503,9 @@ Subject: [PATCH] apply RPi patch of 6.6.26 (openEuler 6.6.0-25.0.0) .../dts/broadcom/bcm283x-rpi-csi1-2lane.dtsi | 1 + .../dts/broadcom/bcm283x-rpi-lan7515.dtsi | 1 + arch/arm64/boot/dts/overlays | 1 + - arch/arm64/configs/bcm2711_defconfig | 1672 ++++ - arch/arm64/configs/bcm2712_defconfig | 1675 ++++ - arch/arm64/configs/bcmrpi3_defconfig | 1560 ++++ + arch/arm64/configs/bcm2711_defconfig | 1677 ++++ + arch/arm64/configs/bcm2712_defconfig | 1680 ++++ + arch/arm64/configs/bcmrpi3_defconfig | 1561 ++++ arch/arm64/crypto/aes-cipher-glue.c | 11 + arch/arm64/crypto/aes-glue.c | 4 +- arch/arm64/crypto/aes-neonbs-glue.c | 5 - @@ -527,7 +530,7 @@ Subject: [PATCH] apply RPi patch of 6.6.26 (openEuler 6.6.0-25.0.0) drivers/char/tpm/tpm_tis_spi_main.c | 4 + drivers/clk/Kconfig | 19 + drivers/clk/Makefile | 4 + - drivers/clk/bcm/clk-bcm2835.c | 206 +- + drivers/clk/bcm/clk-bcm2835.c | 210 +- drivers/clk/bcm/clk-raspberrypi.c | 34 +- drivers/clk/clk-hifiberry-dachd.c | 331 + drivers/clk/clk-hifiberry-dacpro.c | 181 + @@ -537,7 +540,7 @@ Subject: [PATCH] apply RPi patch of 6.6.26 (openEuler 6.6.0-25.0.0) drivers/dma/Makefile | 1 + drivers/dma/bcm2708-dmaengine.c | 281 + drivers/dma/bcm2835-dma.c | 735 +- - .../dma/dw-axi-dmac/dw-axi-dmac-platform.c | 134 +- + .../dma/dw-axi-dmac/dw-axi-dmac-platform.c | 137 +- drivers/dma/dw-axi-dmac/dw-axi-dmac.h | 1 + drivers/firmware/psci/psci.c | 9 +- drivers/firmware/raspberrypi.c | 149 +- @@ -553,12 +556,12 @@ Subject: [PATCH] apply RPi patch of 6.6.26 (openEuler 6.6.0-25.0.0) drivers/gpu/drm/Kconfig | 2 + drivers/gpu/drm/Makefile | 1 + drivers/gpu/drm/bridge/Kconfig | 1 + - drivers/gpu/drm/bridge/tc358762.c | 2 +- + drivers/gpu/drm/bridge/tc358762.c | 26 +- drivers/gpu/drm/drm_atomic_helper.c | 18 +- drivers/gpu/drm/drm_atomic_state_helper.c | 14 + drivers/gpu/drm/drm_atomic_uapi.c | 19 + drivers/gpu/drm/drm_color_mgmt.c | 40 +- - drivers/gpu/drm/drm_connector.c | 68 +- + drivers/gpu/drm/drm_connector.c | 77 +- drivers/gpu/drm/drm_fb_helper.c | 11 +- drivers/gpu/drm/drm_modes.c | 5 +- drivers/gpu/drm/drm_probe_helper.c | 5 +- @@ -571,7 +574,7 @@ Subject: [PATCH] apply RPi patch of 6.6.26 (openEuler 6.6.0-25.0.0) drivers/gpu/drm/panel/panel-ilitek-ili9881c.c | 955 ++- .../gpu/drm/panel/panel-jdi-lt070me05000.c | 19 +- .../drm/panel/panel-raspberrypi-touchscreen.c | 44 +- - drivers/gpu/drm/panel/panel-simple.c | 234 +- + drivers/gpu/drm/panel/panel-simple.c | 238 +- drivers/gpu/drm/panel/panel-sitronix-st7701.c | 407 +- drivers/gpu/drm/panel/panel-tdo-y17p.c | 277 + drivers/gpu/drm/panel/panel-waveshare-dsi.c | 434 + @@ -582,19 +585,19 @@ Subject: [PATCH] apply RPi patch of 6.6.26 (openEuler 6.6.0-25.0.0) drivers/gpu/drm/rp1/rp1-dpi/rp1_dpi.c | 415 + drivers/gpu/drm/rp1/rp1-dpi/rp1_dpi.h | 69 + drivers/gpu/drm/rp1/rp1-dpi/rp1_dpi_cfg.c | 510 ++ - drivers/gpu/drm/rp1/rp1-dpi/rp1_dpi_hw.c | 486 ++ + drivers/gpu/drm/rp1/rp1-dpi/rp1_dpi_hw.c | 492 ++ drivers/gpu/drm/rp1/rp1-dsi/Kconfig | 14 + drivers/gpu/drm/rp1/rp1-dsi/Makefile | 5 + drivers/gpu/drm/rp1/rp1-dsi/rp1_dsi.c | 535 ++ drivers/gpu/drm/rp1/rp1-dsi/rp1_dsi.h | 94 + drivers/gpu/drm/rp1/rp1-dsi/rp1_dsi_dma.c | 443 + - drivers/gpu/drm/rp1/rp1-dsi/rp1_dsi_dsi.c | 1504 ++++ + drivers/gpu/drm/rp1/rp1-dsi/rp1_dsi_dsi.c | 1513 ++++ drivers/gpu/drm/rp1/rp1-vec/Kconfig | 11 + drivers/gpu/drm/rp1/rp1-vec/Makefile | 5 + - drivers/gpu/drm/rp1/rp1-vec/rp1_vec.c | 506 ++ - drivers/gpu/drm/rp1/rp1-vec/rp1_vec.h | 69 + + drivers/gpu/drm/rp1/rp1-vec/rp1_vec.c | 602 ++ + drivers/gpu/drm/rp1/rp1-vec/rp1_vec.h | 72 + drivers/gpu/drm/rp1/rp1-vec/rp1_vec_cfg.c | 508 ++ - drivers/gpu/drm/rp1/rp1-vec/rp1_vec_hw.c | 508 ++ + drivers/gpu/drm/rp1/rp1-vec/rp1_vec_hw.c | 568 ++ drivers/gpu/drm/rp1/rp1-vec/vec_regs.h | 1420 ++++ drivers/gpu/drm/solomon/ssd130x.c | 2 +- drivers/gpu/drm/tiny/ili9486.c | 1 - @@ -615,13 +618,14 @@ Subject: [PATCH] apply RPi patch of 6.6.26 (openEuler 6.6.0-25.0.0) drivers/gpu/drm/vc4/tests/vc4_test_lbm_size.c | 308 + .../gpu/drm/vc4/tests/vc4_test_pv_muxing.c | 225 +- drivers/gpu/drm/vc4/vc4_bo.c | 28 +- - drivers/gpu/drm/vc4/vc4_crtc.c | 185 +- + drivers/gpu/drm/vc4/vc4_crtc.c | 197 +- drivers/gpu/drm/vc4/vc4_debugfs.c | 3 +- drivers/gpu/drm/vc4/vc4_drv.c | 90 +- - drivers/gpu/drm/vc4/vc4_drv.h | 143 +- + drivers/gpu/drm/vc4/vc4_drv.h | 144 +- + drivers/gpu/drm/vc4/vc4_dsi.c | 98 +- drivers/gpu/drm/vc4/vc4_firmware_kms.c | 2077 +++++ drivers/gpu/drm/vc4/vc4_gem.c | 24 +- - drivers/gpu/drm/vc4/vc4_hdmi.c | 214 +- + drivers/gpu/drm/vc4/vc4_hdmi.c | 216 +- drivers/gpu/drm/vc4/vc4_hdmi.h | 31 + drivers/gpu/drm/vc4/vc4_hdmi_phy.c | 640 ++ drivers/gpu/drm/vc4/vc4_hdmi_regs.h | 222 +- @@ -720,7 +724,7 @@ Subject: [PATCH] apply RPi patch of 6.6.26 (openEuler 6.6.0-25.0.0) drivers/media/platform/Makefile | 2 + drivers/media/platform/bcm2835/Kconfig | 21 + drivers/media/platform/bcm2835/Makefile | 3 + - .../media/platform/bcm2835/bcm2835-unicam.c | 3516 ++++++++ + .../media/platform/bcm2835/bcm2835-unicam.c | 3528 ++++++++ .../media/platform/bcm2835/vc4-regs-unicam.h | 253 + drivers/media/platform/raspberrypi/Kconfig | 6 + drivers/media/platform/raspberrypi/Makefile | 4 + @@ -733,7 +737,7 @@ Subject: [PATCH] apply RPi patch of 6.6.26 (openEuler 6.6.0-25.0.0) .../platform/raspberrypi/rp1_cfe/Makefile | 6 + .../media/platform/raspberrypi/rp1_cfe/cfe.c | 2423 ++++++ .../media/platform/raspberrypi/rp1_cfe/cfe.h | 43 + - .../platform/raspberrypi/rp1_cfe/cfe_fmts.h | 316 + + .../platform/raspberrypi/rp1_cfe/cfe_fmts.h | 318 + .../media/platform/raspberrypi/rp1_cfe/csi2.c | 624 ++ .../media/platform/raspberrypi/rp1_cfe/csi2.h | 90 + .../media/platform/raspberrypi/rp1_cfe/dphy.c | 177 + @@ -835,8 +839,8 @@ Subject: [PATCH] apply RPi patch of 6.6.26 (openEuler 6.6.0-25.0.0) drivers/pinctrl/bcm/Kconfig | 9 + drivers/pinctrl/bcm/Makefile | 1 + drivers/pinctrl/bcm/pinctrl-bcm2712.c | 1247 +++ - drivers/pinctrl/bcm/pinctrl-bcm2835.c | 37 +- - drivers/pinctrl/pinctrl-rp1.c | 1600 ++++ + drivers/pinctrl/bcm/pinctrl-bcm2835.c | 44 +- + drivers/pinctrl/pinctrl-rp1.c | 1605 ++++ drivers/platform/x86/lenovo-yogabook.c | 2 +- drivers/pmdomain/bcm/bcm2835-power.c | 29 +- drivers/power/reset/gpio-poweroff.c | 21 +- @@ -858,7 +862,7 @@ Subject: [PATCH] apply RPi patch of 6.6.26 (openEuler 6.6.0-25.0.0) drivers/regulator/Kconfig | 10 + drivers/regulator/Makefile | 1 + drivers/regulator/pwm-regulator.c | 4 +- - .../regulator/rpi-panel-attiny-regulator.c | 18 +- + .../regulator/rpi-panel-attiny-regulator.c | 27 +- drivers/regulator/rpi-panel-v2-regulator.c | 189 + drivers/reset/Kconfig | 2 +- drivers/reset/reset-brcmstb-rescal.c | 10 + @@ -948,6 +952,7 @@ Subject: [PATCH] apply RPi patch of 6.6.26 (openEuler 6.6.0-25.0.0) drivers/usb/dwc3/core.h | 17 +- drivers/usb/dwc3/host.c | 9 +- drivers/usb/gadget/file_storage.c | 3676 +++++++++ + drivers/usb/gadget/function/uvc_configfs.c | 4 +- drivers/usb/host/Kconfig | 10 + drivers/usb/host/Makefile | 1 + drivers/usb/host/dwc_common_port/Makefile | 58 + @@ -1022,7 +1027,7 @@ Subject: [PATCH] apply RPi patch of 6.6.26 (openEuler 6.6.0-25.0.0) drivers/video/backlight/lp855x_bl.c | 2 +- drivers/video/backlight/pwm_bl.c | 12 +- drivers/video/backlight/rpi_backlight.c | 119 + - drivers/video/fbdev/Kconfig | 27 + + drivers/video/fbdev/Kconfig | 28 + drivers/video/fbdev/Makefile | 2 + drivers/video/fbdev/bcm2708_fb.c | 1274 +++ drivers/video/fbdev/core/fb_chrdev.c | 35 + @@ -1083,38 +1088,38 @@ Subject: [PATCH] apply RPi patch of 6.6.26 (openEuler 6.6.0-25.0.0) scripts/Makefile.lib | 19 + sound/soc/bcm/Kconfig | 269 + sound/soc/bcm/Makefile | 71 +- - sound/soc/bcm/allo-boss-dac.c | 468 ++ + sound/soc/bcm/allo-boss-dac.c | 471 ++ sound/soc/bcm/allo-boss2-dac.c | 1130 +++ sound/soc/bcm/allo-katana-codec.c | 386 + sound/soc/bcm/allo-piano-dac-plus.c | 1064 +++ sound/soc/bcm/allo-piano-dac.c | 122 + - .../bcm/audioinjector-isolated-soundcard.c | 183 + + .../bcm/audioinjector-isolated-soundcard.c | 184 + sound/soc/bcm/audioinjector-octo-soundcard.c | 347 + - sound/soc/bcm/audioinjector-pi-soundcard.c | 189 + + sound/soc/bcm/audioinjector-pi-soundcard.c | 190 + sound/soc/bcm/audiosense-pi.c | 248 + sound/soc/bcm/bcm2835-i2s.c | 18 +- sound/soc/bcm/chipdip-dac.c | 275 + sound/soc/bcm/dacberry400.c | 259 + sound/soc/bcm/digidac1-soundcard.c | 421 + - sound/soc/bcm/dionaudio_loco-v2.c | 117 + - sound/soc/bcm/dionaudio_loco.c | 117 + + sound/soc/bcm/dionaudio_loco-v2.c | 118 + + sound/soc/bcm/dionaudio_loco.c | 121 + sound/soc/bcm/fe-pi-audio.c | 154 + sound/soc/bcm/googlevoicehat-codec.c | 214 + - sound/soc/bcm/hifiberry_dacplus.c | 560 ++ - sound/soc/bcm/hifiberry_dacplusadc.c | 396 + - sound/soc/bcm/hifiberry_dacplusadcpro.c | 603 ++ + sound/soc/bcm/hifiberry_dacplus.c | 563 ++ + sound/soc/bcm/hifiberry_dacplusadc.c | 399 + + sound/soc/bcm/hifiberry_dacplusadcpro.c | 606 ++ sound/soc/bcm/hifiberry_dacplusdsp.c | 90 + sound/soc/bcm/hifiberry_dacplushd.c | 238 + - sound/soc/bcm/i-sabre-q2m.c | 159 + + sound/soc/bcm/i-sabre-q2m.c | 160 + sound/soc/bcm/iqaudio-codec.c | 278 + sound/soc/bcm/iqaudio-dac.c | 224 + sound/soc/bcm/justboom-both.c | 267 + sound/soc/bcm/justboom-dac.c | 147 + sound/soc/bcm/pifi-40.c | 282 + sound/soc/bcm/pisound.c | 1255 +++ - sound/soc/bcm/rpi-cirrus.c | 1024 +++ + sound/soc/bcm/rpi-cirrus.c | 1027 +++ sound/soc/bcm/rpi-proto.c | 147 + - sound/soc/bcm/rpi-simple-soundcard.c | 520 ++ + sound/soc/bcm/rpi-simple-soundcard.c | 523 ++ sound/soc/bcm/rpi-wm8804-soundcard.c | 549 ++ sound/soc/codecs/Kconfig | 26 +- sound/soc/codecs/Makefile | 8 + @@ -1134,7 +1139,7 @@ Subject: [PATCH] apply RPi patch of 6.6.26 (openEuler 6.6.0-25.0.0) sound/soc/soc-core.c | 14 +- sound/usb/card.c | 8 +- sound/usb/quirks.c | 2 + - 1130 files changed, 229605 insertions(+), 4281 deletions(-) + 1135 files changed, 230272 insertions(+), 4326 deletions(-) create mode 100644 Documentation/admin-guide/media/bcm2835-isp.rst create mode 100644 Documentation/devicetree/bindings/display/panel/panel-dsi.yaml create mode 100644 Documentation/devicetree/bindings/hwmon/microchip,emc2305.yaml @@ -1419,6 +1424,7 @@ Subject: [PATCH] apply RPi patch of 6.6.26 (openEuler 6.6.0-25.0.0) create mode 100644 arch/arm/boot/dts/overlays/pifi-dac-zero-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/pifi-mini-210-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/piglow-overlay.dts + create mode 100644 arch/arm/boot/dts/overlays/pineboards-hat-ai-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/piscreen-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/piscreen2r-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/pisound-overlay.dts @@ -1452,6 +1458,7 @@ Subject: [PATCH] apply RPi patch of 6.6.26 (openEuler 6.6.0-25.0.0) create mode 100644 arch/arm/boot/dts/overlays/rra-digidac1-wm8741-audio-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/sainsmart18-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/sc16is750-i2c-overlay.dts + create mode 100644 arch/arm/boot/dts/overlays/sc16is750-spi0-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/sc16is752-i2c-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/sc16is752-spi0-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/sc16is752-spi1-overlay.dts @@ -1495,6 +1502,7 @@ Subject: [PATCH] apply RPi patch of 6.6.26 (openEuler 6.6.0-25.0.0) create mode 100644 arch/arm/boot/dts/overlays/ssd1306-spi-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/ssd1331-spi-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/ssd1351-spi-overlay.dts + create mode 100644 arch/arm/boot/dts/overlays/sunfounder-pironman5-overlay.dts create mode 100755 arch/arm/boot/dts/overlays/superaudioboard-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/sx150x-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/tc358743-audio-overlay.dts @@ -7074,10 +7082,10 @@ index 000000000000..7796e545da43 +}; diff --git a/arch/arm/boot/dts/broadcom/bcm2709-rpi-cm2.dts b/arch/arm/boot/dts/broadcom/bcm2709-rpi-cm2.dts new file mode 100644 -index 000000000000..396771880798 +index 000000000000..5a5f910edba1 --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm2709-rpi-cm2.dts -@@ -0,0 +1,223 @@ +@@ -0,0 +1,219 @@ +/dts-v1/; + +#include "bcm2709.dtsi" @@ -7204,17 +7212,6 @@ index 000000000000..396771880798 + }; +}; + -+&soc { -+ virtgpio: virtgpio { -+ compatible = "brcm,bcm2835-virtgpio"; -+ gpio-controller; -+ #gpio-cells = <2>; -+ firmware = <&firmware>; -+ status = "okay"; -+ }; -+ -+}; -+ +&firmware { + expgpio: expgpio { + compatible = "raspberrypi,firmware-gpio"; @@ -7230,6 +7227,13 @@ index 000000000000..396771880798 + "NC"; + status = "okay"; + }; ++ ++ virtgpio: virtgpio { ++ compatible = "brcm,bcm2835-virtgpio"; ++ gpio-controller; ++ #gpio-cells = <2>; ++ status = "okay"; ++ }; +}; + +&spi0 { @@ -7352,10 +7356,10 @@ index 000000000000..868f65f922ff +}; diff --git a/arch/arm/boot/dts/broadcom/bcm270x-rpi.dtsi b/arch/arm/boot/dts/broadcom/bcm270x-rpi.dtsi new file mode 100644 -index 000000000000..360fb05fe80e +index 000000000000..bc533f329640 --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm270x-rpi.dtsi -@@ -0,0 +1,186 @@ +@@ -0,0 +1,201 @@ +/* Downstream modifications to bcm2835-rpi.dtsi */ + +/ { @@ -7455,6 +7459,21 @@ index 000000000000..360fb05fe80e + drm_fb0_vc4 = <&aliases>, "drm-fb0=",&vc4; + drm_fb1_vc4 = <&aliases>, "drm-fb1=",&vc4; + drm_fb2_vc4 = <&aliases>, "drm-fb2=",&vc4; ++ ++ cam1_sync = <&csi1>, "sync-gpios:0=", <&gpio>, ++ <&csi1>, "sync-gpios:4", ++ <&csi1>, "sync-gpios:8=0", ; ++ cam1_sync_inverted = <&csi1>, "sync-gpios:0=", <&gpio>, ++ <&csi1>, "sync-gpios:4", ++ <&csi1>, "sync-gpios:8=0", ; ++ cam0_sync = <&csi0>, "sync-gpios:0=", <&gpio>, ++ <&csi0>, "sync-gpios:4", ++ <&csi0>, "sync-gpios:8=0", ; ++ cam0_sync_inverted = <&csi0>, "sync-gpios:0=", <&gpio>, ++ <&csi0>, "sync-gpios:4", ++ <&csi0>, "sync-gpios:8=0", ; ++ ++ strict_gpiod = <&chosen>, "bootargs=pinctrl_bcm2835.persist_gpio_outputs=n"; + }; +}; + @@ -8662,10 +8681,10 @@ index 000000000000..b893affe6997 +}; diff --git a/arch/arm/boot/dts/broadcom/bcm2710-rpi-cm3.dts b/arch/arm/boot/dts/broadcom/bcm2710-rpi-cm3.dts new file mode 100644 -index 000000000000..08a33038e3f5 +index 000000000000..8206368b0aff --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm2710-rpi-cm3.dts -@@ -0,0 +1,223 @@ +@@ -0,0 +1,219 @@ +/dts-v1/; + +#include "bcm2710.dtsi" @@ -8792,17 +8811,6 @@ index 000000000000..08a33038e3f5 + }; +}; + -+&soc { -+ virtgpio: virtgpio { -+ compatible = "brcm,bcm2835-virtgpio"; -+ gpio-controller; -+ #gpio-cells = <2>; -+ firmware = <&firmware>; -+ status = "okay"; -+ }; -+ -+}; -+ +&firmware { + expgpio: expgpio { + compatible = "raspberrypi,firmware-gpio"; @@ -8818,6 +8826,13 @@ index 000000000000..08a33038e3f5 + "NC"; + status = "okay"; + }; ++ ++ virtgpio: virtgpio { ++ compatible = "brcm,bcm2835-virtgpio"; ++ gpio-controller; ++ #gpio-cells = <2>; ++ status = "okay"; ++ }; +}; + +&spi0 { @@ -10077,10 +10092,10 @@ index 000000000000..9fdb9278c5a2 +}; diff --git a/arch/arm/boot/dts/broadcom/bcm2711-rpi-cm4s.dts b/arch/arm/boot/dts/broadcom/bcm2711-rpi-cm4s.dts new file mode 100644 -index 000000000000..4cabd53bf45d +index 000000000000..e62932f1a5a1 --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm2711-rpi-cm4s.dts -@@ -0,0 +1,297 @@ +@@ -0,0 +1,298 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; +#define BCM2711 @@ -10222,14 +10237,6 @@ index 000000000000..4cabd53bf45d + soc { + /delete-node/ pixelvalve@7e807000; + /delete-node/ hdmi@7e902000; -+ -+ virtgpio: virtgpio { -+ compatible = "brcm,bcm2835-virtgpio"; -+ gpio-controller; -+ #gpio-cells = <2>; -+ firmware = <&firmware>; -+ status = "okay"; -+ }; + }; +}; + @@ -10252,6 +10259,15 @@ index 000000000000..4cabd53bf45d + /delete-node/ wifi-pwrseq; +}; + ++&firmware { ++ virtgpio: virtgpio { ++ compatible = "brcm,bcm2835-virtgpio"; ++ gpio-controller; ++ #gpio-cells = <2>; ++ status = "okay"; ++ }; ++}; ++ +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; @@ -10991,7 +11007,7 @@ index 4a379a14966d..09dbe7b3ca39 100644 }; diff --git a/arch/arm/boot/dts/broadcom/bcm2712-rpi-5-b.dts b/arch/arm/boot/dts/broadcom/bcm2712-rpi-5-b.dts new file mode 100644 -index 000000000000..f0e752436b68 +index 000000000000..84edb08b1197 --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm2712-rpi-5-b.dts @@ -0,0 +1,863 @@ @@ -11423,7 +11439,7 @@ index 000000000000..f0e752436b68 + +/ { + chosen: chosen { -+ bootargs = "reboot=w coherent_pool=1M 8250.nr_uarts=1 pci=pcie_bus_safe snd_bcm2835.enable_compat_alsa=0 snd_bcm2835.enable_hdmi=1"; ++ bootargs = "reboot=w coherent_pool=1M 8250.nr_uarts=1 pci=pcie_bus_safe"; + stdout-path = "serial10:115200n8"; + }; + @@ -11902,10 +11918,10 @@ index 000000000000..47ce4ff5049a +}; diff --git a/arch/arm/boot/dts/broadcom/bcm2712-rpi-cm5.dtsi b/arch/arm/boot/dts/broadcom/bcm2712-rpi-cm5.dtsi new file mode 100644 -index 000000000000..068138904695 +index 000000000000..b90d24a40bc1 --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm2712-rpi-cm5.dtsi -@@ -0,0 +1,860 @@ +@@ -0,0 +1,888 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include @@ -12252,7 +12268,7 @@ index 000000000000..068138904695 + +/* SDIO1 is used to drive the eMMC/SD card */ +&sdio1 { -+ pinctrl-0 = <&emmc_cmddat_pulls>, <&emmc_ds_pull>, <&emmc_aon_cd_pins>; ++ pinctrl-0 = <&emmc_cmddat_pulls>, <&emmc_ds_pull>; + pinctrl-names = "default"; + vqmmc-supply = <&sd_io_1v8_reg>; + vmmc-supply = <&sd_vcc_reg>; @@ -12267,10 +12283,9 @@ index 000000000000..068138904695 +}; + +&pinctrl_aon { -+ emmc_aon_cd_pins: emmc_aon_cd_pins { -+ function = "sd_card_g"; -+ pins = "aon_gpio5"; -+ bias-pull-up; ++ ant_pins: ant_pins { ++ function = "gpio"; ++ pins = "aon_gpio5", "aon_gpio6"; + }; + + /* Slight hack - only one PWM pin (status LED) is usable */ @@ -12334,7 +12349,7 @@ index 000000000000..068138904695 + +/ { + chosen: chosen { -+ bootargs = "reboot=w coherent_pool=1M 8250.nr_uarts=1 pci=pcie_bus_safe snd_bcm2835.enable_compat_alsa=0 snd_bcm2835.enable_hdmi=1"; ++ bootargs = "reboot=w coherent_pool=1M 8250.nr_uarts=1 pci=pcie_bus_safe"; + stdout-path = "serial10:115200n8"; + }; + @@ -12373,7 +12388,7 @@ index 000000000000..068138904695 + +/* SDIO2 drives the WLAN interface */ +&sdio2 { -+ pinctrl-0 = <&sdio2_30_pins>; ++ pinctrl-0 = <&sdio2_30_pins>, <&ant_pins>; + pinctrl-names = "default"; + bus-width = <4>; + vmmc-supply = <&wl_on_reg>; @@ -12582,6 +12597,22 @@ index 000000000000..068138904695 + output-high; + line-name = "RP1 RUN pin"; + }; ++ ++ ant1: ant1-hog { ++ gpio-hog; ++ gpios = <5 GPIO_ACTIVE_HIGH>; ++ /* internal antenna enabled */ ++ output-high; ++ line-name = "ant1"; ++ }; ++ ++ ant2: ant2-hog { ++ gpio-hog; ++ gpios = <6 GPIO_ACTIVE_HIGH>; ++ /* external antenna disabled */ ++ output-low; ++ line-name = "ant2"; ++ }; +}; + +&rp1_gpio { @@ -12752,6 +12783,19 @@ index 000000000000..068138904695 + drm_fb2_rp1_dpi = <&aliases>, "drm-fb2=",&dpi; + drm_fb2_vc4 = <&aliases>, "drm-fb2=",&vc4; + ++ ant1 = <&ant1>,"output-high?=on", ++ <&ant1>, "output-low?=off", ++ <&ant2>, "output-high?=off", ++ <&ant2>, "output-low?=on"; ++ ant2 = <&ant1>,"output-high?=off", ++ <&ant1>, "output-low?=on", ++ <&ant2>, "output-high?=on", ++ <&ant2>, "output-low?=off"; ++ noant = <&ant1>,"output-high?=off", ++ <&ant1>, "output-low?=on", ++ <&ant2>, "output-high?=off", ++ <&ant2>, "output-low?=on"; ++ + fan_temp0 = <&cpu_tepid>,"temperature:0"; + fan_temp1 = <&cpu_warm>,"temperature:0"; + fan_temp2 = <&cpu_hot>,"temperature:0"; @@ -12768,10 +12812,10 @@ index 000000000000..068138904695 +}; diff --git a/arch/arm/boot/dts/broadcom/bcm2712-rpi.dtsi b/arch/arm/boot/dts/broadcom/bcm2712-rpi.dtsi new file mode 100644 -index 000000000000..359a30d6ef5f +index 000000000000..f88de824e9d7 --- /dev/null +++ b/arch/arm/boot/dts/broadcom/bcm2712-rpi.dtsi -@@ -0,0 +1,336 @@ +@@ -0,0 +1,337 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include @@ -12873,6 +12917,7 @@ index 000000000000..359a30d6ef5f + nvmem_cust_rw = <&nvmem_cust>,"rw?"; + nvmem_priv_rw = <&nvmem_priv>,"rw?"; + nvmem_mac_rw = <&nvmem_mac>,"rw?"; ++ strict_gpiod = <&chosen>, "bootargs=pinctrl_rp1.persist_gpio_outputs=n"; + }; +}; + @@ -14626,9 +14671,18 @@ index 000000000000..119946d878db + pinctrl-1 = <&i2c0_gpio44>; +}; diff --git a/arch/arm/boot/dts/broadcom/bcm283x.dtsi b/arch/arm/boot/dts/broadcom/bcm283x.dtsi -index 2ca8a2505a4d..8ac38cdb9ffc 100644 +index 2ca8a2505a4d..c7a645647323 100644 --- a/arch/arm/boot/dts/broadcom/bcm283x.dtsi +++ b/arch/arm/boot/dts/broadcom/bcm283x.dtsi +@@ -363,7 +363,7 @@ dsi0: dsi@7e209000 { + #size-cells = <0>; + #clock-cells = <1>; + +- clocks = <&clocks BCM2835_PLLA_DSI0>, ++ clocks = <&clocks BCM2835_PLLD_DSI0>, + <&clocks BCM2835_CLOCK_DSI0E>, + <&clocks BCM2835_CLOCK_DSI0P>; + clock-names = "phy", "escape", "pixel"; @@ -415,7 +415,7 @@ pwm: pwm@7e20c000 { reg = <0x7e20c000 0x28>; clocks = <&clocks BCM2835_CLOCK_PWM>; @@ -14640,10 +14694,10 @@ index 2ca8a2505a4d..8ac38cdb9ffc 100644 }; diff --git a/arch/arm/boot/dts/broadcom/rp1.dtsi b/arch/arm/boot/dts/broadcom/rp1.dtsi new file mode 100644 -index 000000000000..551a02a955a1 +index 000000000000..fd9fb2dde0f7 --- /dev/null +++ b/arch/arm/boot/dts/broadcom/rp1.dtsi -@@ -0,0 +1,1306 @@ +@@ -0,0 +1,1307 @@ +#include +#include +#include @@ -15111,6 +15165,7 @@ index 000000000000..551a02a955a1 + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; ++ gpio-ranges = <&rp1_gpio 0 0 54>; + + rp1_uart0_14_15: rp1_uart0_14_15 { + pin_txd { @@ -15723,8 +15778,8 @@ index 000000000000..551a02a955a1 + snps,parkmode-disable-ss-quirk; + snps,parkmode-disable-hs-quirk; + snps,parkmode-disable-fsls-quirk; -+ snps,tx-max-burst-prd = <8>; -+ snps,tx-thr-num-pkt-prd = <2>; ++ snps,tx-max-burst = /bits/ 8 <8>; ++ snps,tx-thr-num-pkt = /bits/ 8 <2>; + interrupts = ; + status = "disabled"; + }; @@ -15739,8 +15794,8 @@ index 000000000000..551a02a955a1 + snps,parkmode-disable-ss-quirk; + snps,parkmode-disable-hs-quirk; + snps,parkmode-disable-fsls-quirk; -+ snps,tx-max-burst-prd = <8>; -+ snps,tx-thr-num-pkt-prd = <2>; ++ snps,tx-max-burst = /bits/ 8 <8>; ++ snps,tx-thr-num-pkt = /bits/ 8 <2>; + interrupts = ; + status = "disabled"; + }; @@ -15952,10 +16007,10 @@ index 000000000000..551a02a955a1 +}; diff --git a/arch/arm/boot/dts/overlays/Makefile b/arch/arm/boot/dts/overlays/Makefile new file mode 100644 -index 000000000000..bdd02b8c6f0f +index 000000000000..86e499122ca9 --- /dev/null +++ b/arch/arm/boot/dts/overlays/Makefile -@@ -0,0 +1,333 @@ +@@ -0,0 +1,336 @@ +# Overlays for the Raspberry Pi platform + +dtb-$(CONFIG_ARCH_BCM2835) += overlay_map.dtb hat_map.dtb @@ -16154,6 +16209,7 @@ index 000000000000..bdd02b8c6f0f + pifi-dac-zero.dtbo \ + pifi-mini-210.dtbo \ + piglow.dtbo \ ++ pineboards-hat-ai.dtbo \ + piscreen.dtbo \ + piscreen2r.dtbo \ + pisound.dtbo \ @@ -16187,6 +16243,7 @@ index 000000000000..bdd02b8c6f0f + rra-digidac1-wm8741-audio.dtbo \ + sainsmart18.dtbo \ + sc16is750-i2c.dtbo \ ++ sc16is750-spi0.dtbo \ + sc16is752-i2c.dtbo \ + sc16is752-spi0.dtbo \ + sc16is752-spi1.dtbo \ @@ -16230,6 +16287,7 @@ index 000000000000..bdd02b8c6f0f + ssd1306-spi.dtbo \ + ssd1331-spi.dtbo \ + ssd1351-spi.dtbo \ ++ sunfounder-pironman5.dtbo \ + superaudioboard.dtbo \ + sx150x.dtbo \ + tc358743.dtbo \ @@ -16291,10 +16349,10 @@ index 000000000000..bdd02b8c6f0f +clean-files := *.dtbo diff --git a/arch/arm/boot/dts/overlays/README b/arch/arm/boot/dts/overlays/README new file mode 100644 -index 000000000000..cca16ab81f9e +index 000000000000..7cb552f4784a --- /dev/null +++ b/arch/arm/boot/dts/overlays/README -@@ -0,0 +1,5346 @@ +@@ -0,0 +1,5389 @@ +Introduction +============ + @@ -16427,11 +16485,28 @@ index 000000000000..cca16ab81f9e +Info: Configures the base Raspberry Pi hardware +Load: +Params: -+ ant1 Select antenna 1 (default). CM4 only. ++ act_led_trigger Choose which activity the LED tracks. ++ Use "heartbeat" for a nice load indicator. ++ (default "mmc") + -+ ant2 Select antenna 2. CM4 only. ++ act_led_activelow Set to "on" to invert the sense of the LED ++ (default "off") ++ N.B. For Pi 3B, 3B+, 3A+ and 4B, use the act-led ++ overlay. + -+ noant Disable both antennas. CM4 only. ++ act_led_gpio Set which GPIO to use for the activity LED ++ (in case you want to connect it to an external ++ device) ++ (default "16" on a non-Plus board, "47" on a ++ Plus or Pi 2) ++ N.B. For Pi 3B, 3B+, 3A+ and 4B, use the act-led ++ overlay. ++ ++ ant1 Select antenna 1 (default). CM4/5 only. ++ ++ ant2 Select antenna 2. CM4/5 only. ++ ++ noant Disable both antennas. CM4/5 only. + + audio Set to "on" to enable the onboard ALSA audio + interface (default "off") @@ -16467,6 +16542,18 @@ index 000000000000..cca16ab81f9e + Default of GPIO expander 5 on CM4, but override + switches to normal GPIO. + ++ cam0_sync Enable a GPIO to reflect frame sync from CSI0, ++ going high on frame start, and low on frame end. ++ ++ cam0_sync_inverted Enable a GPIO to reflect frame sync from CSI0 ++ going low on frame start, and high on frame end. ++ ++ cam1_sync Enable a GPIO to reflect frame sync from CSI1, ++ going high on frame start, and low on frame end. ++ ++ cam1_sync_inverted Enable a GPIO to reflect frame sync from CSI1 ++ going low on frame start, and high on frame end. ++ + cooling_fan Enables the Pi 5 cooling fan (enabled + automatically by the firmware) + @@ -16625,12 +16712,11 @@ index 000000000000..cca16ab81f9e + pciex1_tperst_clk_ms Alias for pcie_tperst_clk_ms + (2712 only, default "0") + -+ spi Set to "on" to enable the spi interfaces -+ (default "off") -+ -+ spi_dma4 Use to enable 40-bit DMA on spi interfaces -+ (the assigned value doesn't matter) -+ (2711 only) ++ pwr_led_trigger ++ pwr_led_activelow ++ pwr_led_gpio ++ As for act_led_*, but using the PWR LED. ++ Not available on Model A/B boards. + + random Set to "on" to enable the hardware random + number generator (default "on") @@ -16671,6 +16757,19 @@ index 000000000000..cca16ab81f9e + sdio_overclock Clock (in MHz) to use when the MMC framework + requests 50MHz for the SDIO/WLAN interface. + ++ spi Set to "on" to enable the spi interfaces ++ (default "off") ++ ++ spi_dma4 Use to enable 40-bit DMA on spi interfaces ++ (the assigned value doesn't matter) ++ (2711 only) ++ ++ strict_gpiod Return GPIOs to inputs when they are released. ++ If using the gpiod utilities, it is necessary ++ to keep a gpioset running (e.g. with ++ --mode=wait) in order for an output value to ++ persist. ++ + suspend Make the power button trigger a suspend rather + than a power-off (2712 only, default "off") + @@ -16695,29 +16794,6 @@ index 000000000000..cca16ab81f9e + with or without colon separators, written in the + natural (big-endian) order. + -+ act_led_trigger Choose which activity the LED tracks. -+ Use "heartbeat" for a nice load indicator. -+ (default "mmc") -+ -+ act_led_activelow Set to "on" to invert the sense of the LED -+ (default "off") -+ N.B. For Pi 3B, 3B+, 3A+ and 4B, use the act-led -+ overlay. -+ -+ act_led_gpio Set which GPIO to use for the activity LED -+ (in case you want to connect it to an external -+ device) -+ (default "16" on a non-Plus board, "47" on a -+ Plus or Pi 2) -+ N.B. For Pi 3B, 3B+, 3A+ and 4B, use the act-led -+ overlay. -+ -+ pwr_led_trigger -+ pwr_led_activelow -+ pwr_led_gpio -+ As for act_led_*, but using the PWR LED. -+ Not available on Model A/B boards. -+ + N.B. It is recommended to only enable those interfaces that are needed. + Leaving all interfaces enabled can lead to unwanted behaviour (i2c_vc + interfering with Pi Camera, I2S and SPI hogging GPIO pins, etc.) @@ -19897,6 +19973,12 @@ index 000000000000..cca16ab81f9e +Params: + + ++Name: pineboards-hat-ai ++Info: Pineboards Hat Ai! overlay for the Google Coral Edge TPU ++Load: dtoverlay=pineboards-hat-ai ++Params: ++ ++ +Name: piscreen +Info: PiScreen display by OzzMaker.com +Load: dtoverlay=piscreen,= @@ -20117,7 +20199,7 @@ index 000000000000..cca16ab81f9e + + +Name: qca7000 -+Info: in-tech's Evaluation Board for PLC Stamp micro ++Info: Evaluation Board for PLC Stamp micro + This uses spi0 and a separate GPIO interrupt to connect the QCA7000. +Load: dtoverlay=qca7000,= +Params: int_pin GPIO pin for interrupt signal (default 23) @@ -20126,7 +20208,7 @@ index 000000000000..cca16ab81f9e + + +Name: qca7000-uart0 -+Info: in-tech's Evaluation Board for PLC Stamp micro (UART) ++Info: Evaluation Board for PLC Stamp micro (UART) + This uses uart0/ttyAMA0 over GPIOs 14 & 15 to connect the QCA7000. + But it requires disabling of onboard Bluetooth on + Pi 3B, 3B+, 3A+, 4B and Zero W. @@ -20401,6 +20483,14 @@ index 000000000000..cca16ab81f9e + xtal On-board crystal frequency (default 14745600) + + ++Name: sc16is750-spi0 ++Info: Overlay for the NXP SC16IS750 UART with SPI Interface ++ Enables the chip on SPI0. ++Load: dtoverlay=sc16is750-spi0,= ++Params: int_pin GPIO used for IRQ (default 24) ++ xtal On-board crystal frequency (default 14745600) ++ ++ +Name: sc16is752-i2c +Info: Overlay for the NXP SC16IS752 dual UART with I2C Interface + Enables the chip on I2C1 at 0x48 (or the "addr" parameter value). To @@ -20946,6 +21036,13 @@ index 000000000000..cca16ab81f9e + reset_pin GPIO pin for RESET (default 25) + + ++Name: sunfounder-pironman5 ++Info: Overlay for SunFounder Pironman 5 ++Load: dtoverlay=sunfounder-pironman5,= ++Params: ir Enable IR or not (on or off, default on) ++ ir_pins Change IR receiver pin (default 12) ++ ++ +Name: superaudioboard +Info: Configures the SuperAudioBoard sound card +Load: dtoverlay=superaudioboard,= @@ -21154,8 +21251,10 @@ index 000000000000..cca16ab81f9e + + +Name: vc4-fkms-v3d -+Info: Enable Eric Anholt's DRM VC4 V3D driver on top of the dispmanx ++Info: Enable the kernel DRM VC4 V3D driver on top of the dispmanx + display stack. ++ NB The firmware will not allow this overlay to load on a Pi with less ++ than 512MB as memory is too tight. +Load: dtoverlay=vc4-fkms-v3d, +Params: cma-512 CMA is 512MB (needs 1GB) + cma-448 CMA is 448MB (needs 1GB) @@ -21171,7 +21270,7 @@ index 000000000000..cca16ab81f9e + + +Name: vc4-fkms-v3d-pi4 -+Info: Enable Eric Anholt's DRM VC4 V3D driver on top of the dispmanx ++Info: Enable the kernel DRM VC4 V3D driver on top of the dispmanx + display stack. +Load: dtoverlay=vc4-fkms-v3d-pi4, +Params: cma-512 CMA is 512MB (needs 1GB) @@ -21440,7 +21539,9 @@ index 000000000000..cca16ab81f9e + + +Name: vc4-kms-v3d -+Info: Enable Eric Anholt's DRM VC4 HDMI/HVS/V3D driver. ++Info: Enable the kernel DRM VC4 HDMI/HVS/V3D driver. ++ NB The firmware will not allow this overlay to load on a Pi with less ++ than 512MB as memory is too tight. +Load: dtoverlay=vc4-kms-v3d, +Params: cma-512 CMA is 512MB (needs 1GB) + cma-448 CMA is 448MB (needs 1GB) @@ -21461,7 +21562,7 @@ index 000000000000..cca16ab81f9e + + +Name: vc4-kms-v3d-pi4 -+Info: Enable Eric Anholt's DRM VC4 HDMI/HVS/V3D driver for Pi4. ++Info: Enable the kernel DRM VC4 HDMI/HVS/V3D driver for Pi4. +Load: dtoverlay=vc4-kms-v3d-pi4, +Params: cma-512 CMA is 512MB + cma-448 CMA is 448MB @@ -24099,10 +24200,10 @@ index 000000000000..8f9c6a887064 +}; diff --git a/arch/arm/boot/dts/overlays/camera-mux-2port-overlay.dts b/arch/arm/boot/dts/overlays/camera-mux-2port-overlay.dts new file mode 100644 -index 000000000000..13d86cc693b3 +index 000000000000..f8baee20220a --- /dev/null +++ b/arch/arm/boot/dts/overlays/camera-mux-2port-overlay.dts -@@ -0,0 +1,545 @@ +@@ -0,0 +1,547 @@ +// SPDX-License-Identifier: GPL-2.0-only +// Overlay to configure a 2 port camera multiplexer +// @@ -24558,6 +24659,7 @@ index 000000000000..13d86cc693b3 + <&imx708_0>,"lens-focus:0=", <&imx708_0_vcm>; + cam0-ov5647 = <&mux_in0>, "remote-endpoint:0=",<&ov5647_0_ep>, + <&ov5647_0_ep>, "remote-endpoint:0=",<&mux_in0>, ++ <&mux_in0>, "clock-noncontinuous?", + <&ov5647_0>, "status=okay"; + cam0-ov7251 = <&mux_in0>, "remote-endpoint:0=",<&ov7251_0_ep>, + <&ov7251_0_ep>, "remote-endpoint:0=",<&mux_in0>, @@ -24610,6 +24712,7 @@ index 000000000000..13d86cc693b3 + <&imx708_1>,"lens-focus:0=", <&imx708_1_vcm>; + cam1-ov5647 = <&mux_in1>, "remote-endpoint:0=",<&ov5647_1_ep>, + <&ov5647_1_ep>, "remote-endpoint:0=",<&mux_in1>, ++ <&mux_in1>, "clock-noncontinuous?", + <&ov5647_1>, "status=okay"; + cam1-ov7251 = <&mux_in1>, "remote-endpoint:0=",<&ov7251_1_ep>, + <&ov7251_1_ep>, "remote-endpoint:0=",<&mux_in1>, @@ -24650,10 +24753,10 @@ index 000000000000..13d86cc693b3 +}; diff --git a/arch/arm/boot/dts/overlays/camera-mux-4port-overlay.dts b/arch/arm/boot/dts/overlays/camera-mux-4port-overlay.dts new file mode 100644 -index 000000000000..c8f8f594cd61 +index 000000000000..45c41d9c8da1 --- /dev/null +++ b/arch/arm/boot/dts/overlays/camera-mux-4port-overlay.dts -@@ -0,0 +1,952 @@ +@@ -0,0 +1,956 @@ +// SPDX-License-Identifier: GPL-2.0-only + +// Overlay to configure a 4 port camera multiplexer @@ -25404,6 +25507,7 @@ index 000000000000..c8f8f594cd61 + <&imx708_0>,"lens-focus:0=", <&imx708_0_vcm>; + cam0-ov5647 = <&mux_in0>, "remote-endpoint:0=",<&ov5647_0_ep>, + <&ov5647_0_ep>, "remote-endpoint:0=",<&mux_in0>, ++ <&mux_in0>, "clock-noncontinuous?", + <&ov5647_0>, "status=okay"; + cam0-ov7251 = <&mux_in0>, "remote-endpoint:0=",<&ov7251_0_ep>, + <&ov7251_0_ep>, "remote-endpoint:0=",<&mux_in0>, @@ -25456,6 +25560,7 @@ index 000000000000..c8f8f594cd61 + <&imx708_1>,"lens-focus:0=", <&imx708_1_vcm>; + cam1-ov5647 = <&mux_in1>, "remote-endpoint:0=",<&ov5647_1_ep>, + <&ov5647_1_ep>, "remote-endpoint:0=",<&mux_in1>, ++ <&mux_in1>, "clock-noncontinuous?", + <&ov5647_1>, "status=okay"; + cam1-ov7251 = <&mux_in1>, "remote-endpoint:0=",<&ov7251_1_ep>, + <&ov7251_1_ep>, "remote-endpoint:0=",<&mux_in1>, @@ -25508,6 +25613,7 @@ index 000000000000..c8f8f594cd61 + <&imx708_2>,"lens-focus:0=", <&imx708_2_vcm>; + cam2-ov5647 = <&mux_in2>, "remote-endpoint:0=",<&ov5647_2_ep>, + <&ov5647_2_ep>, "remote-endpoint:0=",<&mux_in2>, ++ <&mux_in2>, "clock-noncontinuous?", + <&ov5647_2>, "status=okay"; + cam2-ov7251 = <&mux_in2>, "remote-endpoint:0=",<&ov7251_2_ep>, + <&ov7251_2_ep>, "remote-endpoint:0=",<&mux_in2>, @@ -25560,6 +25666,7 @@ index 000000000000..c8f8f594cd61 + <&imx708_3>,"lens-focus:0=", <&imx708_3_vcm>; + cam3-ov5647 = <&mux_in3>, "remote-endpoint:0=",<&ov5647_3_ep>, + <&ov5647_3_ep>, "remote-endpoint:0=",<&mux_in3>, ++ <&mux_in3>, "clock-noncontinuous?", + <&ov5647_3>, "status=okay"; + cam3-ov7251 = <&mux_in3>, "remote-endpoint:0=",<&ov7251_3_ep>, + <&ov7251_3_ep>, "remote-endpoint:0=",<&mux_in3>, @@ -31725,10 +31832,10 @@ index 000000000000..cd31eac7e333 +}; diff --git a/arch/arm/boot/dts/overlays/i2c-sensor-common.dtsi b/arch/arm/boot/dts/overlays/i2c-sensor-common.dtsi new file mode 100755 -index 000000000000..2f7d1fe402eb +index 000000000000..83b2a1286426 --- /dev/null +++ b/arch/arm/boot/dts/overlays/i2c-sensor-common.dtsi -@@ -0,0 +1,578 @@ +@@ -0,0 +1,597 @@ +// Definitions for I2C based sensors using the Industrial IO or HWMON interface. +/dts-v1/; +/plugin/; @@ -32038,6 +32145,8 @@ index 000000000000..2f7d1fe402eb + maxim,ir-led-current-microamp = <7000>; + interrupt-parent = <&gpio>; + interrupts = <4 2>; ++ pinctrl-0 = <&int_pins>; ++ pinctrl-names = "default"; + }; + }; + }; @@ -32167,6 +32276,8 @@ index 000000000000..2f7d1fe402eb + reg = <0x68>; + interrupt-parent = <&gpio>; + interrupts = <4 2>; ++ pinctrl-0 = <&int_pins>; ++ pinctrl-names = "default"; + }; + }; + }; @@ -32184,6 +32295,8 @@ index 000000000000..2f7d1fe402eb + reg = <0x68>; + interrupt-parent = <&gpio>; + interrupts = <4 2>; ++ pinctrl-0 = <&int_pins>; ++ pinctrl-names = "default"; + }; + }; + }; @@ -32254,6 +32367,17 @@ index 000000000000..2f7d1fe402eb + }; + }; + ++ fragment@99 { ++ target = <&gpio>; ++ __dormant__ { ++ int_pins: int_pins@4 { ++ brcm,pins = <4>; ++ brcm,function = <0>; /* in */ ++ brcm,pull = <0>; /* none */ ++ }; ++ }; ++ }; ++ + __overrides__ { + bme280 = <0>,"+0"; + bmp085 = <0>,"+1"; @@ -32276,7 +32400,7 @@ index 000000000000..2f7d1fe402eb + sgp30 = <0>,"+16"; + ccs811 = <0>, "+17"; + bh1750 = <0>, "+18"; -+ max30102 = <0>,"+19"; ++ max30102 = <0>,"+19+99"; + aht10 = <0>,"+20"; + mcp980x = <0>,"+21"; + jc42 = <0>,"+22"; @@ -32285,8 +32409,8 @@ index 000000000000..2f7d1fe402eb + ms5805 = <0>,"+25"; + ms5837 = <0>,"+26"; + ms8607 = <0>,"+27"; -+ mpu6050 = <0>,"+28"; -+ mpu9250 = <0>,"+29"; ++ mpu6050 = <0>,"+28+99"; ++ mpu9250 = <0>,"+29+99"; + bno055 = <0>,"+31"; + sht4x = <0>,"+32"; + adt7410 = <0>,"+34"; @@ -32300,7 +32424,9 @@ index 000000000000..2f7d1fe402eb + <&mpu6050>,"reg:0", <&mpu9250>,"reg:0", + <&bno055>,"reg:0", <&sht4x>,"reg:0", + <&bmp380>,"reg:0", <&adt7410>,"reg:0"; -+ int_pin = <&max30102>, "interrupts:0", ++ int_pin = <&int_pins>, "brcm,pins:0", ++ <&int_pins>, "reg:0", ++ <&max30102>, "interrupts:0", + <&mpu6050>, "interrupts:0", + <&mpu9250>, "interrupts:0"; + no_timeout = <&jc42>, "smbus-timeout-disable?"; @@ -37508,7 +37634,7 @@ index 000000000000..f7e44d29e101 +}; diff --git a/arch/arm/boot/dts/overlays/midi-uart0-pi5-overlay.dts b/arch/arm/boot/dts/overlays/midi-uart0-pi5-overlay.dts new file mode 100644 -index 000000000000..6cd1f3ed2d8d +index 000000000000..837d1b014e28 --- /dev/null +++ b/arch/arm/boot/dts/overlays/midi-uart0-pi5-overlay.dts @@ -0,0 +1,35 @@ @@ -37519,10 +37645,10 @@ index 000000000000..6cd1f3ed2d8d + +/* + * Fake a higher clock rate to get a larger divisor, and thereby a lower -+ * baudrate. The real clock is 100MHz, which we scale so that requesting ++ * baudrate. The real clock is 50MHz, which we scale so that requesting + * 38.4kHz results in an actual 31.25kHz. + * -+ * 100000000*38400/31250 = 122880000 ++ * 50000000*38400/31250 = 61440000 + */ + +/{ @@ -37535,7 +37661,7 @@ index 000000000000..6cd1f3ed2d8d + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-output-names = "uart0_pclk"; -+ clock-frequency = <122880000>; ++ clock-frequency = <61440000>; + }; + }; + }; @@ -37598,7 +37724,7 @@ index 000000000000..e0bc410acbff +}; diff --git a/arch/arm/boot/dts/overlays/midi-uart1-pi5-overlay.dts b/arch/arm/boot/dts/overlays/midi-uart1-pi5-overlay.dts new file mode 100644 -index 000000000000..18f526865eed +index 000000000000..e803876622a9 --- /dev/null +++ b/arch/arm/boot/dts/overlays/midi-uart1-pi5-overlay.dts @@ -0,0 +1,35 @@ @@ -37609,10 +37735,10 @@ index 000000000000..18f526865eed + +/* + * Fake a higher clock rate to get a larger divisor, and thereby a lower -+ * baudrate. The real clock is 100MHz, which we scale so that requesting ++ * baudrate. The real clock is 50MHz, which we scale so that requesting + * 38.4kHz results in an actual 31.25kHz. + * -+ * 100000000*38400/31250 = 122880000 ++ * 50000000*38400/31250 = 61440000 + */ + +/{ @@ -37625,7 +37751,7 @@ index 000000000000..18f526865eed + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-output-names = "uart1_pclk"; -+ clock-frequency = <122880000>; ++ clock-frequency = <61440000>; + }; + }; + }; @@ -37682,7 +37808,7 @@ index 000000000000..5c6985f41ea2 + diff --git a/arch/arm/boot/dts/overlays/midi-uart2-pi5-overlay.dts b/arch/arm/boot/dts/overlays/midi-uart2-pi5-overlay.dts new file mode 100644 -index 000000000000..5e1e0c6fd7a9 +index 000000000000..4f07e7de2df3 --- /dev/null +++ b/arch/arm/boot/dts/overlays/midi-uart2-pi5-overlay.dts @@ -0,0 +1,35 @@ @@ -37693,10 +37819,10 @@ index 000000000000..5e1e0c6fd7a9 + +/* + * Fake a higher clock rate to get a larger divisor, and thereby a lower -+ * baudrate. The real clock is 100MHz, which we scale so that requesting ++ * baudrate. The real clock is 50MHz, which we scale so that requesting + * 38.4kHz results in an actual 31.25kHz. + * -+ * 100000000*38400/31250 = 122880000 ++ * 50000000*38400/31250 = 61440000 + */ + +/{ @@ -37709,7 +37835,7 @@ index 000000000000..5e1e0c6fd7a9 + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-output-names = "uart2_pclk"; -+ clock-frequency = <122880000>; ++ clock-frequency = <61440000>; + }; + }; + }; @@ -37767,7 +37893,7 @@ index 000000000000..052027db0564 + diff --git a/arch/arm/boot/dts/overlays/midi-uart3-pi5-overlay.dts b/arch/arm/boot/dts/overlays/midi-uart3-pi5-overlay.dts new file mode 100644 -index 000000000000..705a2793d00c +index 000000000000..478220d41edc --- /dev/null +++ b/arch/arm/boot/dts/overlays/midi-uart3-pi5-overlay.dts @@ -0,0 +1,35 @@ @@ -37778,10 +37904,10 @@ index 000000000000..705a2793d00c + +/* + * Fake a higher clock rate to get a larger divisor, and thereby a lower -+ * baudrate. The real clock is 100MHz, which we scale so that requesting ++ * baudrate. The real clock is 50MHz, which we scale so that requesting + * 38.4kHz results in an actual 31.25kHz. + * -+ * 100000000*38400/31250 = 122880000 ++ * 50000000*38400/31250 = 61440000 + */ + +/{ @@ -37794,7 +37920,7 @@ index 000000000000..705a2793d00c + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-output-names = "uart3_pclk"; -+ clock-frequency = <122880000>; ++ clock-frequency = <61440000>; + }; + }; + }; @@ -37852,7 +37978,7 @@ index 000000000000..5f09a7ccd675 + diff --git a/arch/arm/boot/dts/overlays/midi-uart4-pi5-overlay.dts b/arch/arm/boot/dts/overlays/midi-uart4-pi5-overlay.dts new file mode 100644 -index 000000000000..0d2f823ed7dd +index 000000000000..827bd5e951ba --- /dev/null +++ b/arch/arm/boot/dts/overlays/midi-uart4-pi5-overlay.dts @@ -0,0 +1,35 @@ @@ -37863,10 +37989,10 @@ index 000000000000..0d2f823ed7dd + +/* + * Fake a higher clock rate to get a larger divisor, and thereby a lower -+ * baudrate. The real clock is 100MHz, which we scale so that requesting ++ * baudrate. The real clock is 50MHz, which we scale so that requesting + * 38.4kHz results in an actual 31.25kHz. + * -+ * 100000000*38400/31250 = 122880000 ++ * 50000000*38400/31250 = 61440000 + */ + +/{ @@ -37879,7 +38005,7 @@ index 000000000000..0d2f823ed7dd + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-output-names = "uart4_pclk"; -+ clock-frequency = <122880000>; ++ clock-frequency = <61440000>; + }; + }; + }; @@ -38601,10 +38727,10 @@ index 000000000000..a1714d6941c3 +}; diff --git a/arch/arm/boot/dts/overlays/ov5647-overlay.dts b/arch/arm/boot/dts/overlays/ov5647-overlay.dts new file mode 100644 -index 000000000000..37fe46412439 +index 000000000000..2b1ef618de05 --- /dev/null +++ b/arch/arm/boot/dts/overlays/ov5647-overlay.dts -@@ -0,0 +1,93 @@ +@@ -0,0 +1,94 @@ +// SPDX-License-Identifier: GPL-2.0-only +// Definitions for OV5647 camera module on VC I2C bus +/dts-v1/; @@ -38641,6 +38767,7 @@ index 000000000000..37fe46412439 + csi_ep: endpoint { + remote-endpoint = <&cam_endpoint>; + data-lanes = <1 2>; ++ clock-noncontinuous; + }; + }; + }; @@ -40603,6 +40730,30 @@ index 000000000000..075bceef158c + }; + }; +}; +diff --git a/arch/arm/boot/dts/overlays/pineboards-hat-ai-overlay.dts b/arch/arm/boot/dts/overlays/pineboards-hat-ai-overlay.dts +new file mode 100644 +index 000000000000..8160272f4705 +--- /dev/null ++++ b/arch/arm/boot/dts/overlays/pineboards-hat-ai-overlay.dts +@@ -0,0 +1,18 @@ ++/* ++ * Device Tree overlay for Pineboards Hat Ai!. ++ * Compatible with the Google Coral Edge TPU (Single and Dual Edge). ++ */ ++ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "brcm,bcm2712"; ++ ++ fragment@0 { ++ target = <&pcie1>; ++ __overlay__ { ++ msi-parent = <&pcie1>; ++ }; ++ }; ++}; diff --git a/arch/arm/boot/dts/overlays/piscreen-overlay.dts b/arch/arm/boot/dts/overlays/piscreen-overlay.dts new file mode 100644 index 000000000000..29bcd41f39cf @@ -41737,12 +41888,12 @@ index 000000000000..3324d4160653 +}; diff --git a/arch/arm/boot/dts/overlays/qca7000-overlay.dts b/arch/arm/boot/dts/overlays/qca7000-overlay.dts new file mode 100644 -index 000000000000..f695f36024fa +index 000000000000..cc5a4fda4e01 --- /dev/null +++ b/arch/arm/boot/dts/overlays/qca7000-overlay.dts @@ -0,0 +1,55 @@ +// Overlay for the Qualcomm Atheros QCA7000 on PLC Stamp micro EVK -+// Visit: https://in-tech-smartcharging.com/products/evaluation-tools/plc-stamp-micro-2-evaluation-board for details ++// Visit: https://chargebyte.com/products/evaluation-tools/plc-stamp-micro-2-evaluation-board for details + +/dts-v1/; +/plugin/; @@ -42593,10 +42744,10 @@ index 000000000000..c51f1c030a55 +}; diff --git a/arch/arm/boot/dts/overlays/sc16is750-i2c-overlay.dts b/arch/arm/boot/dts/overlays/sc16is750-i2c-overlay.dts new file mode 100644 -index 000000000000..04d74d62897b +index 000000000000..09c08c1c5433 --- /dev/null +++ b/arch/arm/boot/dts/overlays/sc16is750-i2c-overlay.dts -@@ -0,0 +1,43 @@ +@@ -0,0 +1,57 @@ +/dts-v1/; +/plugin/; + @@ -42616,6 +42767,8 @@ index 000000000000..04d74d62897b + clocks = <&sc16is750_clk>; + interrupt-parent = <&gpio>; + interrupts = <24 2>; /* IRQ_TYPE_EDGE_FALLING */ ++ pinctrl-0 = <&int_pins>; ++ pinctrl-names = "default"; + gpio-controller; + #gpio-cells = <2>; + i2c-max-frequency = <400000>; @@ -42634,18 +42787,99 @@ index 000000000000..04d74d62897b + }; + }; + ++ fragment@2 { ++ target = <&gpio>; ++ __overlay__ { ++ int_pins: int_pins@18 { ++ brcm,pins = <24>; ++ brcm,function = <0>; /* in */ ++ brcm,pull = <0>; /* none */ ++ }; ++ }; ++ }; ++ + __overrides__ { -+ int_pin = <&sc16is750>,"interrupts:0"; ++ int_pin = <&sc16is750>,"interrupts:0", <&int_pins>,"brcm,pins:0", ++ <&int_pins>,"reg:0"; + addr = <&sc16is750>,"reg:0", <&sc16is750_clk>,"name"; + xtal = <&sc16is750_clk>,"clock-frequency:0"; + }; +}; +diff --git a/arch/arm/boot/dts/overlays/sc16is750-spi0-overlay.dts b/arch/arm/boot/dts/overlays/sc16is750-spi0-overlay.dts +new file mode 100644 +index 000000000000..b289ee900edf +--- /dev/null ++++ b/arch/arm/boot/dts/overlays/sc16is750-spi0-overlay.dts +@@ -0,0 +1,63 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "brcm,bcm2835"; ++ ++ fragment@0 { ++ target = <&spi0>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "okay"; ++ ++ sc16is750: sc16is750@0 { ++ compatible = "nxp,sc16is750"; ++ reg = <0>; /* CE0 */ ++ clocks = <&sc16is750_clk>; ++ interrupt-parent = <&gpio>; ++ interrupts = <24 2>; /* IRQ_TYPE_EDGE_FALLING */ ++ pinctrl-0 = <&int_pins>; ++ pinctrl-names = "default"; ++ gpio-controller; ++ #gpio-cells = <2>; ++ spi-max-frequency = <4000000>; ++ }; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&spidev0>; ++ __overlay__ { ++ status = "disabled"; ++ }; ++ }; ++ ++ fragment@2 { ++ target-path = "/"; ++ __overlay__ { ++ sc16is750_clk: sc16is750_spi0_0_clk { ++ compatible = "fixed-clock"; ++ #clock-cells = <0>; ++ clock-frequency = <14745600>; ++ }; ++ }; ++ }; ++ ++ fragment@3 { ++ target = <&gpio>; ++ __overlay__ { ++ int_pins: int_pins@18 { ++ brcm,pins = <24>; ++ brcm,function = <0>; /* in */ ++ brcm,pull = <0>; /* none */ ++ }; ++ }; ++ }; ++ ++ __overrides__ { ++ int_pin = <&sc16is750>,"interrupts:0", <&int_pins>,"brcm,pins:0", ++ <&int_pins>,"reg:0"; ++ xtal = <&sc16is750_clk>,"clock-frequency:0"; ++ }; ++}; diff --git a/arch/arm/boot/dts/overlays/sc16is752-i2c-overlay.dts b/arch/arm/boot/dts/overlays/sc16is752-i2c-overlay.dts new file mode 100644 -index 000000000000..da05e981314c +index 000000000000..a7c538943859 --- /dev/null +++ b/arch/arm/boot/dts/overlays/sc16is752-i2c-overlay.dts -@@ -0,0 +1,43 @@ +@@ -0,0 +1,57 @@ +/dts-v1/; +/plugin/; + @@ -42665,6 +42899,8 @@ index 000000000000..da05e981314c + clocks = <&sc16is752_clk>; + interrupt-parent = <&gpio>; + interrupts = <24 2>; /* IRQ_TYPE_EDGE_FALLING */ ++ pinctrl-0 = <&int_pins>; ++ pinctrl-names = "default"; + gpio-controller; + #gpio-cells = <2>; + i2c-max-frequency = <400000>; @@ -42683,18 +42919,30 @@ index 000000000000..da05e981314c + }; + }; + ++ fragment@2 { ++ target = <&gpio>; ++ __overlay__ { ++ int_pins: int_pins@18 { ++ brcm,pins = <24>; ++ brcm,function = <0>; /* in */ ++ brcm,pull = <0>; /* none */ ++ }; ++ }; ++ }; ++ + __overrides__ { -+ int_pin = <&sc16is752>,"interrupts:0"; ++ int_pin = <&sc16is752>,"interrupts:0", <&int_pins>,"brcm,pins:0", ++ <&int_pins>,"reg:0"; + addr = <&sc16is752>,"reg:0",<&sc16is752_clk>,"name"; + xtal = <&sc16is752_clk>,"clock-frequency:0"; + }; +}; diff --git a/arch/arm/boot/dts/overlays/sc16is752-spi0-overlay.dts b/arch/arm/boot/dts/overlays/sc16is752-spi0-overlay.dts new file mode 100644 -index 000000000000..a49a04722b99 +index 000000000000..5f8941085831 --- /dev/null +++ b/arch/arm/boot/dts/overlays/sc16is752-spi0-overlay.dts -@@ -0,0 +1,49 @@ +@@ -0,0 +1,63 @@ +/dts-v1/; +/plugin/; + @@ -42714,6 +42962,8 @@ index 000000000000..a49a04722b99 + clocks = <&sc16is752_clk>; + interrupt-parent = <&gpio>; + interrupts = <24 2>; /* IRQ_TYPE_EDGE_FALLING */ ++ pinctrl-0 = <&int_pins>; ++ pinctrl-names = "default"; + gpio-controller; + #gpio-cells = <2>; + spi-max-frequency = <4000000>; @@ -42739,17 +42989,29 @@ index 000000000000..a49a04722b99 + }; + }; + ++ fragment@3 { ++ target = <&gpio>; ++ __overlay__ { ++ int_pins: int_pins@18 { ++ brcm,pins = <24>; ++ brcm,function = <0>; /* in */ ++ brcm,pull = <0>; /* none */ ++ }; ++ }; ++ }; ++ + __overrides__ { -+ int_pin = <&sc16is752>,"interrupts:0"; ++ int_pin = <&sc16is752>,"interrupts:0", <&int_pins>,"brcm,pins:0", ++ <&int_pins>,"reg:0"; + xtal = <&sc16is752_clk>,"clock-frequency:0"; + }; +}; diff --git a/arch/arm/boot/dts/overlays/sc16is752-spi1-overlay.dts b/arch/arm/boot/dts/overlays/sc16is752-spi1-overlay.dts new file mode 100644 -index 000000000000..730c6e8cd614 +index 000000000000..a9b64a98c278 --- /dev/null +++ b/arch/arm/boot/dts/overlays/sc16is752-spi1-overlay.dts -@@ -0,0 +1,67 @@ +@@ -0,0 +1,76 @@ +/dts-v1/; +/plugin/; + @@ -42768,6 +43030,12 @@ index 000000000000..730c6e8cd614 + brcm,pins = <18>; + brcm,function = <1>; /* output */ + }; ++ ++ int_pins: int_pins@18 { ++ brcm,pins = <24>; ++ brcm,function = <0>; /* in */ ++ brcm,pull = <0>; /* none */ ++ }; + }; + }; + @@ -42787,6 +43055,8 @@ index 000000000000..730c6e8cd614 + clocks = <&sc16is752_clk>; + interrupt-parent = <&gpio>; + interrupts = <24 2>; /* IRQ_TYPE_EDGE_FALLING */ ++ pinctrl-0 = <&int_pins>; ++ pinctrl-names = "default"; + gpio-controller; + #gpio-cells = <2>; + spi-max-frequency = <4000000>; @@ -42813,7 +43083,8 @@ index 000000000000..730c6e8cd614 + }; + + __overrides__ { -+ int_pin = <&sc16is752>,"interrupts:0"; ++ int_pin = <&sc16is752>,"interrupts:0", <&int_pins>,"brcm,pins:0", ++ <&int_pins>,"reg:0"; + xtal = <&sc16is752_clk>,"clock-frequency:0"; + }; +}; @@ -45287,6 +45558,63 @@ index 000000000000..ffc872c60648 + <&ssd1351_pins>,"brcm,pins:0"; + }; +}; +diff --git a/arch/arm/boot/dts/overlays/sunfounder-pironman5-overlay.dts b/arch/arm/boot/dts/overlays/sunfounder-pironman5-overlay.dts +new file mode 100644 +index 000000000000..29893d5467d9 +--- /dev/null ++++ b/arch/arm/boot/dts/overlays/sunfounder-pironman5-overlay.dts +@@ -0,0 +1,51 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "brcm,bcm2835"; ++ ++ fragment@0 { ++ target = <&i2c1>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++ fragment@1 { ++ target = <&spi0>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++ fragment@2 { ++ target-path = "/"; ++ __overlay__ { ++ gpio_ir: ir-receiver@c { ++ compatible = "gpio-ir-receiver"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&gpio_ir_pins>; ++ ++ // pin number, high or low ++ gpios = <&gpio 12 1>; ++ ++ // parameter for keymap name ++ linux,rc-map-name = "rc-rc6-mce"; ++ ++ status = "okay"; ++ }; ++ }; ++ }; ++ fragment@3 { ++ target = <&gpio>; ++ __overlay__ { ++ gpio_ir_pins: gpio_ir_pins@c { ++ brcm,pins = <12>; ++ brcm,function = <0>; ++ brcm,pull = <2>; ++ }; ++ }; ++ }; ++ __overrides__ { ++ ir = <&gpio_ir>,"status"; ++ ir_pins = <&gpio_ir>,"gpios:4", <&gpio_ir>,"reg:0", <&gpio_ir_pins>,"brcm,pins:0", <&gpio_ir_pins>,"reg:0"; ++ }; ++}; diff --git a/arch/arm/boot/dts/overlays/superaudioboard-overlay.dts b/arch/arm/boot/dts/overlays/superaudioboard-overlay.dts new file mode 100755 index 000000000000..1006d5fe9e06 @@ -51287,10 +51615,10 @@ index 000000000000..3dd0b384079d +}; diff --git a/arch/arm/configs/bcm2709_defconfig b/arch/arm/configs/bcm2709_defconfig new file mode 100644 -index 000000000000..a45c2db93d69 +index 000000000000..f54eaec96297 --- /dev/null +++ b/arch/arm/configs/bcm2709_defconfig -@@ -0,0 +1,1583 @@ +@@ -0,0 +1,1585 @@ +CONFIG_LOCALVERSION="-v7" +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_SYSVIPC=y @@ -51558,6 +51886,7 @@ index 000000000000..a45c2db93d69 +CONFIG_IP_NF_MATCH_TTL=m +CONFIG_IP_NF_FILTER=m +CONFIG_IP_NF_TARGET_REJECT=m ++CONFIG_IP_NF_TARGET_SYNPROXY=m +CONFIG_IP_NF_NAT=m +CONFIG_IP_NF_TARGET_MASQUERADE=m +CONFIG_IP_NF_TARGET_NETMAP=m @@ -52249,6 +52578,7 @@ index 000000000000..a45c2db93d69 +CONFIG_DRM_UDL=m +CONFIG_DRM_PANEL_SIMPLE=m +CONFIG_DRM_PANEL_ILITEK_ILI9806E=m ++CONFIG_DRM_PANEL_ILITEK_ILI9881C=m +CONFIG_DRM_PANEL_JDI_LT070ME05000=m +CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN=m +CONFIG_DRM_PANEL_SITRONIX_ST7701=m @@ -52876,10 +53206,10 @@ index 000000000000..a45c2db93d69 +# CONFIG_UPROBE_EVENTS is not set diff --git a/arch/arm/configs/bcm2711_defconfig b/arch/arm/configs/bcm2711_defconfig new file mode 100644 -index 000000000000..2bf13fd55bed +index 000000000000..442e18282bdb --- /dev/null +++ b/arch/arm/configs/bcm2711_defconfig -@@ -0,0 +1,1610 @@ +@@ -0,0 +1,1615 @@ +CONFIG_LOCALVERSION="-v7l" +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_SYSVIPC=y @@ -53148,6 +53478,7 @@ index 000000000000..2bf13fd55bed +CONFIG_IP_NF_MATCH_TTL=m +CONFIG_IP_NF_FILTER=m +CONFIG_IP_NF_TARGET_REJECT=m ++CONFIG_IP_NF_TARGET_SYNPROXY=m +CONFIG_IP_NF_NAT=m +CONFIG_IP_NF_TARGET_MASQUERADE=m +CONFIG_IP_NF_TARGET_NETMAP=m @@ -53378,6 +53709,10 @@ index 000000000000..2bf13fd55bed +CONFIG_VETH=m +CONFIG_NET_VRF=m +CONFIG_BCMGENET=y ++CONFIG_IGB=m ++CONFIG_IXGBE=m ++CONFIG_I40E=m ++CONFIG_IGC=m +CONFIG_ENC28J60=m +CONFIG_LAN743X=m +CONFIG_QCA7000_SPI=m @@ -54492,10 +54827,10 @@ index 000000000000..2bf13fd55bed +# CONFIG_UPROBE_EVENTS is not set diff --git a/arch/arm/configs/bcmrpi_defconfig b/arch/arm/configs/bcmrpi_defconfig new file mode 100644 -index 000000000000..1c1ffb4ae498 +index 000000000000..4c2cf05be22b --- /dev/null +++ b/arch/arm/configs/bcmrpi_defconfig -@@ -0,0 +1,1576 @@ +@@ -0,0 +1,1578 @@ +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_SYSVIPC=y +CONFIG_POSIX_MQUEUE=y @@ -54758,6 +55093,7 @@ index 000000000000..1c1ffb4ae498 +CONFIG_IP_NF_MATCH_TTL=m +CONFIG_IP_NF_FILTER=m +CONFIG_IP_NF_TARGET_REJECT=m ++CONFIG_IP_NF_TARGET_SYNPROXY=m +CONFIG_IP_NF_NAT=m +CONFIG_IP_NF_TARGET_MASQUERADE=m +CONFIG_IP_NF_TARGET_NETMAP=m @@ -55448,6 +55784,7 @@ index 000000000000..1c1ffb4ae498 +CONFIG_DRM_UDL=m +CONFIG_DRM_PANEL_SIMPLE=m +CONFIG_DRM_PANEL_ILITEK_ILI9806E=m ++CONFIG_DRM_PANEL_ILITEK_ILI9881C=m +CONFIG_DRM_PANEL_JDI_LT070ME05000=m +CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN=m +CONFIG_DRM_PANEL_SITRONIX_ST7701=m @@ -58296,10 +58633,10 @@ index 000000000000..ded08646b6f6 \ No newline at end of file diff --git a/arch/arm64/configs/bcm2711_defconfig b/arch/arm64/configs/bcm2711_defconfig new file mode 100644 -index 000000000000..6ac8c83f6842 +index 000000000000..38ef9d2d8221 --- /dev/null +++ b/arch/arm64/configs/bcm2711_defconfig -@@ -0,0 +1,1672 @@ +@@ -0,0 +1,1677 @@ +CONFIG_LOCALVERSION="-v8" +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_SYSVIPC=y @@ -58578,6 +58915,7 @@ index 000000000000..6ac8c83f6842 +CONFIG_IP_NF_MATCH_TTL=m +CONFIG_IP_NF_FILTER=m +CONFIG_IP_NF_TARGET_REJECT=m ++CONFIG_IP_NF_TARGET_SYNPROXY=m +CONFIG_IP_NF_NAT=m +CONFIG_IP_NF_TARGET_MASQUERADE=m +CONFIG_IP_NF_TARGET_NETMAP=m @@ -58816,6 +59154,10 @@ index 000000000000..6ac8c83f6842 +CONFIG_VSOCKMON=m +CONFIG_BCMGENET=y +CONFIG_MACB=y ++CONFIG_IGB=m ++CONFIG_IXGBE=m ++CONFIG_I40E=m ++CONFIG_IGC=m +CONFIG_ENC28J60=m +CONFIG_LAN743X=m +CONFIG_QCA7000_SPI=m @@ -59974,10 +60316,10 @@ index 000000000000..6ac8c83f6842 +# CONFIG_STRICT_DEVMEM is not set diff --git a/arch/arm64/configs/bcm2712_defconfig b/arch/arm64/configs/bcm2712_defconfig new file mode 100644 -index 000000000000..875b905be102 +index 000000000000..67e9a9703528 --- /dev/null +++ b/arch/arm64/configs/bcm2712_defconfig -@@ -0,0 +1,1675 @@ +@@ -0,0 +1,1680 @@ +CONFIG_LOCALVERSION="-v8-16k" +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_SYSVIPC=y @@ -60259,6 +60601,7 @@ index 000000000000..875b905be102 +CONFIG_IP_NF_MATCH_TTL=m +CONFIG_IP_NF_FILTER=m +CONFIG_IP_NF_TARGET_REJECT=m ++CONFIG_IP_NF_TARGET_SYNPROXY=m +CONFIG_IP_NF_NAT=m +CONFIG_IP_NF_TARGET_MASQUERADE=m +CONFIG_IP_NF_TARGET_NETMAP=m @@ -60497,6 +60840,10 @@ index 000000000000..875b905be102 +CONFIG_VSOCKMON=m +CONFIG_BCMGENET=y +CONFIG_MACB=y ++CONFIG_IGB=m ++CONFIG_IXGBE=m ++CONFIG_I40E=m ++CONFIG_IGC=m +CONFIG_ENC28J60=m +CONFIG_LAN743X=m +CONFIG_QCA7000_SPI=m @@ -61655,10 +62002,10 @@ index 000000000000..875b905be102 +# CONFIG_STRICT_DEVMEM is not set diff --git a/arch/arm64/configs/bcmrpi3_defconfig b/arch/arm64/configs/bcmrpi3_defconfig new file mode 100644 -index 000000000000..ffa7195abfad +index 000000000000..38ee19e19f46 --- /dev/null +++ b/arch/arm64/configs/bcmrpi3_defconfig -@@ -0,0 +1,1560 @@ +@@ -0,0 +1,1561 @@ +CONFIG_LOCALVERSION="-v8" +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_SYSVIPC=y @@ -61928,6 +62275,7 @@ index 000000000000..ffa7195abfad +CONFIG_IP_NF_MATCH_TTL=m +CONFIG_IP_NF_FILTER=m +CONFIG_IP_NF_TARGET_REJECT=m ++CONFIG_IP_NF_TARGET_SYNPROXY=m +CONFIG_IP_NF_NAT=m +CONFIG_IP_NF_TARGET_MASQUERADE=m +CONFIG_IP_NF_TARGET_NETMAP=m @@ -65350,7 +65698,7 @@ index 18969cbd4bb1..0cec77182970 100644 obj-$(CONFIG_COMMON_CLK_S2MPS11) += clk-s2mps11.o obj-$(CONFIG_COMMON_CLK_SCMI) += clk-scmi.o diff --git a/drivers/clk/bcm/clk-bcm2835.c b/drivers/clk/bcm/clk-bcm2835.c -index fb04734afc80..eecb2daa423f 100644 +index fb04734afc80..6b6f77ba0a79 100644 --- a/drivers/clk/bcm/clk-bcm2835.c +++ b/drivers/clk/bcm/clk-bcm2835.c @@ -36,6 +36,7 @@ @@ -65361,7 +65709,15 @@ index fb04734afc80..eecb2daa423f 100644 #define CM_PASSWORD 0x5a000000 -@@ -296,6 +297,8 @@ +@@ -106,6 +107,7 @@ + #define CM_UARTDIV 0x0f4 + #define CM_VECCTL 0x0f8 + #define CM_VECDIV 0x0fc ++#define CM_DSI0HSCK 0x120 + #define CM_PULSECTL 0x190 + #define CM_PULSEDIV 0x194 + #define CM_SDCCTL 0x1a8 +@@ -296,6 +298,8 @@ #define SOC_BCM2711 BIT(1) #define SOC_ALL (SOC_BCM2835 | SOC_BCM2711) @@ -65370,7 +65726,7 @@ index fb04734afc80..eecb2daa423f 100644 /* * Names of clocks used within the driver that need to be replaced * with an external parent's name. This array is in the order that -@@ -314,6 +317,7 @@ static const char *const cprman_parent_names[] = { +@@ -314,6 +318,7 @@ static const char *const cprman_parent_names[] = { struct bcm2835_cprman { struct device *dev; void __iomem *regs; @@ -65378,7 +65734,7 @@ index fb04734afc80..eecb2daa423f 100644 spinlock_t regs_lock; /* spinlock for all clocks */ unsigned int soc; -@@ -643,15 +647,17 @@ static int bcm2835_pll_on(struct clk_hw *hw) +@@ -643,15 +648,17 @@ static int bcm2835_pll_on(struct clk_hw *hw) spin_unlock(&cprman->regs_lock); /* Wait for the PLL to lock. */ @@ -65404,7 +65760,7 @@ index fb04734afc80..eecb2daa423f 100644 } cprman_write(cprman, data->a2w_ctrl_reg, -@@ -1039,6 +1045,30 @@ static unsigned long bcm2835_clock_get_rate(struct clk_hw *hw, +@@ -1039,6 +1046,30 @@ static unsigned long bcm2835_clock_get_rate(struct clk_hw *hw, return rate; } @@ -65435,7 +65791,7 @@ index fb04734afc80..eecb2daa423f 100644 static void bcm2835_clock_wait_busy(struct bcm2835_clock *clock) { struct bcm2835_cprman *cprman = clock->cprman; -@@ -1097,8 +1127,10 @@ static int bcm2835_clock_on(struct clk_hw *hw) +@@ -1097,8 +1128,10 @@ static int bcm2835_clock_on(struct clk_hw *hw) return 0; } @@ -65448,7 +65804,7 @@ index fb04734afc80..eecb2daa423f 100644 { struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); struct bcm2835_cprman *cprman = clock->cprman; -@@ -1108,15 +1140,24 @@ static int bcm2835_clock_set_rate(struct clk_hw *hw, +@@ -1108,15 +1141,24 @@ static int bcm2835_clock_set_rate(struct clk_hw *hw, spin_lock(&cprman->regs_lock); @@ -65481,7 +65837,7 @@ index fb04734afc80..eecb2daa423f 100644 ctl |= (div & CM_DIV_FRAC_MASK) ? CM_FRAC : 0; cprman_write(cprman, data->ctl_reg, ctl); -@@ -1127,6 +1168,12 @@ static int bcm2835_clock_set_rate(struct clk_hw *hw, +@@ -1127,6 +1169,12 @@ static int bcm2835_clock_set_rate(struct clk_hw *hw, return 0; } @@ -65494,7 +65850,7 @@ index fb04734afc80..eecb2daa423f 100644 static bool bcm2835_clk_is_pllc(struct clk_hw *hw) { -@@ -1310,6 +1357,7 @@ static const struct clk_ops bcm2835_clock_clk_ops = { +@@ -1310,6 +1358,7 @@ static const struct clk_ops bcm2835_clock_clk_ops = { .unprepare = bcm2835_clock_off, .recalc_rate = bcm2835_clock_get_rate, .set_rate = bcm2835_clock_set_rate, @@ -65502,7 +65858,7 @@ index fb04734afc80..eecb2daa423f 100644 .determine_rate = bcm2835_clock_determine_rate, .set_parent = bcm2835_clock_set_parent, .get_parent = bcm2835_clock_get_parent, -@@ -1327,7 +1375,7 @@ static int bcm2835_vpu_clock_is_on(struct clk_hw *hw) +@@ -1327,7 +1376,7 @@ static int bcm2835_vpu_clock_is_on(struct clk_hw *hw) */ static const struct clk_ops bcm2835_vpu_clock_clk_ops = { .is_prepared = bcm2835_vpu_clock_is_on, @@ -65511,7 +65867,7 @@ index fb04734afc80..eecb2daa423f 100644 .set_rate = bcm2835_clock_set_rate, .determine_rate = bcm2835_clock_determine_rate, .set_parent = bcm2835_clock_set_parent, -@@ -1335,6 +1383,8 @@ static const struct clk_ops bcm2835_vpu_clock_clk_ops = { +@@ -1335,6 +1384,8 @@ static const struct clk_ops bcm2835_vpu_clock_clk_ops = { .debug_init = bcm2835_clock_debug_init, }; @@ -65520,7 +65876,7 @@ index fb04734afc80..eecb2daa423f 100644 static struct clk_hw *bcm2835_register_pll(struct bcm2835_cprman *cprman, const void *data) { -@@ -1352,6 +1402,9 @@ static struct clk_hw *bcm2835_register_pll(struct bcm2835_cprman *cprman, +@@ -1352,6 +1403,9 @@ static struct clk_hw *bcm2835_register_pll(struct bcm2835_cprman *cprman, init.ops = &bcm2835_pll_clk_ops; init.flags = pll_data->flags | CLK_IGNORE_UNUSED; @@ -65530,7 +65886,7 @@ index fb04734afc80..eecb2daa423f 100644 pll = kzalloc(sizeof(*pll), GFP_KERNEL); if (!pll) return NULL; -@@ -1407,6 +1460,13 @@ bcm2835_register_pll_divider(struct bcm2835_cprman *cprman, +@@ -1407,6 +1461,13 @@ bcm2835_register_pll_divider(struct bcm2835_cprman *cprman, divider->div.hw.init = &init; divider->div.table = NULL; @@ -65544,7 +65900,7 @@ index fb04734afc80..eecb2daa423f 100644 divider->cprman = cprman; divider->data = divider_data; -@@ -1460,6 +1520,15 @@ static struct clk_hw *bcm2835_register_clock(struct bcm2835_cprman *cprman, +@@ -1460,6 +1521,15 @@ static struct clk_hw *bcm2835_register_clock(struct bcm2835_cprman *cprman, init.name = clock_data->name; init.flags = clock_data->flags | CLK_IGNORE_UNUSED; @@ -65560,7 +65916,7 @@ index fb04734afc80..eecb2daa423f 100644 /* * Pass the CLK_SET_RATE_PARENT flag if we are allowed to propagate * rate changes on at least of the parents. -@@ -1471,7 +1540,6 @@ static struct clk_hw *bcm2835_register_clock(struct bcm2835_cprman *cprman, +@@ -1471,7 +1541,6 @@ static struct clk_hw *bcm2835_register_clock(struct bcm2835_cprman *cprman, init.ops = &bcm2835_vpu_clock_clk_ops; } else { init.ops = &bcm2835_clock_clk_ops; @@ -65568,7 +65924,7 @@ index fb04734afc80..eecb2daa423f 100644 /* If the clock wasn't actually enabled at boot, it's not * critical. -@@ -1696,16 +1764,12 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { +@@ -1696,16 +1765,12 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { .hold_mask = CM_PLLA_HOLDCORE, .fixed_divider = 1, .flags = CLK_SET_RATE_PARENT), @@ -65591,7 +65947,7 @@ index fb04734afc80..eecb2daa423f 100644 [BCM2835_PLLA_DSI0] = REGISTER_PLL_DIV( SOC_ALL, .name = "plla_dsi0", -@@ -2006,14 +2070,12 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { +@@ -2006,14 +2071,12 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { .int_bits = 6, .frac_bits = 0, .tcnt_mux = 3), @@ -65612,7 +65968,7 @@ index fb04734afc80..eecb2daa423f 100644 /* * VPU clock. This doesn't have an enable bit, since it drives * the bus for everything else, and is special so it doesn't need -@@ -2176,21 +2238,6 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { +@@ -2176,21 +2239,6 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { .tcnt_mux = 28, .round_up = true), @@ -65634,7 +65990,7 @@ index fb04734afc80..eecb2daa423f 100644 /* dsi clocks */ [BCM2835_CLOCK_DSI0E] = REGISTER_PER_CLK( SOC_ALL, -@@ -2240,6 +2287,8 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { +@@ -2240,6 +2288,8 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { .ctl_reg = CM_PERIICTL), }; @@ -65643,7 +65999,7 @@ index fb04734afc80..eecb2daa423f 100644 /* * Permanently take a reference on the parent of the SDRAM clock. * -@@ -2259,6 +2308,21 @@ static int bcm2835_mark_sdc_parent_critical(struct clk *sdc) +@@ -2259,6 +2309,21 @@ static int bcm2835_mark_sdc_parent_critical(struct clk *sdc) return clk_prepare_enable(parent); } @@ -65665,7 +66021,7 @@ index fb04734afc80..eecb2daa423f 100644 static int bcm2835_clk_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; -@@ -2267,7 +2331,9 @@ static int bcm2835_clk_probe(struct platform_device *pdev) +@@ -2267,7 +2332,9 @@ static int bcm2835_clk_probe(struct platform_device *pdev) const struct bcm2835_clk_desc *desc; const size_t asize = ARRAY_SIZE(clk_desc_array); const struct cprman_plat_data *pdata; @@ -65675,10 +66031,13 @@ index fb04734afc80..eecb2daa423f 100644 int ret; pdata = of_device_get_match_data(&pdev->dev); -@@ -2286,6 +2352,21 @@ static int bcm2835_clk_probe(struct platform_device *pdev) +@@ -2286,6 +2353,24 @@ static int bcm2835_clk_probe(struct platform_device *pdev) if (IS_ERR(cprman->regs)) return PTR_ERR(cprman->regs); ++ /* Mux DSI0 clock to PLLD */ ++ cprman_write(cprman, CM_DSI0HSCK, 1); ++ + fw_node = of_parse_phandle(dev->of_node, "firmware", 0); + if (fw_node) { + struct rpi_firmware *fw = rpi_firmware_get(fw_node); @@ -65697,7 +66056,7 @@ index fb04734afc80..eecb2daa423f 100644 memcpy(cprman->real_parent_names, cprman_parent_names, sizeof(cprman_parent_names)); of_clk_parent_fill(dev->of_node, cprman->real_parent_names, -@@ -2319,8 +2400,15 @@ static int bcm2835_clk_probe(struct platform_device *pdev) +@@ -2319,8 +2404,15 @@ static int bcm2835_clk_probe(struct platform_device *pdev) if (ret) return ret; @@ -65714,7 +66073,7 @@ index fb04734afc80..eecb2daa423f 100644 } static const struct cprman_plat_data cprman_bcm2835_plat_data = { -@@ -2346,7 +2434,15 @@ static struct platform_driver bcm2835_clk_driver = { +@@ -2346,7 +2438,15 @@ static struct platform_driver bcm2835_clk_driver = { .probe = bcm2835_clk_probe, }; @@ -70825,7 +71184,7 @@ index 0807fb9eb262..e159f976a6b1 100644 MODULE_ALIAS("platform:bcm2835-dma"); MODULE_DESCRIPTION("BCM2835 DMA engine driver"); diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c -index dd02f84e404d..5874620bf7ed 100644 +index dd02f84e404d..43053530aa0b 100644 --- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c +++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c @@ -12,6 +12,7 @@ @@ -71047,7 +71406,17 @@ index dd02f84e404d..5874620bf7ed 100644 llp = desc->hw_desc[0].llp; /* Managed transfer list */ -@@ -849,6 +930,8 @@ dw_axi_dma_chan_prep_slave_sg(struct dma_chan *dchan, struct scatterlist *sgl, +@@ -835,6 +916,9 @@ dw_axi_dma_chan_prep_slave_sg(struct dma_chan *dchan, struct scatterlist *sgl, + mem = sg_dma_address(sg); + len = sg_dma_len(sg); + num_segments = DIV_ROUND_UP(sg_dma_len(sg), axi_block_len); ++ if (!num_segments) ++ continue; ++ + segment_len = DIV_ROUND_UP(sg_dma_len(sg), num_segments); + + do { +@@ -849,6 +933,8 @@ dw_axi_dma_chan_prep_slave_sg(struct dma_chan *dchan, struct scatterlist *sgl, } while (len >= segment_len); } @@ -71056,7 +71425,7 @@ index dd02f84e404d..5874620bf7ed 100644 /* Set end-of-link to the last link descriptor of list */ set_desc_last(&desc->hw_desc[num_sgs - 1]); -@@ -956,6 +1039,8 @@ dma_chan_prep_dma_memcpy(struct dma_chan *dchan, dma_addr_t dst_adr, +@@ -956,6 +1042,8 @@ dma_chan_prep_dma_memcpy(struct dma_chan *dchan, dma_addr_t dst_adr, num++; } @@ -71065,7 +71434,7 @@ index dd02f84e404d..5874620bf7ed 100644 /* Set end-of-link to the last link descriptor of list */ set_desc_last(&desc->hw_desc[num - 1]); /* Managed transfer list */ -@@ -1004,7 +1089,7 @@ static void axi_chan_dump_lli(struct axi_dma_chan *chan, +@@ -1004,7 +1092,7 @@ static void axi_chan_dump_lli(struct axi_dma_chan *chan, static void axi_chan_list_dump_lli(struct axi_dma_chan *chan, struct axi_dma_desc *desc_head) { @@ -71074,7 +71443,7 @@ index dd02f84e404d..5874620bf7ed 100644 int i; for (i = 0; i < count; i++) -@@ -1047,11 +1132,11 @@ static noinline void axi_chan_handle_err(struct axi_dma_chan *chan, u32 status) +@@ -1047,11 +1135,11 @@ static noinline void axi_chan_handle_err(struct axi_dma_chan *chan, u32 status) static void axi_chan_block_xfer_complete(struct axi_dma_chan *chan) { @@ -71087,7 +71456,7 @@ index dd02f84e404d..5874620bf7ed 100644 u64 llp; int i; -@@ -1073,6 +1158,7 @@ static void axi_chan_block_xfer_complete(struct axi_dma_chan *chan) +@@ -1073,6 +1161,7 @@ static void axi_chan_block_xfer_complete(struct axi_dma_chan *chan) if (chan->cyclic) { desc = vd_to_axi_desc(vd); if (desc) { @@ -71095,7 +71464,7 @@ index dd02f84e404d..5874620bf7ed 100644 llp = lo_hi_readq(chan->chan_regs + CH_LLP); for (i = 0; i < count; i++) { hw_desc = &desc->hw_desc[i]; -@@ -1325,6 +1411,10 @@ static int parse_device_properties(struct axi_dma_chip *chip) +@@ -1325,6 +1414,10 @@ static int parse_device_properties(struct axi_dma_chip *chip) chip->dw->hdata->nr_masters = tmp; @@ -73427,10 +73796,62 @@ index 3e6a4e2044c0..b1c5ef817598 100644 Driver for display connectors with support for DDC and hot-plug detection. Most display controllers handle display connectors diff --git a/drivers/gpu/drm/bridge/tc358762.c b/drivers/gpu/drm/bridge/tc358762.c -index 46198af9eebb..8b856bc2ed5b 100644 +index 46198af9eebb..3f6db0f66812 100644 --- a/drivers/gpu/drm/bridge/tc358762.c +++ b/drivers/gpu/drm/bridge/tc358762.c -@@ -294,7 +294,7 @@ static int tc358762_probe(struct mipi_dsi_device *dsi) +@@ -53,6 +53,12 @@ + #define LCDCTRL_VSPOL BIT(19) /* Polarity of VSYNC signal */ + #define LCDCTRL_VSDELAY(v) (((v) & 0xfff) << 20) /* VSYNC delay */ + ++/* First parameter is in the 16bits, second is in the top 16bits */ ++#define LCD_HS_HBP 0x0424 ++#define LCD_HDISP_HFP 0x0428 ++#define LCD_VS_VBP 0x042c ++#define LCD_VDISP_VFP 0x0430 ++ + /* SPI Master Registers */ + #define SPICMR 0x0450 + #define SPITCR 0x0454 +@@ -139,6 +145,15 @@ static int tc358762_init(struct tc358762 *ctx) + tc358762_write(ctx, LCDCTRL, lcdctrl); + + tc358762_write(ctx, SYSCTRL, 0x040f); ++ ++ tc358762_write(ctx, LCD_HS_HBP, (ctx->mode.hsync_end - ctx->mode.hsync_start) | ++ ((ctx->mode.htotal - ctx->mode.hsync_end) << 16)); ++ tc358762_write(ctx, LCD_HDISP_HFP, ctx->mode.hdisplay | ++ ((ctx->mode.hsync_start - ctx->mode.hdisplay) << 16)); ++ tc358762_write(ctx, LCD_VS_VBP, (ctx->mode.vsync_end - ctx->mode.vsync_start) | ++ ((ctx->mode.vtotal - ctx->mode.vsync_end) << 16)); ++ tc358762_write(ctx, LCD_VDISP_VFP, ctx->mode.vdisplay | ++ ((ctx->mode.vsync_start - ctx->mode.vdisplay) << 16)); + msleep(100); + + tc358762_write(ctx, PPI_STARTPPI, PPI_START_FUNCTION); +@@ -185,14 +200,6 @@ static void tc358762_pre_enable(struct drm_bridge *bridge, struct drm_bridge_sta + usleep_range(5000, 10000); + } + +- ctx->pre_enabled = true; +-} +- +-static void tc358762_enable(struct drm_bridge *bridge, struct drm_bridge_state *state) +-{ +- struct tc358762 *ctx = bridge_to_tc358762(bridge); +- int ret; +- + ret = tc358762_init(ctx); + if (ret < 0) + dev_err(ctx->dev, "error initializing bridge (%d)\n", ret); +@@ -219,7 +226,6 @@ static void tc358762_bridge_mode_set(struct drm_bridge *bridge, + static const struct drm_bridge_funcs tc358762_bridge_funcs = { + .atomic_post_disable = tc358762_post_disable, + .atomic_pre_enable = tc358762_pre_enable, +- .atomic_enable = tc358762_enable, + .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, + .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, + .atomic_reset = drm_atomic_helper_bridge_reset, +@@ -294,7 +300,7 @@ static int tc358762_probe(struct mipi_dsi_device *dsi) ret = mipi_dsi_attach(dsi); if (ret < 0) { drm_bridge_remove(&ctx->bridge); @@ -73630,7 +74051,7 @@ index d021497841b8..973c6aeff8a1 100644 * drm_color_lut_check - check validity of lookup table * @lut: property blob containing LUT to check diff --git a/drivers/gpu/drm/drm_connector.c b/drivers/gpu/drm/drm_connector.c -index c44d5bcf1284..75ce5af3502b 100644 +index c44d5bcf1284..fa125167c018 100644 --- a/drivers/gpu/drm/drm_connector.c +++ b/drivers/gpu/drm/drm_connector.c @@ -33,6 +33,7 @@ @@ -73755,6 +74176,24 @@ index c44d5bcf1284..75ce5af3502b 100644 * Drivers can set up this property by calling * drm_mode_create_tv_properties(). */ +@@ -2637,10 +2697,15 @@ int drm_connector_set_orientation_from_panel( + { + enum drm_panel_orientation orientation; + +- if (panel && panel->funcs && panel->funcs->get_orientation) ++ if (panel && panel->funcs && panel->funcs->get_orientation) { + orientation = panel->funcs->get_orientation(panel); +- else ++ } else { + orientation = DRM_MODE_PANEL_ORIENTATION_UNKNOWN; ++ if (panel) { ++ of_drm_get_panel_orientation(panel->dev->of_node, ++ &orientation); ++ } ++ } + + return drm_connector_set_panel_orientation(connector, orientation); + } diff --git a/drivers/gpu/drm/drm_fb_helper.c b/drivers/gpu/drm/drm_fb_helper.c index d612133e2cf7..7d4ed1530ac2 100644 --- a/drivers/gpu/drm/drm_fb_helper.c @@ -75666,7 +76105,7 @@ index 4618c892cdd6..4c418962aa9b 100644 /* Look up the DSI host. It needs to probe before we do. */ endpoint = of_graph_get_next_endpoint(dev->of_node, NULL); diff --git a/drivers/gpu/drm/panel/panel-simple.c b/drivers/gpu/drm/panel/panel-simple.c -index 51f838befb32..035ee7a2f8a0 100644 +index 51f838befb32..0d436f0ec197 100644 --- a/drivers/gpu/drm/panel/panel-simple.c +++ b/drivers/gpu/drm/panel/panel-simple.c @@ -40,6 +40,7 @@ @@ -75699,19 +76138,28 @@ index 51f838befb32..035ee7a2f8a0 100644 return num; } -@@ -439,9 +432,9 @@ static int panel_simple_get_timings(struct drm_panel *panel, - - static enum drm_panel_orientation panel_simple_get_orientation(struct drm_panel *panel) - { -- struct panel_simple *p = to_panel_simple(panel); -+ //struct panel_simple *p = to_panel_simple(panel); - -- return p->orientation; -+ return DRM_MODE_PANEL_ORIENTATION_UNKNOWN; +@@ -437,20 +430,12 @@ static int panel_simple_get_timings(struct drm_panel *panel, + return p->desc->num_timings; } +-static enum drm_panel_orientation panel_simple_get_orientation(struct drm_panel *panel) +-{ +- struct panel_simple *p = to_panel_simple(panel); +- +- return p->orientation; +-} +- static const struct drm_panel_funcs panel_simple_funcs = { -@@ -487,6 +480,7 @@ static int panel_dpi_probe(struct device *dev, + .disable = panel_simple_disable, + .unprepare = panel_simple_unprepare, + .prepare = panel_simple_prepare, + .enable = panel_simple_enable, + .get_modes = panel_simple_get_modes, +- .get_orientation = panel_simple_get_orientation, + .get_timings = panel_simple_get_timings, + }; + +@@ -487,6 +472,7 @@ static int panel_dpi_probe(struct device *dev, of_property_read_u32(np, "width-mm", &desc->size.width); of_property_read_u32(np, "height-mm", &desc->size.height); @@ -75719,7 +76167,7 @@ index 51f838befb32..035ee7a2f8a0 100644 /* Extract bus_flags from display_timing */ bus_flags = 0; -@@ -496,6 +490,8 @@ static int panel_dpi_probe(struct device *dev, +@@ -496,6 +482,8 @@ static int panel_dpi_probe(struct device *dev, /* We do not know the connector for the DT node, so guess it */ desc->connector_type = DRM_MODE_CONNECTOR_DPI; @@ -75728,7 +76176,7 @@ index 51f838befb32..035ee7a2f8a0 100644 panel->desc = desc; -@@ -575,12 +571,6 @@ static int panel_simple_probe(struct device *dev, const struct panel_desc *desc) +@@ -575,12 +563,6 @@ static int panel_simple_probe(struct device *dev, const struct panel_desc *desc) return dev_err_probe(dev, PTR_ERR(panel->enable_gpio), "failed to request GPIO\n"); @@ -75741,7 +76189,7 @@ index 51f838befb32..035ee7a2f8a0 100644 ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0); if (ddc) { panel->ddc = of_find_i2c_adapter_by_node(ddc); -@@ -2032,6 +2022,32 @@ static const struct panel_desc friendlyarm_hd702e = { +@@ -2032,6 +2014,32 @@ static const struct panel_desc friendlyarm_hd702e = { }, }; @@ -75774,7 +76222,7 @@ index 51f838befb32..035ee7a2f8a0 100644 static const struct drm_display_mode giantplus_gpg482739qs5_mode = { .clock = 9000, .hdisplay = 480, -@@ -2212,6 +2228,38 @@ static const struct panel_desc innolux_at043tn24 = { +@@ -2212,6 +2220,38 @@ static const struct panel_desc innolux_at043tn24 = { .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE, }; @@ -75813,20 +76261,20 @@ index 51f838befb32..035ee7a2f8a0 100644 static const struct drm_display_mode innolux_at070tn92_mode = { .clock = 33333, .hdisplay = 800, -@@ -3372,6 +3420,31 @@ static const struct panel_desc rocktech_rk043fn48h = { +@@ -3372,6 +3412,31 @@ static const struct panel_desc rocktech_rk043fn48h = { .connector_type = DRM_MODE_CONNECTOR_DPI, }; +static const struct drm_display_mode raspberrypi_7inch_mode = { -+ .clock = 27777, ++ .clock = 30000, + .hdisplay = 800, -+ .hsync_start = 800 + 59, -+ .hsync_end = 800 + 59 + 2, -+ .htotal = 800 + 59 + 2 + 46, ++ .hsync_start = 800 + 131, ++ .hsync_end = 800 + 131 + 2, ++ .htotal = 800 + 131 + 2 + 45, + .vdisplay = 480, + .vsync_start = 480 + 7, + .vsync_end = 480 + 7 + 2, -+ .vtotal = 480 + 7 + 2 + 21, ++ .vtotal = 480 + 7 + 2 + 22, + .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC, +}; + @@ -75845,7 +76293,7 @@ index 51f838befb32..035ee7a2f8a0 100644 static const struct display_timing rocktech_rk070er9427_timing = { .pixelclock = { 26400000, 33300000, 46800000 }, .hactive = { 800, 800, 800 }, -@@ -4269,6 +4342,9 @@ static const struct of_device_id platform_of_match[] = { +@@ -4269,6 +4334,9 @@ static const struct of_device_id platform_of_match[] = { }, { .compatible = "friendlyarm,hd702e", .data = &friendlyarm_hd702e, @@ -75855,7 +76303,7 @@ index 51f838befb32..035ee7a2f8a0 100644 }, { .compatible = "giantplus,gpg482739qs5", .data = &giantplus_gpg482739qs5 -@@ -4290,6 +4366,9 @@ static const struct of_device_id platform_of_match[] = { +@@ -4290,6 +4358,9 @@ static const struct of_device_id platform_of_match[] = { }, { .compatible = "innolux,at043tn24", .data = &innolux_at043tn24, @@ -75865,7 +76313,7 @@ index 51f838befb32..035ee7a2f8a0 100644 }, { .compatible = "innolux,at070tn92", .data = &innolux_at070tn92, -@@ -4422,6 +4501,9 @@ static const struct of_device_id platform_of_match[] = { +@@ -4422,6 +4493,9 @@ static const struct of_device_id platform_of_match[] = { }, { .compatible = "rocktech,rk043fn48h", .data = &rocktech_rk043fn48h, @@ -75875,7 +76323,7 @@ index 51f838befb32..035ee7a2f8a0 100644 }, { .compatible = "rocktech,rk070er9427", .data = &rocktech_rk070er9427, -@@ -4776,6 +4858,9 @@ static const struct panel_desc_dsi osd101t2045_53ts = { +@@ -4776,6 +4850,9 @@ static const struct panel_desc_dsi osd101t2045_53ts = { .lanes = 4, }; @@ -75885,7 +76333,7 @@ index 51f838befb32..035ee7a2f8a0 100644 static const struct of_device_id dsi_of_match[] = { { .compatible = "auo,b080uan01", -@@ -4798,21 +4883,138 @@ static const struct of_device_id dsi_of_match[] = { +@@ -4798,21 +4875,138 @@ static const struct of_device_id dsi_of_match[] = { }, { .compatible = "osddisplays,osd101t2045-53ts", .data = &osd101t2045_53ts @@ -78407,10 +78855,10 @@ index 000000000000..cd328b98d4da +} diff --git a/drivers/gpu/drm/rp1/rp1-dpi/rp1_dpi_hw.c b/drivers/gpu/drm/rp1/rp1-dpi/rp1_dpi_hw.c new file mode 100644 -index 000000000000..c4aaa57f07dd +index 000000000000..5b90c69d696a --- /dev/null +++ b/drivers/gpu/drm/rp1/rp1-dpi/rp1_dpi_hw.c -@@ -0,0 +1,486 @@ +@@ -0,0 +1,492 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * DRM Driver for DPI output on Raspberry Pi RP1 @@ -78732,8 +79180,14 @@ index 000000000000..c4aaa57f07dd + *shift |= OSHIFT_RGB(29, 19, 9); + return OMASK_RGB(0x3fc, 0x3fc, 0x3fc); + ++ case MEDIA_BUS_FMT_RGB565_1X24_CPADHI: ++ /* This should match Raspberry Pi legacy "mode 3" */ ++ *shift |= OSHIFT_RGB(26, 17, 6); ++ *rgbsz &= DPI_DMA_RGBSZ_BPP_MASK; ++ return OMASK_RGB(0x3e0, 0x3f0, 0x3e0); ++ + default: -+ /* RGB666_1x24_CPADHI, BGR666_1X24_CPADHI and "RGB565_666" formats */ ++ /* RGB666_1x24_CPADHI, BGR666_1X24_CPADHI and "mode 4" formats */ + *shift |= OSHIFT_RGB(27, 17, 7); + *rgbsz &= DPI_DMA_RGBSZ_BPP_MASK; + return OMASK_RGB(0x3f0, 0x3f0, 0x3f0); @@ -80020,10 +80474,10 @@ index 000000000000..85bb0615bae9 +} diff --git a/drivers/gpu/drm/rp1/rp1-dsi/rp1_dsi_dsi.c b/drivers/gpu/drm/rp1/rp1-dsi/rp1_dsi_dsi.c new file mode 100644 -index 000000000000..f6fefa4acb3b +index 000000000000..7935e00720f3 --- /dev/null +++ b/drivers/gpu/drm/rp1/rp1-dsi/rp1_dsi_dsi.c -@@ -0,0 +1,1504 @@ +@@ -0,0 +1,1513 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * DRM Driver for DSI output on Raspberry Pi RP1 @@ -81362,10 +81816,17 @@ index 000000000000..f6fefa4acb3b + return 0x005; +} + ++/* Maximum frequency for LP escape clock (20MHz), and some magic numbers */ ++#define RP1DSI_ESC_CLK_KHZ 20000 ++#define RP1DSI_TO_CLK_DIV 5 ++#define RP1DSI_HSTX_TO_MIN 0x200 ++#define RP1DSI_LPRX_TO_VAL 0x400 ++#define RP1DSI_BTA_TO_VAL 0xd00 ++ +void rp1dsi_dsi_setup(struct rp1_dsi *dsi, struct drm_display_mode const *mode) +{ + u32 timeout, mask, vid_mode_cfg; -+ u32 freq_khz; ++ int lane_kbps; + unsigned int bpp = mipi_dsi_pixel_format_to_bpp(dsi->display_format); + + DSI_WRITE(DSI_PHY_IF_CFG, dsi->lanes - 1); @@ -81375,28 +81836,33 @@ index 000000000000..f6fefa4acb3b + /* a conservative guess (LP escape is slow!) */ + DSI_WRITE(DSI_DPI_LP_CMD_TIM, 0x00100000); + -+ /* Drop to LP where possible */ ++ /* Drop to LP where possible; use LP Escape for all commands */ + vid_mode_cfg = 0xbf00; + if (!(dsi->display_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)) + vid_mode_cfg |= 0x01; + if (dsi->display_flags & MIPI_DSI_MODE_VIDEO_BURST) + vid_mode_cfg |= 0x02; + DSI_WRITE(DSI_VID_MODE_CFG, vid_mode_cfg); -+ -+ /* Use LP Escape Data signalling for all commands */ + DSI_WRITE(DSI_CMD_MODE_CFG, 0x10F7F00); ++ + /* Select Command Mode */ + DSI_WRITE(DSI_MODE_CFG, 1); -+ /* XXX magic number */ -+ DSI_WRITE(DSI_TO_CNT_CFG, 0x02000200); -+ /* XXX magic number */ -+ DSI_WRITE(DSI_BTA_TO_CNT, 0x800); + ++ /* Set timeouts and clock dividers */ ++ DSI_WRITE(DSI_TO_CNT_CFG, ++ (max((bpp * mode->htotal) / (7 * RP1DSI_TO_CLK_DIV * dsi->lanes), ++ RP1DSI_HSTX_TO_MIN) << 16) | ++ RP1DSI_LPRX_TO_VAL); ++ DSI_WRITE(DSI_BTA_TO_CNT, RP1DSI_BTA_TO_VAL); ++ lane_kbps = (bpp * mode->clock) / dsi->lanes; ++ DSI_WRITE(DSI_CLKMGR_CFG, ++ (RP1DSI_TO_CLK_DIV << 8) | ++ max(2, lane_kbps / (8 * RP1DSI_ESC_CLK_KHZ) + 1)); ++ ++ /* Configure video timings */ + DSI_WRITE(DSI_VID_PKT_SIZE, mode->hdisplay); + DSI_WRITE(DSI_VID_NUM_CHUNKS, 0); + DSI_WRITE(DSI_VID_NULL_SIZE, 0); -+ -+ /* Note, unlike Argon firmware, here we DON'T consider sync to be concurrent with porch */ + DSI_WRITE(DSI_VID_HSA_TIME, + (bpp * (mode->hsync_end - mode->hsync_start)) / (8 * dsi->lanes)); + DSI_WRITE(DSI_VID_HBP_TIME, @@ -81407,9 +81873,8 @@ index 000000000000..f6fefa4acb3b + DSI_WRITE(DSI_VID_VFP_LINES, (mode->vsync_start - mode->vdisplay)); + DSI_WRITE(DSI_VID_VACTIVE_LINES, mode->vdisplay); + -+ freq_khz = (bpp * mode->clock) / dsi->lanes; -+ -+ dphy_init_khz(dsi, rp1dsi_refclk_freq(dsi) / 1000, freq_khz); ++ /* Init PHY */ ++ dphy_init_khz(dsi, rp1dsi_refclk_freq(dsi) / 1000, lane_kbps); + + DSI_WRITE(DSI_PHY_TMR_LPCLK_CFG, + (hsfreq_table[dsi->hsfreq_index].clk_lp2hs << DSI_PHY_TMR_LP2HS_LSB) | @@ -81418,8 +81883,6 @@ index 000000000000..f6fefa4acb3b + (hsfreq_table[dsi->hsfreq_index].data_lp2hs << DSI_PHY_TMR_LP2HS_LSB) | + (hsfreq_table[dsi->hsfreq_index].data_hs2lp << DSI_PHY_TMR_HS2LP_LSB)); + -+ DSI_WRITE(DSI_CLKMGR_CFG, 0x00000505); -+ + /* Wait for PLL lock */ + for (timeout = (1 << 14); timeout != 0; --timeout) { + usleep_range(10, 50); @@ -81558,10 +82021,10 @@ index 000000000000..7e941cad342e +obj-$(CONFIG_DRM_RP1_VEC) += drm-rp1-vec.o diff --git a/drivers/gpu/drm/rp1/rp1-vec/rp1_vec.c b/drivers/gpu/drm/rp1/rp1-vec/rp1_vec.c new file mode 100644 -index 000000000000..34a6033e3430 +index 000000000000..9d6cd17e8ac8 --- /dev/null +++ b/drivers/gpu/drm/rp1/rp1-vec/rp1_vec.c -@@ -0,0 +1,506 @@ +@@ -0,0 +1,602 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * DRM Driver for VEC output on Raspberry Pi RP1 @@ -81612,6 +82075,63 @@ index 000000000000..34a6033e3430 + +#include "rp1_vec.h" + ++/* ++ * Linux doesn't make it easy to create custom video modes for the console ++ * with non-CVT timings; so add a module parameter for it. The format is: ++ * ",,,,,,,,[,i]" ++ * (where each comma may be replaced by any sequence of punctuation). ++ * pclk should be 108000/n for 5 <= n <= 16 (twice this for "fake" modes). ++ */ ++ ++static char *rp1vec_cmode_str; ++module_param_named(cmode, rp1vec_cmode_str, charp, 0600); ++MODULE_PARM_DESC(cmode, "Custom video mode:\n" ++ "\t\t,,,,,,,,[,i]\n"); ++ ++static struct drm_display_mode *rp1vec_parse_custom_mode(struct drm_device *dev) ++{ ++ char const *p = rp1vec_cmode_str; ++ struct drm_display_mode *mode; ++ unsigned int n, vals[9]; ++ ++ if (!p) ++ return NULL; ++ ++ for (n = 0; n < 9; n++) { ++ unsigned int v = 0; ++ ++ if (!isdigit(*p)) ++ return NULL; ++ do { ++ v = 10u * v + (*p - '0'); ++ } while (isdigit(*++p)); ++ ++ vals[n] = v; ++ while (ispunct(*p)) ++ p++; ++ } ++ ++ mode = drm_mode_create(dev); ++ if (!mode) ++ return NULL; ++ ++ mode->clock = vals[0]; ++ mode->hdisplay = vals[1]; ++ mode->hsync_start = mode->hdisplay + vals[2]; ++ mode->hsync_end = mode->hsync_start + vals[3]; ++ mode->htotal = mode->hsync_end + vals[4]; ++ mode->vdisplay = vals[5]; ++ mode->vsync_start = mode->vdisplay + vals[6]; ++ mode->vsync_end = mode->vsync_start + vals[7]; ++ mode->vtotal = mode->vsync_end + vals[8]; ++ mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED; ++ mode->flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC; ++ if (strchr(p, 'i')) ++ mode->flags |= DRM_MODE_FLAG_INTERLACE; ++ ++ return mode; ++} ++ +static void rp1vec_pipe_update(struct drm_simple_display_pipe *pipe, + struct drm_plane_state *old_state) +{ @@ -81722,63 +82242,143 @@ index 000000000000..34a6033e3430 + drm_connector_cleanup(connector); +} + -+static const struct drm_display_mode rp1vec_modes[4] = { ++/* ++ * Check the mode roughly matches something we can generate. ++ * The choice of hardware TV mode depends on total lines and frame rate. ++ * Within each hardware mode, allow pixel clock, image size and offsets ++ * to vary, up to a maximum horizontal active period and line count. ++ * Don't check sync timings here: the HW driver will sanitize them. ++ */ ++ ++static enum drm_mode_status rp1vec_mode_valid(struct drm_device *dev, ++ const struct drm_display_mode *mode) ++{ ++ int prog = !(mode->flags & DRM_MODE_FLAG_INTERLACE); ++ int fake_31khz = prog && mode->vtotal >= 500; ++ int vtotal_2fld = mode->vtotal << (prog && !fake_31khz); ++ int vdisplay_2fld = mode->vdisplay << (prog && !fake_31khz); ++ int real_clock = mode->clock >> fake_31khz; ++ ++ /* Check pixel clock is in the permitted range */ ++ if (real_clock < 6750) ++ return MODE_CLOCK_LOW; ++ else if (real_clock > 21600) ++ return MODE_CLOCK_HIGH; ++ ++ /* Try to match against the 525-line 60Hz mode (System M) */ ++ if (vtotal_2fld >= 524 && vtotal_2fld <= 526 && vdisplay_2fld <= 486 && ++ mode->htotal * vtotal_2fld > 32 * real_clock && ++ mode->htotal * vtotal_2fld < 34 * real_clock && ++ 37 * mode->hdisplay <= 2 * real_clock) /* 54us */ ++ return MODE_OK; ++ ++ /* All other supported TV Systems (625-, 405-, 819-line) are 50Hz */ ++ if (mode->htotal * vtotal_2fld > 39 * real_clock && ++ mode->htotal * vtotal_2fld < 41 * real_clock) { ++ if (vtotal_2fld >= 624 && vtotal_2fld <= 626 && vdisplay_2fld <= 576 && ++ 37 * mode->hdisplay <= 2 * real_clock) /* 54us */ ++ return MODE_OK; ++ ++ if (vtotal_2fld == 405 && vdisplay_2fld <= 380 && ++ 49 * mode->hdisplay <= 4 * real_clock) /* 81.6us */ ++ return MODE_OK; ++ ++ if (vtotal_2fld == 819 && vdisplay_2fld <= 738 && ++ 25 * mode->hdisplay <= real_clock) /* 40us */ ++ return MODE_OK; ++ } ++ ++ return MODE_BAD; ++} ++ ++static const struct drm_display_mode rp1vec_modes[6] = { + { /* Full size 525/60i with Rec.601 pixel rate */ + DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, + 720, 720 + 16, 720 + 16 + 64, 858, 0, + 480, 480 + 6, 480 + 6 + 6, 525, 0, ++ DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | + DRM_MODE_FLAG_INTERLACE) + }, + { /* Cropped and horizontally squashed to be TV-safe */ + DRM_MODE("704x432i", DRM_MODE_TYPE_DRIVER, 15429, + 704, 704 + 76, 704 + 76 + 72, 980, 0, + 432, 432 + 30, 432 + 30 + 6, 525, 0, ++ DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | + DRM_MODE_FLAG_INTERLACE) + }, + { /* Full size 625/50i with Rec.601 pixel rate */ + DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, + 720, 720 + 12, 720 + 12 + 64, 864, 0, + 576, 576 + 5, 576 + 5 + 5, 625, 0, ++ DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | + DRM_MODE_FLAG_INTERLACE) + }, + { /* Cropped and squashed, for square(ish) pixels */ + DRM_MODE("704x512i", DRM_MODE_TYPE_DRIVER, 15429, + 704, 704 + 72, 704 + 72 + 72, 987, 0, + 512, 512 + 37, 512 + 37 + 5, 625, 0, ++ DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | ++ DRM_MODE_FLAG_INTERLACE) ++ }, ++ { /* System A (405 lines) */ ++ DRM_MODE("544x380i", DRM_MODE_TYPE_DRIVER, 6750, ++ 544, 544 + 12, 544 + 12 + 60, 667, 0, ++ 380, 380 + 0, 380 + 0 + 8, 405, 0, ++ DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | ++ DRM_MODE_FLAG_INTERLACE) ++ }, ++ { /* System E (819 lines) */ ++ DRM_MODE("848x738i", DRM_MODE_TYPE_DRIVER, 21600, ++ 848, 848 + 12, 848 + 12 + 54, 1055, 0, ++ 738, 738 + 6, 738 + 6 + 1, 819, 0, ++ DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | + DRM_MODE_FLAG_INTERLACE) + } +}; + +/* -+ * Advertise standard and preferred video modes. ++ * Advertise a custom mode, if specified; then those from the table above. ++ * From each interlaced mode above, derive a half-height progressive one. + * -+ * From each interlaced mode in the table above, derive a progressive one. ++ * This driver always supports all 525-line and 625-line standard modes ++ * regardless of connector's tv_mode; non-standard combinations generally ++ * default to PAL[-BDGHIK] or NTSC[-M] (with a special case for "PAL60"). + * -+ * This driver always supports all 50Hz and 60Hz video modes, regardless -+ * of connector's tv_mode; nonstandard combinations generally default -+ * to PAL[-BDGHIKL] or NTSC[-M] depending on resolution and field-rate -+ * (except that "PAL" with 525/60 will be implemented as "PAL60"). -+ * However, the preferred mode will depend on the default TV mode. ++ * The "vintage" standards (System A, System E) are advertised only when ++ * the default tv_mode was DRM_MODE_TV_MODE_MONOCHROME, and only interlaced. + */ + +static int rp1vec_connector_get_modes(struct drm_connector *connector) +{ -+ u64 val; -+ int i, prog, n = 0; -+ bool prefer625 = false; ++ u64 tvstd; ++ int i, prog, limit, n = 0, preferred_lines = 525; ++ struct drm_display_mode *mode; + + if (!drm_object_property_get_default_value(&connector->base, + connector->dev->mode_config.tv_mode_property, -+ &val)) -+ prefer625 = (val == DRM_MODE_TV_MODE_PAL || -+ val == DRM_MODE_TV_MODE_PAL_N || -+ val == DRM_MODE_TV_MODE_SECAM); ++ &tvstd)) ++ preferred_lines = (tvstd == DRM_MODE_TV_MODE_PAL || ++ tvstd == DRM_MODE_TV_MODE_PAL_N || ++ tvstd >= DRM_MODE_TV_MODE_SECAM) ? 625 : 525; + -+ for (i = 0; i < ARRAY_SIZE(rp1vec_modes); i++) { ++ mode = rp1vec_parse_custom_mode(connector->dev); ++ if (mode) { ++ if (rp1vec_mode_valid(connector->dev, mode) == 0) { ++ drm_mode_set_name(mode); ++ drm_mode_probed_add(connector, mode); ++ n++; ++ preferred_lines = 0; ++ } else { ++ drm_mode_destroy(connector->dev, mode); ++ } ++ } ++ ++ limit = (tvstd < DRM_MODE_TV_MODE_MONOCHROME) ? 4 : ARRAY_SIZE(rp1vec_modes); ++ for (i = 0; i < limit; i++) { + for (prog = 0; prog < 2; prog++) { -+ struct drm_display_mode *mode = -+ drm_mode_duplicate(connector->dev, -+ &rp1vec_modes[i]); ++ mode = drm_mode_duplicate(connector->dev, &rp1vec_modes[i]); ++ if (!mode) ++ return n; + + if (prog) { + mode->flags &= ~DRM_MODE_FLAG_INTERLACE; @@ -81786,15 +82386,15 @@ index 000000000000..34a6033e3430 + mode->vsync_start >>= 1; + mode->vsync_end >>= 1; + mode->vtotal >>= 1; -+ } -+ -+ if (mode->hdisplay == 704 && -+ mode->vtotal == (prefer625 ? 625 : 525)) ++ } else if (mode->hdisplay == 704 && mode->vtotal == preferred_lines) { + mode->type |= DRM_MODE_TYPE_PREFERRED; -+ ++ } + drm_mode_set_name(mode); + drm_mode_probed_add(connector, mode); + n++; ++ ++ if (mode->vtotal == 405 || mode->vtotal == 819) ++ break; /* Don't offer progressive for Systems A, E */ + } + } + @@ -81824,49 +82424,6 @@ index 000000000000..34a6033e3430 + return 0; +} + -+static enum drm_mode_status rp1vec_mode_valid(struct drm_device *dev, -+ const struct drm_display_mode *mode) -+{ -+ /* -+ * Check the mode roughly matches something we can generate. -+ * The hardware driver is very prescriptive about pixel clocks, -+ * line and frame durations, but we'll tolerate rounding errors. -+ * Within each hardware mode, allow image size and position to vary -+ * (to fine-tune overscan correction or emulate retro devices). -+ * Don't check sync timings here: the HW driver will sanitize them. -+ */ -+ -+ int prog = !(mode->flags & DRM_MODE_FLAG_INTERLACE); -+ int vtotal_full = mode->vtotal << prog; -+ int vdisplay_full = mode->vdisplay << prog; -+ -+ /* Reject very small frames */ -+ if (vtotal_full < 256 || mode->hdisplay < 256) -+ return MODE_BAD; -+ -+ /* Check lines, frame period (ms) and vertical size limit */ -+ if (vtotal_full >= 524 && vtotal_full <= 526 && -+ mode->htotal * vtotal_full > 33 * mode->clock && -+ mode->htotal * vtotal_full < 34 * mode->clock && -+ vdisplay_full <= 480) -+ goto vgood; -+ if (vtotal_full >= 624 && vtotal_full <= 626 && -+ mode->htotal * vtotal_full > 39 * mode->clock && -+ mode->htotal * vtotal_full < 41 * mode->clock && -+ vdisplay_full <= 576) -+ goto vgood; -+ return MODE_BAD; -+ -+vgood: -+ /* Check pixel rate (kHz) and horizontal size limit */ -+ if (mode->clock == 13500 && mode->hdisplay <= 720) -+ return MODE_OK; -+ if (mode->clock >= 15428 && mode->clock <= 15429 && -+ mode->hdisplay <= 800) -+ return MODE_OK; -+ return MODE_BAD; -+} -+ +static const struct drm_connector_helper_funcs rp1vec_connector_helper_funcs = { + .get_modes = rp1vec_connector_get_modes, + .atomic_check = rp1vec_connector_atomic_check, @@ -81974,10 +82531,12 @@ index 000000000000..34a6033e3430 + vec->drm.dev_private = vec; + platform_set_drvdata(pdev, &vec->drm); + -+ vec->drm.mode_config.max_width = 800; -+ vec->drm.mode_config.max_height = 576; ++ vec->drm.mode_config.min_width = 256; ++ vec->drm.mode_config.min_height = 128; ++ vec->drm.mode_config.max_width = 848; /* for System E */ ++ vec->drm.mode_config.max_height = 738; /* for System E */ + vec->drm.mode_config.preferred_depth = 32; -+ vec->drm.mode_config.prefer_shadow = 0; ++ vec->drm.mode_config.prefer_shadow = 0; + vec->drm.mode_config.quirk_addfb_prefer_host_byte_order = true; + vec->drm.mode_config.funcs = &rp1vec_mode_funcs; + drm_vblank_init(&vec->drm, 1); @@ -82070,10 +82629,10 @@ index 000000000000..34a6033e3430 +MODULE_AUTHOR("Nick Hollinghurst"); diff --git a/drivers/gpu/drm/rp1/rp1-vec/rp1_vec.h b/drivers/gpu/drm/rp1/rp1-vec/rp1_vec.h new file mode 100644 -index 000000000000..16ee80f18c9b +index 000000000000..ae283a25b0a4 --- /dev/null +++ b/drivers/gpu/drm/rp1/rp1-vec/rp1_vec.h -@@ -0,0 +1,69 @@ +@@ -0,0 +1,72 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * DRM Driver for DSI output on Raspberry Pi RP1 @@ -82097,12 +82656,15 @@ index 000000000000..16ee80f18c9b +#define RP1VEC_NUM_HW_BLOCKS 2 + +#define RP1VEC_SUPPORTED_TV_MODES \ -+ (BIT(DRM_MODE_TV_MODE_NTSC) | \ ++ (BIT(DRM_MODE_TV_MODE_NTSC) | \ + BIT(DRM_MODE_TV_MODE_NTSC_443) | \ -+ BIT(DRM_MODE_TV_MODE_NTSC_J) | \ -+ BIT(DRM_MODE_TV_MODE_PAL) | \ -+ BIT(DRM_MODE_TV_MODE_PAL_M) | \ -+ BIT(DRM_MODE_TV_MODE_PAL_N)) ++ BIT(DRM_MODE_TV_MODE_NTSC_J) | \ ++ BIT(DRM_MODE_TV_MODE_PAL) | \ ++ BIT(DRM_MODE_TV_MODE_PAL_M) | \ ++ BIT(DRM_MODE_TV_MODE_PAL_N) | \ ++ BIT(DRM_MODE_TV_MODE_MONOCHROME)) ++ ++#define RP1VEC_VDAC_KHZ 108000 + +/* ---------------------------------------------------------------------- */ + @@ -82121,7 +82683,7 @@ index 000000000000..16ee80f18c9b + /* Block (VCC, CFG) base addresses, and current state */ + void __iomem *hw_base[RP1VEC_NUM_HW_BLOCKS]; + u32 cur_fmt; -+ bool vec_running, pipe_enabled; ++ bool fake_31khz, vec_running, pipe_enabled; + struct completion finished; +}; + @@ -82130,8 +82692,8 @@ index 000000000000..16ee80f18c9b + +void rp1vec_hw_setup(struct rp1_vec *vec, + u32 in_format, -+ struct drm_display_mode const *mode, -+ int tvstd); ++ struct drm_display_mode const *mode, ++ int tvstd); +void rp1vec_hw_update(struct rp1_vec *vec, dma_addr_t addr, u32 offset, u32 stride); +void rp1vec_hw_stop(struct rp1_vec *vec); +int rp1vec_hw_busy(struct rp1_vec *vec); @@ -82659,10 +83221,10 @@ index 000000000000..241dedee5889 +} diff --git a/drivers/gpu/drm/rp1/rp1-vec/rp1_vec_hw.c b/drivers/gpu/drm/rp1/rp1-vec/rp1_vec_hw.c new file mode 100644 -index 000000000000..b9a67a8a330c +index 000000000000..3fb57f7d931c --- /dev/null +++ b/drivers/gpu/drm/rp1/rp1-vec/rp1_vec_hw.c -@@ -0,0 +1,508 @@ +@@ -0,0 +1,568 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * DRM Driver for VEC output on Raspberry Pi RP1 @@ -82683,11 +83245,18 @@ index 000000000000..b9a67a8a330c +#include "rp1_vec.h" +#include "vec_regs.h" + -+#define BITS(field, val) (((val) << (field ## _LSB)) & (field ## _BITS)) -+ ++#define BITS(field, val) (((val) << (field ## _LSB)) & (field ## _BITS)) +#define VEC_WRITE(reg, val) writel((val), vec->hw_base[RP1VEC_HW_BLOCK_VEC] + (reg ## _OFFSET)) +#define VEC_READ(reg) readl(vec->hw_base[RP1VEC_HW_BLOCK_VEC] + (reg ## _OFFSET)) + ++static void rp1vec_write_regs(struct rp1_vec *vec, u32 offset, u32 const *vals, u32 num) ++{ ++ while (num--) { ++ writel(*vals++, vec->hw_base[RP1VEC_HW_BLOCK_VEC] + offset); ++ offset += 4; ++ } ++} ++ +int rp1vec_hw_busy(struct rp1_vec *vec) +{ + /* Read the undocumented "pline_busy" flag */ @@ -82711,32 +83280,32 @@ index 000000000000..b9a67a8a330c + { + .format = DRM_FORMAT_XRGB8888, + .mask = MASK_RGB(0x3fc, 0x3fc, 0x3fc), -+ .shift = SHIFT_RGB(23, 15, 7), -+ .rgbsz = BITS(VEC_RGBSZ_BYTES_PER_PIXEL_MINUS1, 3), ++ .shift = SHIFT_RGB(23, 15, 7), ++ .rgbsz = BITS(VEC_RGBSZ_BYTES_PER_PIXEL_MINUS1, 3), + }, + { + .format = DRM_FORMAT_XBGR8888, + .mask = MASK_RGB(0x3fc, 0x3fc, 0x3fc), -+ .shift = SHIFT_RGB(7, 15, 23), -+ .rgbsz = BITS(VEC_RGBSZ_BYTES_PER_PIXEL_MINUS1, 3), ++ .shift = SHIFT_RGB(7, 15, 23), ++ .rgbsz = BITS(VEC_RGBSZ_BYTES_PER_PIXEL_MINUS1, 3), + }, + { + .format = DRM_FORMAT_RGB888, + .mask = MASK_RGB(0x3fc, 0x3fc, 0x3fc), -+ .shift = SHIFT_RGB(23, 15, 7), -+ .rgbsz = BITS(VEC_RGBSZ_BYTES_PER_PIXEL_MINUS1, 2), ++ .shift = SHIFT_RGB(23, 15, 7), ++ .rgbsz = BITS(VEC_RGBSZ_BYTES_PER_PIXEL_MINUS1, 2), + }, + { + .format = DRM_FORMAT_BGR888, + .mask = MASK_RGB(0x3fc, 0x3fc, 0x3fc), -+ .shift = SHIFT_RGB(7, 15, 23), -+ .rgbsz = BITS(VEC_RGBSZ_BYTES_PER_PIXEL_MINUS1, 2), ++ .shift = SHIFT_RGB(7, 15, 23), ++ .rgbsz = BITS(VEC_RGBSZ_BYTES_PER_PIXEL_MINUS1, 2), + }, + { + .format = DRM_FORMAT_RGB565, + .mask = MASK_RGB(0x3e0, 0x3f0, 0x3e0), -+ .shift = SHIFT_RGB(15, 10, 4), -+ .rgbsz = BITS(VEC_RGBSZ_SCALE_R, 5) | ++ .shift = SHIFT_RGB(15, 10, 4), ++ .rgbsz = BITS(VEC_RGBSZ_SCALE_R, 5) | + BITS(VEC_RGBSZ_SCALE_G, 6) | + BITS(VEC_RGBSZ_SCALE_B, 5) | + BITS(VEC_RGBSZ_BYTES_PER_PIXEL_MINUS1, 1), @@ -82744,354 +83313,277 @@ index 000000000000..b9a67a8a330c +}; + +/* -+ * Hardware mode descriptions (@ 108 MHz clock rate). -+ * These rely largely on "canned" register settings. ++ * Hardware mode descriptions (@ 108 MHz VDAC clock) ++ * See "vec_regs.h" for further descriptions of these registers and fields. ++ * Driver should adjust some values for other TV standards and for pixel rate, ++ * and must ensure that ((de_end - de_bgn) % rate) == 0. + */ + +struct rp1vec_hwmode { -+ u16 total_cols; /* max active columns incl. padding and windowing */ -+ u16 rows_per_field; /* active lines per field (including partial ones) */ -+ u16 ref_hfp; /* nominal (hsync_start - hdisplay) when max width */ -+ u16 ref_vfp; /* nominal (vsync_start - vdisplay) when max height */ -+ bool interlaced; /* set for interlaced */ -+ bool first_field_odd; /* set for interlaced and 30fps */ -+ u32 yuv_scaling; /* three 10-bit fields {Y, U, V} in 2.8 format */ -+ u32 back_end_regs[28]; /* All registers 0x80 .. 0xEC */ ++ u16 max_rows_per_field; /* active lines per field (including partial ones) */ ++ u16 ref_vfp; /* nominal (vsync_start - vdisplay) when max height */ ++ bool interlaced; /* set for interlaced */ ++ bool first_field_odd; /* depends confusingly on line numbering convention */ ++ s16 scale_v; /* V scale in 2.8 format (for power-of-2 CIC rates) */ ++ s16 scale_u; /* U scale in 2.8 format (for power-of-2 CIC rates) */ ++ u16 scale_y; /* Y scale in 2.8 format (for power-of-2 CIC rates) */ ++ u16 de_end; /* end of horizontal Data Active period at 108MHz */ ++ u16 de_bgn; /* start of horizontal Data Active period */ ++ u16 half_lines_per_field; /* number of half lines per field */ ++ s16 pedestal; /* pedestal (1024 = 100IRE) including FIR overshoot */ ++ u16 scale_luma; /* back end luma scaling in 1.15 format wrt DAC FSD */ ++ u16 scale_sync; /* back end sync scaling / blanking level as above */ ++ u32 scale_burst_chroma; /* back end { burst, chroma } scaling */ ++ u32 misc; /* Contents of the "EC" register except rate,shift */ ++ u64 nco_freq; /* colour carrier frequency * (2**64) / 108MHz */ ++ u32 timing_regs[14]; /* other back end registers 0x84 .. 0xB8 */ +}; + -+/* { NTSC, PAL, PAL-M } x { progressive, interlaced } x { 13.5 MHz, 15.428571 MHz } */ -+static const struct rp1vec_hwmode rp1vec_hwmodes[3][2][2] = { ++/* { NTSC, PAL, PAL-M } x { progressive, interlaced } */ ++static const struct rp1vec_hwmode rp1vec_hwmodes[3][2] = { + { + /* NTSC */ + { -+ { -+ .total_cols = 724, -+ .rows_per_field = 240, -+ .ref_hfp = 12, -+ .ref_vfp = 2, -+ .interlaced = false, -+ .first_field_odd = false, -+ .yuv_scaling = 0x1071d0cf, -+ .back_end_regs = { -+ 0x039f1a3f, 0x03e10cc6, 0x0d6801fb, 0x023d034c, -+ 0x00f80b6d, 0x00000005, 0x0006000b, 0x000c0011, -+ 0x000a0106, 0x00000000, 0x00000000, 0x00000000, -+ 0x00000000, 0x00170106, 0x00000000, 0x004c020e, -+ 0x00000000, 0x007bffff, 0x38518c9a, 0x11195561, -+ 0x02000200, 0xc1f07c1f, 0x087c1f07, 0x00000000, -+ 0x0be20200, 0x20f0f800, 0x265c7f00, 0x000801ec, -+ }, -+ }, { -+ .total_cols = 815, -+ .rows_per_field = 240, -+ .ref_hfp = 16, -+ .ref_vfp = 2, -+ .interlaced = false, -+ .first_field_odd = false, -+ .yuv_scaling = 0x1c131962, -+ .back_end_regs = { -+ 0x03ce1a17, 0x03e10cc6, 0x0d6801fb, 0x023d034c, -+ 0x00f80b6d, 0x00000005, 0x0006000b, 0x000c0011, -+ 0x000a0106, 0x00000000, 0x00000000, 0x00000000, -+ 0x00000000, 0x00170106, 0x00000000, 0x004c020e, -+ 0x00000000, 0x007bffff, 0x38518c9a, 0x11195561, -+ 0x02000200, 0xc1f07c1f, 0x087c1f07, 0x00000000, -+ 0x0be20200, 0x20f0f800, 0x265c7f00, 0x000801ac, -+ }, ++ .max_rows_per_field = 240, ++ .ref_vfp = 2, ++ .interlaced = false, ++ .first_field_odd = false, ++ .scale_v = 0x0cf, ++ .scale_u = 0x074, ++ .scale_y = 0x107, ++ .de_end = 0x1a4f, ++ .de_bgn = 0x038f, ++ .half_lines_per_field = 524, /* also works with 526/2 lines */ ++ .pedestal = 0x04c, ++ .scale_luma = 0x8c9a, ++ .scale_sync = 0x3851, ++ .scale_burst_chroma = 0x11195561, ++ .misc = 0x00090c00, /* 5-tap FIR, SEQ_EN, 4 fld sync */ ++ .nco_freq = 0x087c1f07c1f07c1f, ++ .timing_regs = { ++ 0x03e10cc6, 0x0d6801fb, 0x023d034c, 0x00f80b6d, ++ 0x00000005, 0x0006000b, 0x000c0011, 0x000a0106, ++ 0x00000000, 0x00000000, 0x00000000, 0x00000000, ++ 0x00170106, 0x00000000 + }, + }, { -+ { -+ .total_cols = 724, -+ .rows_per_field = 243, -+ .ref_hfp = 12, -+ .ref_vfp = 3, -+ .interlaced = true, -+ .first_field_odd = true, -+ .yuv_scaling = 0x1071d0cf, -+ .back_end_regs = { -+ 0x039f1a3f, 0x03e10cc6, 0x0d6801fb, 0x023d034c, -+ 0x00f80b6d, 0x00000005, 0x0006000b, 0x000c0011, -+ 0x000a0107, 0x0111020d, 0x00000000, 0x00000000, -+ 0x011c020d, 0x00150106, 0x0107011b, 0x004c020d, -+ 0x00000000, 0x007bffff, 0x38518c9a, 0x11195561, -+ 0x02000200, 0xc1f07c1f, 0x087c1f07, 0x00000000, -+ 0x0be20200, 0x20f0f800, 0x265c7f00, 0x00094dee, -+ }, -+ }, { -+ .total_cols = 815, -+ .rows_per_field = 243, -+ .ref_hfp = 16, -+ .ref_vfp = 3, -+ .interlaced = true, -+ .first_field_odd = true, -+ .yuv_scaling = 0x1c131962, -+ .back_end_regs = { -+ 0x03ce1a17, 0x03e10cc6, 0x0d6801fb, 0x023d034c, -+ 0x00f80b6d, 0x00000005, 0x0006000b, 0x000c0011, -+ 0x000a0107, 0x0111020d, 0x00000000, 0x00000000, -+ 0x011c020d, 0x00150106, 0x0107011b, 0x004c020d, -+ 0x00000000, 0x007bffff, 0x38518c9a, 0x11195561, -+ 0x02000200, 0xc1f07c1f, 0x087c1f07, 0x00000000, -+ 0x0be20200, 0x20f0f800, 0x265c7f00, 0x00094dae, -+ }, ++ .max_rows_per_field = 243, ++ .ref_vfp = 3, ++ .interlaced = true, ++ .first_field_odd = true, ++ .scale_v = 0x0cf, ++ .scale_u = 0x074, ++ .scale_y = 0x107, ++ .de_end = 0x1a4f, ++ .de_bgn = 0x038f, ++ .half_lines_per_field = 525, ++ .pedestal = 0x04c, ++ .scale_luma = 0x8c9a, ++ .scale_sync = 0x3851, ++ .scale_burst_chroma = 0x11195561, ++ .misc = 0x00094c02, /* 5-tap FIR, SEQ_EN, 2 flds, 4 fld sync, ilace */ ++ .nco_freq = 0x087c1f07c1f07c1f, ++ .timing_regs = { ++ 0x03e10cc6, 0x0d6801fb, 0x023d034c, 0x00f80b6d, ++ 0x00000005, 0x0006000b, 0x000c0011, 0x000a0107, ++ 0x0111020d, 0x00000000, 0x00000000, 0x011c020d, ++ 0x00150106, 0x0107011b, + }, + }, + }, { + /* PAL */ + { -+ { -+ .total_cols = 724, -+ .rows_per_field = 288, -+ .ref_hfp = 16, -+ .ref_vfp = 2, -+ .interlaced = false, -+ .first_field_odd = false, -+ .yuv_scaling = 0x11c1f8e0, -+ .back_end_regs = { -+ 0x04061aa6, 0x046e0cee, 0x0d8001fb, 0x025c034f, -+ 0x00fd0b84, 0x026c0270, 0x00000004, 0x00050009, -+ 0x00070135, 0x00000000, 0x00000000, 0x00000000, -+ 0x00000000, 0x00170136, 0x00000000, 0x000a0270, -+ 0x00000000, 0x007bffff, 0x3b1389d8, 0x0caf53b5, -+ 0x02000200, 0xcc48c1d1, 0x0a8262b2, 0x00000000, -+ 0x0be20200, 0x20f0f800, 0x265c7f00, 0x000801ed, -+ }, -+ }, { -+ .total_cols = 804, -+ .rows_per_field = 288, -+ .ref_hfp = 24, -+ .ref_vfp = 2, -+ .interlaced = false, -+ .first_field_odd = false, -+ .yuv_scaling = 0x1e635d7f, -+ .back_end_regs = { -+ 0x045b1a57, 0x046e0cee, 0x0d8001fb, 0x025c034f, -+ 0x00fd0b84, 0x026c0270, 0x00000004, 0x00050009, -+ 0x00070135, 0x00000000, 0x00000000, 0x00000000, -+ 0x00000000, 0x00170136, 0x00000000, 0x000a0270, -+ 0x00000000, 0x007bffff, 0x3b1389d8, 0x0caf53b5, -+ 0x02000200, 0xcc48c1d1, 0x0a8262b2, 0x00000000, -+ 0x0be20200, 0x20f0f800, 0x265c7f00, 0x000801ad, -+ }, ++ .max_rows_per_field = 288, ++ .ref_vfp = 2, ++ .interlaced = false, ++ .first_field_odd = false, ++ .scale_v = 0x0e0, ++ .scale_u = 0x07e, ++ .scale_y = 0x11c, ++ .de_end = 0x1ab6, ++ .de_bgn = 0x03f6, ++ .half_lines_per_field = 624, ++ .pedestal = 0x00a, /* nonzero for max FIR overshoot after CIC */ ++ .scale_luma = 0x89d8, ++ .scale_sync = 0x3c00, ++ .scale_burst_chroma = 0x0caf53b5, ++ .misc = 0x00091c01, /* 5-tap FIR, SEQ_EN, 8 fld sync, PAL */ ++ .nco_freq = 0x0a8262b2cc48c1d1, ++ .timing_regs = { ++ 0x046e0cee, 0x0d8001fb, 0x025c034f, 0x00fd0b84, ++ 0x026c0270, 0x00000004, 0x00050009, 0x00070135, ++ 0x00000000, 0x00000000, 0x00000000, 0x00000000, ++ 0x00170136, 0x00000000, + }, + }, { -+ { -+ .total_cols = 724, -+ .rows_per_field = 288, -+ .ref_hfp = 16, -+ .ref_vfp = 5, -+ .interlaced = true, -+ .first_field_odd = false, -+ .yuv_scaling = 0x11c1f8e0, -+ .back_end_regs = { -+ 0x04061aa6, 0x046e0cee, 0x0d8001fb, 0x025c034f, -+ 0x00fd0b84, 0x026c0270, 0x00000004, 0x00050009, -+ 0x00070135, 0x013f026d, 0x00060136, 0x0140026e, -+ 0x0150026e, 0x00180136, 0x026f0017, 0x000a0271, -+ 0x00000000, 0x007bffff, 0x3b1389d8, 0x0caf53b5, -+ 0x02000200, 0xcc48c1d1, 0x0a8262b2, 0x00000000, -+ 0x0be20200, 0x20f0f800, 0x265c7f00, 0x0009ddef, -+ }, -+ }, { -+ .total_cols = 804, -+ .rows_per_field = 288, -+ .ref_hfp = 24, -+ .ref_vfp = 5, -+ .interlaced = true, -+ .first_field_odd = false, -+ .yuv_scaling = 0x1e635d7f, -+ .back_end_regs = { -+ 0x045b1a57, 0x046e0cee, 0x0d8001fb, 0x025c034f, -+ 0x00fd0b84, 0x026c0270, 0x00000004, 0x00050009, -+ 0x00070135, 0x013f026d, 0x00060136, 0x0140026e, -+ 0x0150026e, 0x00180136, 0x026f0017, 0x000a0271, -+ 0x00000000, 0x007bffff, 0x3b1389d8, 0x0caf53b5, -+ 0x02000200, 0xcc48c1d1, 0x0a8262b2, 0x00000000, -+ 0x0be20200, 0x20f0f800, 0x265c7f00, 0x0009ddaf, -+ }, ++ .max_rows_per_field = 288, ++ .ref_vfp = 5, ++ .interlaced = true, ++ .first_field_odd = false, ++ .scale_v = 0x0e0, ++ .scale_u = 0x07e, ++ .scale_y = 0x11c, ++ .de_end = 0x1ab6, ++ .de_bgn = 0x03f6, ++ .half_lines_per_field = 625, ++ .pedestal = 0x00a, ++ .scale_luma = 0x89d8, ++ .scale_sync = 0x3c00, ++ .scale_burst_chroma = 0x0caf53b5, ++ .misc = 0x0009dc03, /* 5-tap FIR, SEQ_EN, 4 flds, 8 fld sync, ilace, PAL */ ++ .nco_freq = 0x0a8262b2cc48c1d1, ++ .timing_regs = { ++ 0x046e0cee, 0x0d8001fb, 0x025c034f, 0x00fd0b84, ++ 0x026c0270, 0x00000004, 0x00050009, 0x00070135, ++ 0x013f026d, 0x00060136, 0x0140026e, 0x0150026e, ++ 0x00180136, 0x026f0017, + }, + }, + }, { + /* PAL-M */ + { -+ { -+ .total_cols = 724, -+ .rows_per_field = 240, -+ .ref_hfp = 12, -+ .ref_vfp = 2, -+ .interlaced = false, -+ .first_field_odd = false, -+ .yuv_scaling = 0x11c1f8e0, -+ .back_end_regs = { -+ 0x039f1a3f, 0x03e10cc6, 0x0d6801fb, 0x023c034c, -+ 0x00f80b6e, 0x00000005, 0x0006000b, 0x000c0011, -+ 0x000a0106, 0x00000000, 0x00000000, 0x00000000, -+ 0x00000000, 0x00170106, 0x00000000, 0x000a020c, -+ 0x00000000, 0x007bffff, 0x385189d8, 0x0d5c53b5, -+ 0x02000200, 0xd6d33ea8, 0x0879bbf8, 0x00000000, -+ 0x0be20200, 0x20f0f800, 0x265c7f00, 0x000801ed, -+ }, -+ }, { -+ .total_cols = 815, -+ .rows_per_field = 240, -+ .ref_hfp = 16, -+ .ref_vfp = 2, -+ .interlaced = false, -+ .first_field_odd = false, -+ .yuv_scaling = 0x1e635d7f, -+ .back_end_regs = { -+ 0x03ce1a17, 0x03e10cc6, 0x0d6801fb, 0x023c034c, -+ 0x00f80b6e, 0x00000005, 0x0006000b, 0x000c0011, -+ 0x000a0106, 0x00000000, 0x00000000, 0x00000000, -+ 0x00000000, 0x00170106, 0x00000000, 0x000a020c, -+ 0x00000000, 0x007bffff, 0x385189d8, 0x0d5c53b5, -+ 0x02000200, 0xd6d33ea8, 0x0879bbf8, 0x00000000, -+ 0x0be20200, 0x20f0f800, 0x265c7f00, 0x000801ad, -+ }, ++ .max_rows_per_field = 240, ++ .ref_vfp = 2, ++ .interlaced = false, ++ .first_field_odd = false, ++ .scale_v = 0x0e0, ++ .scale_u = 0x07e, ++ .scale_y = 0x11c, ++ .de_end = 0x1a4f, ++ .de_bgn = 0x038f, ++ .half_lines_per_field = 524, ++ .pedestal = 0x00a, ++ .scale_luma = 0x89d8, ++ .scale_sync = 0x3851, ++ .scale_burst_chroma = 0x0d5c53b5, ++ .misc = 0x00091c01, /* 5-tap FIR, SEQ_EN, 8 fld sync PAL */ ++ .nco_freq = 0x0879bbf8d6d33ea8, ++ .timing_regs = { ++ 0x03e10cc6, 0x0d6801fb, 0x023c034c, 0x00f80b6e, ++ 0x00000005, 0x0006000b, 0x000c0011, 0x000a0106, ++ 0x00000000, 0x00000000, 0x00000000, 0x00000000, ++ 0x00170106, 0x00000000, + }, + }, { -+ { -+ .total_cols = 724, -+ .rows_per_field = 243, -+ .ref_hfp = 12, -+ .ref_vfp = 3, -+ .interlaced = true, -+ .first_field_odd = true, -+ .yuv_scaling = 0x11c1f8e0, -+ .back_end_regs = { -+ 0x039f1a3f, 0x03e10cc6, 0x0d6801fb, 0x023c034c, -+ 0x00f80b6e, 0x00140019, 0x00000005, 0x0006000b, -+ 0x00090103, 0x010f0209, 0x00080102, 0x010e020a, -+ 0x0119020a, 0x00120103, 0x01040118, 0x000a020d, -+ 0x00000000, 0x007bffff, 0x385189d8, 0x0d5c53b5, -+ 0x02000200, 0xd6d33ea8, 0x0879bbf8, 0x00000000, -+ 0x0be20200, 0x20f0f800, 0x265c7f00, 0x0009ddef, -+ }, -+ }, { -+ .total_cols = 815, -+ .rows_per_field = 243, -+ .ref_hfp = 16, -+ .ref_vfp = 3, -+ .interlaced = true, -+ .first_field_odd = true, -+ .yuv_scaling = 0x1e635d7f, -+ .back_end_regs = { -+ 0x03ce1a17, 0x03e10cc6, 0x0d6801fb, 0x023c034c, -+ 0x00f80b6e, 0x00140019, 0x00000005, 0x0006000b, -+ 0x00090103, 0x010f0209, 0x00080102, 0x010e020a, -+ 0x0119020a, 0x00120103, 0x01040118, 0x000a020d, -+ 0x00000000, 0x007bffff, 0x385189d8, 0x0d5c53b5, -+ 0x02000200, 0xd6d33ea8, 0x0879bbf8, 0x00000000, -+ 0x0be20200, 0x20f0f800, 0x265c7f00, 0x0009ddaf, -+ }, ++ .max_rows_per_field = 243, ++ .ref_vfp = 3, ++ .interlaced = true, ++ .first_field_odd = true, ++ .scale_v = 0x0e0, ++ .scale_u = 0x07e, ++ .scale_y = 0x11c, ++ .de_end = 0x1a4f, ++ .de_bgn = 0x038f, ++ .half_lines_per_field = 525, ++ .pedestal = 0x00a, ++ .scale_luma = 0x89d8, ++ .scale_sync = 0x3851, ++ .scale_burst_chroma = 0x0d5c53b5, ++ .misc = 0x0009dc03, /* 5-tap FIR, SEQ_EN, 4 flds, 8 fld sync, ilace, PAL */ ++ .nco_freq = 0x0879bbf8d6d33ea8, ++ .timing_regs = { ++ 0x03e10cc6, 0x0d6801fb, 0x023c034c, 0x00f80b6e, ++ 0x00140019, 0x00000005, 0x0006000b, 0x00090103, ++ 0x010f0209, 0x00080102, 0x010e020a, 0x0119020a, ++ 0x00120103, 0x01040118, + }, + }, + }, +}; + ++/* System A, System E */ ++static const struct rp1vec_hwmode rp1vec_vintage_modes[2] = { ++ { ++ .max_rows_per_field = 190, ++ .ref_vfp = 0, ++ .interlaced = true, ++ .first_field_odd = true, ++ .scale_v = 0, ++ .scale_u = 0, ++ .scale_y = 0x11c, ++ .de_end = 0x2920, ++ .de_bgn = 0x06a0, ++ .half_lines_per_field = 405, ++ .pedestal = 0x00a, ++ .scale_luma = 0x89d8, ++ .scale_sync = 0x3c00, ++ .scale_burst_chroma = 0, ++ .misc = 0x00084002, /* 5-tap FIR, 2 fields, interlace */ ++ .nco_freq = 0, ++ .timing_regs = { ++ 0x06f01430, 0x14d503cc, 0x00000000, 0x000010de, ++ 0x00000000, 0x00000007, 0x00000000, 0x00000000, ++ 0x00000000, 0x00000000, 0x00000000, 0x00d90195, ++ 0x000e00ca, 0x00cb00d8, ++ }, ++ }, { ++ .max_rows_per_field = 369, ++ .ref_vfp = 6, ++ .interlaced = true, ++ .first_field_odd = true, ++ .scale_v = 0, ++ .scale_u = 0, ++ .scale_y = 0x11c, ++ .de_end = 0x145f, ++ .de_bgn = 0x03a7, ++ .half_lines_per_field = 819, ++ .pedestal = 0x0010, ++ .scale_luma = 0x89d8, ++ .scale_sync = 0x3b13, ++ .scale_burst_chroma = 0, ++ .misc = 0x00084002, /* 5-tap FIR, 2 fields, interlace */ ++ .nco_freq = 0, ++ .timing_regs = { ++ 0x03c10a08, 0x0a4d0114, 0x00000000, 0x000008a6, ++ 0x00000000, 0x00000000, 0x00000000, 0x00000000, ++ 0x00000000, 0x00000000, 0x00000000, 0x01c10330, ++ 0x00270196, 0x019701c0, ++ }, ++ }, ++}; ++ ++static const u32 rp1vec_fir_regs[4] = { ++ 0x00000000, 0x0be20200, 0x20f0f800, 0x265c7f00, ++}; ++ ++/* ++ * Correction for the 4th order CIC filter's gain of (rate ** 4) ++ * expressed as a right-shift and a reciprocal scale factor (Q12). ++ * These arrays are indexed by [rate - 4] where 4 <= rate <= 16. ++ */ ++ ++static const int rp1vec_scale_table[13] = { ++ 4096, 6711, 6473, 6988, ++ 4096, 5114, 6711, 4584, ++ 6473, 4699, 6988, 5302, ++ 4096 ++}; ++ ++static const u32 rp1vec_rate_shift_table[13] = { ++ BITS(VEC_DAC_EC_INTERP_RATE_MINUS1, 3) | BITS(VEC_DAC_EC_INTERP_SHIFT_MINUS1, 7), ++ BITS(VEC_DAC_EC_INTERP_RATE_MINUS1, 4) | BITS(VEC_DAC_EC_INTERP_SHIFT_MINUS1, 9), ++ BITS(VEC_DAC_EC_INTERP_RATE_MINUS1, 5) | BITS(VEC_DAC_EC_INTERP_SHIFT_MINUS1, 10), ++ BITS(VEC_DAC_EC_INTERP_RATE_MINUS1, 6) | BITS(VEC_DAC_EC_INTERP_SHIFT_MINUS1, 11), ++ BITS(VEC_DAC_EC_INTERP_RATE_MINUS1, 7) | BITS(VEC_DAC_EC_INTERP_SHIFT_MINUS1, 11), ++ BITS(VEC_DAC_EC_INTERP_RATE_MINUS1, 8) | BITS(VEC_DAC_EC_INTERP_SHIFT_MINUS1, 12), ++ BITS(VEC_DAC_EC_INTERP_RATE_MINUS1, 9) | BITS(VEC_DAC_EC_INTERP_SHIFT_MINUS1, 13), ++ BITS(VEC_DAC_EC_INTERP_RATE_MINUS1, 10) | BITS(VEC_DAC_EC_INTERP_SHIFT_MINUS1, 13), ++ BITS(VEC_DAC_EC_INTERP_RATE_MINUS1, 11) | BITS(VEC_DAC_EC_INTERP_SHIFT_MINUS1, 14), ++ BITS(VEC_DAC_EC_INTERP_RATE_MINUS1, 12) | BITS(VEC_DAC_EC_INTERP_SHIFT_MINUS1, 14), ++ BITS(VEC_DAC_EC_INTERP_RATE_MINUS1, 13) | BITS(VEC_DAC_EC_INTERP_SHIFT_MINUS1, 15), ++ BITS(VEC_DAC_EC_INTERP_RATE_MINUS1, 14) | BITS(VEC_DAC_EC_INTERP_SHIFT_MINUS1, 15), ++ BITS(VEC_DAC_EC_INTERP_RATE_MINUS1, 15) | BITS(VEC_DAC_EC_INTERP_SHIFT_MINUS1, 15), ++}; ++ +void rp1vec_hw_setup(struct rp1_vec *vec, + u32 in_format, + struct drm_display_mode const *mode, + int tvstd) +{ -+ unsigned int i, mode_family, mode_ilaced, mode_narrow; ++ int i, mode_family, w, h; + const struct rp1vec_hwmode *hwm; -+ int w, h, hpad, vpad; -+ -+ /* Pick the appropriate "base" mode, which we may modify */ -+ mode_ilaced = !!(mode->flags & DRM_MODE_FLAG_INTERLACE); -+ if (mode->vtotal >= 272 * (1 + mode_ilaced)) -+ mode_family = 1; -+ else if (tvstd == DRM_MODE_TV_MODE_PAL_M || tvstd == DRM_MODE_TV_MODE_PAL) -+ mode_family = 2; -+ else -+ mode_family = 0; -+ mode_narrow = (mode->clock >= 14336); -+ hwm = &rp1vec_hwmodes[mode_family][mode_ilaced][mode_narrow]; -+ dev_info(&vec->pdev->dev, -+ "%s: in_fmt=\'%c%c%c%c\' mode=%dx%d%s [%d%d%d] tvstd=%d", -+ __func__, in_format, in_format >> 8, in_format >> 16, in_format >> 24, -+ mode->hdisplay, mode->vdisplay, (mode_ilaced) ? "i" : "", -+ mode_family, mode_ilaced, mode_narrow, tvstd); -+ -+ w = mode->hdisplay; -+ h = mode->vdisplay >> mode_ilaced; -+ if (w > hwm->total_cols) -+ w = hwm->total_cols; -+ if (h > hwm->rows_per_field) -+ h = hwm->rows_per_field; -+ -+ /* -+ * Add padding so a framebuffer with the given dimensions and -+ * [hv]sync_start can be displayed in the chosen hardware mode. -+ * -+ * |<----- mode->hsync_start ----->| -+ * |<------ w ------>| | -+ * | | >|--|< ref_hfp -+ * |<- hpad ->| -+ * |<------------ total_cols ----------->| -+ * ________FRAMEBUFFERCONTENTS__________ -+ * ' `--\____/-<\/\/\>-' -+ */ -+ hpad = max(0, mode->hsync_start - hwm->ref_hfp - w); -+ hpad = min(hpad, hwm->total_cols - w); -+ vpad = max(0, ((mode->vsync_start - hwm->ref_vfp) >> mode_ilaced) - h); -+ vpad = min(vpad, hwm->rows_per_field - h); -+ -+ /* Configure the hardware */ -+ VEC_WRITE(VEC_APB_TIMEOUT, 0x38); -+ VEC_WRITE(VEC_QOS, -+ BITS(VEC_QOS_DQOS, 0x0) | -+ BITS(VEC_QOS_ULEV, 0x8) | -+ BITS(VEC_QOS_UQOS, 0x2) | -+ BITS(VEC_QOS_LLEV, 0x4) | -+ BITS(VEC_QOS_LQOS, 0x7)); -+ VEC_WRITE(VEC_DMA_AREA, -+ BITS(VEC_DMA_AREA_COLS_MINUS1, w - 1) | -+ BITS(VEC_DMA_AREA_ROWS_PER_FIELD_MINUS1, h - 1)); -+ VEC_WRITE(VEC_YUV_SCALING, hwm->yuv_scaling); -+ VEC_WRITE(VEC_BACK_PORCH, -+ BITS(VEC_BACK_PORCH_HBP_MINUS1, hwm->total_cols - w - hpad - 1) | -+ BITS(VEC_BACK_PORCH_VBP_MINUS1, hwm->rows_per_field - h - vpad - 1)); -+ VEC_WRITE(VEC_FRONT_PORCH, -+ BITS(VEC_FRONT_PORCH_HFP_MINUS1, hpad - 1) | -+ BITS(VEC_FRONT_PORCH_VFP_MINUS1, vpad - 1)); -+ VEC_WRITE(VEC_MODE, -+ BITS(VEC_MODE_HIGH_WATER, 0xE0) | -+ BITS(VEC_MODE_ALIGN16, !((w | mode->hdisplay) & 15)) | -+ BITS(VEC_MODE_VFP_EN, (vpad > 0)) | -+ BITS(VEC_MODE_VBP_EN, (hwm->rows_per_field > h + vpad)) | -+ BITS(VEC_MODE_HFP_EN, (hpad > 0)) | -+ BITS(VEC_MODE_HBP_EN, (hwm->total_cols > w + hpad)) | -+ BITS(VEC_MODE_FIELDS_PER_FRAME_MINUS1, hwm->interlaced) | -+ BITS(VEC_MODE_FIRST_FIELD_ODD, hwm->first_field_odd)); -+ for (i = 0; i < ARRAY_SIZE(hwm->back_end_regs); ++i) { -+ writel(hwm->back_end_regs[i], -+ vec->hw_base[RP1VEC_HW_BLOCK_VEC] + 0x80 + 4 * i); -+ } -+ -+ /* Apply modifications */ -+ if (tvstd == DRM_MODE_TV_MODE_NTSC_J && mode_family == 0) { -+ /* Reduce pedestal (not quite to zero, for FIR overshoot); increase gain */ -+ VEC_WRITE(VEC_DAC_BC, -+ BITS(VEC_DAC_BC_S11_PEDESTAL, 10) | -+ (hwm->back_end_regs[(0xBC - 0x80) / 4] & ~VEC_DAC_BC_S11_PEDESTAL_BITS)); -+ VEC_WRITE(VEC_DAC_C8, -+ BITS(VEC_DAC_C8_U16_SCALE_LUMA, 0x9400) | -+ (hwm->back_end_regs[(0xC8 - 0x80) / 4] & -+ ~VEC_DAC_C8_U16_SCALE_LUMA_BITS)); -+ } else if ((tvstd == DRM_MODE_TV_MODE_NTSC_443 || tvstd == DRM_MODE_TV_MODE_PAL) && -+ mode_family != 1) { -+ /* Change colour carrier frequency to 4433618.75 Hz; disable hard sync */ -+ VEC_WRITE(VEC_DAC_D4, 0xcc48c1d1); -+ VEC_WRITE(VEC_DAC_D8, 0x0a8262b2); -+ VEC_WRITE(VEC_DAC_EC, -+ hwm->back_end_regs[(0xEC - 0x80) / 4] & ~VEC_DAC_EC_SEQ_EN_BITS); -+ } else if (tvstd == DRM_MODE_TV_MODE_PAL_N && mode_family == 1) { -+ /* Change colour carrier frequency to 3582056.25 Hz */ -+ VEC_WRITE(VEC_DAC_D4, 0x9ce075f7); -+ VEC_WRITE(VEC_DAC_D8, 0x087da511); -+ } ++ int wmax, hpad_r, vpad_b, rate, ref_2mid, usr_2mid; ++ u32 misc; + + /* Input pixel format conversion */ + for (i = 0; i < ARRAY_SIZE(my_formats); ++i) { @@ -83106,9 +83598,135 @@ index 000000000000..b9a67a8a330c + VEC_WRITE(VEC_SHIFT, my_formats[i].shift); + VEC_WRITE(VEC_RGBSZ, my_formats[i].rgbsz); + -+ VEC_WRITE(VEC_IRQ_FLAGS, 0xffffffff); -+ rp1vec_hw_vblank_ctrl(vec, 1); ++ /* Pick an appropriate "base" mode, which we may modify. ++ * Note that this driver supports a limited selection of video modes. ++ * (A complete TV mode cannot be directly inferred from a DRM display mode: ++ * features such as chroma burst sequence, half-lines and equalizing pulses ++ * would be under-specified, and timings prone to rounding errors.) ++ */ ++ if (mode->vtotal == 405 || mode->vtotal == 819) { ++ /* Systems A and E (interlaced only) */ ++ vec->fake_31khz = false; ++ mode_family = 1; ++ hwm = &rp1vec_vintage_modes[(mode->vtotal == 819) ? 1 : 0]; ++ } else { ++ /* 525- and 625-line modes, with half-height and "fake" progressive variants */ ++ vec->fake_31khz = mode->vtotal >= 500 && !(mode->flags & DRM_MODE_FLAG_INTERLACE); ++ h = (mode->vtotal >= 500) ? (mode->vtotal >> 1) : mode->vtotal; ++ if (h >= 272) ++ mode_family = 1; /* PAL-625 */ ++ else if (tvstd == DRM_MODE_TV_MODE_PAL_M || tvstd == DRM_MODE_TV_MODE_PAL) ++ mode_family = 2; /* PAL-525 */ ++ else ++ mode_family = 0; /* NTSC-525 */ ++ hwm = &rp1vec_hwmodes[mode_family][(mode->flags & DRM_MODE_FLAG_INTERLACE) ? 1 : 0]; ++ } + ++ /* ++ * Choose the upsampling rate (to 108MHz) in the range 4..16. ++ * Clip dimensions to the limits of the chosen hardware mode, then add ++ * padding as required, making some attempt to respect the DRM mode's ++ * display position (relative to H and V sync start). Note that "wmax" ++ * should be wider than the horizontal active region, to avoid boundary ++ * artifacts (e.g. wmax = 728, w = 720, active ~= 704 in Rec.601 modes). ++ */ ++ i = (vec->fake_31khz) ? (mode->clock >> 1) : mode->clock; ++ rate = (i < (RP1VEC_VDAC_KHZ / 16)) ? 16 : max(4, (RP1VEC_VDAC_KHZ + 256) / i); ++ wmax = min((hwm->de_end - hwm->de_bgn) / rate, 1020); ++ w = min(mode->hdisplay, wmax); ++ ref_2mid = (hwm->de_bgn + hwm->de_end) / rate + 4; /* + 4 for FIR delay */ ++ usr_2mid = (2 * (mode->htotal - mode->hsync_start) + w) * 2 * (hwm->timing_regs[1] >> 16) / ++ (rate * mode->htotal); ++ hpad_r = (wmax - w + ref_2mid - usr_2mid) >> 1; ++ hpad_r = min(max(0, hpad_r), wmax - w); ++ h = mode->vdisplay >> (hwm->interlaced || vec->fake_31khz); ++ h = min(h, 0 + hwm->max_rows_per_field); ++ vpad_b = ((mode->vsync_start - hwm->ref_vfp) >> (hwm->interlaced || vec->fake_31khz)) - h; ++ vpad_b = min(max(0, vpad_b), hwm->max_rows_per_field - h); ++ ++ /* Configure the hardware "front end" (in the sysclock domain) */ ++ VEC_WRITE(VEC_APB_TIMEOUT, 0x38); ++ VEC_WRITE(VEC_QOS, ++ BITS(VEC_QOS_DQOS, 0x0) | ++ BITS(VEC_QOS_ULEV, 0x8) | ++ BITS(VEC_QOS_UQOS, 0x2) | ++ BITS(VEC_QOS_LLEV, 0x4) | ++ BITS(VEC_QOS_LQOS, 0x7)); ++ VEC_WRITE(VEC_DMA_AREA, ++ BITS(VEC_DMA_AREA_COLS_MINUS1, w - 1) | ++ BITS(VEC_DMA_AREA_ROWS_PER_FIELD_MINUS1, h - 1)); ++ VEC_WRITE(VEC_YUV_SCALING, ++ BITS(VEC_YUV_SCALING_U10_SCALE_Y, ++ (hwm->scale_y * rp1vec_scale_table[rate - 4] + 2048) >> 12) | ++ BITS(VEC_YUV_SCALING_S10_SCALE_U, ++ (hwm->scale_u * rp1vec_scale_table[rate - 4] + 2048) >> 12) | ++ BITS(VEC_YUV_SCALING_S10_SCALE_V, ++ (hwm->scale_v * rp1vec_scale_table[rate - 4] + 2048) >> 12)); ++ VEC_WRITE(VEC_BACK_PORCH, ++ BITS(VEC_BACK_PORCH_HBP_MINUS1, wmax - w - hpad_r - 1) | ++ BITS(VEC_BACK_PORCH_VBP_MINUS1, hwm->max_rows_per_field - h - vpad_b - 1)); ++ VEC_WRITE(VEC_FRONT_PORCH, ++ BITS(VEC_FRONT_PORCH_HFP_MINUS1, hpad_r - 1) | ++ BITS(VEC_FRONT_PORCH_VFP_MINUS1, vpad_b - 1)); ++ VEC_WRITE(VEC_MODE, ++ BITS(VEC_MODE_HIGH_WATER, 0xE0) | ++ BITS(VEC_MODE_ALIGN16, !((w | mode->hdisplay) & 15)) | ++ BITS(VEC_MODE_VFP_EN, (vpad_b > 0)) | ++ BITS(VEC_MODE_VBP_EN, (hwm->max_rows_per_field > h + vpad_b)) | ++ BITS(VEC_MODE_HFP_EN, (hpad_r > 0)) | ++ BITS(VEC_MODE_HBP_EN, (wmax > w + hpad_r)) | ++ BITS(VEC_MODE_FIELDS_PER_FRAME_MINUS1, hwm->interlaced) | ++ BITS(VEC_MODE_FIRST_FIELD_ODD, hwm->first_field_odd)); ++ ++ /* Configure the hardware "back end" (in the VDAC clock domain) */ ++ VEC_WRITE(VEC_DAC_80, ++ BITS(VEC_DAC_80_U14_DE_BGN, hwm->de_bgn) | ++ BITS(VEC_DAC_80_U14_DE_END, hwm->de_bgn + wmax * rate)); ++ rp1vec_write_regs(vec, 0x84, hwm->timing_regs, ARRAY_SIZE(hwm->timing_regs)); ++ VEC_WRITE(VEC_DAC_C0, 0x0); /* DAC control/status -- not wired up in RP1 */ ++ VEC_WRITE(VEC_DAC_C4, 0x007bffff); /* DAC control -- not wired up in RP1 */ ++ misc = hwm->half_lines_per_field; ++ if (misc == 524 && (mode->vtotal >> vec->fake_31khz) == 263) ++ misc += 2; ++ if (tvstd == DRM_MODE_TV_MODE_NTSC_J && mode_family == 0) { ++ /* NTSC-J modification: reduce pedestal and increase gain */ ++ VEC_WRITE(VEC_DAC_BC, ++ BITS(VEC_DAC_BC_U11_HALF_LINES_PER_FIELD, misc) | ++ BITS(VEC_DAC_BC_S11_PEDESTAL, 0x00a)); ++ VEC_WRITE(VEC_DAC_C8, ++ BITS(VEC_DAC_C8_U16_SCALE_LUMA, 0x9400) | ++ BITS(VEC_DAC_C8_U16_SCALE_SYNC, hwm->scale_sync)); ++ } else { ++ VEC_WRITE(VEC_DAC_BC, ++ BITS(VEC_DAC_BC_U11_HALF_LINES_PER_FIELD, misc) | ++ BITS(VEC_DAC_BC_S11_PEDESTAL, hwm->pedestal)); ++ VEC_WRITE(VEC_DAC_C8, ++ BITS(VEC_DAC_C8_U16_SCALE_LUMA, hwm->scale_luma) | ++ BITS(VEC_DAC_C8_U16_SCALE_SYNC, hwm->scale_sync)); ++ } ++ VEC_WRITE(VEC_DAC_CC, (tvstd >= DRM_MODE_TV_MODE_SECAM) ? 0 : hwm->scale_burst_chroma); ++ VEC_WRITE(VEC_DAC_D0, 0x02000000); /* ADC offsets -- not needed in RP1? */ ++ misc = hwm->misc; ++ if ((tvstd == DRM_MODE_TV_MODE_NTSC_443 || tvstd == DRM_MODE_TV_MODE_PAL) && ++ mode_family != 1) { ++ /* Change colour carrier frequency to 4433618.75 Hz; disable hard sync */ ++ VEC_WRITE(VEC_DAC_D4, 0xcc48c1d1); ++ VEC_WRITE(VEC_DAC_D8, 0x0a8262b2); ++ misc &= ~VEC_DAC_EC_SEQ_EN_BITS; ++ } else if (tvstd == DRM_MODE_TV_MODE_PAL_N && mode_family == 1) { ++ /* Change colour carrier frequency to 3582056.25 Hz */ ++ VEC_WRITE(VEC_DAC_D4, 0x9ce075f7); ++ VEC_WRITE(VEC_DAC_D8, 0x087da511); ++ } else { ++ VEC_WRITE(VEC_DAC_D4, (u32)(hwm->nco_freq)); ++ VEC_WRITE(VEC_DAC_D8, (u32)(hwm->nco_freq >> 32)); ++ } ++ VEC_WRITE(VEC_DAC_EC, misc | rp1vec_rate_shift_table[rate - 4]); ++ rp1vec_write_regs(vec, 0xDC, rp1vec_fir_regs, ARRAY_SIZE(rp1vec_fir_regs)); ++ ++ /* Set up interrupts and initialise VEC. It will start on the next rp1vec_hw_update() */ ++ VEC_WRITE(VEC_IRQ_FLAGS, 0xFFFFFFFFu); ++ rp1vec_hw_vblank_ctrl(vec, 1); + i = rp1vec_hw_busy(vec); + if (i) + dev_warn(&vec->pdev->dev, @@ -83129,6 +83747,10 @@ index 000000000000..b9a67a8a330c + */ + u64 a = addr + offset; + ++ if (vec->fake_31khz) { ++ a += stride; ++ stride *= 2; ++ } + VEC_WRITE(VEC_DMA_STRIDE, stride); + VEC_WRITE(VEC_DMA_ADDR_H, a >> 32); + VEC_WRITE(VEC_DMA_ADDR_L, a & 0xFFFFFFFFu); @@ -87408,7 +88030,7 @@ index 86d629e45307..06c791ace2d8 100644 if (!args->len) diff --git a/drivers/gpu/drm/vc4/vc4_crtc.c b/drivers/gpu/drm/vc4/vc4_crtc.c -index 8b5a7e5eb146..b86b5dc00c15 100644 +index 8b5a7e5eb146..697ced954a50 100644 --- a/drivers/gpu/drm/vc4/vc4_crtc.c +++ b/drivers/gpu/drm/vc4/vc4_crtc.c @@ -83,13 +83,22 @@ static unsigned int @@ -87620,7 +88242,24 @@ index 8b5a7e5eb146..b86b5dc00c15 100644 break; } -@@ -781,14 +843,21 @@ static void vc4_crtc_handle_page_flip(struct vc4_crtc *vc4_crtc) +@@ -765,12 +827,15 @@ static void vc4_disable_vblank(struct drm_crtc *crtc) + { + struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc); + struct drm_device *dev = crtc->dev; ++ struct drm_encoder *encoder = vc4_get_crtc_encoder(crtc, crtc->state); ++ struct vc4_encoder *vc4_encoder = to_vc4_encoder(encoder); + int idx; + + if (!drm_dev_enter(dev, &idx)) + return; + +- CRTC_WRITE(PV_INTEN, 0); ++ if (!vc4_encoder || vc4_encoder->type != VC4_ENCODER_TYPE_DSI0) ++ CRTC_WRITE(PV_INTEN, 0); + + drm_dev_exit(idx); + } +@@ -781,14 +846,21 @@ static void vc4_crtc_handle_page_flip(struct vc4_crtc *vc4_crtc) struct drm_device *dev = crtc->dev; struct vc4_dev *vc4 = to_vc4_dev(dev); struct vc4_hvs *hvs = vc4->hvs; @@ -87644,7 +88283,7 @@ index 8b5a7e5eb146..b86b5dc00c15 100644 drm_crtc_send_vblank_event(crtc, vc4_crtc->event); vc4_crtc->event = NULL; drm_crtc_vblank_put(crtc); -@@ -799,7 +868,8 @@ static void vc4_crtc_handle_page_flip(struct vc4_crtc *vc4_crtc) +@@ -799,7 +871,8 @@ static void vc4_crtc_handle_page_flip(struct vc4_crtc *vc4_crtc) * the CRTC and encoder already reconfigured, leading to * underruns. This can be seen when reconfiguring the CRTC. */ @@ -87654,7 +88293,22 @@ index 8b5a7e5eb146..b86b5dc00c15 100644 } spin_unlock(&vc4_crtc->irq_lock); spin_unlock_irqrestore(&dev->event_lock, flags); -@@ -913,7 +983,7 @@ static int vc4_async_set_fence_cb(struct drm_device *dev, +@@ -807,7 +880,14 @@ static void vc4_crtc_handle_page_flip(struct vc4_crtc *vc4_crtc) + + void vc4_crtc_handle_vblank(struct vc4_crtc *crtc) + { ++ struct drm_encoder *encoder = vc4_get_crtc_encoder(&crtc->base, crtc->base.state); ++ struct vc4_encoder *vc4_encoder = to_vc4_encoder(encoder); ++ + crtc->t_vblank = ktime_get(); ++ ++ if (vc4_encoder && vc4_encoder->vblank) ++ vc4_encoder->vblank(encoder); ++ + drm_crtc_handle_vblank(&crtc->base); + vc4_crtc_handle_page_flip(crtc); + } +@@ -913,7 +993,7 @@ static int vc4_async_set_fence_cb(struct drm_device *dev, struct dma_fence *fence; int ret; @@ -87663,7 +88317,7 @@ index 8b5a7e5eb146..b86b5dc00c15 100644 struct vc4_bo *bo = to_vc4_bo(&dma_bo->base); return vc4_queue_seqno_cb(dev, &flip_state->cb.seqno, bo->seqno, -@@ -1000,7 +1070,7 @@ static int vc4_async_page_flip(struct drm_crtc *crtc, +@@ -1000,7 +1080,7 @@ static int vc4_async_page_flip(struct drm_crtc *crtc, struct vc4_bo *bo = to_vc4_bo(&dma_bo->base); int ret; @@ -87672,7 +88326,7 @@ index 8b5a7e5eb146..b86b5dc00c15 100644 return -ENODEV; /* -@@ -1043,7 +1113,7 @@ int vc4_page_flip(struct drm_crtc *crtc, +@@ -1043,7 +1123,7 @@ int vc4_page_flip(struct drm_crtc *crtc, struct drm_device *dev = crtc->dev; struct vc4_dev *vc4 = to_vc4_dev(dev); @@ -87681,7 +88335,7 @@ index 8b5a7e5eb146..b86b5dc00c15 100644 return vc5_async_page_flip(crtc, fb, event, flags); else return vc4_async_page_flip(crtc, fb, event, flags); -@@ -1074,14 +1144,8 @@ void vc4_crtc_destroy_state(struct drm_crtc *crtc, +@@ -1074,14 +1154,8 @@ void vc4_crtc_destroy_state(struct drm_crtc *crtc, struct vc4_dev *vc4 = to_vc4_dev(crtc->dev); struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(state); @@ -87698,7 +88352,7 @@ index 8b5a7e5eb146..b86b5dc00c15 100644 drm_atomic_helper_crtc_destroy_state(crtc, state); } -@@ -1257,6 +1321,32 @@ const struct vc4_pv_data bcm2711_pv4_data = { +@@ -1257,6 +1331,32 @@ const struct vc4_pv_data bcm2711_pv4_data = { }, }; @@ -87731,7 +88385,7 @@ index 8b5a7e5eb146..b86b5dc00c15 100644 static const struct of_device_id vc4_crtc_dt_match[] = { { .compatible = "brcm,bcm2835-pixelvalve0", .data = &bcm2835_pv0_data }, { .compatible = "brcm,bcm2835-pixelvalve1", .data = &bcm2835_pv1_data }, -@@ -1266,6 +1356,8 @@ static const struct of_device_id vc4_crtc_dt_match[] = { +@@ -1266,6 +1366,8 @@ static const struct of_device_id vc4_crtc_dt_match[] = { { .compatible = "brcm,bcm2711-pixelvalve2", .data = &bcm2711_pv2_data }, { .compatible = "brcm,bcm2711-pixelvalve3", .data = &bcm2711_pv3_data }, { .compatible = "brcm,bcm2711-pixelvalve4", .data = &bcm2711_pv4_data }, @@ -87740,7 +88394,7 @@ index 8b5a7e5eb146..b86b5dc00c15 100644 {} }; -@@ -1338,21 +1430,38 @@ int __vc4_crtc_init(struct drm_device *drm, +@@ -1338,21 +1440,38 @@ int __vc4_crtc_init(struct drm_device *drm, drm_crtc_helper_add(crtc, crtc_helper_funcs); @@ -87750,8 +88404,8 @@ index 8b5a7e5eb146..b86b5dc00c15 100644 - drm_crtc_enable_color_mgmt(crtc, 0, false, crtc->gamma_size); + } -+ ++ + if (vc4->gen == VC4_GEN_4) { /* We support CTM, but only for one CRTC at a time. It's therefore * implemented as private driver state in vc4_kms, not here. @@ -88032,7 +88686,7 @@ index 1b3531374967..220e8625402b 100644 { .compatible = "brcm,cygnus-vc4", }, {}, diff --git a/drivers/gpu/drm/vc4/vc4_drv.h b/drivers/gpu/drm/vc4/vc4_drv.h -index bf66499765fb..70703d28b0b5 100644 +index bf66499765fb..c48314604b9e 100644 --- a/drivers/gpu/drm/vc4/vc4_drv.h +++ b/drivers/gpu/drm/vc4/vc4_drv.h @@ -14,6 +14,7 @@ @@ -88185,7 +88839,15 @@ index bf66499765fb..70703d28b0b5 100644 }; struct vc4_encoder { -@@ -490,6 +524,17 @@ struct drm_encoder *vc4_find_encoder_by_type(struct drm_device *drm, +@@ -469,6 +503,7 @@ struct vc4_encoder { + + void (*post_crtc_disable)(struct drm_encoder *encoder, struct drm_atomic_state *state); + void (*post_crtc_powerdown)(struct drm_encoder *encoder, struct drm_atomic_state *state); ++ void (*vblank)(struct drm_encoder *encoder); + }; + + #define to_vc4_encoder(_encoder) \ +@@ -490,6 +525,17 @@ struct drm_encoder *vc4_find_encoder_by_type(struct drm_device *drm, return NULL; } @@ -88203,7 +88865,7 @@ index bf66499765fb..70703d28b0b5 100644 struct vc4_crtc_data { const char *name; -@@ -502,7 +547,18 @@ struct vc4_crtc_data { +@@ -502,7 +548,18 @@ struct vc4_crtc_data { int hvs_output; }; @@ -88223,7 +88885,7 @@ index bf66499765fb..70703d28b0b5 100644 struct vc4_pv_data { struct vc4_crtc_data base; -@@ -524,6 +580,8 @@ extern const struct vc4_pv_data bcm2711_pv1_data; +@@ -524,6 +581,8 @@ extern const struct vc4_pv_data bcm2711_pv1_data; extern const struct vc4_pv_data bcm2711_pv2_data; extern const struct vc4_pv_data bcm2711_pv3_data; extern const struct vc4_pv_data bcm2711_pv4_data; @@ -88232,7 +88894,7 @@ index bf66499765fb..70703d28b0b5 100644 struct vc4_crtc { struct drm_crtc base; -@@ -534,9 +592,19 @@ struct vc4_crtc { +@@ -534,9 +593,19 @@ struct vc4_crtc { /* Timestamp at start of vblank irq - unaffected by lock delays. */ ktime_t t_vblank; @@ -88255,7 +88917,7 @@ index bf66499765fb..70703d28b0b5 100644 struct drm_pending_vblank_event *event; -@@ -568,6 +636,9 @@ struct vc4_crtc { +@@ -568,6 +637,9 @@ struct vc4_crtc { * access to that value. */ unsigned int current_hvs_channel; @@ -88265,7 +88927,7 @@ index bf66499765fb..70703d28b0b5 100644 }; #define to_vc4_crtc(_crtc) \ -@@ -587,22 +658,27 @@ vc4_crtc_to_vc4_pv_data(const struct vc4_crtc *crtc) +@@ -587,22 +659,27 @@ vc4_crtc_to_vc4_pv_data(const struct vc4_crtc *crtc) return container_of_const(data, struct vc4_pv_data, base); } @@ -88301,7 +88963,7 @@ index bf66499765fb..70703d28b0b5 100644 unsigned long hvs_load; -@@ -639,6 +715,12 @@ struct vc4_crtc_state { +@@ -639,6 +716,12 @@ struct vc4_crtc_state { writel(val, hvs->regs + (offset)); \ } while (0) @@ -88314,7 +88976,7 @@ index bf66499765fb..70703d28b0b5 100644 #define VC4_REG32(reg) { .name = #reg, .offset = reg } struct vc4_exec_info { -@@ -963,6 +1045,9 @@ extern struct platform_driver vc4_dsi_driver; +@@ -963,6 +1046,9 @@ extern struct platform_driver vc4_dsi_driver; /* vc4_fence.c */ extern const struct dma_fence_ops vc4_fence_ops; @@ -88324,7 +88986,7 @@ index bf66499765fb..70703d28b0b5 100644 /* vc4_gem.c */ int vc4_gem_init(struct drm_device *dev); int vc4_submit_cl_ioctl(struct drm_device *dev, void *data, -@@ -1001,10 +1086,14 @@ void vc4_irq_reset(struct drm_device *dev); +@@ -1001,10 +1087,14 @@ void vc4_irq_reset(struct drm_device *dev); /* vc4_hvs.c */ extern struct platform_driver vc4_hvs_driver; @@ -88340,7 +89002,7 @@ index bf66499765fb..70703d28b0b5 100644 int vc4_hvs_atomic_check(struct drm_crtc *crtc, struct drm_atomic_state *state); void vc4_hvs_atomic_begin(struct drm_crtc *crtc, struct drm_atomic_state *state); void vc4_hvs_atomic_enable(struct drm_crtc *crtc, struct drm_atomic_state *state); -@@ -1022,6 +1111,12 @@ int vc4_kms_load(struct drm_device *dev); +@@ -1022,6 +1112,12 @@ int vc4_kms_load(struct drm_device *dev); struct drm_plane *vc4_plane_init(struct drm_device *dev, enum drm_plane_type type, uint32_t possible_crtcs); @@ -88353,6 +89015,186 @@ index bf66499765fb..70703d28b0b5 100644 int vc4_plane_create_additional_planes(struct drm_device *dev); u32 vc4_plane_write_dlist(struct drm_plane *plane, u32 __iomem *dlist); u32 vc4_plane_dlist_size(const struct drm_plane_state *state); +diff --git a/drivers/gpu/drm/vc4/vc4_dsi.c b/drivers/gpu/drm/vc4/vc4_dsi.c +index 46f6c4ce61c5..894154d824ab 100644 +--- a/drivers/gpu/drm/vc4/vc4_dsi.c ++++ b/drivers/gpu/drm/vc4/vc4_dsi.c +@@ -358,6 +358,16 @@ + # define DSI_PHY_AFEC0_CTATADJ_MASK VC4_MASK(3, 0) + # define DSI_PHY_AFEC0_CTATADJ_SHIFT 0 + ++# define DSI0_AFEC0_PD_ALL_LANES (DSI0_PHY_AFEC0_PD | \ ++ DSI0_PHY_AFEC0_PD_BG | \ ++ DSI0_PHY_AFEC0_PD_DLANE1) ++ ++# define DSI1_AFEC0_PD_ALL_LANES (DSI1_PHY_AFEC0_PD | \ ++ DSI1_PHY_AFEC0_PD_BG | \ ++ DSI1_PHY_AFEC0_PD_DLANE3 | \ ++ DSI1_PHY_AFEC0_PD_DLANE2 | \ ++ DSI1_PHY_AFEC0_PD_DLANE1) ++ + #define DSI0_PHY_AFEC1 0x68 + # define DSI0_PHY_AFEC1_IDR_DLANE1_MASK VC4_MASK(10, 8) + # define DSI0_PHY_AFEC1_IDR_DLANE1_SHIFT 8 +@@ -398,7 +408,8 @@ + # define DSI1_CTRL_DISABLE_DISP_ECCC BIT(1) + # define DSI0_CTRL_CTRL0 BIT(0) + # define DSI1_CTRL_EN BIT(0) +-# define DSI0_CTRL_RESET_FIFOS (DSI_CTRL_CLR_LDF | \ ++# define DSI0_CTRL_RESET_FIFOS (DSI0_CTRL_CTRL0 | \ ++ DSI_CTRL_CLR_LDF | \ + DSI0_CTRL_CLR_PBCF | \ + DSI0_CTRL_CLR_CPBCF | \ + DSI0_CTRL_CLR_PDF | \ +@@ -807,6 +818,16 @@ static void vc4_dsi_bridge_disable(struct drm_bridge *bridge, + disp0_ctrl = DSI_PORT_READ(DISP0_CTRL); + disp0_ctrl &= ~DSI_DISP0_ENABLE; + DSI_PORT_WRITE(DISP0_CTRL, disp0_ctrl); ++ ++ /* Reset the DSI and all its fifos. */ ++ DSI_PORT_WRITE(CTRL, DSI_CTRL_SOFT_RESET_CFG | ++ DSI_PORT_BIT(CTRL_RESET_FIFOS)); ++ ++ /* Power down the analogue front end. */ ++ DSI_PORT_WRITE(PHY_AFEC0, DSI_PORT_BIT(PHY_AFEC0_RESET) | ++ DSI_PORT_BIT(PHY_AFEC0_PD) | ++ DSI_PORT_BIT(AFEC0_PD_ALL_LANES)); ++ + } + + static void vc4_dsi_bridge_post_disable(struct drm_bridge *bridge, +@@ -845,6 +866,7 @@ static bool vc4_dsi_bridge_mode_fixup(struct drm_bridge *bridge, + unsigned long pixel_clock_hz = mode->clock * 1000; + unsigned long pll_clock = pixel_clock_hz * dsi->divider; + int divider; ++ u16 htotal; + + /* Find what divider gets us a faster clock than the requested + * pixel clock. +@@ -861,12 +883,27 @@ static bool vc4_dsi_bridge_mode_fixup(struct drm_bridge *bridge, + pixel_clock_hz = pll_clock / dsi->divider; + + adjusted_mode->clock = pixel_clock_hz / 1000; ++ htotal = mode->htotal; ++ ++ if (dsi->variant->port == 0 && mode->clock == 30000 && ++ mode->hdisplay == 800 && mode->htotal == (800 + 59 + 2 + 45) && ++ mode->vdisplay == 480 && mode->vtotal == (480 + 7 + 2 + 22)) { ++ /* ++ * Raspberry Pi 7" panel via TC358762 seems to have an issue on ++ * DSI0 that it doesn't actually follow the vertical timing that ++ * is otherwise identical to that produced on DSI1. ++ * Fixup the mode. ++ */ ++ htotal = 800 + 59 + 2 + 47; ++ adjusted_mode->vtotal = 480 + 7 + 2 + 45; ++ adjusted_mode->crtc_vtotal = 480 + 7 + 2 + 45; ++ } + + /* Given the new pixel clock, adjust HFP to keep vrefresh the same. */ +- adjusted_mode->htotal = adjusted_mode->clock * mode->htotal / ++ adjusted_mode->htotal = adjusted_mode->clock * htotal / + mode->clock; +- adjusted_mode->hsync_end += adjusted_mode->htotal - mode->htotal; +- adjusted_mode->hsync_start += adjusted_mode->htotal - mode->htotal; ++ adjusted_mode->hsync_end += adjusted_mode->htotal - htotal; ++ adjusted_mode->hsync_start += adjusted_mode->htotal - htotal; + + return true; + } +@@ -926,12 +963,31 @@ static void vc4_dsi_bridge_pre_enable(struct drm_bridge *bridge, + "Failed to set phy clock to %ld: %d\n", phy_clock, ret); + } + +- /* Reset the DSI and all its fifos. */ ++ ret = clk_prepare_enable(dsi->escape_clock); ++ if (ret) { ++ DRM_ERROR("Failed to turn on DSI escape clock: %d\n", ret); ++ return; ++ } ++ ++ ret = clk_prepare_enable(dsi->pll_phy_clock); ++ if (ret) { ++ DRM_ERROR("Failed to turn on DSI PLL: %d\n", ret); ++ return; ++ } ++ ++ hs_clock = clk_get_rate(dsi->pll_phy_clock); ++ ++ /* ++ * Reset the DSI and all its fifos. The block must be enabled for the ++ * FIFO resets to trigger. ++ */ + DSI_PORT_WRITE(CTRL, + DSI_CTRL_SOFT_RESET_CFG | + DSI_PORT_BIT(CTRL_RESET_FIFOS)); + + DSI_PORT_WRITE(CTRL, ++ ((dsi->variant->port == 0) ? ++ DSI0_CTRL_CTRL0 : DSI1_CTRL_EN) | + DSI_CTRL_HSDT_EOT_DISABLE | + DSI_CTRL_RX_LPDT_EOT_DISABLE); + +@@ -984,20 +1040,6 @@ static void vc4_dsi_bridge_pre_enable(struct drm_bridge *bridge, + mdelay(1); + } + +- ret = clk_prepare_enable(dsi->escape_clock); +- if (ret) { +- DRM_ERROR("Failed to turn on DSI escape clock: %d\n", ret); +- return; +- } +- +- ret = clk_prepare_enable(dsi->pll_phy_clock); +- if (ret) { +- DRM_ERROR("Failed to turn on DSI PLL: %d\n", ret); +- return; +- } +- +- hs_clock = clk_get_rate(dsi->pll_phy_clock); +- + /* Yes, we set the DSI0P/DSI1P pixel clock to the byte rate, + * not the pixel clock rate. DSIxP take from the APHY's byte, + * DDR2, or DDR4 clock (we use byte) and feed into the PV at +@@ -1113,12 +1155,6 @@ static void vc4_dsi_bridge_pre_enable(struct drm_bridge *bridge, + DSI_DISP1_PFORMAT) | + DSI_DISP1_ENABLE); + +- /* Ungate the block. */ +- if (dsi->variant->port == 0) +- DSI_PORT_WRITE(CTRL, DSI_PORT_READ(CTRL) | DSI0_CTRL_CTRL0); +- else +- DSI_PORT_WRITE(CTRL, DSI_PORT_READ(CTRL) | DSI1_CTRL_EN); +- + /* Bring AFE out of reset. */ + DSI_PORT_WRITE(PHY_AFEC0, + DSI_PORT_READ(PHY_AFEC0) & +@@ -1418,6 +1454,15 @@ static const struct drm_bridge_funcs vc4_dsi_bridge_funcs = { + .mode_fixup = vc4_dsi_bridge_mode_fixup, + }; + ++static void vc4_dsi_reset_fifo(struct drm_encoder *encoder) ++{ ++ struct vc4_dsi *dsi = to_vc4_dsi(encoder); ++ u32 val; ++ ++ val = DSI_PORT_READ(CTRL); ++ DSI_PORT_WRITE(CTRL, val | DSI0_CTRL_CLR_PBCF); ++} ++ + static int vc4_dsi_late_register(struct drm_encoder *encoder) + { + struct drm_device *drm = encoder->dev; +@@ -1662,6 +1707,9 @@ static int vc4_dsi_bind(struct device *dev, struct device *master, void *data) + dsi->encoder.type = dsi->variant->port ? + VC4_ENCODER_TYPE_DSI1 : VC4_ENCODER_TYPE_DSI0; + ++ if (dsi->encoder.type == VC4_ENCODER_TYPE_DSI0) ++ dsi->encoder.vblank = vc4_dsi_reset_fifo; ++ + dsi->regs = vc4_ioremap_regs(pdev, 0); + if (IS_ERR(dsi->regs)) + return PTR_ERR(dsi->regs); diff --git a/drivers/gpu/drm/vc4/vc4_firmware_kms.c b/drivers/gpu/drm/vc4/vc4_firmware_kms.c new file mode 100644 index 000000000000..11ee7eadc804 @@ -90549,7 +91391,7 @@ index 03648f954985..0d94165d4b6b 100644 switch (args->madv) { diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b/drivers/gpu/drm/vc4/vc4_hdmi.c -index 4626fe9aac56..b76bb2c1e2b6 100644 +index 4626fe9aac56..e42b431c29af 100644 --- a/drivers/gpu/drm/vc4/vc4_hdmi.c +++ b/drivers/gpu/drm/vc4/vc4_hdmi.c @@ -41,6 +41,8 @@ @@ -90881,6 +91723,15 @@ index 4626fe9aac56..b76bb2c1e2b6 100644 card->dai_link = dai_link; card->num_links = 1; card->name = vc4_hdmi->variant->card_name; +@@ -2829,7 +2910,7 @@ static irqreturn_t vc4_hdmi_hpd_irq_thread(int irq, void *priv) + struct drm_connector *connector = &vc4_hdmi->connector; + struct drm_device *dev = connector->dev; + +- if (dev && dev->registered) ++ if (dev && dev->registered && !force_hotplug) + drm_connector_helper_hpd_irq_event(connector); + + return IRQ_HANDLED; @@ -3571,6 +3652,7 @@ static int vc4_hdmi_runtime_suspend(struct device *dev) { struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev); @@ -123597,10 +124448,10 @@ index 000000000000..a98aba03598a +obj-$(CONFIG_VIDEO_BCM2835_UNICAM) += bcm2835-unicam.o diff --git a/drivers/media/platform/bcm2835/bcm2835-unicam.c b/drivers/media/platform/bcm2835/bcm2835-unicam.c new file mode 100644 -index 000000000000..65f66327c04f +index 000000000000..a6ad0c0fbef6 --- /dev/null +++ b/drivers/media/platform/bcm2835/bcm2835-unicam.c -@@ -0,0 +1,3516 @@ +@@ -0,0 +1,3528 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * BCM283x / BCM271x Unicam Capture Driver @@ -123652,6 +124503,7 @@ index 000000000000..65f66327c04f +#include +#include +#include ++#include +#include +#include +#include @@ -124146,6 +124998,8 @@ index 000000000000..65f66327c04f + struct v4l2_device v4l2_dev; + struct media_device mdev; + ++ struct gpio_desc *sync_gpio; ++ + /* parent device */ + struct platform_device *pdev; + /* subdevice async Notifier */ @@ -124546,6 +125400,8 @@ index 000000000000..65f66327c04f + if (fe) { + bool inc_seq = unicam->frame_started; + ++ if (unicam->sync_gpio) ++ gpiod_set_value(unicam->sync_gpio, 0); + /* + * Ensure we have swapped buffers already as we can't + * stop the peripheral. If no buffer is available, use a @@ -124606,6 +125462,10 @@ index 000000000000..65f66327c04f + * aka frame start. + */ + ts = ktime_get_ns(); ++ ++ if (unicam->sync_gpio) ++ gpiod_set_value(unicam->sync_gpio, 1); ++ + for (i = 0; i < ARRAY_SIZE(unicam->node); i++) { + if (!unicam->node[i].streaming) + continue; @@ -127010,6 +127870,9 @@ index 000000000000..65f66327c04f + goto err_unicam_put; + } + ++ unicam->sync_gpio = devm_gpiod_get_optional(&pdev->dev, "sync", ++ GPIOD_OUT_LOW); ++ + ret = platform_get_irq(pdev, 0); + if (ret <= 0) { + dev_err(&pdev->dev, "No IRQ resource\n"); @@ -133003,10 +133866,10 @@ index 000000000000..637b63a838c4 +#endif diff --git a/drivers/media/platform/raspberrypi/rp1_cfe/cfe_fmts.h b/drivers/media/platform/raspberrypi/rp1_cfe/cfe_fmts.h new file mode 100644 -index 000000000000..72516c93c5c5 +index 000000000000..29c807253e64 --- /dev/null +++ b/drivers/media/platform/raspberrypi/rp1_cfe/cfe_fmts.h -@@ -0,0 +1,316 @@ +@@ -0,0 +1,318 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * RP1 Camera Front End formats definition @@ -133265,6 +134128,7 @@ index 000000000000..72516c93c5c5 + .code = MEDIA_BUS_FMT_Y8_1X8, + .depth = 8, + .csi_dt = MIPI_CSI2_DT_RAW8, ++ .remap = { V4L2_PIX_FMT_Y16, V4L2_PIX_FMT_PISP_COMP1_MONO }, + }, + { + .fourcc = V4L2_PIX_FMT_Y10P, @@ -133293,6 +134157,7 @@ index 000000000000..72516c93c5c5 + .depth = 16, + .csi_dt = MIPI_CSI2_DT_RAW16, + .flags = CFE_FORMAT_FLAG_FE_OUT, ++ .remap = { V4L2_PIX_FMT_Y16, V4L2_PIX_FMT_PISP_COMP1_MONO }, + }, + { + .fourcc = V4L2_PIX_FMT_PISP_COMP1_MONO, @@ -149621,10 +150486,21 @@ index 000000000000..80a6aea8d6c9 +}; +builtin_platform_driver(bcm2712_pinctrl_driver); diff --git a/drivers/pinctrl/bcm/pinctrl-bcm2835.c b/drivers/pinctrl/bcm/pinctrl-bcm2835.c -index 1489191a213f..8b178b8d7242 100644 +index 1489191a213f..cfb51cf2f766 100644 --- a/drivers/pinctrl/bcm/pinctrl-bcm2835.c +++ b/drivers/pinctrl/bcm/pinctrl-bcm2835.c -@@ -420,15 +420,32 @@ static void bcm2835_gpio_irq_handle_bank(struct bcm2835_pinctrl *pc, +@@ -244,6 +244,10 @@ static const char * const irq_type_names[] = { + [IRQ_TYPE_LEVEL_LOW] = "level-low", + }; + ++static bool persist_gpio_outputs = true; ++module_param(persist_gpio_outputs, bool, 0644); ++MODULE_PARM_DESC(persist_gpio_outputs, "Enable GPIO_OUT persistence when pin is freed"); ++ + static inline u32 bcm2835_gpio_rd(struct bcm2835_pinctrl *pc, unsigned reg) + { + return readl(pc->base + reg); +@@ -420,15 +424,32 @@ static void bcm2835_gpio_irq_handle_bank(struct bcm2835_pinctrl *pc, unsigned long events; unsigned offset; unsigned gpio; @@ -149657,7 +150533,7 @@ index 1489191a213f..8b178b8d7242 100644 } static void bcm2835_gpio_irq_handler(struct irq_desc *desc) -@@ -668,11 +685,7 @@ static int bcm2835_gpio_irq_set_type(struct irq_data *data, unsigned int type) +@@ -668,11 +689,7 @@ static int bcm2835_gpio_irq_set_type(struct irq_data *data, unsigned int type) static void bcm2835_gpio_irq_ack(struct irq_data *data) { @@ -149670,22 +150546,21 @@ index 1489191a213f..8b178b8d7242 100644 } static int bcm2835_gpio_irq_set_wake(struct irq_data *data, unsigned int on) -@@ -926,9 +939,12 @@ static int bcm2835_pmx_free(struct pinctrl_dev *pctldev, +@@ -926,6 +943,13 @@ static int bcm2835_pmx_free(struct pinctrl_dev *pctldev, unsigned offset) { struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev); + enum bcm2835_fsel fsel = bcm2835_pinctrl_fsel_get(pc, offset); + -+ /* Return non-GPIOs to GPIO_IN */ -+ if (fsel != BCM2835_FSEL_GPIO_IN && fsel != BCM2835_FSEL_GPIO_OUT) -+ bcm2835_pinctrl_fsel_set(pc, offset, BCM2835_FSEL_GPIO_IN); ++ if (fsel == BCM2835_FSEL_GPIO_IN) ++ return 0; ++ ++ if (persist_gpio_outputs && fsel == BCM2835_FSEL_GPIO_OUT) ++ return 0; -- /* disable by setting to GPIO_IN */ -- bcm2835_pinctrl_fsel_set(pc, offset, BCM2835_FSEL_GPIO_IN); - return 0; - } - -@@ -970,10 +986,7 @@ static void bcm2835_pmx_gpio_disable_free(struct pinctrl_dev *pctldev, + /* disable by setting to GPIO_IN */ + bcm2835_pinctrl_fsel_set(pc, offset, BCM2835_FSEL_GPIO_IN); +@@ -970,10 +994,7 @@ static void bcm2835_pmx_gpio_disable_free(struct pinctrl_dev *pctldev, struct pinctrl_gpio_range *range, unsigned offset) { @@ -149693,11 +150568,11 @@ index 1489191a213f..8b178b8d7242 100644 - - /* disable by setting to GPIO_IN */ - bcm2835_pinctrl_fsel_set(pc, offset, BCM2835_FSEL_GPIO_IN); -+ (void)bcm2835_pmx_free(pctldev, offset); ++ bcm2835_pmx_free(pctldev, offset); } static int bcm2835_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, -@@ -1355,7 +1368,7 @@ static int bcm2835_pinctrl_probe(struct platform_device *pdev) +@@ -1355,12 +1376,15 @@ static int bcm2835_pinctrl_probe(struct platform_device *pdev) girq->default_type = IRQ_TYPE_NONE; girq->handler = handle_level_irq; @@ -149706,12 +150581,20 @@ index 1489191a213f..8b178b8d7242 100644 if (err) { dev_err(dev, "could not add GPIO chip\n"); goto out_remove; + } + ++ dev_info(dev, "GPIO_OUT persistence: %s\n", ++ persist_gpio_outputs ? "yes" : "no"); ++ + return 0; + + out_remove: diff --git a/drivers/pinctrl/pinctrl-rp1.c b/drivers/pinctrl/pinctrl-rp1.c new file mode 100644 -index 000000000000..b2729c5e6a92 +index 000000000000..6684b171e98b --- /dev/null +++ b/drivers/pinctrl/pinctrl-rp1.c -@@ -0,0 +1,1600 @@ +@@ -0,0 +1,1605 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Driver for Raspberry Pi RP1 GPIO unit (pinctrl + GPIO) @@ -150287,6 +151170,10 @@ index 000000000000..b2729c5e6a92 + [IRQ_TYPE_LEVEL_LOW] = "level-low", +}; + ++static bool persist_gpio_outputs = true; ++module_param(persist_gpio_outputs, bool, 0644); ++MODULE_PARM_DESC(persist_gpio_outputs, "Enable GPIO_OUT persistence when pin is freed"); ++ +static int rp1_pinconf_set(struct pinctrl_dev *pctldev, + unsigned int offset, unsigned long *configs, + unsigned int num_configs); @@ -150915,11 +151802,12 @@ index 000000000000..b2729c5e6a92 + struct rp1_pin_info *pin = rp1_get_pin_pctl(pctldev, offset); + u32 fsel = rp1_get_fsel(pin); + -+ /* Return non-GPIOs to GPIO_IN */ -+ if (fsel != RP1_FSEL_GPIO) { -+ rp1_set_dir(pin, RP1_DIR_INPUT); -+ rp1_set_fsel(pin, RP1_FSEL_GPIO); -+ } ++ /* Return all pins to GPIO_IN, unless persist_gpio_outputs is set */ ++ if (persist_gpio_outputs && fsel == RP1_FSEL_GPIO) ++ return 0; ++ ++ rp1_set_dir(pin, RP1_DIR_INPUT); ++ rp1_set_fsel(pin, RP1_FSEL_GPIO); + + return 0; +} @@ -152575,7 +153463,7 @@ index e33d10df7a76..226ca4c62673 100644 dev_err(&rdev->dev, "Failed to configure PWM: %d\n", ret); return ret; diff --git a/drivers/regulator/rpi-panel-attiny-regulator.c b/drivers/regulator/rpi-panel-attiny-regulator.c -index f52c3d47ecea..477bd96312e5 100644 +index f52c3d47ecea..ab0250fe2837 100644 --- a/drivers/regulator/rpi-panel-attiny-regulator.c +++ b/drivers/regulator/rpi-panel-attiny-regulator.c @@ -143,24 +143,8 @@ static int attiny_lcd_power_disable(struct regulator_dev *rdev) @@ -152593,17 +153481,40 @@ index f52c3d47ecea..477bd96312e5 100644 - break; - usleep_range(10000, 12000); - } -- + - mutex_unlock(&state->lock); - - if (ret < 0) - return ret; - +- - return data & PC_RST_BRIDGE_N; + return state->port_states[REG_PORTC - REG_PORTA] & PC_RST_BRIDGE_N; } static const struct regulator_init_data attiny_regulator_default = { +@@ -386,6 +370,14 @@ static void attiny_i2c_remove(struct i2c_client *client) + mutex_destroy(&state->lock); + } + ++static void attiny_i2c_shutdown(struct i2c_client *client) ++{ ++ struct attiny_lcd *state = i2c_get_clientdata(client); ++ ++ regmap_write(state->regmap, REG_PWM, 0); ++ regmap_write(state->regmap, REG_POWERON, 0); ++} ++ + static const struct of_device_id attiny_dt_ids[] = { + { .compatible = "raspberrypi,7inch-touchscreen-panel-regulator" }, + {}, +@@ -400,6 +392,7 @@ static struct i2c_driver attiny_regulator_driver = { + }, + .probe = attiny_i2c_probe, + .remove = attiny_i2c_remove, ++ .shutdown = attiny_i2c_shutdown, + }; + + module_i2c_driver(attiny_regulator_driver); diff --git a/drivers/regulator/rpi-panel-v2-regulator.c b/drivers/regulator/rpi-panel-v2-regulator.c new file mode 100644 index 000000000000..2a885f94e6b7 @@ -159593,7 +160504,7 @@ index 000000000000..bc27a04ee9bd \ No newline at end of file diff --git a/drivers/staging/vc04_services/bcm2835-codec/bcm2835-v4l2-codec.c b/drivers/staging/vc04_services/bcm2835-codec/bcm2835-v4l2-codec.c new file mode 100644 -index 000000000000..b9640f71cc5d +index 000000000000..fed27d4cccd4 --- /dev/null +++ b/drivers/staging/vc04_services/bcm2835-codec/bcm2835-v4l2-codec.c @@ -0,0 +1,3964 @@ @@ -159855,14 +160766,14 @@ index 000000000000..b9640f71cc5d + }, { + .fourcc = V4L2_PIX_FMT_BGR32, + .depth = 32, -+ .bytesperline_align = { 32, 32, 32, 32, 32 }, ++ .bytesperline_align = { 64, 64, 64, 64, 64 }, + .flags = 0, + .mmal_fmt = MMAL_ENCODING_BGRA, + .size_multiplier_x2 = 2, + }, { + .fourcc = V4L2_PIX_FMT_RGBA32, + .depth = 32, -+ .bytesperline_align = { 32, 32, 32, 32, 32 }, ++ .bytesperline_align = { 64, 64, 64, 64, 64 }, + .flags = 0, + .mmal_fmt = MMAL_ENCODING_RGBA, + .size_multiplier_x2 = 2, @@ -175089,8 +176000,25 @@ index 000000000000..a896d73f7a93 + kref_put(&fsg->ref, fsg_release); +} +module_exit(fsg_cleanup); +diff --git a/drivers/usb/gadget/function/uvc_configfs.c b/drivers/usb/gadget/function/uvc_configfs.c +index 9bf0e985acfa..d16c04d2961b 100644 +--- a/drivers/usb/gadget/function/uvc_configfs.c ++++ b/drivers/usb/gadget/function/uvc_configfs.c +@@ -92,10 +92,10 @@ static int __uvcg_iter_item_entries(const char *page, size_t len, + + while (pg - page < len) { + i = 0; +- while (i < sizeof(buf) && (pg - page < len) && ++ while (i < bufsize && (pg - page < len) && + *pg != '\0' && *pg != '\n') + buf[i++] = *pg++; +- if (i == sizeof(buf)) { ++ if (i == bufsize) { + ret = -EINVAL; + goto out_free_buf; + } diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig -index 4448d0ab06f0..4228565fed85 100644 +index 4448d0ab06f0..fdd73e4d4ad8 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig @@ -678,6 +678,16 @@ config USB_RENESAS_USBHS_HCD @@ -175099,7 +176027,7 @@ index 4448d0ab06f0..4228565fed85 100644 +config USB_DWCOTG + bool "Synopsis DWC host support" -+ depends on USB && (FIQ || ARM64) ++ depends on USB=y && (FIQ || ARM64) + help + The Synopsis DWC controller is a dual-role + host/peripheral/OTG ("On The Go") USB controllers. @@ -231861,16 +232789,17 @@ index 000000000000..14a0d9b03739 +MODULE_DESCRIPTION("Raspberry Pi mailbox based Backlight Driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/video/fbdev/Kconfig b/drivers/video/fbdev/Kconfig -index 35b3ca2fb50a..a9718a3de63c 100644 +index 35b3ca2fb50a..9682b8711f71 100644 --- a/drivers/video/fbdev/Kconfig +++ b/drivers/video/fbdev/Kconfig -@@ -61,6 +61,20 @@ config FB_MACMODES +@@ -61,6 +61,21 @@ config FB_MACMODES tristate depends on FB +config FB_BCM2708 + tristate "BCM2708 framebuffer support" + depends on FB && RASPBERRYPI_FIRMWARE ++ select FB_DEVICE + select FB_CFB_FILLRECT + select FB_CFB_COPYAREA + select FB_CFB_IMAGEBLIT @@ -231885,7 +232814,7 @@ index 35b3ca2fb50a..a9718a3de63c 100644 config FB_GRVGA tristate "Aeroflex Gaisler framebuffer support" depends on FB && SPARC -@@ -1963,6 +1977,19 @@ config FB_LS2K500 +@@ -1963,6 +1978,19 @@ config FB_LS2K500 If you want to compile it as a module, say M here and read . @@ -238978,7 +239907,7 @@ index e3f5680a564c..ded9cf87d603 100644 for (;;) { tmp = *p; diff --git a/mm/page_alloc.c b/mm/page_alloc.c -index b17fec17f6bf..d769c3173c1b 100644 +index 4652dc453964..b9ab4d4b2353 100644 --- a/mm/page_alloc.c +++ b/mm/page_alloc.c @@ -206,6 +206,27 @@ EXPORT_SYMBOL(node_states); @@ -239009,7 +239938,7 @@ index b17fec17f6bf..d769c3173c1b 100644 /* * A cached value of the page's pageblock's migratetype, used when the page is * put on a pcplist. Used to avoid the pageblock migratetype lookup when -@@ -2120,12 +2141,13 @@ __rmqueue(struct zone *zone, unsigned int order, int migratetype, +@@ -2123,12 +2144,13 @@ __rmqueue(struct zone *zone, unsigned int order, int migratetype, if (IS_ENABLED(CONFIG_CMA)) { /* * Balance movable allocations between regular and CMA areas by @@ -240942,10 +241871,10 @@ index 7c2d7899603b..46d1ece070a3 100644 +obj-$(CONFIG_SND_DACBERRY400) += snd-soc-dacberry400.o diff --git a/sound/soc/bcm/allo-boss-dac.c b/sound/soc/bcm/allo-boss-dac.c new file mode 100644 -index 000000000000..cd817730ab40 +index 000000000000..a5d37004ac98 --- /dev/null +++ b/sound/soc/bcm/allo-boss-dac.c -@@ -0,0 +1,468 @@ +@@ -0,0 +1,471 @@ +/* + * ALSA ASoC Machine Driver for Allo Boss DAC + * @@ -241226,6 +242155,9 @@ index 000000000000..cd817730ab40 + struct snd_soc_component *component = asoc_rtd_to_codec(rtd, 0)->component; + struct snd_soc_card *card = rtd->card; + ++ /* Using powers of 2 allows for an integer clock divisor */ ++ width = width <= 16 ? 16 : 32; ++ + /* Mute before changing sample rate */ + snd_allo_boss_gpio_mute(card); + @@ -244142,10 +245074,10 @@ index 000000000000..61640fb95431 +MODULE_LICENSE("GPL v2"); diff --git a/sound/soc/bcm/audioinjector-isolated-soundcard.c b/sound/soc/bcm/audioinjector-isolated-soundcard.c new file mode 100644 -index 000000000000..127d49691935 +index 000000000000..1bb3c2cea693 --- /dev/null +++ b/sound/soc/bcm/audioinjector-isolated-soundcard.c -@@ -0,0 +1,183 @@ +@@ -0,0 +1,184 @@ +/* + * ASoC Driver for AudioInjector.net isolated soundcard + * @@ -244264,6 +245196,7 @@ index 000000000000..127d49691935 + +static struct snd_soc_card snd_soc_audioinjector_isolated = { + .name = "audioinjector-isolated-soundcard", ++ .owner = THIS_MODULE, + .dai_link = audioinjector_isolated_dai, + .num_links = ARRAY_SIZE(audioinjector_isolated_dai), + @@ -244684,10 +245617,10 @@ index 000000000000..b6395f04d1e3 +MODULE_ALIAS("platform:audioinjector-octo-soundcard"); diff --git a/sound/soc/bcm/audioinjector-pi-soundcard.c b/sound/soc/bcm/audioinjector-pi-soundcard.c new file mode 100644 -index 000000000000..ad337201c558 +index 000000000000..e675cceb3d69 --- /dev/null +++ b/sound/soc/bcm/audioinjector-pi-soundcard.c -@@ -0,0 +1,189 @@ +@@ -0,0 +1,190 @@ +/* + * ASoC Driver for AudioInjector Pi add on soundcard + * @@ -244815,6 +245748,7 @@ index 000000000000..ad337201c558 + +static struct snd_soc_card snd_soc_audioinjector = { + .name = "audioinjector-pi-soundcard", ++ .owner = THIS_MODULE, + .dai_link = audioinjector_pi_soundcard_dai, + .num_links = ARRAY_SIZE(audioinjector_pi_soundcard_dai), + @@ -246159,10 +247093,10 @@ index 000000000000..4649c6f75c59 +MODULE_LICENSE("GPL v2"); diff --git a/sound/soc/bcm/dionaudio_loco-v2.c b/sound/soc/bcm/dionaudio_loco-v2.c new file mode 100644 -index 000000000000..ca48aef621b6 +index 000000000000..49aeaf121a3f --- /dev/null +++ b/sound/soc/bcm/dionaudio_loco-v2.c -@@ -0,0 +1,117 @@ +@@ -0,0 +1,118 @@ +/* + * ASoC Driver for Dion Audio LOCO-V2 DAC-AMP + * @@ -246224,6 +247158,7 @@ index 000000000000..ca48aef621b6 +/* audio machine driver */ +static struct snd_soc_card snd_rpi_dionaudio_loco_v2 = { + .name = "Dion Audio LOCO-V2", ++ .owner = THIS_MODULE, + .dai_link = snd_rpi_dionaudio_loco_v2_dai, + .num_links = ARRAY_SIZE(snd_rpi_dionaudio_loco_v2_dai), +}; @@ -246282,10 +247217,10 @@ index 000000000000..ca48aef621b6 +MODULE_LICENSE("GPL v2"); diff --git a/sound/soc/bcm/dionaudio_loco.c b/sound/soc/bcm/dionaudio_loco.c new file mode 100644 -index 000000000000..48deb4cd3c8e +index 000000000000..06c0c01c87ee --- /dev/null +++ b/sound/soc/bcm/dionaudio_loco.c -@@ -0,0 +1,117 @@ +@@ -0,0 +1,121 @@ +/* + * ASoC Driver for Dion Audio LOCO DAC-AMP + * @@ -246322,6 +247257,9 @@ index 000000000000..48deb4cd3c8e + unsigned int sample_bits = + snd_pcm_format_width(params_format(params)); + ++ /* Using powers of 2 allows for an integer clock divisor */ ++ sample_bits = sample_bits <= 16 ? 16 : 32; ++ + return snd_soc_dai_set_bclk_ratio(cpu_dai, sample_bits * 2); +} + @@ -246350,6 +247288,7 @@ index 000000000000..48deb4cd3c8e +/* audio machine driver */ +static struct snd_soc_card snd_rpi_dionaudio_loco = { + .name = "snd_rpi_dionaudio_loco", ++ .owner = THIS_MODULE, + .dai_link = snd_rpi_dionaudio_loco_dai, + .num_links = ARRAY_SIZE(snd_rpi_dionaudio_loco_dai), +}; @@ -246785,10 +247724,10 @@ index 000000000000..a2015896966c +MODULE_LICENSE("GPL v2"); diff --git a/sound/soc/bcm/hifiberry_dacplus.c b/sound/soc/bcm/hifiberry_dacplus.c new file mode 100644 -index 000000000000..0cd7979dee54 +index 000000000000..e400b1159836 --- /dev/null +++ b/sound/soc/bcm/hifiberry_dacplus.c -@@ -0,0 +1,560 @@ +@@ -0,0 +1,563 @@ +/* + * ASoC Driver for HiFiBerry DAC+ / DAC Pro / AMP100 + * @@ -247088,6 +248027,9 @@ index 000000000000..0cd7979dee54 + int channels = params_channels(params); + int width = snd_pcm_format_width(params_format(params)); + ++ /* Using powers of 2 allows for an integer clock divisor */ ++ width = width <= 16 ? 16 : 32; ++ + if (snd_rpi_hifiberry_is_dacpro) { + struct snd_soc_component *component = asoc_rtd_to_codec(rtd, 0)->component; + @@ -247351,10 +248293,10 @@ index 000000000000..0cd7979dee54 +MODULE_LICENSE("GPL v2"); diff --git a/sound/soc/bcm/hifiberry_dacplusadc.c b/sound/soc/bcm/hifiberry_dacplusadc.c new file mode 100644 -index 000000000000..55e8e3eb00da +index 000000000000..9d2711485e0e --- /dev/null +++ b/sound/soc/bcm/hifiberry_dacplusadc.c -@@ -0,0 +1,396 @@ +@@ -0,0 +1,399 @@ +/* + * ASoC Driver for HiFiBerry DAC+ / DAC Pro with ADC + * @@ -247588,6 +248530,9 @@ index 000000000000..55e8e3eb00da + int channels = params_channels(params); + int width = snd_pcm_format_width(params_format(params)); + ++ /* Using powers of 2 allows for an integer clock divisor */ ++ width = width <= 16 ? 16 : 32; ++ + if (snd_rpi_hifiberry_is_dacpro) { + struct snd_soc_component *component = asoc_rtd_to_codec(rtd, 0)->component; + @@ -247753,10 +248698,10 @@ index 000000000000..55e8e3eb00da +MODULE_LICENSE("GPL v2"); diff --git a/sound/soc/bcm/hifiberry_dacplusadcpro.c b/sound/soc/bcm/hifiberry_dacplusadcpro.c new file mode 100644 -index 000000000000..17ca9dfe5442 +index 000000000000..70e59c0cd797 --- /dev/null +++ b/sound/soc/bcm/hifiberry_dacplusadcpro.c -@@ -0,0 +1,603 @@ +@@ -0,0 +1,606 @@ +/* + * ASoC Driver for HiFiBerry DAC+ / DAC Pro with ADC PRO Version (SW control) + * @@ -248148,6 +249093,9 @@ index 000000000000..17ca9dfe5442 + struct snd_soc_dai_driver *drv = dai->driver; + const struct snd_soc_dai_ops *ops = drv->ops; + ++ /* Using powers of 2 allows for an integer clock divisor */ ++ width = width <= 16 ? 16 : 32; ++ + if (snd_rpi_hifiberry_is_dacpro) { + snd_rpi_hifiberry_dacplusadcpro_set_sclk(dac, + params_rate(params)); @@ -248702,10 +249650,10 @@ index 000000000000..7e7e514a3019 +MODULE_LICENSE("GPL v2"); diff --git a/sound/soc/bcm/i-sabre-q2m.c b/sound/soc/bcm/i-sabre-q2m.c new file mode 100644 -index 000000000000..dfd1644cb94a +index 000000000000..502b9847be19 --- /dev/null +++ b/sound/soc/bcm/i-sabre-q2m.c -@@ -0,0 +1,159 @@ +@@ -0,0 +1,160 @@ +/* + * ASoC Driver for I-Sabre Q2M + * @@ -248761,8 +249709,9 @@ index 000000000000..dfd1644cb94a + struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0); + int bclk_ratio; + -+ bclk_ratio = snd_pcm_format_width( -+ params_format(params)) * params_channels(params); ++ /* Using powers of 2 allows for an integer clock divisor */ ++ bclk_ratio = (snd_pcm_format_width(params_format(params)) <= 16 ? 16 : 32) * ++ params_channels(params); + return snd_soc_dai_set_bclk_ratio(cpu_dai, bclk_ratio); +} + @@ -251356,10 +252305,10 @@ index 000000000000..688be6e189c6 +MODULE_LICENSE("GPL v2"); diff --git a/sound/soc/bcm/rpi-cirrus.c b/sound/soc/bcm/rpi-cirrus.c new file mode 100644 -index 000000000000..6e317b31d9ac +index 000000000000..679e8a064f9b --- /dev/null +++ b/sound/soc/bcm/rpi-cirrus.c -@@ -0,0 +1,1024 @@ +@@ -0,0 +1,1027 @@ +/* + * ASoC machine driver for Cirrus Logic Audio Card + * (with WM5102 and WM8804 codecs) @@ -252070,6 +253019,9 @@ index 000000000000..6e317b31d9ac + unsigned int rate = params_rate(params); + unsigned int clk_freq = calc_sysclk(rate); + ++ /* Using powers of 2 allows for an integer clock divisor */ ++ width = width <= 16 ? 16 : 32; ++ + mutex_lock(&priv->lock); + + dev_dbg(card->dev, "hw_params: setting rate to %d\n", rate); @@ -252539,10 +253491,10 @@ index 000000000000..9a5cf91719fb +MODULE_LICENSE("GPL"); diff --git a/sound/soc/bcm/rpi-simple-soundcard.c b/sound/soc/bcm/rpi-simple-soundcard.c new file mode 100644 -index 000000000000..1c6b55b80cae +index 000000000000..cc0f123570cd --- /dev/null +++ b/sound/soc/bcm/rpi-simple-soundcard.c -@@ -0,0 +1,520 @@ +@@ -0,0 +1,523 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * rpi-simple-soundcard.c -- ALSA SoC Raspberry Pi soundcard. @@ -252679,10 +253631,13 @@ index 000000000000..1c6b55b80cae + return 0; // BCLK is configured in .init + + /* The simple drivers just set the bclk_ratio to sample_bits * 2 so -+ * hard-code this for now. More complex drivers could just replace ++ * hard-code this for now, but sticking to powers of 2 to allow for ++ * integer clock divisors. More complex drivers could just replace + * the hw_params routine. + */ + sample_bits = snd_pcm_format_width(params_format(params)); ++ sample_bits = sample_bits <= 16 ? 16 : 32; ++ + return snd_soc_dai_set_bclk_ratio(cpu_dai, sample_bits * 2); +} + diff --git a/raspberrypi-kernel.spec b/raspberrypi-kernel.spec index 8cb78ba..9ede26a 100644 --- a/raspberrypi-kernel.spec +++ b/raspberrypi-kernel.spec @@ -2,13 +2,13 @@ %global KernelVer %{version}-%{release}.raspi.%{_target_cpu} -%global hulkrelease 25.0.0 +%global hulkrelease 26.0.0 %global debug_package %{nil} Name: raspberrypi-kernel Version: 6.6.0 -Release: %{hulkrelease}.3 +Release: %{hulkrelease}.4 Summary: Linux Kernel License: GPLv2 URL: http://www.kernel.org/ @@ -260,12 +260,16 @@ fi /usr/src/kernels/%{KernelVer} %changelog +* Wed May 15 2024 heppen - 6.6.0-26.0.0.4 +- update kernel version to openEuler 6.6.0-26.0.0 +- update Raspberry Pi patch, last commit (abc50146600eb2cb93aec321d003970296950343): staging: bcm2835-codec: 32bpp RGB formats need a 64byte alignment + * Fri May 10 2024 heppen - 6.6.0-25.0.0.3 -- update kernel version to openEuler 6.6.0.25.0.0 +- update kernel version to openEuler 6.6.0-25.0.0 * Thu Apr 25 2024 heppen - 6.6.0-22.0.0.2 - add subpackage raspberrypi-kernel-devel -- update kernel version to openEuler 6.6.0.22.0.0 +- update kernel version to openEuler 6.6.0-22.0.0 * Wed Apr 17 2024 Yafen Fang - 6.6.0-19.0.0.1 - update kernel version to openEuler 6.6.0-19.0.0