diff --git a/0000-raspberrypi-kernel.patch b/0000-raspberrypi-kernel.patch index 0e60454..c8ae472 100644 --- a/0000-raspberrypi-kernel.patch +++ b/0000-raspberrypi-kernel.patch @@ -1,162 +1,187 @@ -From 841ff0f5f922bae6091ade91698cbe5c3b5650cb Mon Sep 17 00:00:00 2001 -From: yafen -Date: Sun, 22 May 2022 05:00:13 +0800 -Subject: [PATCH] apply RPi patch of 5.10.95 +From b609199a78451b9d24d2432728a2fba22afc3bff Mon Sep 17 00:00:00 2001 +From: Yafen +Date: Tue, 16 Apr 2024 06:59:06 +0800 +Subject: [PATCH] apply RPi patch of 6.6.26 (openEuler 6.6.0-19.0.0) --- .../admin-guide/media/bcm2835-isp.rst | 127 + - .../clock/raspberrypi,firmware-clocks.yaml | 32 + - .../bindings/display/brcm,bcm2711-hdmi.yaml | 20 +- + .../bindings/display/brcm,bcm2711-hdmi.yaml | 2 + .../bindings/display/brcm,bcm2835-dsi0.yaml | 1 + - .../bindings/display/brcm,bcm2835-hdmi.yaml | 118 +- - .../bindings/display/brcm,bcm2835-vc4.yaml | 5 + - .../bindings/display/brcm,bcm2835-vec.yaml | 4 +- + .../bindings/display/brcm,bcm2835-hvs.yaml | 5 +- + .../display/brcm,bcm2835-pixelvalve0.yaml | 3 + + .../bindings/display/brcm,bcm2835-txp.yaml | 5 +- + .../bindings/display/brcm,bcm2835-vc4.yaml | 1 + + .../display/panel/ilitek,ili9881c.yaml | 2 + + .../bindings/display/panel/panel-dsi.yaml | 118 + .../bindings/display/panel/panel-simple.yaml | 4 + - .../devicetree/bindings/hwmon/rpi-poe-fan.txt | 55 + + .../devicetree/bindings/gpu/brcm,bcm-v3d.yaml | 1 + + .../bindings/hwmon/microchip,emc2305.yaml | 54 + .../bindings/media/bcm2835-unicam.txt | 85 + - .../devicetree/bindings/media/i2c/imx219.txt | 59 + - .../devicetree/bindings/media/i2c/imx290.txt | 7 +- + .../devicetree/bindings/media/i2c/ad5398.txt | 20 + + .../bindings/media/i2c/arducam,64mp.yaml | 115 + + .../bindings/media/i2c/arducam-pivariety.yaml | 112 + + .../media/i2c/dongwoon,dw9807-vcm.yaml | 16 +- .../devicetree/bindings/media/i2c/imx378.yaml | 113 + .../devicetree/bindings/media/i2c/imx477.yaml | 113 + .../devicetree/bindings/media/i2c/imx519.yaml | 113 + .../devicetree/bindings/media/i2c/irs1125.txt | 48 + + .../bindings/media/i2c/ovti,ov64a40.yaml | 98 + + .../bindings/media/i2c/rohm,bu64754.yaml | 48 + + .../i2c/{imx258.yaml => sony,imx258.yaml} | 9 +- + .../bindings/media/i2c/sony,imx708.yaml | 128 + .../bindings/media/rpivid_hevc.yaml | 72 + .../bindings/misc/brcm,bcm2835-smi-dev.txt | 17 + .../bindings/misc/brcm,bcm2835-smi.txt | 48 + + .../bindings/mmc/snps,dwcmshc-sdhci.yaml | 5 + + .../devicetree/bindings/net/cdns,macb.yaml | 16 + .../bindings/net/microchip,lan78xx.txt | 3 + - .../devicetree/bindings/nvmem/rmem.yaml | 49 + + .../bindings/pci/brcm,stb-pcie.yaml | 8 + .../devicetree/bindings/pci/brcmstb-pcie.txt | 59 + - .../bindings/power/reset/gpio-poweroff.txt | 1 + + .../bindings/power/reset/gpio-poweroff.txt | 42 + + .../devicetree/bindings/pwm/pwm-rp1.yaml | 38 + + .../devicetree/bindings/rtc/rtc-rpi.txt | 22 + .../devicetree/bindings/serial/pl011.yaml | 6 + + .../devicetree/bindings/sound/pcm512x.txt | 9 +- + .../devicetree/bindings/spi/spi-gpio.yaml | 4 + + .../devicetree/bindings/usb/snps,dwc3.yaml | 9 +- .../devicetree/bindings/vendor-prefixes.txt | 463 ++ - .../devicetree/bindings/vendor-prefixes.yaml | 4 + + .../devicetree/bindings/vendor-prefixes.yaml | 6 + .../devicetree/configfs-overlays.txt | 31 + - Documentation/hwmon/rpi-poe-fan | 15 + + Documentation/driver-api/pwm.rst | 17 +- .../userspace-api/media/drivers/index.rst | 1 + - .../media/v4l/ext-ctrls-codec.rst | 46 +- - .../media/v4l/ext-ctrls-image-source.rst | 20 + .../userspace-api/media/v4l/meta-formats.rst | 2 + - .../media/v4l/pixfmt-compressed.rst | 1 + .../v4l/pixfmt-meta-bcm2835-isp-stats.rst | 41 + .../media/v4l/pixfmt-meta-sensor-data.rst | 32 + .../media/v4l/pixfmt-nv12-col128.rst | 215 + - .../userspace-api/media/v4l/pixfmt-nv12.rst | 14 +- .../userspace-api/media/v4l/pixfmt-y12p.rst | 45 + .../userspace-api/media/v4l/pixfmt-y14p.rst | 54 + - .../media/v4l/subdev-formats.rst | 144 + - .../userspace-api/media/v4l/yuv-formats.rst | 3 + - MAINTAINERS | 48 + - Makefile | 3 + - arch/arm/boot/dts/Makefile | 31 +- - arch/arm/boot/dts/bcm2708-rpi-b-plus.dts | 131 + - arch/arm/boot/dts/bcm2708-rpi-b-rev1.dts | 134 + - arch/arm/boot/dts/bcm2708-rpi-b.dts | 121 + - arch/arm/boot/dts/bcm2708-rpi-bt.dtsi | 26 + - arch/arm/boot/dts/bcm2708-rpi-cm.dts | 106 + - arch/arm/boot/dts/bcm2708-rpi-cm.dtsi | 22 + - arch/arm/boot/dts/bcm2708-rpi-zero-w.dts | 178 + - arch/arm/boot/dts/bcm2708-rpi-zero.dts | 125 + - arch/arm/boot/dts/bcm2708-rpi.dtsi | 36 + - arch/arm/boot/dts/bcm2708.dtsi | 12 + - arch/arm/boot/dts/bcm2709-rpi-2-b.dts | 131 + - arch/arm/boot/dts/bcm2709-rpi.dtsi | 5 + - arch/arm/boot/dts/bcm2709.dtsi | 22 + - arch/arm/boot/dts/bcm270x-rpi.dtsi | 155 + - arch/arm/boot/dts/bcm270x.dtsi | 272 + - arch/arm/boot/dts/bcm2710-rpi-2-b.dts | 131 + - arch/arm/boot/dts/bcm2710-rpi-3-b-plus.dts | 210 + - arch/arm/boot/dts/bcm2710-rpi-3-b.dts | 212 + - arch/arm/boot/dts/bcm2710-rpi-cm3.dts | 146 + - arch/arm/boot/dts/bcm2710-rpi-zero-2-w.dts | 199 + - arch/arm/boot/dts/bcm2710-rpi-zero-2.dts | 1 + - arch/arm/boot/dts/bcm2710.dtsi | 25 + - arch/arm/boot/dts/bcm2711-rpi-4-b.dts | 330 +- - arch/arm/boot/dts/bcm2711-rpi-400.dts | 637 ++ - arch/arm/boot/dts/bcm2711-rpi-cm4.dts | 652 ++ - arch/arm/boot/dts/bcm2711-rpi-cm4s.dts | 467 ++ - arch/arm/boot/dts/bcm2711-rpi.dtsi | 205 + - arch/arm/boot/dts/bcm2711.dtsi | 72 +- - arch/arm/boot/dts/bcm271x-rpi-bt.dtsi | 26 + - arch/arm/boot/dts/bcm2835-common.dtsi | 14 +- - arch/arm/boot/dts/bcm2835-rpi-a-plus.dts | 5 + - arch/arm/boot/dts/bcm2835-rpi-a.dts | 7 + - arch/arm/boot/dts/bcm2835-rpi-b-plus.dts | 5 + - arch/arm/boot/dts/bcm2835-rpi-b-rev2.dts | 7 + - arch/arm/boot/dts/bcm2835-rpi-b.dts | 7 + - arch/arm/boot/dts/bcm2835-rpi-cm1-io1.dts | 5 + - arch/arm/boot/dts/bcm2835-rpi-zero-w.dts | 5 + - arch/arm/boot/dts/bcm2835-rpi-zero.dts | 5 + - arch/arm/boot/dts/bcm2835-rpi.dtsi | 19 +- - arch/arm/boot/dts/bcm2835.dtsi | 2 +- - arch/arm/boot/dts/bcm2836-rpi-2-b.dts | 5 + - arch/arm/boot/dts/bcm2837-rpi-3-a-plus.dts | 5 + - arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts | 5 + - arch/arm/boot/dts/bcm2837-rpi-3-b.dts | 5 + - arch/arm/boot/dts/bcm2837-rpi-cm3-io3.dts | 5 + - arch/arm/boot/dts/bcm283x-rpi-csi0-2lane.dtsi | 4 + - arch/arm/boot/dts/bcm283x-rpi-csi1-2lane.dtsi | 4 + - arch/arm/boot/dts/bcm283x-rpi-csi1-4lane.dtsi | 4 + - .../boot/dts/bcm283x-rpi-i2c0mux_0_28.dtsi | 4 + - .../boot/dts/bcm283x-rpi-i2c0mux_0_44.dtsi | 4 + - .../boot/dts/bcm283x-rpi-usb-peripheral.dtsi | 7 - - arch/arm/boot/dts/bcm283x.dtsi | 34 +- - arch/arm/boot/dts/overlays/Makefile | 257 + - arch/arm/boot/dts/overlays/README | 3861 +++++++++ - .../arm/boot/dts/overlays/act-led-overlay.dts | 27 + + .../media/v4l/pixfmt-yuv-planar.rst | 12 + + .../media/v4l/subdev-formats.rst | 143 + + .../userspace-api/media/v4l/yuv-formats.rst | 21 + + MAINTAINERS | 83 +- + README.md | 30 + + arch/arm/boot/dts/Makefile | 5 + + arch/arm/boot/dts/broadcom/Makefile | 35 + + .../boot/dts/broadcom/bcm2708-rpi-b-plus.dts | 210 + + .../boot/dts/broadcom/bcm2708-rpi-b-rev1.dts | 223 + + arch/arm/boot/dts/broadcom/bcm2708-rpi-b.dts | 198 + + .../arm/boot/dts/broadcom/bcm2708-rpi-bt.dtsi | 38 + + arch/arm/boot/dts/broadcom/bcm2708-rpi-cm.dts | 174 + + .../arm/boot/dts/broadcom/bcm2708-rpi-cm.dtsi | 27 + + .../boot/dts/broadcom/bcm2708-rpi-zero-w.dts | 254 + + .../boot/dts/broadcom/bcm2708-rpi-zero.dts | 189 + + arch/arm/boot/dts/broadcom/bcm2708-rpi.dtsi | 57 + + arch/arm/boot/dts/broadcom/bcm2708.dtsi | 19 + + .../arm/boot/dts/broadcom/bcm2709-rpi-2-b.dts | 204 + + .../arm/boot/dts/broadcom/bcm2709-rpi-cm2.dts | 223 + + arch/arm/boot/dts/broadcom/bcm2709-rpi.dtsi | 8 + + arch/arm/boot/dts/broadcom/bcm2709.dtsi | 29 + + arch/arm/boot/dts/broadcom/bcm270x-rpi.dtsi | 186 + + arch/arm/boot/dts/broadcom/bcm270x.dtsi | 294 + + .../arm/boot/dts/broadcom/bcm2710-rpi-2-b.dts | 204 + + .../dts/broadcom/bcm2710-rpi-3-b-plus.dts | 299 + + .../arm/boot/dts/broadcom/bcm2710-rpi-3-b.dts | 297 + + .../arm/boot/dts/broadcom/bcm2710-rpi-cm3.dts | 223 + + .../dts/broadcom/bcm2710-rpi-zero-2-w.dts | 261 + + .../boot/dts/broadcom/bcm2710-rpi-zero-2.dts | 1 + + arch/arm/boot/dts/broadcom/bcm2710.dtsi | 32 + + .../arm/boot/dts/broadcom/bcm2711-rpi-4-b.dts | 262 +- + .../arm/boot/dts/broadcom/bcm2711-rpi-400.dts | 49 +- + .../arm/boot/dts/broadcom/bcm2711-rpi-cm4.dts | 510 ++ + .../boot/dts/broadcom/bcm2711-rpi-cm4s.dts | 297 + + .../arm/boot/dts/broadcom/bcm2711-rpi-ds.dtsi | 561 ++ + arch/arm/boot/dts/broadcom/bcm2711-rpi.dtsi | 13 + + arch/arm/boot/dts/broadcom/bcm2711.dtsi | 2 +- + .../arm/boot/dts/broadcom/bcm2712-rpi-5-b.dts | 863 ++ + .../dts/broadcom/bcm2712-rpi-cm5-cm4io.dts | 20 + + .../dts/broadcom/bcm2712-rpi-cm5-cm5io.dts | 10 + + .../boot/dts/broadcom/bcm2712-rpi-cm5.dtsi | 860 ++ + arch/arm/boot/dts/broadcom/bcm2712-rpi.dtsi | 336 + + arch/arm/boot/dts/broadcom/bcm2712.dtsi | 1304 +++ + .../boot/dts/broadcom/bcm2712d0-rpi-5-b.dts | 107 + + .../arm/boot/dts/broadcom/bcm271x-rpi-bt.dtsi | 38 + + .../dts/broadcom/bcm283x-rpi-csi0-2lane.dtsi | 4 + + .../dts/broadcom/bcm283x-rpi-csi1-2lane.dtsi | 4 + + .../dts/broadcom/bcm283x-rpi-csi1-4lane.dtsi | 4 + + .../broadcom/bcm283x-rpi-i2c0mux_0_28.dtsi | 4 + + .../broadcom/bcm283x-rpi-i2c0mux_0_44.dtsi | 4 + + arch/arm/boot/dts/broadcom/bcm283x.dtsi | 2 +- + arch/arm/boot/dts/broadcom/rp1.dtsi | 1306 +++ + arch/arm/boot/dts/overlays/Makefile | 333 + + arch/arm/boot/dts/overlays/README | 5346 ++++++++++++ + .../arm/boot/dts/overlays/act-led-overlay.dts | 28 + .../dts/overlays/adafruit-st7735r-overlay.dts | 83 + .../boot/dts/overlays/adafruit18-overlay.dts | 55 + .../dts/overlays/adau1977-adc-overlay.dts | 40 + .../dts/overlays/adau7002-simple-overlay.dts | 52 + .../arm/boot/dts/overlays/ads1015-overlay.dts | 98 + - .../arm/boot/dts/overlays/ads1115-overlay.dts | 103 + + .../arm/boot/dts/overlays/ads1115-overlay.dts | 135 + .../arm/boot/dts/overlays/ads7846-overlay.dts | 89 + .../boot/dts/overlays/adv7282m-overlay.dts | 73 + .../boot/dts/overlays/adv728x-m-overlay.dts | 37 + .../overlays/akkordion-iqdacplus-overlay.dts | 49 + - .../allo-boss-dac-pcm512x-audio-overlay.dts | 59 + + .../allo-boss-dac-pcm512x-audio-overlay.dts | 61 + .../overlays/allo-boss2-dac-audio-overlay.dts | 57 + .../dts/overlays/allo-digione-overlay.dts | 44 + - .../allo-katana-dac-audio-overlay.dts | 57 + + .../allo-katana-dac-audio-overlay.dts | 58 + .../allo-piano-dac-pcm512x-audio-overlay.dts | 54 + ...o-piano-dac-plus-pcm512x-audio-overlay.dts | 57 + arch/arm/boot/dts/overlays/anyspi-overlay.dts | 205 + - .../boot/dts/overlays/apds9960-overlay.dts | 57 + + .../boot/dts/overlays/apds9960-overlay.dts | 55 + .../boot/dts/overlays/applepi-dac-overlay.dts | 57 + + .../dts/overlays/arducam-64mp-overlay.dts | 91 + + arch/arm/boot/dts/overlays/arducam-64mp.dtsi | 34 + + .../overlays/arducam-pivariety-overlay.dts | 94 + .../boot/dts/overlays/at86rf233-overlay.dts | 57 + .../overlays/audioinjector-addons-overlay.dts | 60 + + .../audioinjector-bare-i2s-overlay.dts | 50 + ...dioinjector-isolated-soundcard-overlay.dts | 55 + .../overlays/audioinjector-ultra-overlay.dts | 71 + .../audioinjector-wm8731-audio-overlay.dts | 39 + .../dts/overlays/audiosense-pi-overlay.dts | 82 + - .../boot/dts/overlays/audremap-overlay.dts | 42 + + .../boot/dts/overlays/audremap-overlay.dts | 38 + .../boot/dts/overlays/balena-fin-overlay.dts | 125 + + .../boot/dts/overlays/bcm2712d0-overlay.dts | 75 + + .../dts/overlays/camera-mux-2port-overlay.dts | 545 ++ + .../dts/overlays/camera-mux-4port-overlay.dts | 952 +++ .../arm/boot/dts/overlays/cap1106-overlay.dts | 52 + .../boot/dts/overlays/chipdip-dac-overlay.dts | 46 + + .../dts/overlays/cirrus-wm5102-overlay.dts | 172 + + .../dts/overlays/cm-swap-i2c0-overlay.dts | 27 + arch/arm/boot/dts/overlays/cma-overlay.dts | 36 + + .../crystalfontz-cfa050_pi_m-overlay.dts | 124 + .../dts/overlays/cutiepi-panel-overlay.dts | 117 + - arch/arm/boot/dts/overlays/dht11-overlay.dts | 41 + + .../boot/dts/overlays/dacberry400-overlay.dts | 71 + + arch/arm/boot/dts/overlays/dht11-overlay.dts | 48 + + .../dts/overlays/dionaudio-kiwi-overlay.dts | 39 + .../dts/overlays/dionaudio-loco-overlay.dts | 39 + .../overlays/dionaudio-loco-v2-overlay.dts | 49 + - .../boot/dts/overlays/disable-bt-overlay.dts | 64 + + .../boot/dts/overlays/disable-bt-overlay.dts | 59 + + .../dts/overlays/disable-bt-pi5-overlay.dts | 17 + + .../dts/overlays/disable-emmc2-overlay.dts | 13 + .../dts/overlays/disable-wifi-overlay.dts | 20 + + .../dts/overlays/disable-wifi-pi5-overlay.dts | 13 + arch/arm/boot/dts/overlays/dpi18-overlay.dts | 39 + .../boot/dts/overlays/dpi18cpadhi-overlay.dts | 26 + arch/arm/boot/dts/overlays/dpi24-overlay.dts | 39 + arch/arm/boot/dts/overlays/draws-overlay.dts | 208 + .../arm/boot/dts/overlays/dwc-otg-overlay.dts | 14 + arch/arm/boot/dts/overlays/dwc2-overlay.dts | 26 + - .../boot/dts/overlays/edt-ft5406-overlay.dts | 26 + - arch/arm/boot/dts/overlays/edt-ft5406.dtsi | 47 + + .../boot/dts/overlays/edt-ft5406-overlay.dts | 46 + + arch/arm/boot/dts/overlays/edt-ft5406.dtsi | 49 + .../boot/dts/overlays/enc28j60-overlay.dts | 53 + .../dts/overlays/enc28j60-spi2-overlay.dts | 47 + .../arm/boot/dts/overlays/exc3000-overlay.dts | 48 + arch/arm/boot/dts/overlays/fbtft-overlay.dts | 611 ++ .../boot/dts/overlays/fe-pi-audio-overlay.dts | 70 + .../boot/dts/overlays/fsm-demo-overlay.dts | 104 + + arch/arm/boot/dts/overlays/gc9a01-overlay.dts | 151 + .../boot/dts/overlays/ghost-amp-overlay.dts | 145 + arch/arm/boot/dts/overlays/goodix-overlay.dts | 46 + .../googlevoicehat-soundcard-overlay.dts | 49 + - .../boot/dts/overlays/gpio-fan-overlay.dts | 79 + + .../dts/overlays/gpio-charger-overlay.dts | 42 + + .../boot/dts/overlays/gpio-fan-overlay.dts | 89 + + .../boot/dts/overlays/gpio-hog-overlay.dts | 27 + .../arm/boot/dts/overlays/gpio-ir-overlay.dts | 49 + .../boot/dts/overlays/gpio-ir-tx-overlay.dts | 36 + .../boot/dts/overlays/gpio-key-overlay.dts | 48 + @@ -165,16 +190,22 @@ Subject: [PATCH] apply RPi patch of 5.10.95 .../boot/dts/overlays/gpio-no-irq-overlay.dts | 14 + .../dts/overlays/gpio-poweroff-overlay.dts | 39 + .../dts/overlays/gpio-shutdown-overlay.dts | 86 + + arch/arm/boot/dts/overlays/hat_map.dts | 98 + .../boot/dts/overlays/hd44780-lcd-overlay.dts | 46 + .../hdmi-backlight-hwhack-gpio-overlay.dts | 47 + .../dts/overlays/hifiberry-amp-overlay.dts | 39 + - .../dts/overlays/hifiberry-amp100-overlay.dts | 64 + + .../dts/overlays/hifiberry-amp100-overlay.dts | 67 + + .../dts/overlays/hifiberry-amp3-overlay.dts | 57 + + .../overlays/hifiberry-amp4pro-overlay.dts | 63 + .../dts/overlays/hifiberry-dac-overlay.dts | 34 + - .../overlays/hifiberry-dacplus-overlay.dts | 65 + + .../dts/overlays/hifiberry-dac8x-overlay.dts | 50 + + .../overlays/hifiberry-dacplus-overlay.dts | 68 + + .../hifiberry-dacplus-pro-overlay.dts | 64 + + .../hifiberry-dacplus-std-overlay.dts | 65 + .../overlays/hifiberry-dacplusadc-overlay.dts | 72 + - .../hifiberry-dacplusadcpro-overlay.dts | 70 + + .../hifiberry-dacplusadcpro-overlay.dts | 72 + .../overlays/hifiberry-dacplusdsp-overlay.dts | 34 + - .../overlays/hifiberry-dacplushd-overlay.dts | 106 + + .../overlays/hifiberry-dacplushd-overlay.dts | 94 + .../dts/overlays/hifiberry-digi-overlay.dts | 41 + .../overlays/hifiberry-digi-pro-overlay.dts | 43 + .../boot/dts/overlays/highperi-overlay.dts | 63 + @@ -183,34 +214,55 @@ Subject: [PATCH] apply RPi patch of 5.10.95 arch/arm/boot/dts/overlays/hy28b-overlay.dts | 148 + .../boot/dts/overlays/i-sabre-q2m-overlay.dts | 39 + .../boot/dts/overlays/i2c-bcm2708-overlay.dts | 13 + + .../arm/boot/dts/overlays/i2c-fan-overlay.dts | 108 + .../boot/dts/overlays/i2c-gpio-overlay.dts | 47 + - .../arm/boot/dts/overlays/i2c-mux-overlay.dts | 139 + - .../dts/overlays/i2c-pwm-pca9685a-overlay.dts | 26 + - .../arm/boot/dts/overlays/i2c-rtc-common.dtsi | 323 + + .../arm/boot/dts/overlays/i2c-mux-overlay.dts | 183 + + .../dts/overlays/i2c-pwm-pca9685a-overlay.dts | 61 + + .../arm/boot/dts/overlays/i2c-rtc-common.dtsi | 367 + .../dts/overlays/i2c-rtc-gpio-overlay.dts | 31 + - .../arm/boot/dts/overlays/i2c-rtc-overlay.dts | 34 + - .../boot/dts/overlays/i2c-sensor-overlay.dts | 340 + + .../arm/boot/dts/overlays/i2c-rtc-overlay.dts | 42 + + .../boot/dts/overlays/i2c-sensor-common.dtsi | 578 ++ + .../boot/dts/overlays/i2c-sensor-overlay.dts | 42 + arch/arm/boot/dts/overlays/i2c0-overlay.dts | 83 + + .../boot/dts/overlays/i2c0-pi5-overlay.dts | 34 + arch/arm/boot/dts/overlays/i2c1-overlay.dts | 44 + - arch/arm/boot/dts/overlays/i2c3-overlay.dts | 36 + - arch/arm/boot/dts/overlays/i2c4-overlay.dts | 36 + - arch/arm/boot/dts/overlays/i2c5-overlay.dts | 36 + - arch/arm/boot/dts/overlays/i2c6-overlay.dts | 36 + + .../boot/dts/overlays/i2c1-pi5-overlay.dts | 34 + + .../boot/dts/overlays/i2c2-pi5-overlay.dts | 21 + + arch/arm/boot/dts/overlays/i2c3-overlay.dts | 34 + + .../boot/dts/overlays/i2c3-pi5-overlay.dts | 22 + + arch/arm/boot/dts/overlays/i2c4-overlay.dts | 34 + + arch/arm/boot/dts/overlays/i2c5-overlay.dts | 34 + + arch/arm/boot/dts/overlays/i2c6-overlay.dts | 34 + + .../arm/boot/dts/overlays/i2s-dac-overlay.dts | 34 + .../dts/overlays/i2s-gpio28-31-overlay.dts | 18 + .../boot/dts/overlays/ilitek251x-overlay.dts | 45 + - arch/arm/boot/dts/overlays/imx219-overlay.dts | 96 + + arch/arm/boot/dts/overlays/imx219-overlay.dts | 89 + + arch/arm/boot/dts/overlays/imx219.dtsi | 27 + + arch/arm/boot/dts/overlays/imx258-overlay.dts | 131 + + arch/arm/boot/dts/overlays/imx258.dtsi | 27 + arch/arm/boot/dts/overlays/imx290-overlay.dts | 32 + - .../boot/dts/overlays/imx290_327-overlay.dtsi | 125 + - arch/arm/boot/dts/overlays/imx378-overlay.dts | 10 + - arch/arm/boot/dts/overlays/imx477-overlay.dts | 10 + - .../boot/dts/overlays/imx477_378-overlay.dtsi | 99 + - arch/arm/boot/dts/overlays/imx519-overlay.dts | 96 + + .../boot/dts/overlays/imx290_327-overlay.dtsi | 112 + + arch/arm/boot/dts/overlays/imx290_327.dtsi | 24 + + arch/arm/boot/dts/overlays/imx296-overlay.dts | 114 + + arch/arm/boot/dts/overlays/imx327-overlay.dts | 33 + + arch/arm/boot/dts/overlays/imx378-overlay.dts | 17 + + arch/arm/boot/dts/overlays/imx462-overlay.dts | 39 + + arch/arm/boot/dts/overlays/imx477-overlay.dts | 17 + + .../boot/dts/overlays/imx477_378-overlay.dtsi | 92 + + arch/arm/boot/dts/overlays/imx477_378.dtsi | 24 + + arch/arm/boot/dts/overlays/imx519-overlay.dts | 93 + + arch/arm/boot/dts/overlays/imx519.dtsi | 34 + + arch/arm/boot/dts/overlays/imx708-overlay.dts | 105 + + arch/arm/boot/dts/overlays/imx708.dtsi | 35 + + .../interludeaudio-analog-overlay.dts | 73 + + .../interludeaudio-digital-overlay.dts | 49 + .../dts/overlays/iqaudio-codec-overlay.dts | 42 + .../boot/dts/overlays/iqaudio-dac-overlay.dts | 46 + .../dts/overlays/iqaudio-dacplus-overlay.dts | 49 + .../iqaudio-digi-wm8804-audio-overlay.dts | 47 + + arch/arm/boot/dts/overlays/iqs550-overlay.dts | 59 + .../arm/boot/dts/overlays/irs1125-overlay.dts | 90 + - .../dts/overlays/jedec-spi-nor-overlay.dts | 309 + + .../dts/overlays/jedec-spi-nor-overlay.dts | 136 + .../dts/overlays/justboom-both-overlay.dts | 65 + .../dts/overlays/justboom-dac-overlay.dts | 46 + .../dts/overlays/justboom-digi-overlay.dts | 41 + @@ -218,7 +270,7 @@ Subject: [PATCH] apply RPi patch of 5.10.95 .../boot/dts/overlays/max98357a-overlay.dts | 84 + .../boot/dts/overlays/maxtherm-overlay.dts | 186 + .../boot/dts/overlays/mbed-dac-overlay.dts | 64 + - .../boot/dts/overlays/mcp23017-overlay.dts | 69 + + .../boot/dts/overlays/mcp23017-overlay.dts | 103 + .../boot/dts/overlays/mcp23s17-overlay.dts | 732 ++ .../dts/overlays/mcp2515-can0-overlay.dts | 73 + .../dts/overlays/mcp2515-can1-overlay.dts | 73 + @@ -227,27 +279,41 @@ Subject: [PATCH] apply RPi patch of 5.10.95 .../arm/boot/dts/overlays/mcp3008-overlay.dts | 205 + .../arm/boot/dts/overlays/mcp3202-overlay.dts | 205 + .../arm/boot/dts/overlays/mcp342x-overlay.dts | 164 + - .../dts/overlays/media-center-overlay.dts | 134 + - .../boot/dts/overlays/merus-amp-overlay.dts | 60 + + .../dts/overlays/media-center-overlay.dts | 86 + + .../boot/dts/overlays/merus-amp-overlay.dts | 59 + .../boot/dts/overlays/midi-uart0-overlay.dts | 36 + + .../dts/overlays/midi-uart0-pi5-overlay.dts | 35 + .../boot/dts/overlays/midi-uart1-overlay.dts | 43 + + .../dts/overlays/midi-uart1-pi5-overlay.dts | 35 + .../boot/dts/overlays/midi-uart2-overlay.dts | 37 + + .../dts/overlays/midi-uart2-pi5-overlay.dts | 35 + .../boot/dts/overlays/midi-uart3-overlay.dts | 38 + + .../dts/overlays/midi-uart3-pi5-overlay.dts | 35 + .../boot/dts/overlays/midi-uart4-overlay.dts | 38 + + .../dts/overlays/midi-uart4-pi5-overlay.dts | 35 + .../boot/dts/overlays/midi-uart5-overlay.dts | 38 + .../boot/dts/overlays/minipitft13-overlay.dts | 70 + - .../boot/dts/overlays/miniuart-bt-overlay.dts | 93 + + .../boot/dts/overlays/miniuart-bt-overlay.dts | 83 + + .../dts/overlays/mipi-dbi-spi-overlay.dts | 175 + .../boot/dts/overlays/mlx90640-overlay.dts | 22 + arch/arm/boot/dts/overlays/mmc-overlay.dts | 46 + - .../arm/boot/dts/overlays/mpu6050-overlay.dts | 29 + .../arm/boot/dts/overlays/mz61581-overlay.dts | 117 + - arch/arm/boot/dts/overlays/ov5647-overlay.dts | 99 + - arch/arm/boot/dts/overlays/ov7251-overlay.dts | 94 + - arch/arm/boot/dts/overlays/ov9281-overlay.dts | 95 + - arch/arm/boot/dts/overlays/overlay_map.dts | 166 + - .../arm/boot/dts/overlays/papirus-overlay.dts | 89 + + arch/arm/boot/dts/overlays/ov2311-overlay.dts | 77 + + arch/arm/boot/dts/overlays/ov2311.dtsi | 26 + + arch/arm/boot/dts/overlays/ov5647-overlay.dts | 93 + + arch/arm/boot/dts/overlays/ov5647.dtsi | 25 + + .../arm/boot/dts/overlays/ov64a40-overlay.dts | 91 + + arch/arm/boot/dts/overlays/ov64a40.dtsi | 34 + + arch/arm/boot/dts/overlays/ov7251-overlay.dts | 77 + + arch/arm/boot/dts/overlays/ov7251.dtsi | 28 + + arch/arm/boot/dts/overlays/ov9281-overlay.dts | 78 + + arch/arm/boot/dts/overlays/ov9281.dtsi | 27 + + arch/arm/boot/dts/overlays/overlay_map.dts | 493 ++ + .../arm/boot/dts/overlays/papirus-overlay.dts | 84 + .../arm/boot/dts/overlays/pca953x-overlay.dts | 240 + + .../arm/boot/dts/overlays/pcf857x-overlay.dts | 32 + .../dts/overlays/pcie-32bit-dma-overlay.dts | 38 + + .../overlays/pcie-32bit-dma-pi5-overlay.dts | 26 + arch/arm/boot/dts/overlays/pibell-overlay.dts | 81 + .../dts/overlays/pifacedigital-overlay.dts | 144 + .../arm/boot/dts/overlays/pifi-40-overlay.dts | 50 + @@ -255,31 +321,36 @@ Subject: [PATCH] apply RPi patch of 5.10.95 .../dts/overlays/pifi-dac-zero-overlay.dts | 49 + .../dts/overlays/pifi-mini-210-overlay.dts | 42 + arch/arm/boot/dts/overlays/piglow-overlay.dts | 97 + - .../boot/dts/overlays/piscreen-overlay.dts | 102 + + .../boot/dts/overlays/piscreen-overlay.dts | 107 + .../boot/dts/overlays/piscreen2r-overlay.dts | 106 + - .../arm/boot/dts/overlays/pisound-overlay.dts | 120 + - .../arm/boot/dts/overlays/pitft22-overlay.dts | 69 + - .../overlays/pitft28-capacitive-overlay.dts | 91 + - .../overlays/pitft28-resistive-overlay.dts | 119 + - .../overlays/pitft35-resistive-overlay.dts | 119 + - .../boot/dts/overlays/pps-gpio-overlay.dts | 38 + - .../boot/dts/overlays/pwm-2chan-overlay.dts | 49 + + .../arm/boot/dts/overlays/pisound-overlay.dts | 118 + + .../boot/dts/overlays/pisound-pi5-overlay.dts | 31 + + .../arm/boot/dts/overlays/pitft22-overlay.dts | 71 + + .../overlays/pitft28-capacitive-overlay.dts | 93 + + .../overlays/pitft28-resistive-overlay.dts | 126 + + .../overlays/pitft35-resistive-overlay.dts | 127 + + .../boot/dts/overlays/pps-gpio-overlay.dts | 39 + + .../boot/dts/overlays/proto-codec-overlay.dts | 39 + + .../boot/dts/overlays/pwm-2chan-overlay.dts | 48 + .../boot/dts/overlays/pwm-ir-tx-overlay.dts | 40 + - arch/arm/boot/dts/overlays/pwm-overlay.dts | 45 + + arch/arm/boot/dts/overlays/pwm-overlay.dts | 44 + + arch/arm/boot/dts/overlays/pwm1-overlay.dts | 59 + .../arm/boot/dts/overlays/qca7000-overlay.dts | 55 + .../dts/overlays/qca7000-uart0-overlay.dts | 46 + + .../arm/boot/dts/overlays/ramoops-overlay.dts | 25 + + .../boot/dts/overlays/ramoops-pi4-overlay.dts | 25 + .../dts/overlays/rotary-encoder-overlay.dts | 59 + .../dts/overlays/rpi-backlight-overlay.dts | 21 + - .../overlays/rpi-cirrus-wm5102-overlay.dts | 172 + - .../arm/boot/dts/overlays/rpi-dac-overlay.dts | 34 + - .../boot/dts/overlays/rpi-display-overlay.dts | 91 + + .../dts/overlays/rpi-codeczero-overlay.dts | 9 + + .../boot/dts/overlays/rpi-dacplus-overlay.dts | 17 + + .../boot/dts/overlays/rpi-dacpro-overlay.dts | 17 + + .../dts/overlays/rpi-digiampplus-overlay.dts | 17 + .../boot/dts/overlays/rpi-ft5406-overlay.dts | 25 + - .../arm/boot/dts/overlays/rpi-poe-overlay.dts | 95 + - .../dts/overlays/rpi-poe-plus-overlay.dts | 23 + - .../boot/dts/overlays/rpi-proto-overlay.dts | 39 + + .../arm/boot/dts/overlays/rpi-poe-overlay.dts | 154 + + .../dts/overlays/rpi-poe-plus-overlay.dts | 49 + .../boot/dts/overlays/rpi-sense-overlay.dts | 47 + + .../dts/overlays/rpi-sense-v2-overlay.dts | 47 + arch/arm/boot/dts/overlays/rpi-tv-overlay.dts | 34 + - .../boot/dts/overlays/rpivid-v4l2-overlay.dts | 50 + .../rra-digidac1-wm8741-audio-overlay.dts | 49 + .../boot/dts/overlays/sainsmart18-overlay.dts | 52 + .../dts/overlays/sc16is750-i2c-overlay.dts | 43 + @@ -288,6 +359,7 @@ Subject: [PATCH] apply RPi patch of 5.10.95 .../dts/overlays/sc16is752-spi1-overlay.dts | 67 + arch/arm/boot/dts/overlays/sdhost-overlay.dts | 38 + arch/arm/boot/dts/overlays/sdio-overlay.dts | 77 + + .../boot/dts/overlays/sdio-pi5-overlay.dts | 24 + .../overlays/seeed-can-fd-hat-v1-overlay.dts | 138 + .../overlays/seeed-can-fd-hat-v2-overlay.dts | 117 + .../boot/dts/overlays/sh1106-spi-overlay.dts | 84 + @@ -305,18 +377,24 @@ Subject: [PATCH] apply RPi patch of 5.10.95 .../boot/dts/overlays/spi1-2cs-overlay.dts | 69 + .../boot/dts/overlays/spi1-3cs-overlay.dts | 81 + .../boot/dts/overlays/spi2-1cs-overlay.dts | 57 + + .../dts/overlays/spi2-1cs-pi5-overlay.dts | 33 + .../boot/dts/overlays/spi2-2cs-overlay.dts | 69 + + .../dts/overlays/spi2-2cs-pi5-overlay.dts | 44 + .../boot/dts/overlays/spi2-3cs-overlay.dts | 81 + - .../boot/dts/overlays/spi3-1cs-overlay.dts | 44 + - .../boot/dts/overlays/spi3-2cs-overlay.dts | 56 + - .../boot/dts/overlays/spi4-1cs-overlay.dts | 44 + - .../boot/dts/overlays/spi4-2cs-overlay.dts | 56 + - .../boot/dts/overlays/spi5-1cs-overlay.dts | 44 + - .../boot/dts/overlays/spi5-2cs-overlay.dts | 56 + - .../boot/dts/overlays/spi6-1cs-overlay.dts | 44 + - .../boot/dts/overlays/spi6-2cs-overlay.dts | 56 + + .../boot/dts/overlays/spi3-1cs-overlay.dts | 42 + + .../dts/overlays/spi3-1cs-pi5-overlay.dts | 33 + + .../boot/dts/overlays/spi3-2cs-overlay.dts | 54 + + .../dts/overlays/spi3-2cs-pi5-overlay.dts | 44 + + .../boot/dts/overlays/spi4-1cs-overlay.dts | 42 + + .../boot/dts/overlays/spi4-2cs-overlay.dts | 54 + + .../boot/dts/overlays/spi5-1cs-overlay.dts | 42 + + .../dts/overlays/spi5-1cs-pi5-overlay.dts | 33 + + .../boot/dts/overlays/spi5-2cs-overlay.dts | 54 + + .../dts/overlays/spi5-2cs-pi5-overlay.dts | 44 + + .../boot/dts/overlays/spi6-1cs-overlay.dts | 42 + + .../boot/dts/overlays/spi6-2cs-overlay.dts | 54 + .../arm/boot/dts/overlays/ssd1306-overlay.dts | 36 + - .../boot/dts/overlays/ssd1306-spi-overlay.dts | 84 + + .../boot/dts/overlays/ssd1306-spi-overlay.dts | 85 + .../boot/dts/overlays/ssd1331-spi-overlay.dts | 83 + .../boot/dts/overlays/ssd1351-spi-overlay.dts | 83 + .../dts/overlays/superaudioboard-overlay.dts | 73 + @@ -325,39 +403,58 @@ Subject: [PATCH] apply RPi patch of 5.10.95 .../boot/dts/overlays/tc358743-overlay.dts | 109 + .../boot/dts/overlays/tinylcd35-overlay.dts | 222 + .../boot/dts/overlays/tpm-slb9670-overlay.dts | 44 + + .../boot/dts/overlays/tpm-slb9673-overlay.dts | 50 + arch/arm/boot/dts/overlays/uart0-overlay.dts | 32 + + .../boot/dts/overlays/uart0-pi5-overlay.dts | 18 + arch/arm/boot/dts/overlays/uart1-overlay.dts | 38 + - arch/arm/boot/dts/overlays/uart2-overlay.dts | 27 + - arch/arm/boot/dts/overlays/uart3-overlay.dts | 27 + - arch/arm/boot/dts/overlays/uart4-overlay.dts | 27 + - arch/arm/boot/dts/overlays/uart5-overlay.dts | 27 + + .../boot/dts/overlays/uart1-pi5-overlay.dts | 18 + + arch/arm/boot/dts/overlays/uart2-overlay.dts | 25 + + .../boot/dts/overlays/uart2-pi5-overlay.dts | 18 + + arch/arm/boot/dts/overlays/uart3-overlay.dts | 25 + + .../boot/dts/overlays/uart3-pi5-overlay.dts | 18 + + arch/arm/boot/dts/overlays/uart4-overlay.dts | 25 + + .../boot/dts/overlays/uart4-pi5-overlay.dts | 18 + + arch/arm/boot/dts/overlays/uart5-overlay.dts | 25 + arch/arm/boot/dts/overlays/udrc-overlay.dts | 128 + .../dts/overlays/ugreen-dabboard-overlay.dts | 49 + .../boot/dts/overlays/upstream-overlay.dts | 101 + .../dts/overlays/upstream-pi4-overlay.dts | 137 + - .../dts/overlays/vc4-fkms-v3d-overlay.dts | 40 + - .../dts/overlays/vc4-fkms-v3d-pi4-overlay.dts | 44 + - .../overlays/vc4-kms-dpi-generic-overlay.dts | 74 + + .../dts/overlays/vc4-fkms-v3d-overlay.dts | 46 + + .../dts/overlays/vc4-fkms-v3d-pi4-overlay.dts | 50 + + .../overlays/vc4-kms-dpi-generic-overlay.dts | 81 + + .../dts/overlays/vc4-kms-dpi-hyperpixel.dtsi | 94 + + .../vc4-kms-dpi-hyperpixel2r-overlay.dts | 114 + + .../vc4-kms-dpi-hyperpixel4-overlay.dts | 57 + + .../vc4-kms-dpi-hyperpixel4sq-overlay.dts | 36 + .../overlays/vc4-kms-dpi-panel-overlay.dts | 69 + arch/arm/boot/dts/overlays/vc4-kms-dpi.dtsi | 111 + - .../overlays/vc4-kms-dsi-7inch-overlay.dts | 118 + + .../overlays/vc4-kms-dsi-7inch-overlay.dts | 124 + + .../overlays/vc4-kms-dsi-generic-overlay.dts | 106 + + .../vc4-kms-dsi-ili9881-5inch-overlay.dts | 122 + + .../vc4-kms-dsi-ili9881-7inch-overlay.dts | 122 + .../vc4-kms-dsi-lt070me05000-overlay.dts | 69 + .../vc4-kms-dsi-lt070me05000-v2-overlay.dts | 64 + + .../vc4-kms-dsi-waveshare-panel-overlay.dts | 126 + .../overlays/vc4-kms-kippah-7inch-overlay.dts | 26 + - .../boot/dts/overlays/vc4-kms-v3d-overlay.dts | 123 + - .../dts/overlays/vc4-kms-v3d-pi4-overlay.dts | 197 + - .../dts/overlays/vc4-kms-vga666-overlay.dts | 100 + + .../boot/dts/overlays/vc4-kms-v3d-overlay.dts | 124 + + .../dts/overlays/vc4-kms-v3d-pi4-overlay.dts | 200 + + .../dts/overlays/vc4-kms-v3d-pi5-overlay.dts | 147 + + .../dts/overlays/vc4-kms-vga666-overlay.dts | 107 + arch/arm/boot/dts/overlays/vga666-overlay.dts | 30 + arch/arm/boot/dts/overlays/vl805-overlay.dts | 18 + .../arm/boot/dts/overlays/w1-gpio-overlay.dts | 40 + + .../boot/dts/overlays/w1-gpio-pi5-overlay.dts | 15 + .../dts/overlays/w1-gpio-pullup-overlay.dts | 42 + + .../overlays/w1-gpio-pullup-pi5-overlay.dts | 15 + arch/arm/boot/dts/overlays/w5500-overlay.dts | 63 + + .../overlays/watterott-display-overlay.dts | 150 + + .../waveshare-can-fd-hat-mode-a-overlay.dts | 140 + + .../waveshare-can-fd-hat-mode-b-overlay.dts | 103 + .../arm/boot/dts/overlays/wittypi-overlay.dts | 44 + .../dts/overlays/wm8960-soundcard-overlay.dts | 82 + - arch/arm/configs/bcm2709_defconfig | 1533 ++++ - arch/arm/configs/bcm2711_defconfig | 1557 ++++ - arch/arm/configs/bcmrpi_defconfig | 1528 ++++ - arch/arm/configs/multi_v7_defconfig | 1 + + arch/arm/configs/bcm2709_defconfig | 1583 ++++ + arch/arm/configs/bcm2711_defconfig | 1610 ++++ + arch/arm/configs/bcmrpi_defconfig | 1576 ++++ arch/arm/include/asm/cacheflush.h | 21 + arch/arm/include/asm/glue-cache.h | 2 + arch/arm/include/asm/irqflags.h | 16 +- @@ -372,12 +469,12 @@ Subject: [PATCH] apply RPi patch of 5.10.95 arch/arm/lib/copy_from_user.S | 4 +- arch/arm/lib/exports_rpi.c | 37 + arch/arm/lib/memcmp_rpi.S | 285 + - arch/arm/lib/memcpy_rpi.S | 63 + + arch/arm/lib/memcpy_rpi.S | 65 + arch/arm/lib/memcpymove.h | 488 ++ arch/arm/lib/memmove_rpi.S | 63 + - arch/arm/lib/memset_rpi.S | 130 + - arch/arm/lib/uaccess_with_memcpy.c | 130 +- - arch/arm/mach-bcm/Kconfig | 10 + + arch/arm/lib/memset_rpi.S | 132 + + arch/arm/lib/uaccess_with_memcpy.c | 125 +- + arch/arm/mach-bcm/Kconfig | 26 + arch/arm/mach-bcm/board_bcm2835.c | 109 + arch/arm/mm/cache-v6.S | 4 +- arch/arm/mm/cache-v7.S | 6 +- @@ -385,345 +482,472 @@ Subject: [PATCH] apply RPi patch of 5.10.95 arch/arm/mm/proc-syms.c | 3 + arch/arm/mm/proc-v6.S | 15 +- arch/arm/vfp/vfpmodule.c | 25 +- - arch/arm64/Kconfig.platforms | 1 + + arch/arm64/Kconfig | 3 +- arch/arm64/boot/dts/Makefile | 2 + - arch/arm64/boot/dts/broadcom/Makefile | 16 +- + arch/arm64/boot/dts/broadcom/Makefile | 18 + .../boot/dts/broadcom/bcm2710-rpi-2-b.dts | 1 + .../dts/broadcom/bcm2710-rpi-3-b-plus.dts | 1 + .../boot/dts/broadcom/bcm2710-rpi-3-b.dts | 1 + .../boot/dts/broadcom/bcm2710-rpi-cm3.dts | 1 + + .../dts/broadcom/bcm2710-rpi-zero-2-w.dts | 1 + .../boot/dts/broadcom/bcm2710-rpi-zero-2.dts | 1 + - .../boot/dts/broadcom/bcm2711-rpi-4-b.dts | 3 +- - .../boot/dts/broadcom/bcm2711-rpi-400.dts | 1 + .../boot/dts/broadcom/bcm2711-rpi-cm4.dts | 1 + + .../boot/dts/broadcom/bcm2711-rpi-cm4s.dts | 1 + + .../boot/dts/broadcom/bcm2712-rpi-5-b.dts | 2 + + .../dts/broadcom/bcm2712-rpi-cm5-cm4io.dts | 2 + + .../dts/broadcom/bcm2712-rpi-cm5-cm5io.dts | 2 + + .../boot/dts/broadcom/bcm2712d0-rpi-5-b.dts | 2 + .../dts/broadcom/bcm283x-rpi-csi1-2lane.dtsi | 1 + .../dts/broadcom/bcm283x-rpi-lan7515.dtsi | 1 + arch/arm64/boot/dts/overlays | 1 + - arch/arm64/configs/bcm2711_defconfig | 1566 ++++ - arch/arm64/configs/bcmrpi3_defconfig | 1411 ++++ - arch/arm64/configs/defconfig | 1 + - arch/arm64/crypto/aes-cipher-glue.c | 10 + + arch/arm64/configs/bcm2711_defconfig | 1672 ++++ + arch/arm64/configs/bcm2712_defconfig | 1675 ++++ + arch/arm64/configs/bcmrpi3_defconfig | 1560 ++++ + arch/arm64/crypto/aes-cipher-glue.c | 11 + arch/arm64/crypto/aes-glue.c | 4 +- arch/arm64/crypto/aes-neonbs-glue.c | 5 - arch/arm64/kernel/armv8_deprecated.c | 5 + - arch/arm64/kernel/cpuinfo.c | 25 + - drivers/bluetooth/btusb.c | 8 + + arch/arm64/kernel/cpuinfo.c | 23 + + arch/arm64/kernel/process.c | 4 +- + arch/arm64/kernel/setup.c | 4 +- + drivers/bluetooth/btbcm.c | 9 +- drivers/bluetooth/hci_h5.c | 3 +- - drivers/char/Kconfig | 2 + - drivers/char/Makefile | 1 + - drivers/char/broadcom/Kconfig | 49 + - drivers/char/broadcom/Makefile | 5 + - drivers/char/broadcom/bcm2835-gpiomem.c | 258 + + drivers/char/Kconfig | 10 + + drivers/char/Makefile | 2 + + drivers/char/broadcom/Kconfig | 33 + + drivers/char/broadcom/Makefile | 3 + drivers/char/broadcom/bcm2835_smi_dev.c | 409 + - drivers/char/broadcom/rpivid-mem.c | 270 + - drivers/char/broadcom/vc_mem.c | 373 + + drivers/char/broadcom/vc_mem.c | 632 ++ drivers/char/broadcom/vcio.c | 186 + drivers/char/hw_random/Kconfig | 2 +- - drivers/char/hw_random/bcm2835-rng.c | 6 +- - drivers/char/hw_random/iproc-rng200.c | 78 +- - drivers/clk/Kconfig | 6 + - drivers/clk/Makefile | 3 + - drivers/clk/bcm/clk-bcm2835.c | 202 +- - drivers/clk/bcm/clk-raspberrypi.c | 7 +- - drivers/clk/clk-allo-dac.c | 161 + - drivers/clk/clk-hifiberry-dachd.c | 333 + - drivers/clk/clk-hifiberry-dacpro.c | 160 + - drivers/clk/clk.c | 127 + + drivers/char/hw_random/bcm2835-rng.c | 26 +- + drivers/char/hw_random/iproc-rng200.c | 79 +- + drivers/char/random.c | 8 + + drivers/char/raspberrypi-gpiomem.c | 276 + + drivers/char/tpm/tpm_tis_spi_main.c | 4 + + drivers/clk/Kconfig | 19 + + drivers/clk/Makefile | 4 + + drivers/clk/bcm/clk-bcm2835.c | 206 +- + drivers/clk/bcm/clk-raspberrypi.c | 34 +- + drivers/clk/clk-hifiberry-dachd.c | 331 + + drivers/clk/clk-hifiberry-dacpro.c | 181 + + drivers/clk/clk-rp1-sdio.c | 600 ++ + drivers/clk/clk-rp1.c | 2422 ++++++ drivers/dma/Kconfig | 4 + drivers/dma/Makefile | 1 + drivers/dma/bcm2708-dmaengine.c | 281 + - drivers/dma/bcm2835-dma.c | 545 +- + drivers/dma/bcm2835-dma.c | 735 +- + .../dma/dw-axi-dmac/dw-axi-dmac-platform.c | 134 +- + drivers/dma/dw-axi-dmac/dw-axi-dmac.h | 1 + + drivers/firmware/psci/psci.c | 9 +- drivers/firmware/raspberrypi.c | 149 +- - drivers/gpio/Kconfig | 23 + + drivers/gpio/Kconfig | 25 +- drivers/gpio/Makefile | 3 + drivers/gpio/gpio-bcm-virt.c | 214 + - drivers/gpio/gpio-fsm.c | 1210 +++ + drivers/gpio/gpio-brcmstb.c | 35 +- + drivers/gpio/gpio-fsm.c | 1212 +++ + drivers/gpio/gpio-mmio.c | 124 +- + drivers/gpio/gpio-pca953x.c | 1 + drivers/gpio/gpio-pwm.c | 144 + drivers/gpio/gpiolib.c | 10 +- drivers/gpu/drm/Kconfig | 2 + drivers/gpu/drm/Makefile | 1 + - .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 42 +- - .../display/amdgpu_dm/amdgpu_dm_mst_types.c | 5 +- - drivers/gpu/drm/arc/arcpgu_crtc.c | 4 +- - .../gpu/drm/arm/display/komeda/komeda_crtc.c | 23 +- - drivers/gpu/drm/arm/hdlcd_crtc.c | 6 +- - drivers/gpu/drm/arm/malidp_crtc.c | 27 +- - drivers/gpu/drm/armada/armada_crtc.c | 23 +- - drivers/gpu/drm/ast/ast_mode.c | 19 +- - .../gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c | 12 +- - drivers/gpu/drm/bridge/panel.c | 4 + - drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 20 +- - drivers/gpu/drm/drm_atomic_helper.c | 106 +- - drivers/gpu/drm/drm_color_mgmt.c | 114 +- - drivers/gpu/drm/drm_connector.c | 70 + - drivers/gpu/drm/drm_edid.c | 13 +- - drivers/gpu/drm/drm_fourcc.c | 3 + - drivers/gpu/drm/drm_framebuffer.c | 16 +- - drivers/gpu/drm/drm_panel.c | 15 +- - drivers/gpu/drm/drm_probe_helper.c | 111 +- - drivers/gpu/drm/drm_simple_kms_helper.c | 14 +- - drivers/gpu/drm/exynos/exynos_drm_crtc.c | 16 +- - drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c | 8 +- - drivers/gpu/drm/gud/Kconfig | 14 + - drivers/gpu/drm/gud/Makefile | 4 + - drivers/gpu/drm/gud/gud_connector.c | 729 ++ - drivers/gpu/drm/gud/gud_drv.c | 696 ++ - drivers/gpu/drm/gud/gud_internal.h | 156 + - drivers/gpu/drm/gud/gud_pipe.c | 601 ++ - .../gpu/drm/hisilicon/hibmc/hibmc_drm_de.c | 8 +- - .../gpu/drm/hisilicon/kirin/kirin_drm_ade.c | 8 +- - drivers/gpu/drm/i915/display/intel_atomic.c | 13 +- - .../gpu/drm/i915/display/intel_connector.c | 3 +- - drivers/gpu/drm/i915/display/intel_display.c | 1 - - drivers/gpu/drm/i915/display/intel_dp_mst.c | 7 +- - drivers/gpu/drm/i915/display/intel_hdmi.c | 5 +- - drivers/gpu/drm/imx/dcss/dcss-crtc.c | 13 +- - drivers/gpu/drm/imx/ipuv3-crtc.c | 16 +- - drivers/gpu/drm/ingenic/ingenic-drm-drv.c | 35 +- - drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 21 +- - drivers/gpu/drm/meson/meson_crtc.c | 12 +- - drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 34 +- - drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c | 10 +- - drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c | 21 +- - drivers/gpu/drm/mxsfb/mxsfb_kms.c | 16 +- - drivers/gpu/drm/nouveau/dispnv50/disp.c | 5 +- - drivers/gpu/drm/nouveau/dispnv50/head.c | 9 +- - drivers/gpu/drm/omapdrm/omap_crtc.c | 22 +- - drivers/gpu/drm/panel/panel-ilitek-ili9881c.c | 253 +- - .../gpu/drm/panel/panel-jdi-lt070me05000.c | 18 +- - .../drm/panel/panel-raspberrypi-touchscreen.c | 49 +- - drivers/gpu/drm/panel/panel-simple.c | 106 +- - drivers/gpu/drm/qxl/qxl_display.c | 6 +- - drivers/gpu/drm/rcar-du/rcar_du_crtc.c | 22 +- - drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 19 +- - drivers/gpu/drm/sti/sti_crtc.c | 6 +- - drivers/gpu/drm/stm/ltdc.c | 7 +- - drivers/gpu/drm/sun4i/sun4i_crtc.c | 17 +- - drivers/gpu/drm/tegra/dc.c | 18 +- - drivers/gpu/drm/tidss/tidss_crtc.c | 20 +- - drivers/gpu/drm/tilcdc/tilcdc_crtc.c | 18 +- - drivers/gpu/drm/v3d/Kconfig | 2 +- - drivers/gpu/drm/v3d/v3d_debugfs.c | 16 +- - drivers/gpu/drm/v3d/v3d_drv.c | 35 +- - drivers/gpu/drm/v3d/v3d_drv.h | 6 + - drivers/gpu/drm/v3d/v3d_gem.c | 59 +- - drivers/gpu/drm/v3d/v3d_irq.c | 10 +- - drivers/gpu/drm/v3d/v3d_mmu.c | 2 + - drivers/gpu/drm/vboxvideo/vbox_mode.c | 6 +- - drivers/gpu/drm/vc4/Kconfig | 1 + - drivers/gpu/drm/vc4/Makefile | 1 + - drivers/gpu/drm/vc4/vc4_crtc.c | 289 +- - drivers/gpu/drm/vc4/vc4_debugfs.c | 7 +- - drivers/gpu/drm/vc4/vc4_dpi.c | 113 +- - drivers/gpu/drm/vc4/vc4_drv.c | 81 +- - drivers/gpu/drm/vc4/vc4_drv.h | 96 +- - drivers/gpu/drm/vc4/vc4_dsi.c | 277 +- - drivers/gpu/drm/vc4/vc4_firmware_kms.c | 1992 +++++ - drivers/gpu/drm/vc4/vc4_gem.c | 3 +- - drivers/gpu/drm/vc4/vc4_hdmi.c | 2207 ++++- - drivers/gpu/drm/vc4/vc4_hdmi.h | 148 +- - drivers/gpu/drm/vc4/vc4_hdmi_phy.c | 45 +- - drivers/gpu/drm/vc4/vc4_hdmi_regs.h | 35 +- - drivers/gpu/drm/vc4/vc4_hvs.c | 309 +- - drivers/gpu/drm/vc4/vc4_kms.c | 181 +- - drivers/gpu/drm/vc4/vc4_perfmon.c | 2 +- - drivers/gpu/drm/vc4/vc4_plane.c | 330 +- - drivers/gpu/drm/vc4/vc4_regs.h | 90 +- - drivers/gpu/drm/vc4/vc4_txp.c | 24 +- - drivers/gpu/drm/vc4/vc4_vec.c | 397 +- + drivers/gpu/drm/bridge/Kconfig | 1 + + drivers/gpu/drm/bridge/tc358762.c | 2 +- + drivers/gpu/drm/drm_atomic_helper.c | 18 +- + drivers/gpu/drm/drm_atomic_state_helper.c | 14 + + drivers/gpu/drm/drm_atomic_uapi.c | 19 + + drivers/gpu/drm/drm_color_mgmt.c | 40 +- + drivers/gpu/drm/drm_connector.c | 68 +- + drivers/gpu/drm/drm_fb_helper.c | 11 +- + drivers/gpu/drm/drm_modes.c | 5 +- + drivers/gpu/drm/drm_probe_helper.c | 5 +- + .../gpu/drm/i915/display/intel_backlight.c | 6 +- + drivers/gpu/drm/i915/display/intel_display.c | 13 + + drivers/gpu/drm/msm/msm_atomic.c | 2 + + drivers/gpu/drm/panel/Kconfig | 32 + + drivers/gpu/drm/panel/Makefile | 3 + + drivers/gpu/drm/panel/panel-ilitek-ili9806e.c | 484 ++ + drivers/gpu/drm/panel/panel-ilitek-ili9881c.c | 955 ++- + .../gpu/drm/panel/panel-jdi-lt070me05000.c | 19 +- + .../drm/panel/panel-raspberrypi-touchscreen.c | 44 +- + drivers/gpu/drm/panel/panel-simple.c | 234 +- + drivers/gpu/drm/panel/panel-sitronix-st7701.c | 407 +- + drivers/gpu/drm/panel/panel-tdo-y17p.c | 277 + + drivers/gpu/drm/panel/panel-waveshare-dsi.c | 434 + + drivers/gpu/drm/rp1/Kconfig | 5 + + drivers/gpu/drm/rp1/Makefile | 4 + + drivers/gpu/drm/rp1/rp1-dpi/Kconfig | 11 + + drivers/gpu/drm/rp1/rp1-dpi/Makefile | 5 + + drivers/gpu/drm/rp1/rp1-dpi/rp1_dpi.c | 415 + + drivers/gpu/drm/rp1/rp1-dpi/rp1_dpi.h | 69 + + drivers/gpu/drm/rp1/rp1-dpi/rp1_dpi_cfg.c | 510 ++ + drivers/gpu/drm/rp1/rp1-dpi/rp1_dpi_hw.c | 486 ++ + drivers/gpu/drm/rp1/rp1-dsi/Kconfig | 14 + + drivers/gpu/drm/rp1/rp1-dsi/Makefile | 5 + + drivers/gpu/drm/rp1/rp1-dsi/rp1_dsi.c | 535 ++ + drivers/gpu/drm/rp1/rp1-dsi/rp1_dsi.h | 94 + + drivers/gpu/drm/rp1/rp1-dsi/rp1_dsi_dma.c | 443 + + drivers/gpu/drm/rp1/rp1-dsi/rp1_dsi_dsi.c | 1504 ++++ + drivers/gpu/drm/rp1/rp1-vec/Kconfig | 11 + + drivers/gpu/drm/rp1/rp1-vec/Makefile | 5 + + drivers/gpu/drm/rp1/rp1-vec/rp1_vec.c | 506 ++ + drivers/gpu/drm/rp1/rp1-vec/rp1_vec.h | 69 + + drivers/gpu/drm/rp1/rp1-vec/rp1_vec_cfg.c | 508 ++ + drivers/gpu/drm/rp1/rp1-vec/rp1_vec_hw.c | 508 ++ + drivers/gpu/drm/rp1/rp1-vec/vec_regs.h | 1420 ++++ + drivers/gpu/drm/solomon/ssd130x.c | 2 +- + drivers/gpu/drm/tiny/ili9486.c | 1 - + drivers/gpu/drm/v3d/v3d_bo.c | 12 +- + drivers/gpu/drm/v3d/v3d_debugfs.c | 258 +- + drivers/gpu/drm/v3d/v3d_drv.c | 37 + + drivers/gpu/drm/v3d/v3d_drv.h | 67 + + drivers/gpu/drm/v3d/v3d_gem.c | 57 + + drivers/gpu/drm/v3d/v3d_irq.c | 55 +- + drivers/gpu/drm/v3d/v3d_mmu.c | 2 - + drivers/gpu/drm/v3d/v3d_regs.h | 51 +- + drivers/gpu/drm/v3d/v3d_sched.c | 180 +- + drivers/gpu/drm/vc4/Makefile | 4 +- + drivers/gpu/drm/vc4/tests/vc4_mock.c | 65 +- + drivers/gpu/drm/vc4/tests/vc4_mock.h | 28 +- + drivers/gpu/drm/vc4/tests/vc4_mock_output.c | 13 +- + drivers/gpu/drm/vc4/tests/vc4_mock_plane.c | 32 +- + drivers/gpu/drm/vc4/tests/vc4_test_lbm_size.c | 308 + + .../gpu/drm/vc4/tests/vc4_test_pv_muxing.c | 225 +- + drivers/gpu/drm/vc4/vc4_bo.c | 28 +- + drivers/gpu/drm/vc4/vc4_crtc.c | 185 +- + drivers/gpu/drm/vc4/vc4_debugfs.c | 3 +- + drivers/gpu/drm/vc4/vc4_drv.c | 90 +- + drivers/gpu/drm/vc4/vc4_drv.h | 143 +- + drivers/gpu/drm/vc4/vc4_firmware_kms.c | 2077 +++++ + drivers/gpu/drm/vc4/vc4_gem.c | 24 +- + drivers/gpu/drm/vc4/vc4_hdmi.c | 214 +- + drivers/gpu/drm/vc4/vc4_hdmi.h | 31 + + drivers/gpu/drm/vc4/vc4_hdmi_phy.c | 640 ++ + drivers/gpu/drm/vc4/vc4_hdmi_regs.h | 222 +- + drivers/gpu/drm/vc4/vc4_hvs.c | 1878 ++++- + drivers/gpu/drm/vc4/vc4_irq.c | 10 +- + drivers/gpu/drm/vc4/vc4_kms.c | 135 +- + drivers/gpu/drm/vc4/vc4_perfmon.c | 20 +- + drivers/gpu/drm/vc4/vc4_plane.c | 1036 ++- + drivers/gpu/drm/vc4/vc4_regs.h | 357 +- + drivers/gpu/drm/vc4/vc4_render_cl.c | 2 +- + drivers/gpu/drm/vc4/vc4_txp.c | 91 +- + drivers/gpu/drm/vc4/vc4_v3d.c | 10 +- + drivers/gpu/drm/vc4/vc4_validate.c | 8 +- + drivers/gpu/drm/vc4/vc4_validate_shaders.c | 2 +- + drivers/gpu/drm/vc4/vc4_vec.c | 172 +- drivers/gpu/drm/vc4/vc_image_types.h | 175 + - drivers/gpu/drm/virtio/virtgpu_display.c | 8 +- - drivers/gpu/drm/vkms/vkms_crtc.c | 24 +- - drivers/gpu/drm/vkms/vkms_writeback.c | 8 +- - drivers/gpu/drm/vmwgfx/vmwgfx_kms.c | 8 +- - drivers/gpu/drm/vmwgfx/vmwgfx_kms.h | 6 +- - drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c | 4 +- - drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c | 4 +- - drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c | 4 +- - drivers/gpu/drm/xlnx/zynqmp_disp.c | 14 +- - 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.../vc04_services/vc-sm-cma/vc_sm_cma_vchi.c | 511 ++ .../vc04_services/vc-sm-cma/vc_sm_cma_vchi.h | 63 + .../vc04_services/vc-sm-cma/vc_sm_defs.h | 297 + .../vc04_services/vc-sm-cma/vc_sm_knl.h | 28 + .../staging/vc04_services/vchiq-mmal/Kconfig | 3 +- .../vc04_services/vchiq-mmal/mmal-common.h | 5 + .../vc04_services/vchiq-mmal/mmal-encodings.h | 66 + + .../vchiq-mmal/mmal-msg-format.h | 10 + .../vc04_services/vchiq-mmal/mmal-msg.h | 54 + - .../vchiq-mmal/mmal-parameters.h | 251 +- - .../vc04_services/vchiq-mmal/mmal-vchiq.c | 413 +- + .../vchiq-mmal/mmal-parameters.h | 253 +- + .../vc04_services/vchiq-mmal/mmal-vchiq.c | 388 +- .../vc04_services/vchiq-mmal/mmal-vchiq.h | 5 + drivers/thermal/broadcom/bcm2711_thermal.c | 2 +- - drivers/thermal/gov_step_wise.c | 33 +- - drivers/tty/serial/8250/8250_bcm2835aux.c | 7 + - drivers/tty/serial/amba-pl011.c | 73 +- - drivers/tty/serial/sc16is7xx.c | 16 +- + drivers/thermal/gov_step_wise.c | 23 +- + drivers/tty/serial/8250/8250.h | 1 + + drivers/tty/serial/8250/8250_bcm2835aux.c | 8 + + drivers/tty/serial/8250/8250_core.c | 15 + + drivers/tty/serial/8250/8250_port.c | 9 + + drivers/tty/serial/amba-pl011.c | 108 + + drivers/tty/serial/sc16is7xx.c | 5 + drivers/usb/Makefile | 1 + drivers/usb/core/generic.c | 1 + drivers/usb/core/hcd.c | 10 + drivers/usb/core/hub.c | 2 +- drivers/usb/core/message.c | 94 + drivers/usb/core/otg_productlist.h | 114 +- + drivers/usb/dwc3/core.c | 58 + + drivers/usb/dwc3/core.h | 17 +- + drivers/usb/dwc3/host.c | 9 +- drivers/usb/gadget/file_storage.c | 3676 +++++++++ drivers/usb/host/Kconfig | 10 + drivers/usb/host/Makefile | 1 + @@ -747,9 +971,9 @@ Subject: [PATCH] apply RPi patch of 5.10.95 drivers/usb/host/dwc_common_port/dwc_modpow.h | 34 + .../usb/host/dwc_common_port/dwc_notifier.c | 319 + .../usb/host/dwc_common_port/dwc_notifier.h | 122 + - drivers/usb/host/dwc_common_port/dwc_os.h | 1276 +++ + drivers/usb/host/dwc_common_port/dwc_os.h | 1275 +++ drivers/usb/host/dwc_common_port/usb.h | 275 + - drivers/usb/host/dwc_otg/Makefile | 85 + + drivers/usb/host/dwc_otg/Makefile | 86 + drivers/usb/host/dwc_otg/doc/doxygen.cfg | 224 + drivers/usb/host/dwc_otg/dummy_audio.c | 1574 ++++ drivers/usb/host/dwc_otg/dwc_cfi_common.h | 142 + @@ -769,12 +993,12 @@ Subject: [PATCH] apply RPi patch of 5.10.95 drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.c | 1433 ++++ drivers/usb/host/dwc_otg/dwc_otg_fiq_fsm.h | 399 + drivers/usb/host/dwc_otg/dwc_otg_fiq_stub.S | 80 + - drivers/usb/host/dwc_otg/dwc_otg_hcd.c | 4363 ++++++++++ + drivers/usb/host/dwc_otg/dwc_otg_hcd.c | 4366 ++++++++++ drivers/usb/host/dwc_otg/dwc_otg_hcd.h | 870 ++ drivers/usb/host/dwc_otg/dwc_otg_hcd_ddma.c | 1135 +++ drivers/usb/host/dwc_otg/dwc_otg_hcd_if.h | 421 + drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c | 2757 +++++++ - drivers/usb/host/dwc_otg/dwc_otg_hcd_linux.c | 1087 +++ + drivers/usb/host/dwc_otg/dwc_otg_hcd_linux.c | 1084 +++ drivers/usb/host/dwc_otg/dwc_otg_hcd_queue.c | 974 +++ drivers/usb/host/dwc_otg/dwc_otg_os_dep.h | 200 + drivers/usb/host/dwc_otg/dwc_otg_pcd.c | 2725 +++++++ @@ -787,174 +1011,201 @@ Subject: [PATCH] apply RPi patch of 5.10.95 drivers/usb/host/dwc_otg/test/dwc_otg_test.pm | 337 + .../usb/host/dwc_otg/test/test_mod_param.pl | 133 + drivers/usb/host/dwc_otg/test/test_sysfs.pl | 193 + - drivers/usb/host/xhci-mem.c | 67 +- - drivers/usb/host/xhci-pci.c | 2 + - drivers/usb/host/xhci-ring.c | 34 +- - drivers/usb/host/xhci.c | 104 +- - drivers/usb/host/xhci.h | 7 +- + drivers/usb/host/xhci-mem.c | 40 +- + drivers/usb/host/xhci-pci.c | 21 +- + drivers/usb/host/xhci-ring.c | 86 +- + drivers/usb/host/xhci.c | 104 + + drivers/usb/host/xhci.h | 10 +- + drivers/usb/phy/phy-generic.c | 7 - drivers/video/backlight/Kconfig | 7 + drivers/video/backlight/Makefile | 1 + + drivers/video/backlight/lm3630a_bl.c | 2 +- + drivers/video/backlight/lp855x_bl.c | 2 +- + drivers/video/backlight/pwm_bl.c | 12 +- drivers/video/backlight/rpi_backlight.c | 119 + drivers/video/fbdev/Kconfig | 27 + drivers/video/fbdev/Makefile | 2 + drivers/video/fbdev/bcm2708_fb.c | 1274 +++ - drivers/video/fbdev/core/cfbimgblt.c | 152 +- - drivers/video/fbdev/core/fbmem.c | 35 + - drivers/video/fbdev/rpisense-fb.c | 296 + + drivers/video/fbdev/core/fb_chrdev.c | 35 + + drivers/video/fbdev/core/fb_defio.c | 3 +- + drivers/video/fbdev/core/fbmem.c | 19 +- + drivers/video/fbdev/rpisense-fb.c | 297 + + drivers/video/fbdev/ssd1307fb.c | 2 +- drivers/video/logo/logo_linux_clut224.ppm | 2483 ++---- - drivers/w1/masters/w1-gpio.c | 2 +- + drivers/w1/masters/w1-gpio.c | 15 +- + drivers/w1/w1.c | 2 + + drivers/w1/w1_io.c | 37 +- drivers/watchdog/bcm2835_wdt.c | 51 +- - include/drm/drm_atomic.h | 20 + - include/drm/drm_atomic_helper.h | 4 - - include/drm/drm_connector.h | 4 + - include/drm/drm_edid.h | 4 +- - include/drm/drm_modeset_helper_vtables.h | 56 +- - include/drm/drm_panel.h | 8 + - include/drm/drm_probe_helper.h | 1 + - include/drm/gud.h | 333 + + include/drm/drm_color_mgmt.h | 3 + + include/drm/drm_connector.h | 7 + + include/drm/drm_mipi_dsi.h | 38 +- + include/drm/drm_plane.h | 37 + + include/dt-bindings/clock/rp1.h | 56 + include/dt-bindings/gpio/gpio-fsm.h | 21 + + include/dt-bindings/mfd/rp1.h | 235 + include/linux/brcmphy.h | 1 + include/linux/broadcom/bcm2835_smi.h | 391 + include/linux/broadcom/vc_mem.h | 39 + - include/linux/clk.h | 4 + - include/linux/hdmi.h | 2 +- + include/linux/fb.h | 2 + + include/linux/gpio/driver.h | 1 + + include/linux/iommu.h | 8 +- include/linux/leds.h | 3 + - include/linux/mfd/bcm2835-pm.h | 1 + include/linux/mfd/rpisense/core.h | 47 + include/linux/mfd/rpisense/framebuffer.h | 32 + include/linux/mfd/rpisense/joystick.h | 35 + include/linux/microchipphy.h | 8 + include/linux/mmc/card.h | 2 + + include/linux/mmc/sd.h | 12 + + include/linux/module.h | 2 +- include/linux/platform_data/dma-bcm2708.h | 143 + + include/linux/pwm.h | 57 +- + include/linux/rp1_platform.h | 20 + include/linux/usb.h | 2 + include/linux/usb/hcd.h | 7 + - include/linux/usb/r8152.h | 37 + - include/media/hevc-ctrls.h | 17 + + include/linux/w1.h | 5 + include/media/media-request.h | 12 + - include/media/v4l2-mediabus.h | 8 + + include/media/raspberrypi/pisp_common.h | 65 + + include/media/raspberrypi/pisp_types.h | 144 + include/media/videobuf2-core.h | 15 + include/soc/bcm2835/raspberrypi-firmware.h | 29 +- - include/sound/hdmi-codec.h | 17 +- - include/sound/pcm_iec958.h | 8 + - include/uapi/drm/drm_fourcc.h | 11 + - include/uapi/drm/drm_mode.h | 1 + + include/uapi/drm/v3d_drm.h | 4 + include/uapi/linux/bcm2835-isp.h | 347 + include/uapi/linux/fb.h | 12 + - include/uapi/linux/media-bus-format.h | 8 +- - include/uapi/linux/v4l2-controls.h | 6 + - include/uapi/linux/videodev2.h | 13 + + include/uapi/linux/media-bus-format.h | 3 + + include/uapi/linux/v4l2-controls.h | 5 + + include/uapi/linux/videodev2.h | 40 + kernel/cgroup/cgroup.c | 38 + kernel/resource.c | 6 + - mm/page_alloc.c | 2 - - mm/zswap.c | 53 +- + mm/page_alloc.c | 28 +- + net/bluetooth/hci_sync.c | 4 +- net/bluetooth/smp.c | 16 +- - scripts/Makefile.dtbinst | 6 +- + net/wireless/certs/debian.hex | 1426 ++++ + scripts/Makefile.dtbinst | 5 +- scripts/Makefile.lib | 19 + - sound/core/pcm_iec958.c | 129 +- - sound/soc/bcm/Kconfig | 298 + - sound/soc/bcm/Makefile | 69 +- - sound/soc/bcm/allo-boss-dac.c | 456 ++ - sound/soc/bcm/allo-boss2-dac.c | 1133 +++ - sound/soc/bcm/allo-katana-codec.c | 388 + - sound/soc/bcm/allo-piano-dac-plus.c | 1063 +++ + sound/soc/bcm/Kconfig | 269 + + sound/soc/bcm/Makefile | 71 +- + sound/soc/bcm/allo-boss-dac.c | 468 ++ + sound/soc/bcm/allo-boss2-dac.c | 1130 +++ + sound/soc/bcm/allo-katana-codec.c | 386 + + sound/soc/bcm/allo-piano-dac-plus.c | 1064 +++ sound/soc/bcm/allo-piano-dac.c | 122 + .../bcm/audioinjector-isolated-soundcard.c | 183 + - sound/soc/bcm/audioinjector-octo-soundcard.c | 346 + - sound/soc/bcm/audioinjector-pi-soundcard.c | 187 + + sound/soc/bcm/audioinjector-octo-soundcard.c | 347 + + sound/soc/bcm/audioinjector-pi-soundcard.c | 189 + sound/soc/bcm/audiosense-pi.c | 248 + + sound/soc/bcm/bcm2835-i2s.c | 18 +- sound/soc/bcm/chipdip-dac.c | 275 + + sound/soc/bcm/dacberry400.c | 259 + sound/soc/bcm/digidac1-soundcard.c | 421 + sound/soc/bcm/dionaudio_loco-v2.c | 117 + sound/soc/bcm/dionaudio_loco.c | 117 + sound/soc/bcm/fe-pi-audio.c | 154 + sound/soc/bcm/googlevoicehat-codec.c | 214 + - sound/soc/bcm/hifiberry_dacplus.c | 527 ++ - sound/soc/bcm/hifiberry_dacplusadc.c | 398 + - sound/soc/bcm/hifiberry_dacplusadcpro.c | 605 ++ + sound/soc/bcm/hifiberry_dacplus.c | 560 ++ + sound/soc/bcm/hifiberry_dacplusadc.c | 396 + + sound/soc/bcm/hifiberry_dacplusadcpro.c | 603 ++ sound/soc/bcm/hifiberry_dacplusdsp.c | 90 + sound/soc/bcm/hifiberry_dacplushd.c | 238 + - sound/soc/bcm/i-sabre-q2m.c | 158 + - sound/soc/bcm/iqaudio-codec.c | 274 + - sound/soc/bcm/iqaudio-dac.c | 223 + - sound/soc/bcm/justboom-both.c | 266 + + sound/soc/bcm/i-sabre-q2m.c | 159 + + sound/soc/bcm/iqaudio-codec.c | 278 + + sound/soc/bcm/iqaudio-dac.c | 224 + + sound/soc/bcm/justboom-both.c | 267 + sound/soc/bcm/justboom-dac.c | 147 + - sound/soc/bcm/pifi-40.c | 283 + - sound/soc/bcm/pisound.c | 1238 +++ - sound/soc/bcm/rpi-cirrus.c | 1025 +++ + sound/soc/bcm/pifi-40.c | 282 + + sound/soc/bcm/pisound.c | 1255 +++ + sound/soc/bcm/rpi-cirrus.c | 1024 +++ sound/soc/bcm/rpi-proto.c | 147 + - sound/soc/bcm/rpi-simple-soundcard.c | 419 + - sound/soc/bcm/rpi-wm8804-soundcard.c | 410 + - sound/soc/codecs/Kconfig | 28 +- + sound/soc/bcm/rpi-simple-soundcard.c | 520 ++ + sound/soc/bcm/rpi-wm8804-soundcard.c | 549 ++ + sound/soc/codecs/Kconfig | 26 +- sound/soc/codecs/Makefile | 8 + + sound/soc/codecs/adau1977-i2c.c | 10 + sound/soc/codecs/cs42xx8-i2c.c | 9 +- - sound/soc/codecs/cs42xx8.c | 2 + - sound/soc/codecs/hdmi-codec.c | 219 +- - sound/soc/codecs/i-sabre-codec.c | 392 + + sound/soc/codecs/cs42xx8.c | 10 + + sound/soc/codecs/i-sabre-codec.c | 389 + sound/soc/codecs/i-sabre-codec.h | 42 + - sound/soc/codecs/ma120x0p.c | 1384 ++++ + sound/soc/codecs/ma120x0p.c | 1380 ++++ sound/soc/codecs/pcm1794a.c | 69 + - sound/soc/codecs/pcm512x.c | 2 +- - sound/soc/codecs/tas5713.c | 363 + + sound/soc/codecs/pcm512x-i2c.c | 4 + + sound/soc/codecs/pcm512x.c | 38 +- + sound/soc/codecs/tas5713.c | 360 + sound/soc/codecs/tas5713.h | 210 + + sound/soc/dwc/dwc-i2s.c | 169 +- + sound/soc/dwc/local.h | 12 + sound/soc/soc-core.c | 14 +- - sound/usb/quirks-table.h | 9 + - sound/usb/quirks.c | 6 + - 895 files changed, 175509 insertions(+), 4829 deletions(-) + sound/usb/card.c | 8 +- + sound/usb/quirks.c | 2 + + 1131 files changed, 229610 insertions(+), 4285 deletions(-) create mode 100644 Documentation/admin-guide/media/bcm2835-isp.rst - create mode 100644 Documentation/devicetree/bindings/clock/raspberrypi,firmware-clocks.yaml - create mode 100644 Documentation/devicetree/bindings/hwmon/rpi-poe-fan.txt + create mode 100644 Documentation/devicetree/bindings/display/panel/panel-dsi.yaml + create mode 100644 Documentation/devicetree/bindings/hwmon/microchip,emc2305.yaml create mode 100644 Documentation/devicetree/bindings/media/bcm2835-unicam.txt - create mode 100644 Documentation/devicetree/bindings/media/i2c/imx219.txt + create mode 100644 Documentation/devicetree/bindings/media/i2c/ad5398.txt + create mode 100644 Documentation/devicetree/bindings/media/i2c/arducam,64mp.yaml + create mode 100644 Documentation/devicetree/bindings/media/i2c/arducam-pivariety.yaml create mode 100644 Documentation/devicetree/bindings/media/i2c/imx378.yaml create mode 100644 Documentation/devicetree/bindings/media/i2c/imx477.yaml create mode 100644 Documentation/devicetree/bindings/media/i2c/imx519.yaml create mode 100644 Documentation/devicetree/bindings/media/i2c/irs1125.txt + create mode 100644 Documentation/devicetree/bindings/media/i2c/ovti,ov64a40.yaml + create mode 100644 Documentation/devicetree/bindings/media/i2c/rohm,bu64754.yaml + rename Documentation/devicetree/bindings/media/i2c/{imx258.yaml => sony,imx258.yaml} (90%) + create mode 100644 Documentation/devicetree/bindings/media/i2c/sony,imx708.yaml create mode 100644 Documentation/devicetree/bindings/media/rpivid_hevc.yaml create mode 100644 Documentation/devicetree/bindings/misc/brcm,bcm2835-smi-dev.txt create mode 100644 Documentation/devicetree/bindings/misc/brcm,bcm2835-smi.txt - create mode 100644 Documentation/devicetree/bindings/nvmem/rmem.yaml create mode 100644 Documentation/devicetree/bindings/pci/brcmstb-pcie.txt + create mode 100644 Documentation/devicetree/bindings/power/reset/gpio-poweroff.txt + create mode 100644 Documentation/devicetree/bindings/pwm/pwm-rp1.yaml + create mode 100644 Documentation/devicetree/bindings/rtc/rtc-rpi.txt create mode 100644 Documentation/devicetree/bindings/vendor-prefixes.txt create mode 100644 Documentation/devicetree/configfs-overlays.txt - create mode 100644 Documentation/hwmon/rpi-poe-fan create mode 100644 Documentation/userspace-api/media/v4l/pixfmt-meta-bcm2835-isp-stats.rst create mode 100644 Documentation/userspace-api/media/v4l/pixfmt-meta-sensor-data.rst create mode 100644 Documentation/userspace-api/media/v4l/pixfmt-nv12-col128.rst create mode 100644 Documentation/userspace-api/media/v4l/pixfmt-y12p.rst create mode 100644 Documentation/userspace-api/media/v4l/pixfmt-y14p.rst - create mode 100644 arch/arm/boot/dts/bcm2708-rpi-b-plus.dts - create mode 100644 arch/arm/boot/dts/bcm2708-rpi-b-rev1.dts - create mode 100644 arch/arm/boot/dts/bcm2708-rpi-b.dts - create mode 100644 arch/arm/boot/dts/bcm2708-rpi-bt.dtsi - create mode 100644 arch/arm/boot/dts/bcm2708-rpi-cm.dts - create mode 100644 arch/arm/boot/dts/bcm2708-rpi-cm.dtsi - create mode 100644 arch/arm/boot/dts/bcm2708-rpi-zero-w.dts - create mode 100644 arch/arm/boot/dts/bcm2708-rpi-zero.dts - create mode 100644 arch/arm/boot/dts/bcm2708-rpi.dtsi - create mode 100644 arch/arm/boot/dts/bcm2708.dtsi - create mode 100644 arch/arm/boot/dts/bcm2709-rpi-2-b.dts - create mode 100644 arch/arm/boot/dts/bcm2709-rpi.dtsi - create mode 100644 arch/arm/boot/dts/bcm2709.dtsi - create mode 100644 arch/arm/boot/dts/bcm270x-rpi.dtsi - create mode 100644 arch/arm/boot/dts/bcm270x.dtsi - create mode 100644 arch/arm/boot/dts/bcm2710-rpi-2-b.dts - create mode 100644 arch/arm/boot/dts/bcm2710-rpi-3-b-plus.dts - create mode 100644 arch/arm/boot/dts/bcm2710-rpi-3-b.dts - create mode 100644 arch/arm/boot/dts/bcm2710-rpi-cm3.dts - create mode 100644 arch/arm/boot/dts/bcm2710-rpi-zero-2-w.dts - create mode 100644 arch/arm/boot/dts/bcm2710-rpi-zero-2.dts - create mode 100644 arch/arm/boot/dts/bcm2710.dtsi - create mode 100644 arch/arm/boot/dts/bcm2711-rpi-400.dts - create mode 100644 arch/arm/boot/dts/bcm2711-rpi-cm4.dts - create mode 100644 arch/arm/boot/dts/bcm2711-rpi-cm4s.dts - create mode 100644 arch/arm/boot/dts/bcm2711-rpi.dtsi - create mode 100644 arch/arm/boot/dts/bcm271x-rpi-bt.dtsi - create mode 100644 arch/arm/boot/dts/bcm283x-rpi-csi0-2lane.dtsi - create mode 100644 arch/arm/boot/dts/bcm283x-rpi-csi1-2lane.dtsi - create mode 100644 arch/arm/boot/dts/bcm283x-rpi-csi1-4lane.dtsi - create mode 100644 arch/arm/boot/dts/bcm283x-rpi-i2c0mux_0_28.dtsi - create mode 100644 arch/arm/boot/dts/bcm283x-rpi-i2c0mux_0_44.dtsi - delete mode 100644 arch/arm/boot/dts/bcm283x-rpi-usb-peripheral.dtsi + create mode 100644 README.md + create mode 100644 arch/arm/boot/dts/broadcom/bcm2708-rpi-b-plus.dts + create mode 100644 arch/arm/boot/dts/broadcom/bcm2708-rpi-b-rev1.dts + create mode 100644 arch/arm/boot/dts/broadcom/bcm2708-rpi-b.dts + create mode 100644 arch/arm/boot/dts/broadcom/bcm2708-rpi-bt.dtsi + create mode 100644 arch/arm/boot/dts/broadcom/bcm2708-rpi-cm.dts + create mode 100644 arch/arm/boot/dts/broadcom/bcm2708-rpi-cm.dtsi + create mode 100644 arch/arm/boot/dts/broadcom/bcm2708-rpi-zero-w.dts + create mode 100644 arch/arm/boot/dts/broadcom/bcm2708-rpi-zero.dts + create mode 100644 arch/arm/boot/dts/broadcom/bcm2708-rpi.dtsi + create mode 100644 arch/arm/boot/dts/broadcom/bcm2708.dtsi + create mode 100644 arch/arm/boot/dts/broadcom/bcm2709-rpi-2-b.dts + create mode 100644 arch/arm/boot/dts/broadcom/bcm2709-rpi-cm2.dts + create mode 100644 arch/arm/boot/dts/broadcom/bcm2709-rpi.dtsi + create mode 100644 arch/arm/boot/dts/broadcom/bcm2709.dtsi + create mode 100644 arch/arm/boot/dts/broadcom/bcm270x-rpi.dtsi + create mode 100644 arch/arm/boot/dts/broadcom/bcm270x.dtsi + create mode 100644 arch/arm/boot/dts/broadcom/bcm2710-rpi-2-b.dts + create mode 100644 arch/arm/boot/dts/broadcom/bcm2710-rpi-3-b-plus.dts + create mode 100644 arch/arm/boot/dts/broadcom/bcm2710-rpi-3-b.dts + create mode 100644 arch/arm/boot/dts/broadcom/bcm2710-rpi-cm3.dts + create mode 100644 arch/arm/boot/dts/broadcom/bcm2710-rpi-zero-2-w.dts + create mode 100644 arch/arm/boot/dts/broadcom/bcm2710-rpi-zero-2.dts + create mode 100644 arch/arm/boot/dts/broadcom/bcm2710.dtsi + create mode 100644 arch/arm/boot/dts/broadcom/bcm2711-rpi-cm4.dts + create mode 100644 arch/arm/boot/dts/broadcom/bcm2711-rpi-cm4s.dts + create mode 100644 arch/arm/boot/dts/broadcom/bcm2711-rpi-ds.dtsi + create mode 100644 arch/arm/boot/dts/broadcom/bcm2712-rpi-5-b.dts + create mode 100644 arch/arm/boot/dts/broadcom/bcm2712-rpi-cm5-cm4io.dts + create mode 100644 arch/arm/boot/dts/broadcom/bcm2712-rpi-cm5-cm5io.dts + create mode 100644 arch/arm/boot/dts/broadcom/bcm2712-rpi-cm5.dtsi + create mode 100644 arch/arm/boot/dts/broadcom/bcm2712-rpi.dtsi + create mode 100644 arch/arm/boot/dts/broadcom/bcm2712.dtsi + create mode 100644 arch/arm/boot/dts/broadcom/bcm2712d0-rpi-5-b.dts + create mode 100644 arch/arm/boot/dts/broadcom/bcm271x-rpi-bt.dtsi + create mode 100644 arch/arm/boot/dts/broadcom/bcm283x-rpi-csi0-2lane.dtsi + create mode 100644 arch/arm/boot/dts/broadcom/bcm283x-rpi-csi1-2lane.dtsi + create mode 100644 arch/arm/boot/dts/broadcom/bcm283x-rpi-csi1-4lane.dtsi + create mode 100644 arch/arm/boot/dts/broadcom/bcm283x-rpi-i2c0mux_0_28.dtsi + create mode 100644 arch/arm/boot/dts/broadcom/bcm283x-rpi-i2c0mux_0_44.dtsi + create mode 100644 arch/arm/boot/dts/broadcom/rp1.dtsi create mode 100644 arch/arm/boot/dts/overlays/Makefile create mode 100644 arch/arm/boot/dts/overlays/README create mode 100644 arch/arm/boot/dts/overlays/act-led-overlay.dts @@ -977,23 +1228,38 @@ Subject: [PATCH] apply RPi patch of 5.10.95 create mode 100755 arch/arm/boot/dts/overlays/anyspi-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/apds9960-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/applepi-dac-overlay.dts + create mode 100644 arch/arm/boot/dts/overlays/arducam-64mp-overlay.dts + create mode 100644 arch/arm/boot/dts/overlays/arducam-64mp.dtsi + create mode 100644 arch/arm/boot/dts/overlays/arducam-pivariety-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/at86rf233-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/audioinjector-addons-overlay.dts + create mode 100644 arch/arm/boot/dts/overlays/audioinjector-bare-i2s-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/audioinjector-isolated-soundcard-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/audioinjector-ultra-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/audioinjector-wm8731-audio-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/audiosense-pi-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/audremap-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/balena-fin-overlay.dts + create mode 100644 arch/arm/boot/dts/overlays/bcm2712d0-overlay.dts + create mode 100644 arch/arm/boot/dts/overlays/camera-mux-2port-overlay.dts + create mode 100644 arch/arm/boot/dts/overlays/camera-mux-4port-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/cap1106-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/chipdip-dac-overlay.dts + create mode 100644 arch/arm/boot/dts/overlays/cirrus-wm5102-overlay.dts + create mode 100644 arch/arm/boot/dts/overlays/cm-swap-i2c0-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/cma-overlay.dts + create mode 100644 arch/arm/boot/dts/overlays/crystalfontz-cfa050_pi_m-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/cutiepi-panel-overlay.dts + create mode 100644 arch/arm/boot/dts/overlays/dacberry400-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/dht11-overlay.dts + create mode 100644 arch/arm/boot/dts/overlays/dionaudio-kiwi-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/dionaudio-loco-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/dionaudio-loco-v2-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/disable-bt-overlay.dts + create mode 100644 arch/arm/boot/dts/overlays/disable-bt-pi5-overlay.dts + create mode 100644 arch/arm/boot/dts/overlays/disable-emmc2-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/disable-wifi-overlay.dts + create mode 100644 arch/arm/boot/dts/overlays/disable-wifi-pi5-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/dpi18-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/dpi18cpadhi-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/dpi24-overlay.dts @@ -1008,10 +1274,13 @@ Subject: [PATCH] apply RPi patch of 5.10.95 create mode 100644 arch/arm/boot/dts/overlays/fbtft-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/fe-pi-audio-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/fsm-demo-overlay.dts + create mode 100644 arch/arm/boot/dts/overlays/gc9a01-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/ghost-amp-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/goodix-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/googlevoicehat-soundcard-overlay.dts + create mode 100644 arch/arm/boot/dts/overlays/gpio-charger-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/gpio-fan-overlay.dts + create mode 100644 arch/arm/boot/dts/overlays/gpio-hog-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/gpio-ir-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/gpio-ir-tx-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/gpio-key-overlay.dts @@ -1020,12 +1289,18 @@ Subject: [PATCH] apply RPi patch of 5.10.95 create mode 100644 arch/arm/boot/dts/overlays/gpio-no-irq-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/gpio-poweroff-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/gpio-shutdown-overlay.dts + create mode 100644 arch/arm/boot/dts/overlays/hat_map.dts create mode 100644 arch/arm/boot/dts/overlays/hd44780-lcd-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/hdmi-backlight-hwhack-gpio-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/hifiberry-amp-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/hifiberry-amp100-overlay.dts + create mode 100644 arch/arm/boot/dts/overlays/hifiberry-amp3-overlay.dts + create mode 100644 arch/arm/boot/dts/overlays/hifiberry-amp4pro-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/hifiberry-dac-overlay.dts + create mode 100644 arch/arm/boot/dts/overlays/hifiberry-dac8x-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/hifiberry-dacplus-overlay.dts + create mode 100644 arch/arm/boot/dts/overlays/hifiberry-dacplus-pro-overlay.dts + create mode 100644 arch/arm/boot/dts/overlays/hifiberry-dacplus-std-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/hifiberry-dacplusadc-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/hifiberry-dacplusadcpro-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/hifiberry-dacplusdsp-overlay.dts @@ -1038,32 +1313,53 @@ Subject: [PATCH] apply RPi patch of 5.10.95 create mode 100644 arch/arm/boot/dts/overlays/hy28b-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/i-sabre-q2m-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/i2c-bcm2708-overlay.dts + create mode 100644 arch/arm/boot/dts/overlays/i2c-fan-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/i2c-gpio-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/i2c-mux-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/i2c-pwm-pca9685a-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/i2c-rtc-common.dtsi create mode 100644 arch/arm/boot/dts/overlays/i2c-rtc-gpio-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/i2c-rtc-overlay.dts + create mode 100755 arch/arm/boot/dts/overlays/i2c-sensor-common.dtsi create mode 100755 arch/arm/boot/dts/overlays/i2c-sensor-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/i2c0-overlay.dts + create mode 100644 arch/arm/boot/dts/overlays/i2c0-pi5-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/i2c1-overlay.dts + create mode 100644 arch/arm/boot/dts/overlays/i2c1-pi5-overlay.dts + create mode 100644 arch/arm/boot/dts/overlays/i2c2-pi5-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/i2c3-overlay.dts + create mode 100644 arch/arm/boot/dts/overlays/i2c3-pi5-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/i2c4-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/i2c5-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/i2c6-overlay.dts + create mode 100644 arch/arm/boot/dts/overlays/i2s-dac-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/i2s-gpio28-31-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/ilitek251x-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/imx219-overlay.dts + create mode 100644 arch/arm/boot/dts/overlays/imx219.dtsi + create mode 100644 arch/arm/boot/dts/overlays/imx258-overlay.dts + create mode 100644 arch/arm/boot/dts/overlays/imx258.dtsi create mode 100644 arch/arm/boot/dts/overlays/imx290-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/imx290_327-overlay.dtsi + create mode 100644 arch/arm/boot/dts/overlays/imx290_327.dtsi + create mode 100644 arch/arm/boot/dts/overlays/imx296-overlay.dts + create mode 100644 arch/arm/boot/dts/overlays/imx327-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/imx378-overlay.dts + create mode 100644 arch/arm/boot/dts/overlays/imx462-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/imx477-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/imx477_378-overlay.dtsi + create mode 100644 arch/arm/boot/dts/overlays/imx477_378.dtsi create mode 100644 arch/arm/boot/dts/overlays/imx519-overlay.dts + create mode 100644 arch/arm/boot/dts/overlays/imx519.dtsi + create mode 100644 arch/arm/boot/dts/overlays/imx708-overlay.dts + create mode 100644 arch/arm/boot/dts/overlays/imx708.dtsi + create mode 100644 arch/arm/boot/dts/overlays/interludeaudio-analog-overlay.dts + create mode 100644 arch/arm/boot/dts/overlays/interludeaudio-digital-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/iqaudio-codec-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/iqaudio-dac-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/iqaudio-dacplus-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/iqaudio-digi-wm8804-audio-overlay.dts + create mode 100644 arch/arm/boot/dts/overlays/iqs550-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/irs1125-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/jedec-spi-nor-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/justboom-both-overlay.dts @@ -1085,24 +1381,38 @@ Subject: [PATCH] apply RPi patch of 5.10.95 create mode 100644 arch/arm/boot/dts/overlays/media-center-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/merus-amp-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/midi-uart0-overlay.dts + create mode 100644 arch/arm/boot/dts/overlays/midi-uart0-pi5-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/midi-uart1-overlay.dts + create mode 100644 arch/arm/boot/dts/overlays/midi-uart1-pi5-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/midi-uart2-overlay.dts + create mode 100644 arch/arm/boot/dts/overlays/midi-uart2-pi5-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/midi-uart3-overlay.dts + create mode 100644 arch/arm/boot/dts/overlays/midi-uart3-pi5-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/midi-uart4-overlay.dts + create mode 100644 arch/arm/boot/dts/overlays/midi-uart4-pi5-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/midi-uart5-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/minipitft13-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/miniuart-bt-overlay.dts + create mode 100644 arch/arm/boot/dts/overlays/mipi-dbi-spi-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/mlx90640-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/mmc-overlay.dts - create mode 100644 arch/arm/boot/dts/overlays/mpu6050-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/mz61581-overlay.dts + create mode 100644 arch/arm/boot/dts/overlays/ov2311-overlay.dts + create mode 100644 arch/arm/boot/dts/overlays/ov2311.dtsi create mode 100644 arch/arm/boot/dts/overlays/ov5647-overlay.dts + create mode 100644 arch/arm/boot/dts/overlays/ov5647.dtsi + create mode 100644 arch/arm/boot/dts/overlays/ov64a40-overlay.dts + create mode 100644 arch/arm/boot/dts/overlays/ov64a40.dtsi create mode 100644 arch/arm/boot/dts/overlays/ov7251-overlay.dts + create mode 100644 arch/arm/boot/dts/overlays/ov7251.dtsi create mode 100644 arch/arm/boot/dts/overlays/ov9281-overlay.dts + create mode 100644 arch/arm/boot/dts/overlays/ov9281.dtsi create mode 100644 arch/arm/boot/dts/overlays/overlay_map.dts create mode 100644 arch/arm/boot/dts/overlays/papirus-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/pca953x-overlay.dts + create mode 100644 arch/arm/boot/dts/overlays/pcf857x-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/pcie-32bit-dma-overlay.dts + create mode 100644 arch/arm/boot/dts/overlays/pcie-32bit-dma-pi5-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/pibell-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/pifacedigital-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/pifi-40-overlay.dts @@ -1113,28 +1423,33 @@ Subject: [PATCH] apply RPi patch of 5.10.95 create mode 100644 arch/arm/boot/dts/overlays/piscreen-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/piscreen2r-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/pisound-overlay.dts + create mode 100644 arch/arm/boot/dts/overlays/pisound-pi5-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/pitft22-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/pitft28-capacitive-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/pitft28-resistive-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/pitft35-resistive-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/pps-gpio-overlay.dts + create mode 100644 arch/arm/boot/dts/overlays/proto-codec-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/pwm-2chan-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/pwm-ir-tx-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/pwm-overlay.dts + create mode 100644 arch/arm/boot/dts/overlays/pwm1-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/qca7000-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/qca7000-uart0-overlay.dts + create mode 100644 arch/arm/boot/dts/overlays/ramoops-overlay.dts + create mode 100644 arch/arm/boot/dts/overlays/ramoops-pi4-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/rotary-encoder-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/rpi-backlight-overlay.dts - create mode 100644 arch/arm/boot/dts/overlays/rpi-cirrus-wm5102-overlay.dts - create mode 100644 arch/arm/boot/dts/overlays/rpi-dac-overlay.dts - create mode 100644 arch/arm/boot/dts/overlays/rpi-display-overlay.dts + create mode 100644 arch/arm/boot/dts/overlays/rpi-codeczero-overlay.dts + create mode 100644 arch/arm/boot/dts/overlays/rpi-dacplus-overlay.dts + create mode 100644 arch/arm/boot/dts/overlays/rpi-dacpro-overlay.dts + create mode 100644 arch/arm/boot/dts/overlays/rpi-digiampplus-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/rpi-ft5406-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/rpi-poe-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/rpi-poe-plus-overlay.dts - create mode 100644 arch/arm/boot/dts/overlays/rpi-proto-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/rpi-sense-overlay.dts + create mode 100644 arch/arm/boot/dts/overlays/rpi-sense-v2-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/rpi-tv-overlay.dts - create mode 100644 arch/arm/boot/dts/overlays/rpivid-v4l2-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/rra-digidac1-wm8741-audio-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/sainsmart18-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/sc16is750-i2c-overlay.dts @@ -1143,6 +1458,7 @@ Subject: [PATCH] apply RPi patch of 5.10.95 create mode 100644 arch/arm/boot/dts/overlays/sc16is752-spi1-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/sdhost-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/sdio-overlay.dts + create mode 100644 arch/arm/boot/dts/overlays/sdio-pi5-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/seeed-can-fd-hat-v1-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/seeed-can-fd-hat-v2-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/sh1106-spi-overlay.dts @@ -1160,14 +1476,20 @@ Subject: [PATCH] apply RPi patch of 5.10.95 create mode 100644 arch/arm/boot/dts/overlays/spi1-2cs-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/spi1-3cs-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/spi2-1cs-overlay.dts + create mode 100644 arch/arm/boot/dts/overlays/spi2-1cs-pi5-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/spi2-2cs-overlay.dts + create mode 100644 arch/arm/boot/dts/overlays/spi2-2cs-pi5-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/spi2-3cs-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/spi3-1cs-overlay.dts + create mode 100644 arch/arm/boot/dts/overlays/spi3-1cs-pi5-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/spi3-2cs-overlay.dts + create mode 100644 arch/arm/boot/dts/overlays/spi3-2cs-pi5-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/spi4-1cs-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/spi4-2cs-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/spi5-1cs-overlay.dts + create mode 100644 arch/arm/boot/dts/overlays/spi5-1cs-pi5-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/spi5-2cs-overlay.dts + create mode 100644 arch/arm/boot/dts/overlays/spi5-2cs-pi5-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/spi6-1cs-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/spi6-2cs-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/ssd1306-overlay.dts @@ -1180,11 +1502,17 @@ Subject: [PATCH] apply RPi patch of 5.10.95 create mode 100644 arch/arm/boot/dts/overlays/tc358743-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/tinylcd35-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/tpm-slb9670-overlay.dts + create mode 100644 arch/arm/boot/dts/overlays/tpm-slb9673-overlay.dts create mode 100755 arch/arm/boot/dts/overlays/uart0-overlay.dts + create mode 100755 arch/arm/boot/dts/overlays/uart0-pi5-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/uart1-overlay.dts + create mode 100755 arch/arm/boot/dts/overlays/uart1-pi5-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/uart2-overlay.dts + create mode 100755 arch/arm/boot/dts/overlays/uart2-pi5-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/uart3-overlay.dts + create mode 100755 arch/arm/boot/dts/overlays/uart3-pi5-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/uart4-overlay.dts + create mode 100755 arch/arm/boot/dts/overlays/uart4-pi5-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/uart5-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/udrc-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/ugreen-dabboard-overlay.dts @@ -1193,20 +1521,34 @@ Subject: [PATCH] apply RPi patch of 5.10.95 create mode 100644 arch/arm/boot/dts/overlays/vc4-fkms-v3d-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/vc4-fkms-v3d-pi4-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/vc4-kms-dpi-generic-overlay.dts + create mode 100644 arch/arm/boot/dts/overlays/vc4-kms-dpi-hyperpixel.dtsi + create mode 100644 arch/arm/boot/dts/overlays/vc4-kms-dpi-hyperpixel2r-overlay.dts + create mode 100644 arch/arm/boot/dts/overlays/vc4-kms-dpi-hyperpixel4-overlay.dts + create mode 100644 arch/arm/boot/dts/overlays/vc4-kms-dpi-hyperpixel4sq-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/vc4-kms-dpi-panel-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/vc4-kms-dpi.dtsi create mode 100644 arch/arm/boot/dts/overlays/vc4-kms-dsi-7inch-overlay.dts + create mode 100644 arch/arm/boot/dts/overlays/vc4-kms-dsi-generic-overlay.dts + create mode 100644 arch/arm/boot/dts/overlays/vc4-kms-dsi-ili9881-5inch-overlay.dts + create mode 100644 arch/arm/boot/dts/overlays/vc4-kms-dsi-ili9881-7inch-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/vc4-kms-dsi-lt070me05000-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/vc4-kms-dsi-lt070me05000-v2-overlay.dts + create mode 100644 arch/arm/boot/dts/overlays/vc4-kms-dsi-waveshare-panel-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/vc4-kms-kippah-7inch-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/vc4-kms-v3d-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/vc4-kms-v3d-pi4-overlay.dts + create mode 100644 arch/arm/boot/dts/overlays/vc4-kms-v3d-pi5-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/vc4-kms-vga666-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/vga666-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/vl805-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/w1-gpio-overlay.dts + create mode 100644 arch/arm/boot/dts/overlays/w1-gpio-pi5-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/w1-gpio-pullup-overlay.dts + create mode 100644 arch/arm/boot/dts/overlays/w1-gpio-pullup-pi5-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/w5500-overlay.dts + create mode 100644 arch/arm/boot/dts/overlays/watterott-display-overlay.dts + create mode 100644 arch/arm/boot/dts/overlays/waveshare-can-fd-hat-mode-a-overlay.dts + create mode 100644 arch/arm/boot/dts/overlays/waveshare-can-fd-hat-mode-b-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/wittypi-overlay.dts create mode 100644 arch/arm/boot/dts/overlays/wm8960-soundcard-overlay.dts create mode 100644 arch/arm/configs/bcm2709_defconfig @@ -1223,59 +1565,123 @@ Subject: [PATCH] apply RPi patch of 5.10.95 create mode 100644 arch/arm64/boot/dts/broadcom/bcm2710-rpi-3-b-plus.dts create mode 100644 arch/arm64/boot/dts/broadcom/bcm2710-rpi-3-b.dts create mode 100644 arch/arm64/boot/dts/broadcom/bcm2710-rpi-cm3.dts + create mode 100644 arch/arm64/boot/dts/broadcom/bcm2710-rpi-zero-2-w.dts create mode 100644 arch/arm64/boot/dts/broadcom/bcm2710-rpi-zero-2.dts - create mode 100644 arch/arm64/boot/dts/broadcom/bcm2711-rpi-400.dts create mode 100644 arch/arm64/boot/dts/broadcom/bcm2711-rpi-cm4.dts + create mode 100644 arch/arm64/boot/dts/broadcom/bcm2711-rpi-cm4s.dts + create mode 100644 arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts + create mode 100644 arch/arm64/boot/dts/broadcom/bcm2712-rpi-cm5-cm4io.dts + create mode 100644 arch/arm64/boot/dts/broadcom/bcm2712-rpi-cm5-cm5io.dts + create mode 100644 arch/arm64/boot/dts/broadcom/bcm2712d0-rpi-5-b.dts create mode 120000 arch/arm64/boot/dts/broadcom/bcm283x-rpi-csi1-2lane.dtsi create mode 120000 arch/arm64/boot/dts/broadcom/bcm283x-rpi-lan7515.dtsi create mode 120000 arch/arm64/boot/dts/overlays create mode 100644 arch/arm64/configs/bcm2711_defconfig + create mode 100644 arch/arm64/configs/bcm2712_defconfig create mode 100644 arch/arm64/configs/bcmrpi3_defconfig create mode 100644 drivers/char/broadcom/Kconfig create mode 100644 drivers/char/broadcom/Makefile - create mode 100644 drivers/char/broadcom/bcm2835-gpiomem.c create mode 100644 drivers/char/broadcom/bcm2835_smi_dev.c - create mode 100644 drivers/char/broadcom/rpivid-mem.c create mode 100644 drivers/char/broadcom/vc_mem.c create mode 100644 drivers/char/broadcom/vcio.c - create mode 100644 drivers/clk/clk-allo-dac.c + create mode 100644 drivers/char/raspberrypi-gpiomem.c create mode 100644 drivers/clk/clk-hifiberry-dachd.c create mode 100644 drivers/clk/clk-hifiberry-dacpro.c + create mode 100644 drivers/clk/clk-rp1-sdio.c + create mode 100644 drivers/clk/clk-rp1.c create mode 100644 drivers/dma/bcm2708-dmaengine.c create mode 100644 drivers/gpio/gpio-bcm-virt.c create mode 100644 drivers/gpio/gpio-fsm.c create mode 100644 drivers/gpio/gpio-pwm.c - create mode 100644 drivers/gpu/drm/gud/Kconfig - create mode 100644 drivers/gpu/drm/gud/Makefile - create mode 100644 drivers/gpu/drm/gud/gud_connector.c - create mode 100644 drivers/gpu/drm/gud/gud_drv.c - create mode 100644 drivers/gpu/drm/gud/gud_internal.h - create mode 100644 drivers/gpu/drm/gud/gud_pipe.c + create mode 100644 drivers/gpu/drm/panel/panel-ilitek-ili9806e.c + create mode 100644 drivers/gpu/drm/panel/panel-tdo-y17p.c + create mode 100644 drivers/gpu/drm/panel/panel-waveshare-dsi.c + create mode 100644 drivers/gpu/drm/rp1/Kconfig + create mode 100644 drivers/gpu/drm/rp1/Makefile + create mode 100644 drivers/gpu/drm/rp1/rp1-dpi/Kconfig + create mode 100644 drivers/gpu/drm/rp1/rp1-dpi/Makefile + create mode 100644 drivers/gpu/drm/rp1/rp1-dpi/rp1_dpi.c + create mode 100644 drivers/gpu/drm/rp1/rp1-dpi/rp1_dpi.h + create mode 100644 drivers/gpu/drm/rp1/rp1-dpi/rp1_dpi_cfg.c + create mode 100644 drivers/gpu/drm/rp1/rp1-dpi/rp1_dpi_hw.c + create mode 100644 drivers/gpu/drm/rp1/rp1-dsi/Kconfig + create mode 100644 drivers/gpu/drm/rp1/rp1-dsi/Makefile + create mode 100644 drivers/gpu/drm/rp1/rp1-dsi/rp1_dsi.c + create mode 100644 drivers/gpu/drm/rp1/rp1-dsi/rp1_dsi.h + create mode 100644 drivers/gpu/drm/rp1/rp1-dsi/rp1_dsi_dma.c + create mode 100644 drivers/gpu/drm/rp1/rp1-dsi/rp1_dsi_dsi.c + create mode 100644 drivers/gpu/drm/rp1/rp1-vec/Kconfig + create mode 100644 drivers/gpu/drm/rp1/rp1-vec/Makefile + create mode 100644 drivers/gpu/drm/rp1/rp1-vec/rp1_vec.c + create mode 100644 drivers/gpu/drm/rp1/rp1-vec/rp1_vec.h + create mode 100644 drivers/gpu/drm/rp1/rp1-vec/rp1_vec_cfg.c + create mode 100644 drivers/gpu/drm/rp1/rp1-vec/rp1_vec_hw.c + create mode 100644 drivers/gpu/drm/rp1/rp1-vec/vec_regs.h + create mode 100644 drivers/gpu/drm/vc4/tests/vc4_test_lbm_size.c create mode 100644 drivers/gpu/drm/vc4/vc4_firmware_kms.c create mode 100644 drivers/gpu/drm/vc4/vc_image_types.h - create mode 100644 drivers/hwmon/rpi-poe-fan.c + create mode 100644 drivers/hwmon/rp1-adc.c create mode 100644 drivers/i2c/busses/i2c-bcm2708.c create mode 100644 drivers/input/joystick/rpisense-js.c + create mode 100644 drivers/iommu/bcm2712-iommu-cache.c + create mode 100644 drivers/iommu/bcm2712-iommu.c + create mode 100644 drivers/iommu/bcm2712-iommu.h + create mode 100644 drivers/irqchip/irq-bcm2712-mip.c create mode 100644 drivers/leds/trigger/ledtrig-actpwr.c create mode 100644 drivers/leds/trigger/ledtrig-input.c + create mode 100644 drivers/media/i2c/ad5398_vcm.c + create mode 100644 drivers/media/i2c/arducam-pivariety.c + create mode 100644 drivers/media/i2c/arducam-pivariety.h + create mode 100644 drivers/media/i2c/arducam_64mp.c + create mode 100644 drivers/media/i2c/bu64754.c create mode 100644 drivers/media/i2c/imx477.c create mode 100644 drivers/media/i2c/imx519.c + create mode 100644 drivers/media/i2c/imx708.c create mode 100644 drivers/media/i2c/irs1125.c create mode 100644 drivers/media/i2c/irs1125.h - create mode 100644 drivers/media/i2c/ov9281.c + create mode 100644 drivers/media/i2c/ov2311.c + create mode 100644 drivers/media/i2c/ov64a40.c create mode 100644 drivers/media/platform/bcm2835/Kconfig create mode 100644 drivers/media/platform/bcm2835/Makefile create mode 100644 drivers/media/platform/bcm2835/bcm2835-unicam.c create mode 100644 drivers/media/platform/bcm2835/vc4-regs-unicam.h + create mode 100644 drivers/media/platform/raspberrypi/Kconfig + create mode 100644 drivers/media/platform/raspberrypi/Makefile + create mode 100644 drivers/media/platform/raspberrypi/pisp_be/Kconfig + create mode 100644 drivers/media/platform/raspberrypi/pisp_be/Makefile + create mode 100644 drivers/media/platform/raspberrypi/pisp_be/pisp_be.c + create mode 100644 drivers/media/platform/raspberrypi/pisp_be/pisp_be_config.h + create mode 100644 drivers/media/platform/raspberrypi/pisp_be/pisp_be_formats.h + create mode 100644 drivers/media/platform/raspberrypi/rp1_cfe/Kconfig + create mode 100644 drivers/media/platform/raspberrypi/rp1_cfe/Makefile + create mode 100644 drivers/media/platform/raspberrypi/rp1_cfe/cfe.c + create mode 100644 drivers/media/platform/raspberrypi/rp1_cfe/cfe.h + create mode 100644 drivers/media/platform/raspberrypi/rp1_cfe/cfe_fmts.h + create mode 100644 drivers/media/platform/raspberrypi/rp1_cfe/csi2.c + create mode 100644 drivers/media/platform/raspberrypi/rp1_cfe/csi2.h + create mode 100644 drivers/media/platform/raspberrypi/rp1_cfe/dphy.c + create mode 100644 drivers/media/platform/raspberrypi/rp1_cfe/dphy.h + create mode 100644 drivers/media/platform/raspberrypi/rp1_cfe/pisp_common.h + create mode 100644 drivers/media/platform/raspberrypi/rp1_cfe/pisp_fe.c + create mode 100644 drivers/media/platform/raspberrypi/rp1_cfe/pisp_fe.h + create mode 100644 drivers/media/platform/raspberrypi/rp1_cfe/pisp_fe_config.h + create mode 100644 drivers/media/platform/raspberrypi/rp1_cfe/pisp_statistics.h + create mode 100644 drivers/media/platform/raspberrypi/rp1_cfe/pisp_types.h + create mode 100644 drivers/mfd/rp1.c create mode 100644 drivers/mfd/rpisense-core.c create mode 100644 drivers/misc/bcm2835_smi.c create mode 100644 drivers/mmc/host/bcm2835-mmc.c create mode 100644 drivers/mmc/host/bcm2835-sdhost.c - create mode 100644 drivers/net/usb/r8153_ecm.c - create mode 100644 drivers/nvmem/rmem.c + create mode 100644 drivers/net/ethernet/realtek/r8169_leds.c + create mode 100644 drivers/nvmem/raspberrypi-otp.c create mode 100644 drivers/of/configfs.c create mode 100644 drivers/perf/raspberrypi_axi_monitor.c + create mode 100644 drivers/pinctrl/bcm/pinctrl-bcm2712.c + create mode 100644 drivers/pinctrl/pinctrl-rp1.c create mode 100644 drivers/power/supply/rpi_poe_power.c + create mode 100644 drivers/pwm/pwm-rp1.c + create mode 100644 drivers/regulator/rpi-panel-v2-regulator.c + create mode 100644 drivers/rtc/rtc-rpi.c create mode 100644 drivers/staging/media/rpivid/Kconfig create mode 100644 drivers/staging/media/rpivid/Makefile create mode 100644 drivers/staging/media/rpivid/rpivid.c @@ -1370,16 +1776,20 @@ Subject: [PATCH] apply RPi patch of 5.10.95 create mode 100644 drivers/video/backlight/rpi_backlight.c create mode 100644 drivers/video/fbdev/bcm2708_fb.c create mode 100644 drivers/video/fbdev/rpisense-fb.c - create mode 100644 include/drm/gud.h + create mode 100644 include/dt-bindings/clock/rp1.h create mode 100644 include/dt-bindings/gpio/gpio-fsm.h + create mode 100644 include/dt-bindings/mfd/rp1.h create mode 100644 include/linux/broadcom/bcm2835_smi.h create mode 100644 include/linux/broadcom/vc_mem.h create mode 100644 include/linux/mfd/rpisense/core.h create mode 100644 include/linux/mfd/rpisense/framebuffer.h create mode 100644 include/linux/mfd/rpisense/joystick.h create mode 100644 include/linux/platform_data/dma-bcm2708.h - create mode 100644 include/linux/usb/r8152.h + create mode 100644 include/linux/rp1_platform.h + create mode 100644 include/media/raspberrypi/pisp_common.h + create mode 100644 include/media/raspberrypi/pisp_types.h create mode 100644 include/uapi/linux/bcm2835-isp.h + create mode 100644 net/wireless/certs/debian.hex create mode 100644 sound/soc/bcm/allo-boss-dac.c create mode 100644 sound/soc/bcm/allo-boss2-dac.c create mode 100644 sound/soc/bcm/allo-katana-codec.c @@ -1390,6 +1800,7 @@ Subject: [PATCH] apply RPi patch of 5.10.95 create mode 100644 sound/soc/bcm/audioinjector-pi-soundcard.c create mode 100644 sound/soc/bcm/audiosense-pi.c create mode 100644 sound/soc/bcm/chipdip-dac.c + create mode 100644 sound/soc/bcm/dacberry400.c create mode 100644 sound/soc/bcm/digidac1-soundcard.c create mode 100644 sound/soc/bcm/dionaudio_loco-v2.c create mode 100644 sound/soc/bcm/dionaudio_loco.c @@ -1551,289 +1962,238 @@ index 000000000000..e1c19f78435e + bcm2835_isp_black_level bcm2835_isp_geq bcm2835_isp_gamma + bcm2835_isp_denoise bcm2835_isp_sharpen + bcm2835_isp_dpc_mode bcm2835_isp_dpc -diff --git a/Documentation/devicetree/bindings/clock/raspberrypi,firmware-clocks.yaml b/Documentation/devicetree/bindings/clock/raspberrypi,firmware-clocks.yaml -new file mode 100644 -index 000000000000..2047e25700c6 ---- /dev/null -+++ b/Documentation/devicetree/bindings/clock/raspberrypi,firmware-clocks.yaml -@@ -0,0 +1,32 @@ -+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -+%YAML 1.2 -+--- -+$id: http://devicetree.org/schemas/clock/raspberrypi,firmware-clocks.yaml# -+$schema: http://devicetree.org/meta-schemas/core.yaml# -+ -+title: RaspberryPi Firmware Clocks Device Tree Bindings -+ -+maintainers: -+ - Maxime Ripard -+ -+properties: -+ "#clock-cells": -+ const: 1 -+ -+ compatible: -+ const: raspberrypi,firmware-clocks -+ -+required: -+ - "#clock-cells" -+ - compatible -+ -+additionalProperties: false -+ -+examples: -+ - | -+ firmware_clocks: firmware-clocks { -+ compatible = "raspberrypi,firmware-clocks"; -+ #clock-cells = <1>; -+ }; -+ -+... diff --git a/Documentation/devicetree/bindings/display/brcm,bcm2711-hdmi.yaml b/Documentation/devicetree/bindings/display/brcm,bcm2711-hdmi.yaml -index 7ce06f9f9f8e..6e8ac910bdd8 100644 +index 5b35adf34c7b..6d11f5955b51 100644 --- a/Documentation/devicetree/bindings/display/brcm,bcm2711-hdmi.yaml +++ b/Documentation/devicetree/bindings/display/brcm,bcm2711-hdmi.yaml -@@ -53,6 +53,24 @@ properties: - - const: audio - - const: cec +@@ -14,6 +14,8 @@ properties: + enum: + - brcm,bcm2711-hdmi0 + - brcm,bcm2711-hdmi1 ++ - brcm,bcm2712-hdmi0 ++ - brcm,bcm2712-hdmi1 -+ interrupts: -+ items: -+ - description: CEC TX interrupt -+ - description: CEC RX interrupt -+ - description: CEC stuck at low interrupt -+ - description: Wake-up interrupt -+ - description: Hotplug connected interrupt -+ - description: Hotplug removed interrupt -+ -+ interrupt-names: -+ items: -+ - const: cec-tx -+ - const: cec-rx -+ - const: cec-low -+ - const: wakeup -+ - const: hpd-connected -+ - const: hpd-removed -+ - ddc: - allOf: - - $ref: /schemas/types.yaml#/definitions/phandle -@@ -90,7 +108,7 @@ required: - - resets - - ddc - --additionalProperties: false -+unevaluatedProperties: false - - examples: - - | + reg: + items: diff --git a/Documentation/devicetree/bindings/display/brcm,bcm2835-dsi0.yaml b/Documentation/devicetree/bindings/display/brcm,bcm2835-dsi0.yaml -index eb44e072b6e5..90ee069ada8d 100644 +index c8b2459d64f6..af638b224619 100644 --- a/Documentation/devicetree/bindings/display/brcm,bcm2835-dsi0.yaml +++ b/Documentation/devicetree/bindings/display/brcm,bcm2835-dsi0.yaml -@@ -20,6 +20,7 @@ properties: - enum: +@@ -21,6 +21,7 @@ properties: + - brcm,bcm2711-dsi1 - brcm,bcm2835-dsi0 - brcm,bcm2835-dsi1 + - brcm,bcm2711-dsi1 reg: maxItems: 1 -diff --git a/Documentation/devicetree/bindings/display/brcm,bcm2835-hdmi.yaml b/Documentation/devicetree/bindings/display/brcm,bcm2835-hdmi.yaml -index f54b4e4808f0..899d8cfa1731 100644 ---- a/Documentation/devicetree/bindings/display/brcm,bcm2835-hdmi.yaml -+++ b/Documentation/devicetree/bindings/display/brcm,bcm2835-hdmi.yaml -@@ -11,24 +11,58 @@ maintainers: - - properties: +diff --git a/Documentation/devicetree/bindings/display/brcm,bcm2835-hvs.yaml b/Documentation/devicetree/bindings/display/brcm,bcm2835-hvs.yaml +index 2e8566f47e63..f91c9dce2a44 100644 +--- a/Documentation/devicetree/bindings/display/brcm,bcm2835-hvs.yaml ++++ b/Documentation/devicetree/bindings/display/brcm,bcm2835-hvs.yaml +@@ -13,6 +13,7 @@ properties: compatible: -- const: brcm,bcm2835-hdmi -+ enum: -+ - brcm,bcm2835-hdmi -+ - brcm,bcm2711-hdmi0 -+ - brcm,bcm2711-hdmi1 + enum: + - brcm,bcm2711-hvs ++ - brcm,bcm2712-hvs + - brcm,bcm2835-hvs reg: -+ oneOf: -+ - items: -+ - description: HDMI register range -+ - description: HD register range -+ -+ - items: -+ - description: HDMI controller register range -+ - description: DVP register range -+ - description: HDMI PHY register range -+ - description: Rate Manager register range -+ - description: Packet RAM register range -+ - description: Metadata RAM register range -+ - description: CSC register range -+ - description: CEC register range -+ - description: HD register range -+ -+ reg-names: - items: -- - description: HDMI register range -- - description: HD register range -+ - const: hdmi -+ - const: dvp -+ - const: phy -+ - const: rm -+ - const: packet -+ - const: metadata -+ - const: csc -+ - const: cec -+ - const: hd - - interrupts: - minItems: 2 - - clocks: -- items: -- - description: The pixel clock -- - description: The HDMI state machine clock -+ oneOf: -+ - items: -+ - description: The pixel clock -+ - description: The HDMI state machine clock -+ -+ - items: -+ - description: The HDMI state machine clock - - clock-names: -- items: -- - const: pixel -+ oneOf: -+ - items: -+ - const: pixel -+ - const: hdmi -+ - - const: hdmi - - ddc: -@@ -50,15 +84,54 @@ properties: - dma-names: - const: audio-rx - -+ resets: -+ maxItems: 1 -+ - required: - - compatible - - reg -- - interrupts - - clocks - - ddc - - additionalProperties: false - -+if: -+ properties: -+ compatible: -+ contains: +@@ -36,7 +37,9 @@ if: + properties: + compatible: + contains: +- const: brcm,bcm2711-hvs + enum: -+ - brcm,bcm2711-hdmi0 -+ - brcm,bcm2711-hdmi1 -+ -+then: -+ properties: -+ reg: -+ minItems: 9 -+ -+ clocks: -+ maxItems: 1 -+ -+ clock-names: -+ maxItems: 1 -+ -+ required: -+ - reg-names -+ - resets -+ -+else: -+ properties: -+ reg: -+ maxItems: 2 -+ -+ clocks: -+ minItems: 2 -+ -+ clock-names: -+ minItems: 2 -+ -+ required: -+ - interrupts -+ - examples: - - | - #include -@@ -76,4 +149,31 @@ examples: - clock-names = "pixel", "hdmi"; - }; ++ - brcm,bcm2711-hvs ++ - brcm,bcm2712-hvs -+ - | -+ hdmi0: hdmi@7ef00700 { -+ compatible = "brcm,bcm2711-hdmi0"; -+ reg = <0x7ef00700 0x300>, -+ <0x7ef00300 0x200>, -+ <0x7ef00f00 0x80>, -+ <0x7ef00f80 0x80>, -+ <0x7ef01b00 0x200>, -+ <0x7ef01f00 0x400>, -+ <0x7ef00200 0x80>, -+ <0x7ef04300 0x100>, -+ <0x7ef20000 0x100>; -+ reg-names = "hdmi", -+ "dvp", -+ "phy", -+ "rm", -+ "packet", -+ "metadata", -+ "csc", -+ "cec", -+ "hd"; -+ clocks = <&firmware_clocks 13>; -+ clock-names = "hdmi"; -+ resets = <&dvp 0>; -+ ddc = <&ddc0>; -+ }; -+ - ... -diff --git a/Documentation/devicetree/bindings/display/brcm,bcm2835-vc4.yaml b/Documentation/devicetree/bindings/display/brcm,bcm2835-vc4.yaml -index 49a5e041aa49..eac739a812f5 100644 ---- a/Documentation/devicetree/bindings/display/brcm,bcm2835-vc4.yaml -+++ b/Documentation/devicetree/bindings/display/brcm,bcm2835-vc4.yaml -@@ -21,6 +21,11 @@ properties: - - brcm,bcm2835-vc4 - - brcm,cygnus-vc4 - -+ raspberrypi,firmware: -+ $ref: /schemas/types.yaml#/definitions/phandle -+ description: > -+ Phandle to the mailbox node to communicate with the firmware. -+ - required: - - compatible - -diff --git a/Documentation/devicetree/bindings/display/brcm,bcm2835-vec.yaml b/Documentation/devicetree/bindings/display/brcm,bcm2835-vec.yaml -index d900cc57b4ec..4d8a6b615e5b 100644 ---- a/Documentation/devicetree/bindings/display/brcm,bcm2835-vec.yaml -+++ b/Documentation/devicetree/bindings/display/brcm,bcm2835-vec.yaml -@@ -11,7 +11,9 @@ maintainers: - - properties: - compatible: -- const: brcm,bcm2835-vec -+ enum: -+ - brcm,bcm2835-vec -+ - brcm,bcm2711-vec + then: + required: +diff --git a/Documentation/devicetree/bindings/display/brcm,bcm2835-pixelvalve0.yaml b/Documentation/devicetree/bindings/display/brcm,bcm2835-pixelvalve0.yaml +index 4e1ba03f6477..6b5b1d3fbc0b 100644 +--- a/Documentation/devicetree/bindings/display/brcm,bcm2835-pixelvalve0.yaml ++++ b/Documentation/devicetree/bindings/display/brcm,bcm2835-pixelvalve0.yaml +@@ -20,6 +20,9 @@ properties: + - brcm,bcm2711-pixelvalve2 + - brcm,bcm2711-pixelvalve3 + - brcm,bcm2711-pixelvalve4 ++ - brcm,bcm2712-pixelvalve0 ++ - brcm,bcm2712-pixelvalve1 ++ - brcm,bcm2712-pixelvalve2 reg: maxItems: 1 +diff --git a/Documentation/devicetree/bindings/display/brcm,bcm2835-txp.yaml b/Documentation/devicetree/bindings/display/brcm,bcm2835-txp.yaml +index bb186197e471..16f45afd2bad 100644 +--- a/Documentation/devicetree/bindings/display/brcm,bcm2835-txp.yaml ++++ b/Documentation/devicetree/bindings/display/brcm,bcm2835-txp.yaml +@@ -11,7 +11,10 @@ maintainers: + + properties: + compatible: +- const: brcm,bcm2835-txp ++ enum: ++ - brcm,bcm2712-mop ++ - brcm,bcm2712-moplet ++ - brcm,bcm2835-txp + + reg: + maxItems: 1 +diff --git a/Documentation/devicetree/bindings/display/brcm,bcm2835-vc4.yaml b/Documentation/devicetree/bindings/display/brcm,bcm2835-vc4.yaml +index 49a5e041aa49..2aa9d5d2afff 100644 +--- a/Documentation/devicetree/bindings/display/brcm,bcm2835-vc4.yaml ++++ b/Documentation/devicetree/bindings/display/brcm,bcm2835-vc4.yaml +@@ -18,6 +18,7 @@ properties: + compatible: + enum: + - brcm,bcm2711-vc5 ++ - brcm,bcm2712-vc6 + - brcm,bcm2835-vc4 + - brcm,cygnus-vc4 + +diff --git a/Documentation/devicetree/bindings/display/panel/ilitek,ili9881c.yaml b/Documentation/devicetree/bindings/display/panel/ilitek,ili9881c.yaml +index e7ab6224b52e..9bed316f6582 100644 +--- a/Documentation/devicetree/bindings/display/panel/ilitek,ili9881c.yaml ++++ b/Documentation/devicetree/bindings/display/panel/ilitek,ili9881c.yaml +@@ -20,6 +20,8 @@ properties: + - feixin,k101-im2byl02 + - tdo,tl050hdv35 + - wanchanglong,w552946aba ++ - raspberrypi,dsi-5inch ++ - raspberrypi,dsi-7inch + - const: ilitek,ili9881c + + backlight: true +diff --git a/Documentation/devicetree/bindings/display/panel/panel-dsi.yaml b/Documentation/devicetree/bindings/display/panel/panel-dsi.yaml +new file mode 100644 +index 000000000000..0576541d9567 +--- /dev/null ++++ b/Documentation/devicetree/bindings/display/panel/panel-dsi.yaml +@@ -0,0 +1,118 @@ ++# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/display/panel/panel-dsi.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: Generic MIPI DSI Panel ++ ++maintainers: ++ - Timon Skerutsch ++ ++allOf: ++ - $ref: panel-common.yaml# ++ ++properties: ++ compatible: ++ description: ++ Shall contain a panel specific compatible and "panel-dsi" ++ in that order. ++ items: ++ - {} ++ - const: panel-dsi ++ ++ dsi-color-format: ++ description: | ++ The color format used by the panel. Only DSI supported formats are allowed. ++ enum: ++ - RGB888 ++ - RGB666 ++ - RGB666_PACKED ++ - RGB565 ++ ++ port: ++ $ref: /schemas/graph.yaml#/$defs/port-base ++ unevaluatedProperties: false ++ description: ++ Panel MIPI DSI input ++ ++ properties: ++ endpoint: ++ $ref: /schemas/media/video-interfaces.yaml# ++ unevaluatedProperties: false ++ ++ properties: ++ data-lanes: true ++ ++ required: ++ - data-lanes ++ ++ mode: ++ description: | ++ DSI mode flags. See DSI Specs for details. ++ These are driver independent features of the DSI bus. ++ items: ++ - const: MODE_VIDEO ++ - const: MODE_VIDEO_BURST ++ - const: MODE_VIDEO_SYNC_PULSE ++ - const: MODE_VIDEO_AUTO_VERT ++ - const: MODE_VIDEO_HSE ++ - const: MODE_VIDEO_NO_HFP ++ - const: MODE_VIDEO_NO_HBP ++ - const: MODE_VIDEO_NO_HSA ++ - const: MODE_VSYNC_FLUSH ++ - const: MODE_NO_EOT_PACKET ++ - const: CLOCK_NON_CONTINUOUS ++ - const: MODE_LPM ++ - const: HS_PKT_END_ALIGNED ++ ++ reg: true ++ backlight: true ++ enable-gpios: true ++ width-mm: true ++ height-mm: true ++ panel-timing: true ++ power-supply: true ++ reset-gpios: true ++ ddc-i2c-bus: true ++ ++required: ++ - panel-timing ++ - reg ++ - power-supply ++ - dsi-color-format ++ - port ++ ++additionalProperties: false ++ ++examples: ++ - | ++ panel { ++ compatible = "panel-mfgr,generic-dsi-panel","panel-dsi"; ++ power-supply = <&vcc_supply>; ++ backlight = <&backlight>; ++ dsi-color-format = "RGB888"; ++ reg = <0>; ++ mode = "MODE_VIDEO", "MODE_VIDEO_BURST", "MODE_NO_EOT_PACKET"; ++ ++ port { ++ panel_dsi_port: endpoint { ++ data-lanes = <1 2>; ++ remote-endpoint = <&dsi_out>; ++ }; ++ }; ++ ++ panel-timing { ++ clock-frequency = <9200000>; ++ hactive = <800>; ++ vactive = <480>; ++ hfront-porch = <8>; ++ hback-porch = <4>; ++ hsync-len = <41>; ++ vback-porch = <2>; ++ vfront-porch = <4>; ++ vsync-len = <10>; ++ }; ++ }; ++ ++... diff --git a/Documentation/devicetree/bindings/display/panel/panel-simple.yaml b/Documentation/devicetree/bindings/display/panel/panel-simple.yaml -index edb53ab0d9eb..f474cc0feed6 100644 +index 25b4589d4a58..209e8475b0a5 100644 --- a/Documentation/devicetree/bindings/display/panel/panel-simple.yaml +++ b/Documentation/devicetree/bindings/display/panel/panel-simple.yaml -@@ -133,6 +133,8 @@ properties: +@@ -158,6 +158,8 @@ properties: - frida,frd350h54004 # FriendlyELEC HD702E 800x1280 LCD panel - friendlyarm,hd702e @@ -1842,7 +2202,7 @@ index edb53ab0d9eb..f474cc0feed6 100644 # GiantPlus GPG48273QS5 4.3" (480x272) WQVGA TFT LCD panel - giantplus,gpg48273qs5 # GiantPlus GPM940B0 3.0" QVGA TFT LCD panel -@@ -147,6 +149,8 @@ properties: +@@ -172,6 +174,8 @@ properties: - ivo,m133nwf4-r0 # Innolux AT043TN24 4.3" WQVGA TFT LCD panel - innolux,at043tn24 @@ -1850,68 +2210,79 @@ index edb53ab0d9eb..f474cc0feed6 100644 + - innolux,at056tn53v1 # Innolux AT070TN92 7.0" WQVGA TFT LCD panel - innolux,at070tn92 - # Innolux G070Y2-L01 7" WVGA (800x480) TFT LCD panel -diff --git a/Documentation/devicetree/bindings/hwmon/rpi-poe-fan.txt b/Documentation/devicetree/bindings/hwmon/rpi-poe-fan.txt + # Innolux G070ACE-L01 7" WVGA (800x480) TFT LCD panel +diff --git a/Documentation/devicetree/bindings/gpu/brcm,bcm-v3d.yaml b/Documentation/devicetree/bindings/gpu/brcm,bcm-v3d.yaml +index dae55b8a267b..97c9afe7b4f8 100644 +--- a/Documentation/devicetree/bindings/gpu/brcm,bcm-v3d.yaml ++++ b/Documentation/devicetree/bindings/gpu/brcm,bcm-v3d.yaml +@@ -16,6 +16,7 @@ properties: + + compatible: + enum: ++ - brcm,2712-v3d + - brcm,2711-v3d + - brcm,7268-v3d + - brcm,7278-v3d +diff --git a/Documentation/devicetree/bindings/hwmon/microchip,emc2305.yaml b/Documentation/devicetree/bindings/hwmon/microchip,emc2305.yaml new file mode 100644 -index 000000000000..c71f8569a4dc +index 000000000000..efdc3cecb03d --- /dev/null -+++ b/Documentation/devicetree/bindings/hwmon/rpi-poe-fan.txt -@@ -0,0 +1,55 @@ -+Bindings for the Raspberry Pi PoE HAT fan ++++ b/Documentation/devicetree/bindings/hwmon/microchip,emc2305.yaml +@@ -0,0 +1,54 @@ ++# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) ++%YAML 1.2 ++--- + -+Required properties: -+- compatible : "raspberrypi,rpi-poe-fan" -+- firmware : Reference to the RPi firmware device node -+- pwms : the PWM that is used to control the PWM fan -+- cooling-levels : PWM duty cycle values in a range from 0 to 255 -+ which correspond to thermal cooling states ++$id: http://devicetree.org/schemas/hwmon/emc2305.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# + -+Example: -+ fan0: rpi-poe-fan@0 { -+ compatible = "raspberrypi,rpi-poe-fan"; -+ firmware = <&firmware>; -+ cooling-min-state = <0>; -+ cooling-max-state = <3>; -+ #cooling-cells = <2>; -+ cooling-levels = <0 50 150 255>; -+ status = "okay"; -+ }; ++title: Microchip EMC230[1|2|3|5] RPM-based PWM Fan Speed Controller + -+ thermal-zones { -+ cpu_thermal: cpu-thermal { -+ trips { -+ threshold: trip-point@0 { -+ temperature = <45000>; -+ hysteresis = <5000>; -+ type = "active"; -+ }; -+ target: trip-point@1 { -+ temperature = <50000>; -+ hysteresis = <2000>; -+ type = "active"; -+ }; -+ cpu_hot: cpu_hot@0 { -+ temperature = <55000>; -+ hysteresis = <2000>; -+ type = "active"; -+ }; -+ }; -+ cooling-maps { -+ map0 { -+ trip = <&threshold>; -+ cooling-device = <&fan0 0 1>; -+ }; -+ map1 { -+ trip = <&target>; -+ cooling-device = <&fan0 1 2>; -+ }; -+ map2 { -+ trip = <&cpu_hot>; -+ cooling-device = <&fan0 2 3>; -+ }; -+ }; -+ }; -+ }; ++properties: ++ compatible: ++ enum: ++ - microchip,emc2305 ++ - microchip,emc2301 ++ emc2305,pwm-min: ++ description: ++ Min pwm of emc2305 ++ maxItems: 1 ++ emc2305,pwm-max: ++ description: ++ Max pwm of emc2305 ++ maxItems: 1 ++ emc2305,pwm-channel: ++ description: ++ Max number of pwm channels ++ maxItems: 1 ++ emcs205,max-state: ++ description: ++ maxItems: 1 ++ emc2305,cooling-levels: ++ description: ++ Quantity of cooling level state. ++ maxItems: 1 ++ ++required: ++ - compatible ++ ++optional: ++ - emc2305,min-pwm ++ - emc2305,max-pwm ++ - emc2305,pwm-channels ++ - emc2305,cooling-levels ++ ++additionalProperties: false ++ ++examples: ++ - | ++ fan { ++ compatible = "microchip,emc2305"; ++ emc2305,pwm-min = <0>; ++ emc2305,pwm-max = <255>; ++ emc2305,pwm-channel = <5> ++ emc2305,cooling-levels = <10>; ++ }; diff --git a/Documentation/devicetree/bindings/media/bcm2835-unicam.txt b/Documentation/devicetree/bindings/media/bcm2835-unicam.txt new file mode 100644 index 000000000000..164d0377dcd2 @@ -2003,93 +2374,311 @@ index 000000000000..164d0377dcd2 + }; + }; + }; -diff --git a/Documentation/devicetree/bindings/media/i2c/imx219.txt b/Documentation/devicetree/bindings/media/i2c/imx219.txt +diff --git a/Documentation/devicetree/bindings/media/i2c/ad5398.txt b/Documentation/devicetree/bindings/media/i2c/ad5398.txt new file mode 100644 -index 000000000000..a02f1ce1e120 +index 000000000000..446ac9717598 --- /dev/null -+++ b/Documentation/devicetree/bindings/media/i2c/imx219.txt -@@ -0,0 +1,59 @@ -+* Sony 1/4.0-Inch 8Mpixel CMOS Digital Image Sensor -+ -+The Sony imx219 is a 1/4.0-inch CMOS active pixel digital image sensor with -+an active array size of 3280H x 2464V. It is programmable through I2C -+interface. The I2C address is fixed to 0x10 as per sensor data sheet. -+Image data is sent through MIPI CSI-2, which is configured as either 2 or 4 -+data lanes. ++++ b/Documentation/devicetree/bindings/media/i2c/ad5398.txt +@@ -0,0 +1,20 @@ ++* Analog Devices AD5398 autofocus coil + +Required Properties: -+- compatible: value should be "sony,imx219" for imx219 sensor -+- reg: I2C bus address of the device -+- clocks: reference to the xclk input clock. -+- clock-names: should be "xclk". -+- DOVDD-supply: Digital I/O voltage supply, 1.8 volts -+- AVDD-supply: Analog voltage supply, 2.8 volts -+- DVDD-supply: Digital core voltage supply, 1.2 volts + -+Optional Properties: -+- xclr-gpios: reference to the GPIO connected to the xclr pin, if any. Must be -+ released after all supplies are applied. -+ This is an active high signal to the imx219. ++ - compatible: Must contain one of: ++ - "adi,ad5398" + -+The imx219 device node should contain one 'port' child node with -+an 'endpoint' subnode. For further reading on port node refer to -+Documentation/devicetree/bindings/media/video-interfaces.txt. ++ - reg: I2C slave address + -+Endpoint node required properties for CSI-2 connection are: -+- remote-endpoint: a phandle to the bus receiver's endpoint node. -+- clock-lanes: should be set to <0> (clock lane on hardware lane 0) -+- data-lanes: should be set to <1 2>, or <1 2 3 4> (two or four lane CSI-2 -+ supported) ++ - VANA-supply: supply of voltage for VANA pin + +Example: -+ sensor@10 { -+ compatible = "sony,imx219"; -+ reg = <0x10>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ clocks = <&imx219_clk>; -+ clock-names = "xclk"; -+ xclr-gpios = <&gpio_sensor 0 0>; -+ DOVDD-supply = <&vgen4_reg>; /* 1.8v */ -+ AVDD-supply = <&vgen3_reg>; /* 2.8v */ -+ DVDD-supply = <&vgen2_reg>; /* 1.2v */ + -+ imx219_clk: camera-clk { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <24000000>; -+ }; ++ ad5398: coil@c { ++ compatible = "adi,ad5398"; ++ reg = <0x0c>; + -+ port { -+ sensor_out: endpoint { -+ remote-endpoint = <&csiss_in>; -+ clock-lanes = <0>; -+ data-lanes = <1 2>; -+ }; -+ }; -+ }; -diff --git a/Documentation/devicetree/bindings/media/i2c/imx290.txt b/Documentation/devicetree/bindings/media/i2c/imx290.txt -index a3cc21410f7c..294e63650d9e 100644 ---- a/Documentation/devicetree/bindings/media/i2c/imx290.txt -+++ b/Documentation/devicetree/bindings/media/i2c/imx290.txt -@@ -1,13 +1,14 @@ - * Sony IMX290 1/2.8-Inch CMOS Image Sensor ++ VANA-supply = <&vaux4>; ++ }; ++ +diff --git a/Documentation/devicetree/bindings/media/i2c/arducam,64mp.yaml b/Documentation/devicetree/bindings/media/i2c/arducam,64mp.yaml +new file mode 100644 +index 000000000000..b71a19782f97 +--- /dev/null ++++ b/Documentation/devicetree/bindings/media/i2c/arducam,64mp.yaml +@@ -0,0 +1,115 @@ ++# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/media/i2c/arducam,64mp.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: Arducam 1/1.7-Inch 64Mpixel CMOS Digital Image Sensor ++ ++maintainers: ++ - Lee Jackson ++ ++description: |- ++ The Arducam 1/1.7-Inch 64Mpixel CMOS active pixel digital image sensor ++ with an active array size of 9248 x 6944. It is programmable through ++ I2C interface. The I2C address is fixed to 0x1A as per sensor data sheet. ++ Image data is sent through MIPI CSI-2, which can be configured for operation ++ with either 2 or 4 data lanes. ++ ++properties: ++ compatible: ++ const: arducam,64mp ++ ++ reg: ++ description: I2C device address ++ maxItems: 1 ++ ++ clocks: ++ maxItems: 1 ++ ++ VDIG-supply: ++ description: ++ Digital I/O voltage supply, 1.05 volts ++ ++ VANA-supply: ++ description: ++ Analog voltage supply, 2.8 volts ++ ++ VDDL-supply: ++ description: ++ Digital core voltage supply, 1.8 volts ++ ++ reset-gpios: ++ description: |- ++ Reference to the GPIO connected to the xclr pin, if any. ++ Must be released (set high) after all supplies and INCK are applied. ++ ++ # See ../video-interfaces.txt for more details ++ port: ++ type: object ++ properties: ++ endpoint: ++ type: object ++ properties: ++ data-lanes: ++ description: |- ++ The sensor supports either two-lane, or four-lane operation. ++ For two-lane operation the property must be set to <1 2>. ++ anyOf: ++ - items: ++ - const: 1 ++ - const: 2 ++ - items: ++ - const: 1 ++ - const: 2 ++ - const: 3 ++ - const: 4 ++ ++ clock-noncontinuous: true ++ ++ link-frequencies: ++ allOf: ++ - $ref: /schemas/types.yaml#/definitions/uint64-array ++ description: ++ Allowed data bus frequencies. ++ ++ required: ++ - link-frequencies ++ ++required: ++ - compatible ++ - reg ++ - clocks ++ - VANA-supply ++ - VDIG-supply ++ - VDDL-supply ++ - port ++ ++additionalProperties: false ++ ++examples: ++ - | ++ i2c0 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ arducam_64mp: sensor@1a { ++ compatible = "arducam,64mp"; ++ reg = <0x1a>; ++ clocks = <&arducam_64mp_clk>; ++ VANA-supply = <&arducam_64mp_vana>; /* 2.8v */ ++ VDIG-supply = <&arducam_64mp_vdig>; /* 1.05v */ ++ VDDL-supply = <&arducam_64mp_vddl>; /* 1.8v */ ++ ++ port { ++ arducam_64mp_0: endpoint { ++ remote-endpoint = <&csi1_ep>; ++ data-lanes = <1 2>; ++ clock-noncontinuous; ++ link-frequencies = /bits/ 64 <456000000>; ++ }; ++ }; ++ }; ++ }; ++ ++... +diff --git a/Documentation/devicetree/bindings/media/i2c/arducam-pivariety.yaml b/Documentation/devicetree/bindings/media/i2c/arducam-pivariety.yaml +new file mode 100644 +index 000000000000..92bf4ff32eb4 +--- /dev/null ++++ b/Documentation/devicetree/bindings/media/i2c/arducam-pivariety.yaml +@@ -0,0 +1,112 @@ ++# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/media/i2c/arducam-pivariety.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: Arducam Pivariety Series CMOS Digital Image Sensor ++ ++maintainers: ++ - Lee Jackson ++ ++description: |- ++ Arducam Pivariety series cameras make compatibility layers for various CMOS ++ sensors and provide a unified command interface. It is programmable through ++ I2C interface. The I2C address is fixed to 0x0C. Image data is sent through ++ MIPI CSI-2, which is configured as either 1, 2 or 4 data lanes. ++ ++properties: ++ compatible: ++ const: arducam,arducam-pivariety ++ ++ reg: ++ description: I2C device address ++ maxItems: 1 ++ ++ clocks: ++ maxItems: 1 ++ ++ VDIG-supply: ++ description: ++ Digital I/O voltage supply, 1.05 volts ++ ++ VANA-supply: ++ description: ++ Analog voltage supply, 2.8 volts ++ ++ VDDL-supply: ++ description: ++ Digital core voltage supply, 1.8 volts ++ ++ reset-gpios: ++ description: |- ++ Reference to the GPIO connected to the xclr pin, if any. ++ Must be released (set high) after all supplies and INCK are applied. ++ ++ # See ../video-interfaces.txt for more details ++ port: ++ type: object ++ properties: ++ endpoint: ++ type: object ++ properties: ++ data-lanes: ++ description: |- ++ The sensor supports either two-lane, or four-lane operation. ++ For two-lane operation the property must be set to <1 2>. ++ items: ++ - const: 1 ++ - const: 2 ++ ++ clock-noncontinuous: ++ type: boolean ++ description: |- ++ MIPI CSI-2 clock is non-continuous if this property is present, ++ otherwise it's continuous. ++ ++ link-frequencies: ++ allOf: ++ - $ref: /schemas/types.yaml#/definitions/uint64-array ++ description: ++ Allowed data bus frequencies. ++ ++ required: ++ - link-frequencies ++ ++required: ++ - compatible ++ - reg ++ - clocks ++ - VANA-supply ++ - VDIG-supply ++ - VDDL-supply ++ - port ++ ++additionalProperties: false ++ ++examples: ++ - | ++ i2c0 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ arducam_pivariety: sensor@0c { ++ compatible = "arducam,arducam-pivariety"; ++ reg = <0x0c>; ++ clocks = <&arducam_pivariety_clk>; ++ VANA-supply = <&arducam_pivariety_vana>; /* 2.8v */ ++ VDIG-supply = <&arducam_pivariety_vdig>; /* 1.05v */ ++ VDDL-supply = <&arducam_pivariety_vddl>; /* 1.8v */ ++ ++ port { ++ arducam_pivariety_0: endpoint { ++ remote-endpoint = <&csi1_ep>; ++ data-lanes = <1 2>; ++ clock-noncontinuous; ++ link-frequencies = /bits/ 64 <493500000>; ++ }; ++ }; ++ }; ++ }; ++ ++... +diff --git a/Documentation/devicetree/bindings/media/i2c/dongwoon,dw9807-vcm.yaml b/Documentation/devicetree/bindings/media/i2c/dongwoon,dw9807-vcm.yaml +index aae246ca3fcf..6de07543e973 100644 +--- a/Documentation/devicetree/bindings/media/i2c/dongwoon,dw9807-vcm.yaml ++++ b/Documentation/devicetree/bindings/media/i2c/dongwoon,dw9807-vcm.yaml +@@ -5,22 +5,32 @@ + $id: http://devicetree.org/schemas/media/i2c/dongwoon,dw9807-vcm.yaml# + $schema: http://devicetree.org/meta-schemas/core.yaml# - The Sony IMX290 is a 1/2.8-Inch CMOS Solid-state image sensor with --Square Pixel for Color Cameras. It is programmable through I2C and 4-wire --interfaces. The sensor output is available via CMOS logic parallel SDR output, -+Square Pixel for Color or Monochrome Cameras. It is programmable through I2C -+and 4-wire interfaces. -+The sensor output is available via CMOS logic parallel SDR output, - Low voltage LVDS DDR output and CSI-2 serial data output. The CSI-2 bus is the - default. No bindings have been defined for the other busses. +-title: Dongwoon Anatech DW9807 voice coil lens driver ++title: Dongwoon Anatech DW9807 and DW9817 voice coil lens driver - Required Properties: --- compatible: Should be "sony,imx290" -+- compatible: Should be "sony,imx290", or "sony,imx290-mono" - - reg: I2C bus address of the device - - clocks: Reference to the xclk clock. - - clock-names: Should be "xclk". + maintainers: + - Sakari Ailus + + description: | + DW9807 is a 10-bit DAC with current sink capability. It is intended for +- controlling voice coil lenses. ++ controlling voice coil lenses. The output drive is 0-100mA. ++ DW9817 is very similar as a 10-bit DAC with current sink capability, ++ however the output drive is a bidirection -100 to +100mA. ++ + + properties: + compatible: +- const: dongwoon,dw9807-vcm ++ items: ++ - enum: ++ - dongwoon,dw9807-vcm ++ - dongwoon,dw9817-vcm + + reg: + maxItems: 1 + ++ VDD-supply: ++ description: ++ Definition of the regulator used as VDD power supply to the driver. ++ + required: + - compatible + - reg diff --git a/Documentation/devicetree/bindings/media/i2c/imx378.yaml b/Documentation/devicetree/bindings/media/i2c/imx378.yaml new file mode 100644 index 000000000000..f832b4bfab93 @@ -2501,6 +3090,331 @@ index 000000000000..25a48028c957 + }; + }; + }; +diff --git a/Documentation/devicetree/bindings/media/i2c/ovti,ov64a40.yaml b/Documentation/devicetree/bindings/media/i2c/ovti,ov64a40.yaml +new file mode 100644 +index 000000000000..15fbe86bba10 +--- /dev/null ++++ b/Documentation/devicetree/bindings/media/i2c/ovti,ov64a40.yaml +@@ -0,0 +1,98 @@ ++# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/media/i2c/ovti,ov64a40.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: OmniVision OV64A40 Image Sensor ++ ++maintainers: ++ - Jacopo Mondi ++ ++allOf: ++ - $ref: /schemas/media/video-interface-devices.yaml# ++ ++properties: ++ compatible: ++ const: ovti,ov64a40 ++ ++ reg: ++ maxItems: 1 ++ ++ clocks: ++ maxItems: 1 ++ ++ avdd-supply: ++ description: Analog voltage supply, 2.8 volts ++ ++ dvdd-supply: ++ description: Digital core voltage supply, 1.1 volts ++ ++ dovdd-supply: ++ description: Digital I/O voltage supply, 1.8 volts ++ ++ powerdown-gpios: ++ maxItems: 1 ++ ++ reset-gpios: ++ maxItems: 1 ++ ++ port: ++ $ref: /schemas/graph.yaml#/$defs/port-base ++ additionalProperties: false ++ ++ properties: ++ endpoint: ++ $ref: /schemas/media/video-interfaces.yaml# ++ additionalProperties: false ++ ++ properties: ++ bus-type: ++ enum: ++ - 1 # MIPI CSI-2 C-PHY ++ - 4 # MIPI CSI-2 D-PHY ++ data-lanes: true ++ link-frequencies: true ++ clock-noncontinuous: true ++ remote-endpoint: true ++ ++required: ++ - compatible ++ - reg ++ - clocks ++ - port ++ ++unevaluatedProperties: false ++ ++examples: ++ - | ++ #include ++ ++ i2c { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ camera@36 { ++ compatible = "ovti,ov64a40"; ++ reg = <0x36>; ++ clocks = <&camera_clk>; ++ dovdd-supply = <&vgen4_reg>; ++ avdd-supply = <&vgen3_reg>; ++ dvdd-supply = <&vgen2_reg>; ++ powerdown-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; ++ reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; ++ rotation = <180>; ++ orientation = <2>; ++ ++ port { ++ endpoint { ++ remote-endpoint = <&mipi_csi2_in>; ++ bus-type = <4>; ++ data-lanes = <1 2 3 4>; ++ link-frequencies = /bits/ 64 <456000000>; ++ }; ++ }; ++ }; ++ }; ++ ++... +diff --git a/Documentation/devicetree/bindings/media/i2c/rohm,bu64754.yaml b/Documentation/devicetree/bindings/media/i2c/rohm,bu64754.yaml +new file mode 100644 +index 000000000000..22da4a46bb0c +--- /dev/null ++++ b/Documentation/devicetree/bindings/media/i2c/rohm,bu64754.yaml +@@ -0,0 +1,48 @@ ++# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) ++# Copyright (C) 2023 Ideas on Board Oy. ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/media/i2c/rohm,bu64754.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: ROHM BU64754 Actuator Driver for Camera Autofocus ++ ++maintainers: ++ - Kieran Bingham ++ ++description: | ++ The BU64754GWZ is an actuator driver IC which can control the actuator ++ position precisely using an internal Hall Sensor. ++ ++properties: ++ compatible: ++ items: ++ - enum: ++ - rohm,bu64754 ++ ++ reg: ++ maxItems: 1 ++ ++ vdd-supply: ++ description: ++ Definition of the regulator used as VDD power supply to the driver. ++ ++required: ++ - compatible ++ - reg ++ ++additionalProperties: false ++ ++examples: ++ - | ++ i2c { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ lens@76 { ++ compatible = "rohm,bu64754"; ++ reg = <0x76>; ++ vdd-supply = <&cam1_reg>; ++ }; ++ }; ++... +diff --git a/Documentation/devicetree/bindings/media/i2c/imx258.yaml b/Documentation/devicetree/bindings/media/i2c/sony,imx258.yaml +similarity index 90% +rename from Documentation/devicetree/bindings/media/i2c/imx258.yaml +rename to Documentation/devicetree/bindings/media/i2c/sony,imx258.yaml +index 80d24220baa0..3415b26b5991 100644 +--- a/Documentation/devicetree/bindings/media/i2c/imx258.yaml ++++ b/Documentation/devicetree/bindings/media/i2c/sony,imx258.yaml +@@ -1,7 +1,7 @@ + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) + %YAML 1.2 + --- +-$id: http://devicetree.org/schemas/media/i2c/imx258.yaml# ++$id: http://devicetree.org/schemas/media/i2c/sony,imx258.yaml# + $schema: http://devicetree.org/meta-schemas/core.yaml# + + title: Sony IMX258 13 Mpixel CMOS Digital Image Sensor +@@ -14,10 +14,15 @@ description: |- + type stacked image sensor with a square pixel array of size 4208 x 3120. It + is programmable through I2C interface. Image data is sent through MIPI + CSI-2. ++ There are a number of variants of the sensor which cannot be detected at ++ runtime, so multiple compatible strings are required to differentiate these. + + properties: + compatible: +- const: sony,imx258 ++ oneOf: ++ - enum: ++ - sony,imx258 ++ - sony,imx258-pdaf + + assigned-clocks: true + assigned-clock-parents: true +diff --git a/Documentation/devicetree/bindings/media/i2c/sony,imx708.yaml b/Documentation/devicetree/bindings/media/i2c/sony,imx708.yaml +new file mode 100644 +index 000000000000..286aad2e8c69 +--- /dev/null ++++ b/Documentation/devicetree/bindings/media/i2c/sony,imx708.yaml +@@ -0,0 +1,128 @@ ++# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/media/i2c/sony,imx708.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: Sony 1/2.3-Inch 12Mpixel CMOS Digital Image Sensor ++ ++maintainers: ++ - Raspberry Pi Kernel Maintenance ++ ++description: |- ++ The Sony IMX708 is a 1/2.3-inch CMOS active pixel digital image sensor ++ with an active array size of 4608H x 2592V. It is programmable through ++ I2C interface. The I2C address is fixed to 0x1A as per sensor data sheet. ++ Image data is sent through MIPI CSI-2, which is configured as either 2 or ++ 4 data lanes. ++ ++properties: ++ compatible: ++ const: sony,imx708 ++ ++ reg: ++ maxItems: 1 ++ ++ clocks: ++ maxItems: 1 ++ ++ clock-names: ++ description: Input clock (6 to 27 MHz) ++ items: ++ - const: inck ++ ++ vdig-supply: ++ description: ++ Digital I/O voltage supply, 1.1 volts ++ ++ vana1-supply: ++ description: ++ Analog1 voltage supply, 2.8 volts ++ ++ vana2-supply: ++ description: ++ Analog2 voltage supply, 1.8 volts ++ ++ vddl-supply: ++ description: ++ Digital core voltage supply, 1.8 volts ++ ++ reset-gpios: ++ description: Sensor reset (XCLR) GPIO ++ maxItems: 1 ++ ++ port: ++ $ref: /schemas/graph.yaml#/$defs/port-base ++ description: | ++ Video output port ++ ++ properties: ++ endpoint: ++ $ref: /schemas/media/video-interfaces.yaml# ++ unevaluatedProperties: false ++ ++ properties: ++ data-lanes: ++ anyOf: ++ - items: ++ - const: 1 ++ - const: 2 ++ - items: ++ - const: 1 ++ - const: 2 ++ - const: 3 ++ - const: 4 ++ ++ link-frequencies: true ++ ++ required: ++ - data-lanes ++ - link-frequencies ++ ++ additionalProperties: false ++ ++required: ++ - compatible ++ - reg ++ - clocks ++ - clock-names ++ - vdig-supply ++ - vana1-supply ++ - vana2-supply ++ - vddl-supply ++ - port ++ ++additionalProperties: false ++ ++examples: ++ - | ++ #include ++ ++ i2c { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ imx708: camera-sensor@1a { ++ compatible = "sony,imx708"; ++ reg = <0x1a>; ++ ++ clocks = <&clk 90>; ++ clock-names = "inck"; ++ ++ vdig-supply = <&camera_vdig>; ++ vana1-supply = <&camera_vana1>; ++ vana2-supply = <&camera_vana2>; ++ vddl-supply = <&camera_vddl>; ++ ++ reset-gpios = <&gpio 35 GPIO_ACTIVE_LOW>; ++ ++ port { ++ imx708_ep: endpoint { ++ data-lanes = <1 2>; ++ link-frequencies = /bits/ 64 <450000000>; ++ remote-endpoint = <&csi_ep>; ++ }; ++ }; ++ }; ++ }; ++... diff --git a/Documentation/devicetree/bindings/media/rpivid_hevc.yaml b/Documentation/devicetree/bindings/media/rpivid_hevc.yaml new file mode 100644 index 000000000000..ce6b81a10303 @@ -2656,6 +3570,63 @@ index 000000000000..b76dc694f1ac + brcm,pull = <2 2 2 2 2 2 0 0 0 0 0 0 0 0>; +}; + +diff --git a/Documentation/devicetree/bindings/mmc/snps,dwcmshc-sdhci.yaml b/Documentation/devicetree/bindings/mmc/snps,dwcmshc-sdhci.yaml +index a43eb837f8da..fb0eb5bb53a5 100644 +--- a/Documentation/devicetree/bindings/mmc/snps,dwcmshc-sdhci.yaml ++++ b/Documentation/devicetree/bindings/mmc/snps,dwcmshc-sdhci.yaml +@@ -16,6 +16,7 @@ allOf: + properties: + compatible: + enum: ++ - raspberrypi,rp1-dwcmshc + - rockchip,rk3568-dwcmshc + - rockchip,rk3588-dwcmshc + - snps,dwcmshc-sdhci +@@ -34,6 +35,8 @@ properties: + - description: axi clock for rockchip specified + - description: block clock for rockchip specified + - description: timer clock for rockchip specified ++ - description: timeout clock for rp1 specified ++ - description: sdio clock generator for rp1 specified + + + clock-names: +@@ -44,6 +47,8 @@ properties: + - const: axi + - const: block + - const: timer ++ - const: timeout ++ - const: sdio + + resets: + maxItems: 5 +diff --git a/Documentation/devicetree/bindings/net/cdns,macb.yaml b/Documentation/devicetree/bindings/net/cdns,macb.yaml +index bf8894a0257e..a9edfe6c1254 100644 +--- a/Documentation/devicetree/bindings/net/cdns,macb.yaml ++++ b/Documentation/devicetree/bindings/net/cdns,macb.yaml +@@ -131,6 +131,22 @@ properties: + Node containing PHY children. If this node is not present, then PHYs will + be direct children. + ++ cdns,aw2w-max-pipe: ++ $ref: /schemas/types.yaml#/definitions/uint32 ++ description: ++ Maximum number of outstanding AXI write requests ++ ++ cdns,ar2r-max-pipe: ++ $ref: /schemas/types.yaml#/definitions/uint32 ++ description: ++ Maximum number of outstanding AXI read requests ++ ++ cdns,use-aw2b-fill: ++ type: boolean ++ description: ++ If set, the maximum number of outstanding write transactions operates ++ between the AW to B AXI channel, instead of the AW to W AXI channel. ++ + patternProperties: + "^ethernet-phy@[0-9a-f]$": + type: object diff --git a/Documentation/devicetree/bindings/net/microchip,lan78xx.txt b/Documentation/devicetree/bindings/net/microchip,lan78xx.txt index 11a679530ae6..104768b85bbc 100644 --- a/Documentation/devicetree/bindings/net/microchip,lan78xx.txt @@ -2670,61 +3641,25 @@ index 11a679530ae6..104768b85bbc 100644 Example: -diff --git a/Documentation/devicetree/bindings/nvmem/rmem.yaml b/Documentation/devicetree/bindings/nvmem/rmem.yaml -new file mode 100644 -index 000000000000..29b53871aa02 ---- /dev/null -+++ b/Documentation/devicetree/bindings/nvmem/rmem.yaml -@@ -0,0 +1,49 @@ -+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -+%YAML 1.2 -+--- -+$id: http://devicetree.org/schemas/nvmem/rmem.yaml# -+$schema: http://devicetree.org/meta-schemas/core.yaml# +diff --git a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml +index 7e15aae7d69e..ad313d76eb7c 100644 +--- a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml ++++ b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml +@@ -77,6 +77,14 @@ properties: + minItems: 1 + maxItems: 3 + ++ brcm,tperst-clk-ms: ++ category: optional ++ type: int ++ description: u32 giving the number of milliseconds to extend ++ the time between internal release of fundamental reset and ++ the deassertion of the external PERST# pin. This has the ++ effect of increasing the Tperst_clk phase of link init. + -+title: Reserved Memory Based nvmem Device -+ -+maintainers: -+ - Nicolas Saenz Julienne -+ -+allOf: -+ - $ref: "nvmem.yaml#" -+ -+properties: -+ compatible: -+ items: -+ - enum: -+ - raspberrypi,bootloader-config -+ - const: nvmem-rmem -+ -+ no-map: -+ $ref: /schemas/types.yaml#/definitions/flag -+ description: -+ Avoid creating a virtual mapping of the region as part of the OS' -+ standard mapping of system memory. -+ -+required: -+ - compatible -+ - no-map -+ -+unevaluatedProperties: false -+ -+examples: -+ - | -+ reserved-memory { -+ #address-cells = <1>; -+ #size-cells = <1>; -+ -+ blconfig: nvram@10000000 { -+ compatible = "raspberrypi,bootloader-config", "nvmem-rmem"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ reg = <0x10000000 0x1000>; -+ no-map; -+ }; -+ }; -+ -+... + required: + - compatible + - reg diff --git a/Documentation/devicetree/bindings/pci/brcmstb-pcie.txt b/Documentation/devicetree/bindings/pci/brcmstb-pcie.txt new file mode 100644 index 000000000000..a1a9ad5e70ca @@ -2791,24 +3726,132 @@ index 000000000000..a1a9ad5e70ca + linux,pci-domain = <0>; + }; diff --git a/Documentation/devicetree/bindings/power/reset/gpio-poweroff.txt b/Documentation/devicetree/bindings/power/reset/gpio-poweroff.txt -index 3e56c1b34a4c..76dd7b06e26a 100644 ---- a/Documentation/devicetree/bindings/power/reset/gpio-poweroff.txt +new file mode 100644 +index 000000000000..76dd7b06e26a +--- /dev/null +++ b/Documentation/devicetree/bindings/power/reset/gpio-poweroff.txt -@@ -31,6 +31,7 @@ Optional properties: - - inactive-delay-ms: Delay (default 100) to wait after driving gpio inactive - - timeout-ms: Time to wait before asserting a WARN_ON(1). If nothing is - specified, 3000 ms is used. +@@ -0,0 +1,42 @@ ++Driver a GPIO line that can be used to turn the power off. ++ ++The driver supports both level triggered and edge triggered power off. ++At driver load time, the driver will request the given gpio line and ++install a handler to power off the system. If the optional properties ++'input' is not found, the GPIO line will be driven in the inactive ++state. Otherwise its configured as an input. ++ ++When the power-off handler is called, the gpio is configured as an ++output, and drive active, so triggering a level triggered power off ++condition. This will also cause an inactive->active edge condition, so ++triggering positive edge triggered power off. After a delay of 100ms, ++the GPIO is set to inactive, thus causing an active->inactive edge, ++triggering negative edge triggered power off. After another 100ms ++delay the GPIO is driver active again. If the power is still on and ++the CPU still running after a 3000ms delay, a WARN_ON(1) is emitted. ++ ++Required properties: ++- compatible : should be "gpio-poweroff". ++- gpios : The GPIO to set high/low, see "gpios property" in ++ Documentation/devicetree/bindings/gpio/gpio.txt. If the pin should be ++ low to power down the board set it to "Active Low", otherwise set ++ gpio to "Active High". ++ ++Optional properties: ++- input : Initially configure the GPIO line as an input. Only reconfigure ++ it to an output when the power-off handler is called. If this optional ++ property is not specified, the GPIO is initialized as an output in its ++ inactive state. ++- active-delay-ms: Delay (default 100) to wait after driving gpio active ++- inactive-delay-ms: Delay (default 100) to wait after driving gpio inactive ++- timeout-ms: Time to wait before asserting a WARN_ON(1). If nothing is ++ specified, 3000 ms is used. +- export : Export the GPIO line to the sysfs system - - Examples: - ++ ++Examples: ++ ++gpio-poweroff { ++ compatible = "gpio-poweroff"; ++ gpios = <&gpio 4 0>; ++ timeout-ms = <3000>; ++}; +diff --git a/Documentation/devicetree/bindings/pwm/pwm-rp1.yaml b/Documentation/devicetree/bindings/pwm/pwm-rp1.yaml +new file mode 100644 +index 000000000000..db9d7085f1c3 +--- /dev/null ++++ b/Documentation/devicetree/bindings/pwm/pwm-rp1.yaml +@@ -0,0 +1,38 @@ ++# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/pwm/pwm-rp1.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: Raspberry Pi RP1 PWM controller ++ ++maintainers: ++ - Naushir Patuck ++ ++properties: ++ compatible: ++ enum: ++ - raspberrypi,rp1-pwm ++ ++ reg: ++ maxItems: 1 ++ ++ "#pwm-cells": ++ const: 3 ++ ++required: ++ - compatible ++ - reg ++ - clocks ++ - "#pwm-cells" ++ ++additionalProperties: false ++ ++examples: ++ - | ++ pwm0: pwm@98000 { ++ compatible = "raspberrypi,rp1-pwm"; ++ reg = <0x0 0x98000 0x0 0x100>; ++ clocks = <&rp1_sys>; ++ #pwm-cells = <3>; ++ }; +diff --git a/Documentation/devicetree/bindings/rtc/rtc-rpi.txt b/Documentation/devicetree/bindings/rtc/rtc-rpi.txt +new file mode 100644 +index 000000000000..ed0d0d0a8464 +--- /dev/null ++++ b/Documentation/devicetree/bindings/rtc/rtc-rpi.txt +@@ -0,0 +1,22 @@ ++* Raspberry Pi RTC ++ ++This is a Linux interface to an RTC managed by firmware, hence it's ++virtual from a Linux perspective. ++ ++The interface uses the firmware mailbox api to access the RTC registers. ++ ++Required properties: ++compatible: should be "raspberrypi,rpi-rtc" ++firmware: Reference to the RPi firmware device node. ++ ++Optional property: ++trickle-charge-microvolt: specify a trickle charge voltage for the backup ++ battery in microvolts. ++ ++Example: ++ ++ rpi_rtc: rpi_rtc { ++ compatible = "raspberrypi,rpi-rtc"; ++ firmware = <&firmware>; ++ trickle-charge-microvolt = <3000000>; ++ }; diff --git a/Documentation/devicetree/bindings/serial/pl011.yaml b/Documentation/devicetree/bindings/serial/pl011.yaml -index c23c93b400f0..5e1d6483b2a9 100644 +index 9571041030b7..f34e2f66d1a3 100644 --- a/Documentation/devicetree/bindings/serial/pl011.yaml +++ b/Documentation/devicetree/bindings/serial/pl011.yaml -@@ -98,6 +98,12 @@ properties: - $ref: /schemas/types.yaml#/definitions/uint32 - default: 3000 +@@ -101,6 +101,12 @@ properties: + on the device. + enum: [1, 4] + cts-event-workaround: + description: @@ -2819,6 +3862,74 @@ index c23c93b400f0..5e1d6483b2a9 100644 required: - compatible - reg +diff --git a/Documentation/devicetree/bindings/sound/pcm512x.txt b/Documentation/devicetree/bindings/sound/pcm512x.txt +index 3aae3b41bd8e..77006a4aec4a 100644 +--- a/Documentation/devicetree/bindings/sound/pcm512x.txt ++++ b/Documentation/devicetree/bindings/sound/pcm512x.txt +@@ -1,12 +1,12 @@ +-PCM512x audio CODECs ++PCM512x and TAS575x audio CODECs/amplifiers + + These devices support both I2C and SPI (configured with pin strapping +-on the board). ++on the board). The TAS575x devices only support I2C. + + Required properties: + +- - compatible : One of "ti,pcm5121", "ti,pcm5122", "ti,pcm5141" or +- "ti,pcm5142" ++ - compatible : One of "ti,pcm5121", "ti,pcm5122", "ti,pcm5141", ++ "ti,pcm5142", "ti,tas5754" or "ti,tas5756" + + - reg : the I2C address of the device for I2C, the chip select + number for SPI. +@@ -25,6 +25,7 @@ Optional properties: + through <6>. The device will be configured for clock input on the + given pll-in pin and PLL output on the given pll-out pin. An + external connection from the pll-out pin to the SCLK pin is assumed. ++ Caution: the TAS-desvices only support gpios 1,2 and 3 + + Examples: + +diff --git a/Documentation/devicetree/bindings/spi/spi-gpio.yaml b/Documentation/devicetree/bindings/spi/spi-gpio.yaml +index 9ce1df93d4c3..d911c203fa45 100644 +--- a/Documentation/devicetree/bindings/spi/spi-gpio.yaml ++++ b/Documentation/devicetree/bindings/spi/spi-gpio.yaml +@@ -43,6 +43,10 @@ properties: + with no chip select is connected. + $ref: /schemas/types.yaml#/definitions/uint32 + ++ sck-idle-input: ++ description: Make SCK an input when inactive. ++ type: boolean ++ + # Deprecated properties + gpio-sck: false + gpio-miso: false +diff --git a/Documentation/devicetree/bindings/usb/snps,dwc3.yaml b/Documentation/devicetree/bindings/usb/snps,dwc3.yaml +index a696f23730d3..d516979b0681 100644 +--- a/Documentation/devicetree/bindings/usb/snps,dwc3.yaml ++++ b/Documentation/devicetree/bindings/usb/snps,dwc3.yaml +@@ -233,12 +233,17 @@ properties: + + snps,parkmode-disable-ss-quirk: + description: +- When set, all SuperSpeed bus instances in park mode are disabled. ++ When set, disable park mode for all Superspeed bus instances. + type: boolean + + snps,parkmode-disable-hs-quirk: + description: +- When set, all HighSpeed bus instances in park mode are disabled. ++ When set, disable park mode for all Highspeed bus instances. ++ type: boolean ++ ++ snps,parkmode-disable-fsls-quirk: ++ description: ++ When set, disable park mode for all Full/Lowspeed bus instances. + type: boolean + + snps,dis_metastability_quirk: diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt new file mode 100644 index 000000000000..f8d32547195b @@ -3289,19 +4400,28 @@ index 000000000000..f8d32547195b +zte ZTE Corp. +zyxel ZyXEL Communications Corp. diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml -index 2735be1a8470..e8a98ec7632d 100644 +index 133cfb2bb05c..d5805b33bd0e 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml -@@ -159,6 +159,8 @@ patternProperties: +@@ -133,6 +133,8 @@ patternProperties: + description: arcx Inc. / Archronix Inc. + "^aries,.*": + description: Aries Embedded GmbH ++ "^arducam,.*": ++ description: Arducam Technology co., Ltd. + "^arm,.*": + description: ARM Ltd. + "^armadeus,.*": +@@ -196,6 +198,8 @@ patternProperties: description: Beckhoff Automation GmbH & Co. KG "^bitmain,.*": description: Bitmain Technologies + "^blokaslabs,.*": + description: Vilniaus Blokas UAB + "^blutek,.*": + description: BluTek Power "^boe,.*": - description: BOE Technology Group Co., Ltd. - "^bosch,.*": -@@ -399,6 +401,8 @@ patternProperties: +@@ -504,6 +508,8 @@ patternProperties: description: General Electric Company "^geekbuying,.*": description: GeekBuying @@ -3347,166 +4467,77 @@ index 000000000000..5fa43e064307 +better suited to different use patterns. The firmware interface is what's +intended to be used by hardware managers in the kernel, while the copy interface +make sense for developers (since it avoids problems with namespaces). -diff --git a/Documentation/hwmon/rpi-poe-fan b/Documentation/hwmon/rpi-poe-fan -new file mode 100644 -index 000000000000..9182ab633993 ---- /dev/null -+++ b/Documentation/hwmon/rpi-poe-fan -@@ -0,0 +1,15 @@ -+Kernel driver rpi-poe-fan -+===================== +diff --git a/Documentation/driver-api/pwm.rst b/Documentation/driver-api/pwm.rst +index 3fdc95f7a1d1..c68ed828fba9 100644 +--- a/Documentation/driver-api/pwm.rst ++++ b/Documentation/driver-api/pwm.rst +@@ -41,11 +41,20 @@ the getter, devm_pwm_get() and devm_fwnode_pwm_get(), also exist. + + After being requested, a PWM has to be configured using:: + +- int pwm_apply_state(struct pwm_device *pwm, struct pwm_state *state); ++ int pwm_apply_might_sleep(struct pwm_device *pwm, struct pwm_state *state); + + This API controls both the PWM period/duty_cycle config and the + enable/disable state. + ++PWM devices can be used from atomic context, if the PWM does not sleep. You ++can check if this the case with:: + -+This driver enables the use of the Raspberry Pi PoE HAT fan. ++ bool pwm_might_sleep(struct pwm_device *pwm); + -+Author: Serge Schneider ++If false, the PWM can also be configured from atomic context with:: + -+Description -+----------- ++ int pwm_apply_atomic(struct pwm_device *pwm, struct pwm_state *state); + -+The driver implements a simple interface for driving the Raspberry Pi PoE -+(Power over Ethernet) HAT fan. The driver passes commands to the Raspberry Pi -+firmware through the mailbox property interface. The firmware then forwards -+the commands to the board over I2C on the ID_EEPROM pins. The driver exposes -+the fan to the user space through the hwmon sysfs interface. + As a consumer, don't rely on the output's state for a disabled PWM. If it's + easily possible, drivers are supposed to emit the inactive state, but some + drivers cannot. If you rely on getting the inactive state, use .duty_cycle=0, +@@ -57,13 +66,13 @@ If supported by the driver, the signal can be optimized, for example to improve + EMI by phase shifting the individual channels of a chip. + + The pwm_config(), pwm_enable() and pwm_disable() functions are just wrappers +-around pwm_apply_state() and should not be used if the user wants to change ++around pwm_apply_might_sleep() and should not be used if the user wants to change + several parameter at once. For example, if you see pwm_config() and + pwm_{enable,disable}() calls in the same function, this probably means you +-should switch to pwm_apply_state(). ++should switch to pwm_apply_might_sleep(). + + The PWM user API also allows one to query the PWM state that was passed to the +-last invocation of pwm_apply_state() using pwm_get_state(). Note this is ++last invocation of pwm_apply_might_sleep() using pwm_get_state(). Note this is + different to what the driver has actually implemented if the request cannot be + satisfied exactly with the hardware in use. There is currently no way for + consumers to get the actually implemented settings. diff --git a/Documentation/userspace-api/media/drivers/index.rst b/Documentation/userspace-api/media/drivers/index.rst -index 05a82f8c0c99..df39e6ad40e3 100644 +index 6708d649afd7..65de8ab99c58 100644 --- a/Documentation/userspace-api/media/drivers/index.rst +++ b/Documentation/userspace-api/media/drivers/index.rst -@@ -33,6 +33,7 @@ For more details see the file COPYING in the source distribution of Linux. - +@@ -36,6 +36,7 @@ For more details see the file COPYING in the source distribution of Linux. cx2341x-uapi + dw100 imx-uapi + bcm2835-isp max2175 - meye-uapi omap3isp-uapi -diff --git a/Documentation/userspace-api/media/v4l/ext-ctrls-codec.rst b/Documentation/userspace-api/media/v4l/ext-ctrls-codec.rst -index b864869b42bc..3163f501afb4 100644 ---- a/Documentation/userspace-api/media/v4l/ext-ctrls-codec.rst -+++ b/Documentation/userspace-api/media/v4l/ext-ctrls-codec.rst -@@ -4111,6 +4111,9 @@ enum v4l2_mpeg_video_hevc_size_of_length_field - - * - __u32 - - ``data_bit_offset`` - - Offset (in bits) to the video data in the current slice data. -+ * - __u32 -+ - ``slice_segment_addr`` -+ - - * - __u8 - - ``nal_unit_type`` - - -@@ -4188,7 +4191,7 @@ enum v4l2_mpeg_video_hevc_size_of_length_field - - - ``num_rps_poc_lt_curr`` - - The number of reference pictures in the long-term set. - * - __u8 -- - ``padding[7]`` -+ - ``padding[5]`` - - Applications and drivers must set this to zero. - * - struct :c:type:`v4l2_hevc_dpb_entry` - - ``dpb[V4L2_HEVC_DPB_ENTRIES_NUM_MAX]`` -@@ -4319,6 +4322,47 @@ enum v4l2_mpeg_video_hevc_size_of_length_field - - - ``padding[6]`` - - Applications and drivers must set this to zero. - -+``V4L2_CID_MPEG_VIDEO_HEVC_SCALING_MATRIX (struct)`` -+ Specifies the scaling matrix (as extracted from the bitstream) for -+ the associated HEVC slice data. The bitstream parameters are -+ defined according to :ref:`hevc`, section 7.4.5 "Scaling list -+ data semantics". For further documentation, refer to the above -+ specification, unless there is an explicit comment stating -+ otherwise. -+ -+ .. note:: -+ -+ This compound control is not yet part of the public kernel API and -+ it is expected to change. -+ -+.. c:type:: v4l2_ctrl_hevc_scaling_matrix -+ -+.. cssclass:: longtable -+ -+.. flat-table:: struct v4l2_ctrl_hevc_scaling_matrix -+ :header-rows: 0 -+ :stub-columns: 0 -+ :widths: 1 1 2 -+ -+ * - __u8 -+ - ``scaling_list_4x4[6][16]`` -+ - -+ * - __u8 -+ - ``scaling_list_8x8[6][64]`` -+ - -+ * - __u8 -+ - ``scaling_list_16x16[6][64]`` -+ - -+ * - __u8 -+ - ``scaling_list_32x32[2][64]`` -+ - -+ * - __u8 -+ - ``scaling_list_dc_coef_16x16[6]`` -+ - -+ * - __u8 -+ - ``scaling_list_dc_coef_32x32[2]`` -+ - -+ - ``V4L2_CID_MPEG_VIDEO_HEVC_DECODE_MODE (enum)`` - Specifies the decoding mode to use. Currently exposes slice-based and - frame-based decoding but new modes might be added later on. -diff --git a/Documentation/userspace-api/media/v4l/ext-ctrls-image-source.rst b/Documentation/userspace-api/media/v4l/ext-ctrls-image-source.rst -index 9457dc340c31..af8fa25026c0 100644 ---- a/Documentation/userspace-api/media/v4l/ext-ctrls-image-source.rst -+++ b/Documentation/userspace-api/media/v4l/ext-ctrls-image-source.rst -@@ -58,3 +58,23 @@ Image Source Control IDs - The unit cell consists of the whole area of the pixel, sensitive and - non-sensitive. - This control is required for automatic calibration of sensors/cameras. -+ -+``V4L2_CID_NOTIFY_GAINS (integer array)`` -+ The sensor is notified what gains will be applied to the different -+ colour channels by subsequent processing (such as by an ISP). The -+ sensor is merely informed of these values in case it performs -+ processing that requires them, but it does not apply them itself to -+ the output pixels. -+ -+ Currently it is defined only for Bayer sensors, and is an array -+ control taking 4 gain values, being the gains for each of the -+ Bayer channels. The gains are always in the order B, Gb, Gr and R, -+ irrespective of the exact Bayer order of the sensor itself. -+ -+ The use of an array allows this control to be extended to sensors -+ with, for example, non-Bayer CFAs (colour filter arrays). -+ -+ The units for the gain values are linear, with the default value -+ representing a gain of exactly 1.0. For example, if this default value -+ is reported as being (say) 128, then a value of 192 would represent -+ a gain of exactly 1.5. + st-vgxy61 diff --git a/Documentation/userspace-api/media/v4l/meta-formats.rst b/Documentation/userspace-api/media/v4l/meta-formats.rst -index fff25357fe86..c1dd92a2d617 100644 +index 0bb61fc5bc00..d421ccdfccfc 100644 --- a/Documentation/userspace-api/media/v4l/meta-formats.rst +++ b/Documentation/userspace-api/media/v4l/meta-formats.rst @@ -12,9 +12,11 @@ These formats are used for the :ref:`metadata` interface only. .. toctree:: :maxdepth: 1 -+ pixfmt-meta-bcm2835-isp-stats - pixfmt-meta-d4xx - pixfmt-meta-intel-ipu3 - pixfmt-meta-rkisp1 -+ pixfmt-meta-sensor-data - pixfmt-meta-uvc - pixfmt-meta-vsp1-hgo - pixfmt-meta-vsp1-hgt -diff --git a/Documentation/userspace-api/media/v4l/pixfmt-compressed.rst b/Documentation/userspace-api/media/v4l/pixfmt-compressed.rst -index d585909bc4e2..f817c643761b 100644 ---- a/Documentation/userspace-api/media/v4l/pixfmt-compressed.rst -+++ b/Documentation/userspace-api/media/v4l/pixfmt-compressed.rst -@@ -200,6 +200,7 @@ Compressed Formats - * ``V4L2_CID_MPEG_VIDEO_HEVC_SPS`` - * ``V4L2_CID_MPEG_VIDEO_HEVC_PPS`` - * ``V4L2_CID_MPEG_VIDEO_HEVC_SLICE_PARAMS`` -+ * ``V4L2_CID_MPEG_VIDEO_HEVC_SCALING_MATRIX`` - See the :ref:`associated Codec Control IDs `. - Buffers associated with this pixel format must contain the appropriate - number of macroblocks to decode a full corresponding frame. ++ metafmt-bcm2835-isp-stats + metafmt-d4xx + metafmt-intel-ipu3 + metafmt-rkisp1 ++ metafmt-sensor-data + metafmt-uvc + metafmt-vsp1-hgo + metafmt-vsp1-hgt diff --git a/Documentation/userspace-api/media/v4l/pixfmt-meta-bcm2835-isp-stats.rst b/Documentation/userspace-api/media/v4l/pixfmt-meta-bcm2835-isp-stats.rst new file mode 100644 index 000000000000..f974774c8252 @@ -3813,38 +4844,6 @@ index 000000000000..196ca33a5dff + + + -diff --git a/Documentation/userspace-api/media/v4l/pixfmt-nv12.rst b/Documentation/userspace-api/media/v4l/pixfmt-nv12.rst -index dd2f38129fe6..359f7ce67114 100644 ---- a/Documentation/userspace-api/media/v4l/pixfmt-nv12.rst -+++ b/Documentation/userspace-api/media/v4l/pixfmt-nv12.rst -@@ -3,9 +3,9 @@ - .. _V4L2-PIX-FMT-NV12: - .. _V4L2-PIX-FMT-NV21: - --****************************************************** --V4L2_PIX_FMT_NV12 ('NV12'), V4L2_PIX_FMT_NV21 ('NV21') --****************************************************** -+******************************************************************************** -+V4L2_PIX_FMT_NV12 ('NV12'), V4L2_PIX_FMT_NV21 ('NV21'), V4L2_PIX_FMT_NV12_COL128 -+******************************************************************************** - - - V4L2_PIX_FMT_NV21 -@@ -31,6 +31,14 @@ with a Cr byte. - If the Y plane has pad bytes after each row, then the CbCr plane has as - many pad bytes after its rows. - -+``V4L2_PIX_FMT_NV12_COL128`` is the tiled version of -+``V4L2_PIX_FMT_NV12`` with the image broken down into 128 pixel wide columns of -+Y followed by the associated combined CbCr plane. -+The normal bytesperline is effectively fixed at 128. However the format -+requires knowledge of the stride between columns, therefore the bytesperline -+value has been repurposed to denote the number of 128 byte long lines between -+the start of each column. -+ - **Byte Order.** - Each cell is one byte. - diff --git a/Documentation/userspace-api/media/v4l/pixfmt-y12p.rst b/Documentation/userspace-api/media/v4l/pixfmt-y12p.rst new file mode 100644 index 000000000000..3704f9180fd7 @@ -3956,18 +4955,41 @@ index 000000000000..27fe14c9a9eb + - Y'\ :sub:`03low bits 5--0`\ (bits 7--2) + + Y'\ :sub:`02low bits 5--4`\ (bits 1--0) +diff --git a/Documentation/userspace-api/media/v4l/pixfmt-yuv-planar.rst b/Documentation/userspace-api/media/v4l/pixfmt-yuv-planar.rst +index 1840224faa41..56ef9ee9c0e1 100644 +--- a/Documentation/userspace-api/media/v4l/pixfmt-yuv-planar.rst ++++ b/Documentation/userspace-api/media/v4l/pixfmt-yuv-planar.rst +@@ -697,6 +697,18 @@ Data in the 12 high bits, zeros in the 4 low bits, arranged in little endian ord + - Cr\ :sub:`11` + + ++V4L2_PIX_FMT_NV12_COL128 ++------------------------ ++ ++``V4L2_PIX_FMT_NV12_COL128`` is the tiled version of ++``V4L2_PIX_FMT_NV12`` with the image broken down into 128 pixel wide columns of ++Y followed by the associated combined CbCr plane. ++The normal bytesperline is effectively fixed at 128. However the format ++requires knowledge of the stride between columns, therefore the bytesperline ++value has been repurposed to denote the number of 128 byte long lines between ++the start of each column. ++ ++ + Fully Planar YUV Formats + ======================== + diff --git a/Documentation/userspace-api/media/v4l/subdev-formats.rst b/Documentation/userspace-api/media/v4l/subdev-formats.rst -index eff6727c69d3..a62c416f1408 100644 +index a3a35eeed708..d7250b6a1695 100644 --- a/Documentation/userspace-api/media/v4l/subdev-formats.rst +++ b/Documentation/userspace-api/media/v4l/subdev-formats.rst -@@ -620,6 +620,43 @@ The following tables list existing packed RGB formats. +@@ -624,6 +624,43 @@ The following tables list existing packed RGB formats. - b\ :sub:`2` - b\ :sub:`1` - b\ :sub:`0` + * .. _MEDIA_BUS_FMT_RGB565_1X24_CPADHI: + + - MEDIA_BUS_FMT_RGB565_1X24_CPADHI -+ - 0x1020 ++ - 0x1022 + - + - + - @@ -4004,14 +5026,14 @@ index eff6727c69d3..a62c416f1408 100644 * .. _MEDIA-BUS-FMT-BGR565-2X8-BE: - MEDIA_BUS_FMT_BGR565_2X8_BE -@@ -908,6 +945,43 @@ The following tables list existing packed RGB formats. +@@ -912,6 +949,43 @@ The following tables list existing packed RGB formats. - g\ :sub:`5` - g\ :sub:`4` - g\ :sub:`3` + * .. _MEDIA-BUS-FMT-BGR666-1X18: + -+ - MEDIA_BUS_FMT_RGB666_1X18 -+ - 0x101f ++ - MEDIA_BUS_FMT-BGR666_1X18 ++ - 0x1023 + - + - + - @@ -4048,14 +5070,14 @@ index eff6727c69d3..a62c416f1408 100644 * .. _MEDIA-BUS-FMT-RGB666-1X18: - MEDIA_BUS_FMT_RGB666_1X18 -@@ -982,6 +1056,43 @@ The following tables list existing packed RGB formats. +@@ -1023,6 +1097,43 @@ The following tables list existing packed RGB formats. - g\ :sub:`2` - g\ :sub:`1` - g\ :sub:`0` + * .. _MEDIA-BUS-FMT-BGR666-1X24_CPADHI: + + - MEDIA_BUS_FMT_BGR666_1X24_CPADHI -+ - 0x101e ++ - 0x1024 + - + - + - @@ -4092,11 +5114,10 @@ index eff6727c69d3..a62c416f1408 100644 * .. _MEDIA-BUS-FMT-RGB666-1X24_CPADHI: - MEDIA_BUS_FMT_RGB666_1X24_CPADHI -@@ -7899,3 +8010,36 @@ formats. - - 0x5001 - - Interleaved raw UYVY and JPEG image format with embedded meta-data - used by Samsung S3C73MX camera sensors. -+ +@@ -8234,3 +8345,35 @@ The following table lists the existing metadata formats. + both sides of the link and the bus format is a fixed + metadata format that is not configurable from userspace. + Width and height will be set to 0 for this format. + + +.. _v4l2-mbus-sensor-data: @@ -4130,32 +5151,66 @@ index eff6727c69d3..a62c416f1408 100644 + `_ + diff --git a/Documentation/userspace-api/media/v4l/yuv-formats.rst b/Documentation/userspace-api/media/v4l/yuv-formats.rst -index 4a05a105a9e6..ba3a5b599362 100644 +index 24b34cdfa6fe..44589ac3e909 100644 --- a/Documentation/userspace-api/media/v4l/yuv-formats.rst +++ b/Documentation/userspace-api/media/v4l/yuv-formats.rst -@@ -28,7 +28,9 @@ to brightness information. - pixfmt-grey - pixfmt-y10 - pixfmt-y12 +@@ -267,7 +267,28 @@ image. + pixfmt-packed-yuv + pixfmt-yuv-planar + pixfmt-yuv-luma + pixfmt-y12p - pixfmt-y14 + pixfmt-y14p - pixfmt-y10b - pixfmt-y10p - pixfmt-y16 -@@ -51,6 +53,7 @@ to brightness information. - pixfmt-nv12 - pixfmt-nv12m - pixfmt-nv12mt + pixfmt-y8i + pixfmt-y12i + pixfmt-uv8 ++ pixfmt-yuyv ++ pixfmt-uyvy ++ pixfmt-yvyu ++ pixfmt-vyuy ++ pixfmt-y41p ++ pixfmt-yuv420 ++ pixfmt-yuv420m ++ pixfmt-yuv422m ++ pixfmt-yuv444m ++ pixfmt-yuv410 ++ pixfmt-yuv422p ++ pixfmt-yuv411p ++ pixfmt-nv12 ++ pixfmt-nv12m ++ pixfmt-nv12mt + pixfmt-nv12-col128 - pixfmt-nv16 - pixfmt-nv16m - pixfmt-nv24 ++ pixfmt-nv16 ++ pixfmt-nv16m ++ pixfmt-nv24 + pixfmt-m420 diff --git a/MAINTAINERS b/MAINTAINERS -index 23a23bd94c00..87dd5d4ac875 100644 +index cd4f9e589245..9c9668adac5d 100644 --- a/MAINTAINERS +++ b/MAINTAINERS -@@ -3417,6 +3417,29 @@ N: bcm113* +@@ -1563,6 +1563,22 @@ S: Maintained + F: drivers/net/arcnet/ + F: include/uapi/linux/if_arcnet.h + ++ARDUCAM 64MP SENSOR DRIVER ++M: Arducam Kernel Maintenance ++L: linux-media@vger.kernel.org ++S: Maintained ++T: git git://linuxtv.org/media_tree.git ++F: Documentation/devicetree/bindings/media/i2c/arducam,64mp.yaml ++F: drivers/media/i2c/arducam_64mp.c ++ ++ARDUCAM PIVARIETY SENSOR DRIVER ++M: Arducam Kernel Maintenance ++L: linux-media@vger.kernel.org ++S: Maintained ++T: git git://linuxtv.org/media_tree.git ++F: Documentation/devicetree/bindings/media/i2c/arducam-pivariety.yaml ++F: drivers/media/i2c/arducam-pivariety.c ++ + ARM AND ARM64 SoC SUB-ARCHITECTURES (COMMON PARTS) + M: Arnd Bergmann + M: Olof Johansson +@@ -3916,6 +3932,29 @@ N: bcm113* N: bcm216* N: kona @@ -4185,24 +5240,56 @@ index 23a23bd94c00..87dd5d4ac875 100644 BROADCOM BCM47XX MIPS ARCHITECTURE M: Hauke Mehrtens M: RafaÅ‚ MiÅ‚ecki -@@ -5513,6 +5536,14 @@ S: Maintained - F: Documentation/devicetree/bindings/display/panel/feiyang,fy07024di26a30d.yaml - F: drivers/gpu/drm/panel/panel-feiyang-fy07024di26a30d.c - -+DRM DRIVER FOR GENERIC USB DISPLAY -+M: Noralf Trønnes -+S: Maintained -+W: https://github.com/notro/gud/wiki -+T: git git://anongit.freedesktop.org/drm/drm-misc -+F: drivers/gpu/drm/gud/ -+F: include/drm/gud.h -+ - DRM DRIVER FOR GRAIN MEDIA GM12U320 PROJECTORS - M: Hans de Goede - S: Maintained -@@ -16402,6 +16433,23 @@ S: Maintained +@@ -15852,6 +15891,14 @@ S: Maintained T: git git://linuxtv.org/media_tree.git - F: drivers/media/i2c/imx355.c + F: drivers/media/i2c/ov5695.c + ++OMNIVISION OV64A40 SENSOR DRIVER ++M: Jacopo Mondi ++L: linux-media@vger.kernel.org ++S: Maintained ++T: git git://linuxtv.org/media_tree.git ++F: Documentation/devicetree/bindings/media/i2c/ovti,ov64a40.yaml ++F: drivers/media/i2c/ov64a40.c ++ + OMNIVISION OV7670 SENSOR DRIVER + L: linux-media@vger.kernel.org + S: Orphan +@@ -17410,7 +17457,7 @@ F: drivers/video/backlight/pwm_bl.c + F: include/dt-bindings/pwm/ + F: include/linux/pwm.h + F: include/linux/pwm_backlight.h +-K: pwm_(config|apply_state|ops) ++K: pwm_(config|apply_might_sleep|apply_atomic|ops) + + PXA GPIO DRIVER + M: Robert Jarzmik +@@ -18602,6 +18649,13 @@ S: Supported + F: drivers/iio/light/rohm-bu27008.c + F: drivers/iio/light/rohm-bu27034.c + ++ROHM BU64754 MOTOR DRIVER FOR CAMERA AUTOFOCUS ++M: Kieran Bingham ++L: linux-media@vger.kernel.org ++S: Maintained ++T: git git://linuxtv.org/media_tree.git ++F: Documentation/devicetree/bindings/media/i2c/rohm,bu64754.yaml ++ + ROHM MULTIFUNCTION BD9571MWV-M PMIC DEVICE DRIVERS + M: Marek Vasut + L: linux-kernel@vger.kernel.org +@@ -19995,7 +20049,7 @@ M: Sakari Ailus + L: linux-media@vger.kernel.org + S: Maintained + T: git git://linuxtv.org/media_tree.git +-F: Documentation/devicetree/bindings/media/i2c/imx258.yaml ++F: Documentation/devicetree/bindings/media/i2c/sony,imx258.yaml + F: drivers/media/i2c/imx258.c + + SONY IMX274 SENSOR DRIVER +@@ -20072,6 +20126,31 @@ T: git git://linuxtv.org/media_tree.git + F: Documentation/devicetree/bindings/media/i2c/sony,imx415.yaml + F: drivers/media/i2c/imx415.c +SONY IMX477 SENSOR DRIVER +M: Raspberry Pi Kernel Maintenance @@ -4220,81 +5307,119 @@ index 23a23bd94c00..87dd5d4ac875 100644 +T: git git://linuxtv.org/media_tree.git +F: Documentation/devicetree/bindings/media/i2c/imx519.yaml +F: drivers/media/i2c/imx519.c ++ ++SONY IMX708 SENSOR DRIVER ++M: Raspberry Pi Kernel Maintenance ++L: linux-media@vger.kernel.org ++S: Maintained ++T: git git://linuxtv.org/media_tree.git ++F: Documentation/devicetree/bindings/media/i2c/sony,imx708.yaml ++F: drivers/media/i2c/imx708.c + SONY MEMORYSTICK SUBSYSTEM M: Maxim Levitsky M: Alex Dubov -diff --git a/Makefile b/Makefile -index 3ebf74787e93..e16eb72067f4 100644 ---- a/Makefile -+++ b/Makefile -@@ -1354,6 +1354,9 @@ ifneq ($(dtstree),) - %.dtb: include/config/kernel.release scripts_dtc - $(Q)$(MAKE) $(build)=$(dtstree) $(dtstree)/$@ - -+%.dtbo: include/config/kernel.release scripts_dtc -+ $(Q)$(MAKE) $(build)=$(dtstree) $(dtstree)/$@ +diff --git a/README.md b/README.md +new file mode 100644 +index 000000000000..e33ba1b6c950 +--- /dev/null ++++ b/README.md +@@ -0,0 +1,30 @@ ++Linux kernel ++============ + - PHONY += dtbs dtbs_install dtbs_check - dtbs: include/config/kernel.release scripts_dtc - $(Q)$(MAKE) $(build)=$(dtstree) ++There are several guides for kernel developers and users. These guides can ++be rendered in a number of formats, like HTML and PDF. Please read ++Documentation/admin-guide/README.rst first. ++ ++In order to build the documentation, use ``make htmldocs`` or ++``make pdfdocs``. The formatted documentation can also be read online at: ++ ++ https://www.kernel.org/doc/html/latest/ ++ ++There are various text files in the Documentation/ subdirectory, ++several of them using the Restructured Text markup notation. ++ ++Please read the Documentation/process/changes.rst file, as it contains the ++requirements for building and running the kernel, and information about ++the problems which may result by upgrading your kernel. ++ ++Build status for rpi-5.15.y: ++[![Pi kernel build tests](https://github.com/raspberrypi/linux/actions/workflows/kernel-build.yml/badge.svg?branch=rpi-5.15.y)](https://github.com/raspberrypi/linux/actions/workflows/kernel-build.yml) ++[![dtoverlaycheck](https://github.com/raspberrypi/linux/actions/workflows/dtoverlaycheck.yml/badge.svg?branch=rpi-5.15.y)](https://github.com/raspberrypi/linux/actions/workflows/dtoverlaycheck.yml) ++ ++Build status for rpi-6.1.y: ++[![Pi kernel build tests](https://github.com/raspberrypi/linux/actions/workflows/kernel-build.yml/badge.svg?branch=rpi-6.1.y)](https://github.com/raspberrypi/linux/actions/workflows/kernel-build.yml) ++[![dtoverlaycheck](https://github.com/raspberrypi/linux/actions/workflows/dtoverlaycheck.yml/badge.svg?branch=rpi-6.1.y)](https://github.com/raspberrypi/linux/actions/workflows/dtoverlaycheck.yml) ++ ++Build status for rpi-6.6.y: ++[![Pi kernel build tests](https://github.com/raspberrypi/linux/actions/workflows/kernel-build.yml/badge.svg?branch=rpi-6.6.y)](https://github.com/raspberrypi/linux/actions/workflows/kernel-build.yml) ++[![dtoverlaycheck](https://github.com/raspberrypi/linux/actions/workflows/dtoverlaycheck.yml/badge.svg?branch=rpi-6.6.y)](https://github.com/raspberrypi/linux/actions/workflows/dtoverlaycheck.yml) diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile -index 7e8151681597..6bcb35ad76ac 100644 +index efe38eb25301..a2a407fb5b28 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile -@@ -1,4 +1,24 @@ - # SPDX-License-Identifier: GPL-2.0 -+ -+dtb-$(CONFIG_ARCH_BCM2835) += \ -+ bcm2708-rpi-b.dtb \ -+ bcm2708-rpi-b-rev1.dtb \ -+ bcm2708-rpi-b-plus.dtb \ -+ bcm2708-rpi-cm.dtb \ -+ bcm2708-rpi-zero.dtb \ -+ bcm2708-rpi-zero-w.dtb \ -+ bcm2710-rpi-zero-2.dtb \ -+ bcm2710-rpi-zero-2-w.dtb \ -+ bcm2709-rpi-2-b.dtb \ -+ bcm2710-rpi-2-b.dtb \ -+ bcm2710-rpi-3-b.dtb \ -+ bcm2710-rpi-3-b-plus.dtb \ -+ bcm2711-rpi-4-b.dtb \ -+ bcm2711-rpi-400.dtb \ -+ bcm2710-rpi-cm3.dtb \ -+ bcm2711-rpi-cm4.dtb \ -+ bcm2711-rpi-cm4s.dtb -+ - dtb-$(CONFIG_ARCH_ALPINE) += \ - alpine-db.dtb - dtb-$(CONFIG_MACH_ARTPEC6) += \ -@@ -92,7 +112,6 @@ dtb-$(CONFIG_ARCH_BCM2835) += \ - bcm2837-rpi-3-b.dtb \ - bcm2837-rpi-3-b-plus.dtb \ - bcm2837-rpi-cm3-io3.dtb \ -- bcm2711-rpi-4-b.dtb \ - bcm2835-rpi-zero.dtb \ - bcm2835-rpi-zero-w.dtb - dtb-$(CONFIG_ARCH_BCM_5301X) += \ -@@ -1409,3 +1428,13 @@ dtb-$(CONFIG_ARCH_ASPEED) += \ - aspeed-bmc-opp-zaius.dtb \ - aspeed-bmc-portwell-neptune.dtb \ - aspeed-bmc-quanta-q71l.dtb +@@ -39,3 +39,8 @@ subdir-y += unisoc + subdir-y += vt8500 + subdir-y += xen + subdir-y += xilinx + +targets += dtbs dtbs_install +targets += $(dtb-y) + -+subdir-y := overlays ++subdir-y += overlays +diff --git a/arch/arm/boot/dts/broadcom/Makefile b/arch/arm/boot/dts/broadcom/Makefile +index 7099d9560033..4af351c7f7b2 100644 +--- a/arch/arm/boot/dts/broadcom/Makefile ++++ b/arch/arm/boot/dts/broadcom/Makefile +@@ -35,6 +35,41 @@ dtb-$(CONFIG_ARCH_BCM2835) += \ + bcm2711-rpi-cm4-io.dtb \ + bcm2835-rpi-zero.dtb \ + bcm2835-rpi-zero-w.dtb + -+# Enable fixups to support overlays on BCM2835 platforms -+ifeq ($(CONFIG_ARCH_BCM2835),y) -+ DTC_FLAGS += -@ -+endif -diff --git a/arch/arm/boot/dts/bcm2708-rpi-b-plus.dts b/arch/arm/boot/dts/bcm2708-rpi-b-plus.dts ++DTC_FLAGS_bcm2708-rpi-b := -@ ++DTC_FLAGS_bcm2708-rpi-b-rev1 := -@ ++DTC_FLAGS_bcm2708-rpi-b-plus := -@ ++DTC_FLAGS_bcm2708-rpi-cm := -@ ++DTC_FLAGS_bcm2708-rpi-zero := -@ ++DTC_FLAGS_bcm2708-rpi-zero-w := -@ ++DTC_FLAGS_bcm2710-rpi-zero-2 := -@ ++DTC_FLAGS_bcm2710-rpi-zero-2-w := -@ ++DTC_FLAGS_bcm2709-rpi-2-b := -@ ++DTC_FLAGS_bcm2710-rpi-2-b := -@ ++DTC_FLAGS_bcm2710-rpi-3-b := -@ ++DTC_FLAGS_bcm2710-rpi-3-b-plus := -@ ++DTC_FLAGS_bcm2709-rpi-cm2 := -@ ++DTC_FLAGS_bcm2710-rpi-cm3 := -@ ++DTC_FLAGS_bcm2711-rpi-cm4 := -@ ++DTC_FLAGS_bcm2711-rpi-cm4s := -@ ++dtb-$(CONFIG_ARCH_BCM2835) += \ ++ bcm2708-rpi-b.dtb \ ++ bcm2708-rpi-b-rev1.dtb \ ++ bcm2708-rpi-b-plus.dtb \ ++ bcm2708-rpi-cm.dtb \ ++ bcm2708-rpi-zero.dtb \ ++ bcm2708-rpi-zero-w.dtb \ ++ bcm2710-rpi-zero-2.dtb \ ++ bcm2710-rpi-zero-2-w.dtb \ ++ bcm2709-rpi-2-b.dtb \ ++ bcm2710-rpi-2-b.dtb \ ++ bcm2710-rpi-3-b.dtb \ ++ bcm2710-rpi-3-b-plus.dtb \ ++ bcm2709-rpi-cm2.dtb \ ++ bcm2710-rpi-cm3.dtb \ ++ bcm2711-rpi-cm4.dtb \ ++ bcm2711-rpi-cm4s.dtb ++ + dtb-$(CONFIG_ARCH_BCMBCA) += \ + bcm947622.dtb \ + bcm963138.dtb \ +diff --git a/arch/arm/boot/dts/broadcom/bcm2708-rpi-b-plus.dts b/arch/arm/boot/dts/broadcom/bcm2708-rpi-b-plus.dts new file mode 100644 -index 000000000000..a7d6427671b4 +index 000000000000..ee72fdac6663 --- /dev/null -+++ b/arch/arm/boot/dts/bcm2708-rpi-b-plus.dts -@@ -0,0 +1,131 @@ ++++ b/arch/arm/boot/dts/broadcom/bcm2708-rpi-b-plus.dts +@@ -0,0 +1,210 @@ +/dts-v1/; + +#include "bcm2708.dtsi" @@ -4302,6 +5427,7 @@ index 000000000000..a7d6427671b4 +#include "bcm283x-rpi-smsc9514.dtsi" +#include "bcm283x-rpi-csi1-2lane.dtsi" +#include "bcm283x-rpi-i2c0mux_0_28.dtsi" ++#include "bcm283x-rpi-led-deprecated.dtsi" + +/ { + compatible = "raspberrypi,model-b-plus", "brcm,bcm2835"; @@ -4309,6 +5435,71 @@ index 000000000000..a7d6427671b4 +}; + +&gpio { ++ /* ++ * Taken from Raspberry-Pi-B-Plus-V1.2-Schematics.pdf ++ * RPI-BPLUS sheet 1 ++ * ++ * Legend: ++ * "NC" = not connected (no rail from the SoC) ++ * "FOO" = GPIO line named "FOO" on the schematic ++ * "FOO_N" = GPIO line named "FOO" on schematic, active low ++ */ ++ gpio-line-names = "ID_SDA", ++ "ID_SCL", ++ "GPIO2", ++ "GPIO3", ++ "GPIO4", ++ "GPIO5", ++ "GPIO6", ++ "GPIO7", ++ "GPIO8", ++ "GPIO9", ++ "GPIO10", ++ "GPIO11", ++ "GPIO12", ++ "GPIO13", ++ "GPIO14", ++ "GPIO15", ++ "GPIO16", ++ "GPIO17", ++ "GPIO18", ++ "GPIO19", ++ "GPIO20", ++ "GPIO21", ++ "GPIO22", ++ "GPIO23", ++ "GPIO24", ++ "GPIO25", ++ "GPIO26", ++ "GPIO27", ++ "SDA0", ++ "SCL0", ++ "NC", /* GPIO30 */ ++ "LAN_RUN", /* GPIO31 */ ++ "CAM_GPIO1", /* GPIO32 */ ++ "NC", /* GPIO33 */ ++ "NC", /* GPIO34 */ ++ "PWR_LOW_N", /* GPIO35 */ ++ "NC", /* GPIO36 */ ++ "NC", /* GPIO37 */ ++ "USB_LIMIT", /* GPIO38 */ ++ "NC", /* GPIO39 */ ++ "PWM0_OUT", /* GPIO40 */ ++ "CAM_GPIO0", /* GPIO41 */ ++ "NC", /* GPIO42 */ ++ "NC", /* GPIO43 */ ++ "ETH_CLK", /* GPIO44 */ ++ "PWM1_OUT", /* GPIO45 */ ++ "HDMI_HPD_N", ++ "STATUS_LED", ++ /* Used by SD Card */ ++ "SD_CLK_R", ++ "SD_CMD_R", ++ "SD_DATA0_R", ++ "SD_DATA1_R", ++ "SD_DATA2_R", ++ "SD_DATA3_R"; ++ + spi0_pins: spi0_pins { + brcm,pins = <9 10 11>; + brcm,function = <4>; /* alt0 */ @@ -4337,6 +5528,7 @@ index 000000000000..a7d6427671b4 + audio_pins: audio_pins { + brcm,pins = <40 45>; + brcm,function = <4>; ++ brcm,pull = <0>; + }; +}; + @@ -4385,17 +5577,18 @@ index 000000000000..a7d6427671b4 + pinctrl-0 = <&i2s_pins>; +}; + -+&leds { -+ act_led: led-act { -+ label = "led0"; -+ linux,default-trigger = "mmc0"; -+ gpios = <&gpio 47 0>; -+ }; ++&led_act { ++ gpios = <&gpio 47 GPIO_ACTIVE_HIGH>; ++ default-state = "off"; ++ linux,default-trigger = "mmc0"; ++}; + -+ pwr_led: led-pwr { -+ label = "led1"; ++&leds { ++ led_pwr: led-pwr { ++ label = "PWR"; ++ gpios = <&gpio 35 GPIO_ACTIVE_HIGH>; ++ default-state = "off"; + linux,default-trigger = "input"; -+ gpios = <&gpio 35 0>; + }; +}; + @@ -4403,7 +5596,7 @@ index 000000000000..a7d6427671b4 + hpd-gpios = <&gpio 46 GPIO_ACTIVE_LOW>; +}; + -+&audio { ++&vchiq { + pinctrl-names = "default"; + pinctrl-0 = <&audio_pins>; +}; @@ -4415,29 +5608,41 @@ index 000000000000..a7d6427671b4 +cam0_reg: &cam_dummy_reg { +}; + ++i2c_arm: &i2c1 { ++}; ++ ++i2c_vc: &i2c0 { ++}; ++ ++i2c_csi_dsi0: &i2c0 { ++}; ++ +/ { + __overrides__ { -+ act_led_gpio = <&act_led>,"gpios:4"; -+ act_led_activelow = <&act_led>,"gpios:8"; -+ act_led_trigger = <&act_led>,"linux,default-trigger"; ++ audio = <&chosen>,"bootargs{on='snd_bcm2835.enable_headphones=1 snd_bcm2835.enable_hdmi=1',off='snd_bcm2835.enable_headphones=0 snd_bcm2835.enable_hdmi=0'}"; + -+ pwr_led_gpio = <&pwr_led>,"gpios:4"; -+ pwr_led_activelow = <&pwr_led>,"gpios:8"; -+ pwr_led_trigger = <&pwr_led>,"linux,default-trigger"; ++ act_led_gpio = <&led_act>,"gpios:4"; ++ act_led_activelow = <&led_act>,"gpios:8"; ++ act_led_trigger = <&led_act>,"linux,default-trigger"; ++ ++ pwr_led_gpio = <&led_pwr>,"gpios:4"; ++ pwr_led_activelow = <&led_pwr>,"gpios:8"; ++ pwr_led_trigger = <&led_pwr>,"linux,default-trigger"; + }; +}; -diff --git a/arch/arm/boot/dts/bcm2708-rpi-b-rev1.dts b/arch/arm/boot/dts/bcm2708-rpi-b-rev1.dts +diff --git a/arch/arm/boot/dts/broadcom/bcm2708-rpi-b-rev1.dts b/arch/arm/boot/dts/broadcom/bcm2708-rpi-b-rev1.dts new file mode 100644 -index 000000000000..af1b477f7927 +index 000000000000..9301e345aea2 --- /dev/null -+++ b/arch/arm/boot/dts/bcm2708-rpi-b-rev1.dts -@@ -0,0 +1,134 @@ ++++ b/arch/arm/boot/dts/broadcom/bcm2708-rpi-b-rev1.dts +@@ -0,0 +1,223 @@ +/dts-v1/; + +#include "bcm2708.dtsi" +#include "bcm2708-rpi.dtsi" +#include "bcm283x-rpi-smsc9512.dtsi" +#include "bcm283x-rpi-csi1-2lane.dtsi" ++#include "bcm283x-rpi-led-deprecated.dtsi" + +/ { + compatible = "raspberrypi,model-b", "brcm,bcm2835"; @@ -4445,6 +5650,73 @@ index 000000000000..af1b477f7927 +}; + +&gpio { ++ /* ++ * Taken from Raspberry-Pi-Rev-1.0-Model-AB-Schematics.pdf ++ * RPI00021 sheet 02 ++ * ++ * Legend: ++ * "NC" = not connected (no rail from the SoC) ++ * "FOO" = GPIO line named "FOO" on the schematic ++ * "FOO_N" = GPIO line named "FOO" on schematic, active low ++ */ ++ gpio-line-names = "SDA0", ++ "SCL0", ++ "SDA1", ++ "SCL1", ++ "GPIO_GCLK", ++ "CAM_GPIO1", ++ "LAN_RUN", ++ "SPI_CE1_N", ++ "SPI_CE0_N", ++ "SPI_MISO", ++ "SPI_MOSI", ++ "SPI_SCLK", ++ "NC", /* GPIO12 */ ++ "NC", /* GPIO13 */ ++ /* Serial port */ ++ "TXD0", ++ "RXD0", ++ "STATUS_LED_N", ++ "GPIO17", ++ "GPIO18", ++ "NC", /* GPIO19 */ ++ "NC", /* GPIO20 */ ++ "GPIO21", ++ "GPIO22", ++ "GPIO23", ++ "GPIO24", ++ "GPIO25", ++ "NC", /* GPIO26 */ ++ "CAM_GPIO0", ++ /* Binary number representing build/revision */ ++ "CONFIG0", ++ "CONFIG1", ++ "CONFIG2", ++ "CONFIG3", ++ "NC", /* GPIO32 */ ++ "NC", /* GPIO33 */ ++ "NC", /* GPIO34 */ ++ "NC", /* GPIO35 */ ++ "NC", /* GPIO36 */ ++ "NC", /* GPIO37 */ ++ "NC", /* GPIO38 */ ++ "NC", /* GPIO39 */ ++ "PWM0_OUT", ++ "NC", /* GPIO41 */ ++ "NC", /* GPIO42 */ ++ "NC", /* GPIO43 */ ++ "NC", /* GPIO44 */ ++ "PWM1_OUT", ++ "HDMI_HPD_P", ++ "SD_CARD_DET", ++ /* Used by SD Card */ ++ "SD_CLK_R", ++ "SD_CMD_R", ++ "SD_DATA0_R", ++ "SD_DATA1_R", ++ "SD_DATA2_R", ++ "SD_DATA3_R"; ++ + spi0_pins: spi0_pins { + brcm,pins = <9 10 11>; + brcm,function = <4>; /* alt0 */ @@ -4473,6 +5745,7 @@ index 000000000000..af1b477f7927 + audio_pins: audio_pins { + brcm,pins = <40 45>; + brcm,function = <4>; ++ brcm,pull = <0>; + }; +}; + @@ -4521,6 +5794,10 @@ index 000000000000..af1b477f7927 + i2c0 = &i2c0; + }; + ++ /* Provide an i2c0mux label to avoid undefined symbols in overlays */ ++ i2c0mux: i2c0mux { ++ }; ++ + __overrides__ { + i2c0 = <&i2c0>, "status"; + }; @@ -4535,19 +5812,17 @@ index 000000000000..af1b477f7927 + pinctrl-0 = <&i2s_pins>; +}; + -+&leds { -+ act_led: led-act { -+ label = "led0"; -+ linux,default-trigger = "mmc0"; -+ gpios = <&gpio 16 1>; -+ }; ++&led_act { ++ gpios = <&gpio 16 GPIO_ACTIVE_LOW>; ++ default-state = "off"; ++ linux,default-trigger = "mmc0"; +}; + +&hdmi { + hpd-gpios = <&gpio 46 GPIO_ACTIVE_HIGH>; +}; + -+&audio { ++&vchiq { + pinctrl-names = "default"; + pinctrl-0 = <&audio_pins>; +}; @@ -4559,19 +5834,37 @@ index 000000000000..af1b477f7927 +cam0_reg: &cam_dummy_reg { +}; + ++i2c_arm: &i2c0 { ++}; ++ ++i2c_vc: &i2c1 { ++}; ++ ++i2c_csi_dsi0: &i2c0 { ++}; ++ +/ { + __overrides__ { -+ act_led_gpio = <&act_led>,"gpios:4"; -+ act_led_activelow = <&act_led>,"gpios:8"; -+ act_led_trigger = <&act_led>,"linux,default-trigger"; ++ audio = <&chosen>,"bootargs{on='snd_bcm2835.enable_headphones=1 snd_bcm2835.enable_hdmi=1',off='snd_bcm2835.enable_headphones=0 snd_bcm2835.enable_hdmi=0'}"; ++ ++ act_led_gpio = <&led_act>,"gpios:4"; ++ act_led_activelow = <&led_act>,"gpios:8"; ++ act_led_trigger = <&led_act>,"linux,default-trigger"; ++ ++ i2c = <&i2c0>,"status"; ++ i2c_arm = <&i2c0>,"status"; ++ i2c_vc = <&i2c1>,"status"; ++ i2c_baudrate = <&i2c0>,"clock-frequency:0"; ++ i2c_arm_baudrate = <&i2c0>,"clock-frequency:0"; ++ i2c_vc_baudrate = <&i2c1>,"clock-frequency:0"; + }; +}; -diff --git a/arch/arm/boot/dts/bcm2708-rpi-b.dts b/arch/arm/boot/dts/bcm2708-rpi-b.dts +diff --git a/arch/arm/boot/dts/broadcom/bcm2708-rpi-b.dts b/arch/arm/boot/dts/broadcom/bcm2708-rpi-b.dts new file mode 100644 -index 000000000000..a5316257a18b +index 000000000000..b8459fd0f497 --- /dev/null -+++ b/arch/arm/boot/dts/bcm2708-rpi-b.dts -@@ -0,0 +1,121 @@ ++++ b/arch/arm/boot/dts/broadcom/bcm2708-rpi-b.dts +@@ -0,0 +1,198 @@ +/dts-v1/; + +#include "bcm2708.dtsi" @@ -4579,6 +5872,7 @@ index 000000000000..a5316257a18b +#include "bcm283x-rpi-smsc9512.dtsi" +#include "bcm283x-rpi-csi1-2lane.dtsi" +#include "bcm283x-rpi-i2c0mux_0_28.dtsi" ++#include "bcm283x-rpi-led-deprecated.dtsi" + +/ { + compatible = "raspberrypi,model-b", "brcm,bcm2835"; @@ -4586,6 +5880,72 @@ index 000000000000..a5316257a18b +}; + +&gpio { ++ /* ++ * Taken from Raspberry-Pi-Rev-2.0-Model-AB-Schematics.pdf ++ * RPI00022 sheet 02 ++ * ++ * Legend: ++ * "NC" = not connected (no rail from the SoC) ++ * "FOO" = GPIO line named "FOO" on the schematic ++ * "FOO_N" = GPIO line named "FOO" on schematic, active low ++ */ ++ gpio-line-names = "SDA0", ++ "SCL0", ++ "SDA1", ++ "SCL1", ++ "GPIO_GCLK", ++ "CAM_GPIO1", ++ "LAN_RUN", ++ "SPI_CE1_N", ++ "SPI_CE0_N", ++ "SPI_MISO", ++ "SPI_MOSI", ++ "SPI_SCLK", ++ "NC", /* GPIO12 */ ++ "NC", /* GPIO13 */ ++ /* Serial port */ ++ "TXD0", ++ "RXD0", ++ "STATUS_LED_N", ++ "GPIO17", ++ "GPIO18", ++ "NC", /* GPIO19 */ ++ "NC", /* GPIO20 */ ++ "CAM_GPIO0", ++ "GPIO22", ++ "GPIO23", ++ "GPIO24", ++ "GPIO25", ++ "NC", /* GPIO26 */ ++ "GPIO27", ++ "GPIO28", ++ "GPIO29", ++ "GPIO30", ++ "GPIO31", ++ "NC", /* GPIO32 */ ++ "NC", /* GPIO33 */ ++ "NC", /* GPIO34 */ ++ "NC", /* GPIO35 */ ++ "NC", /* GPIO36 */ ++ "NC", /* GPIO37 */ ++ "NC", /* GPIO38 */ ++ "NC", /* GPIO39 */ ++ "PWM0_OUT", ++ "NC", /* GPIO41 */ ++ "NC", /* GPIO42 */ ++ "NC", /* GPIO43 */ ++ "NC", /* GPIO44 */ ++ "PWM1_OUT", ++ "HDMI_HPD_P", ++ "SD_CARD_DET", ++ /* Used by SD Card */ ++ "SD_CLK_R", ++ "SD_CMD_R", ++ "SD_DATA0_R", ++ "SD_DATA1_R", ++ "SD_DATA2_R", ++ "SD_DATA3_R"; ++ + spi0_pins: spi0_pins { + brcm,pins = <9 10 11>; + brcm,function = <4>; /* alt0 */ @@ -4614,6 +5974,7 @@ index 000000000000..a5316257a18b + audio_pins: audio_pins { + brcm,pins = <40 45>; + brcm,function = <4>; ++ brcm,pull = <0>; + }; +}; + @@ -4662,19 +6023,17 @@ index 000000000000..a5316257a18b + pinctrl-0 = <&i2s_pins>; +}; + -+&leds { -+ act_led: led-act { -+ label = "led0"; -+ linux,default-trigger = "mmc0"; -+ gpios = <&gpio 16 1>; -+ }; ++&led_act { ++ gpios = <&gpio 16 GPIO_ACTIVE_LOW>; ++ default-state = "off"; ++ linux,default-trigger = "mmc0"; +}; + +&hdmi { + hpd-gpios = <&gpio 46 GPIO_ACTIVE_HIGH>; +}; + -+&audio { ++&vchiq { + pinctrl-names = "default"; + pinctrl-0 = <&audio_pins>; +}; @@ -4686,19 +6045,30 @@ index 000000000000..a5316257a18b +cam0_reg: &cam_dummy_reg { +}; + ++i2c_arm: &i2c1 { ++}; ++ ++i2c_vc: &i2c0 { ++}; ++ ++i2c_csi_dsi0: &i2c0 { ++}; ++ +/ { + __overrides__ { -+ act_led_gpio = <&act_led>,"gpios:4"; -+ act_led_activelow = <&act_led>,"gpios:8"; -+ act_led_trigger = <&act_led>,"linux,default-trigger"; ++ audio = <&chosen>,"bootargs{on='snd_bcm2835.enable_headphones=1 snd_bcm2835.enable_hdmi=1',off='snd_bcm2835.enable_headphones=0 snd_bcm2835.enable_hdmi=0'}"; ++ ++ act_led_gpio = <&led_act>,"gpios:4"; ++ act_led_activelow = <&led_act>,"gpios:8"; ++ act_led_trigger = <&led_act>,"linux,default-trigger"; + }; +}; -diff --git a/arch/arm/boot/dts/bcm2708-rpi-bt.dtsi b/arch/arm/boot/dts/bcm2708-rpi-bt.dtsi +diff --git a/arch/arm/boot/dts/broadcom/bcm2708-rpi-bt.dtsi b/arch/arm/boot/dts/broadcom/bcm2708-rpi-bt.dtsi new file mode 100644 -index 000000000000..a18f80af97d3 +index 000000000000..98555528adae --- /dev/null -+++ b/arch/arm/boot/dts/bcm2708-rpi-bt.dtsi -@@ -0,0 +1,26 @@ ++++ b/arch/arm/boot/dts/broadcom/bcm2708-rpi-bt.dtsi +@@ -0,0 +1,38 @@ +// SPDX-License-Identifier: GPL-2.0 + +&uart0 { @@ -4706,31 +6076,43 @@ index 000000000000..a18f80af97d3 + compatible = "brcm,bcm43438-bt"; + max-speed = <3000000>; + shutdown-gpios = <&gpio 45 GPIO_ACTIVE_HIGH>; -+ status = "disabled"; ++ local-bd-address = [ 00 00 00 00 00 00 ]; ++ fallback-bd-address; // Don't override a valid address ++ status = "okay"; + }; +}; + +&uart1 { + minibt: bluetooth { + compatible = "brcm,bcm43438-bt"; -+ max-speed = <460800>; ++ max-speed = <230400>; + shutdown-gpios = <&gpio 45 GPIO_ACTIVE_HIGH>; ++ local-bd-address = [ 00 00 00 00 00 00 ]; ++ fallback-bd-address; // Don't override a valid address + status = "disabled"; + }; +}; + +/ { ++ aliases { ++ bluetooth = &bt; ++ }; ++ + __overrides__ { ++ bdaddr = <&bt>,"local-bd-address[", ++ <&bt>,"fallback-bd-address?=0", ++ <&minibt>,"local-bd-address[", ++ <&minibt>,"fallback-bd-address?=0"; + krnbt = <&bt>,"status"; -+ krnbt_baudrate = <&bt>,"max-speed:0"; ++ krnbt_baudrate = <&bt>,"max-speed:0", <&minibt>,"max-speed:0"; + }; +}; -diff --git a/arch/arm/boot/dts/bcm2708-rpi-cm.dts b/arch/arm/boot/dts/bcm2708-rpi-cm.dts +diff --git a/arch/arm/boot/dts/broadcom/bcm2708-rpi-cm.dts b/arch/arm/boot/dts/broadcom/bcm2708-rpi-cm.dts new file mode 100644 -index 000000000000..863bd207e323 +index 000000000000..fde85c8c7dca --- /dev/null -+++ b/arch/arm/boot/dts/bcm2708-rpi-cm.dts -@@ -0,0 +1,106 @@ ++++ b/arch/arm/boot/dts/broadcom/bcm2708-rpi-cm.dts +@@ -0,0 +1,174 @@ +/dts-v1/; + +#include "bcm2708-rpi-cm.dtsi" @@ -4744,12 +6126,15 @@ index 000000000000..863bd207e323 +}; + +&cam1_reg { -+ gpio = <&gpio 2 GPIO_ACTIVE_HIGH>; ++ gpio = <&gpio 3 GPIO_ACTIVE_HIGH>; + status = "disabled"; +}; + +cam0_reg: &cam0_regulator { -+ gpio = <&gpio 30 GPIO_ACTIVE_HIGH>; ++ gpio = <&gpio 31 GPIO_ACTIVE_HIGH>; ++}; ++ ++i2c_csi_dsi0: &i2c0 { +}; + +&uart0 { @@ -4757,6 +6142,71 @@ index 000000000000..863bd207e323 +}; + +&gpio { ++ /* ++ * This is based on the official GPU firmware DT blob. ++ * ++ * Legend: ++ * "NC" = not connected (no rail from the SoC) ++ * "FOO" = GPIO line named "FOO" on the schematic ++ * "FOO_N" = GPIO line named "FOO" on schematic, active low ++ */ ++ gpio-line-names = "GPIO0", ++ "GPIO1", ++ "GPIO2", ++ "GPIO3", ++ "GPIO4", ++ "GPIO5", ++ "GPIO6", ++ "GPIO7", ++ "GPIO8", ++ "GPIO9", ++ "GPIO10", ++ "GPIO11", ++ "GPIO12", ++ "GPIO13", ++ "GPIO14", ++ "GPIO15", ++ "GPIO16", ++ "GPIO17", ++ "GPIO18", ++ "GPIO19", ++ "GPIO20", ++ "GPIO21", ++ "GPIO22", ++ "GPIO23", ++ "GPIO24", ++ "GPIO25", ++ "GPIO26", ++ "GPIO27", ++ "GPIO28", ++ "GPIO29", ++ "GPIO30", ++ "GPIO31", ++ "GPIO32", ++ "GPIO33", ++ "GPIO34", ++ "GPIO35", ++ "GPIO36", ++ "GPIO37", ++ "GPIO38", ++ "GPIO39", ++ "GPIO40", ++ "GPIO41", ++ "GPIO42", ++ "GPIO43", ++ "GPIO44", ++ "GPIO45", ++ "HDMI_HPD_N", ++ /* Also used as ACT LED */ ++ "EMMC_EN_N", ++ /* Used by eMMC */ ++ "SD_CLK_R", ++ "SD_CMD_R", ++ "SD_DATA0_R", ++ "SD_DATA1_R", ++ "SD_DATA2_R", ++ "SD_DATA3_R"; ++ + spi0_pins: spi0_pins { + brcm,pins = <9 10 11>; + brcm,function = <4>; /* alt0 */ @@ -4829,7 +6279,7 @@ index 000000000000..863bd207e323 + pinctrl-0 = <&i2s_pins>; +}; + -+&audio { ++&vchiq { + pinctrl-names = "default"; + pinctrl-0 = <&audio_pins>; +}; @@ -4837,40 +6287,45 @@ index 000000000000..863bd207e323 +&hdmi { + hpd-gpios = <&gpio 46 GPIO_ACTIVE_HIGH>; +}; -diff --git a/arch/arm/boot/dts/bcm2708-rpi-cm.dtsi b/arch/arm/boot/dts/bcm2708-rpi-cm.dtsi +diff --git a/arch/arm/boot/dts/broadcom/bcm2708-rpi-cm.dtsi b/arch/arm/boot/dts/broadcom/bcm2708-rpi-cm.dtsi new file mode 100644 -index 000000000000..dd59f884d796 +index 000000000000..10fd4475dd5e --- /dev/null -+++ b/arch/arm/boot/dts/bcm2708-rpi-cm.dtsi -@@ -0,0 +1,22 @@ ++++ b/arch/arm/boot/dts/broadcom/bcm2708-rpi-cm.dtsi +@@ -0,0 +1,27 @@ +#include "bcm2708.dtsi" +#include "bcm2708-rpi.dtsi" ++#include "bcm283x-rpi-led-deprecated.dtsi" + -+&leds { -+ act_led: led-act { -+ label = "led0"; -+ linux,default-trigger = "mmc0"; -+ gpios = <&gpio 47 0>; -+ }; ++&led_act { ++ gpios = <&gpio 47 GPIO_ACTIVE_HIGH>; ++ default-state = "off"; ++ linux,default-trigger = "mmc0"; ++}; ++ ++i2c_arm: &i2c1 { ++}; ++ ++i2c_vc: &i2c0 { +}; + +/ { + __overrides__ { -+ act_led_gpio = <&act_led>,"gpios:4"; -+ act_led_activelow = <&act_led>,"gpios:8"; -+ act_led_trigger = <&act_led>,"linux,default-trigger"; ++ act_led_gpio = <&led_act>,"gpios:4"; ++ act_led_activelow = <&led_act>,"gpios:8"; ++ act_led_trigger = <&led_act>,"linux,default-trigger"; + cam0_reg = <&cam0_reg>,"status"; -+ cam0_reg_gpio = <&cam0_reg>,"gpios:4"; ++ cam0_reg_gpio = <&cam0_reg>,"gpio:4"; + cam1_reg = <&cam1_reg>,"status"; -+ cam1_reg_gpio = <&cam1_reg>,"gpios:4"; ++ cam1_reg_gpio = <&cam1_reg>,"gpio:4"; + }; +}; -diff --git a/arch/arm/boot/dts/bcm2708-rpi-zero-w.dts b/arch/arm/boot/dts/bcm2708-rpi-zero-w.dts +diff --git a/arch/arm/boot/dts/broadcom/bcm2708-rpi-zero-w.dts b/arch/arm/boot/dts/broadcom/bcm2708-rpi-zero-w.dts new file mode 100644 -index 000000000000..e4c6c352f3aa +index 000000000000..011d0fa4c9c0 --- /dev/null -+++ b/arch/arm/boot/dts/bcm2708-rpi-zero-w.dts -@@ -0,0 +1,178 @@ ++++ b/arch/arm/boot/dts/broadcom/bcm2708-rpi-zero-w.dts +@@ -0,0 +1,254 @@ +/dts-v1/; + +#include "bcm2708.dtsi" @@ -4878,13 +6333,14 @@ index 000000000000..e4c6c352f3aa +#include "bcm283x-rpi-csi1-2lane.dtsi" +#include "bcm283x-rpi-i2c0mux_0_28.dtsi" +#include "bcm2708-rpi-bt.dtsi" ++#include "bcm283x-rpi-led-deprecated.dtsi" + +/ { + compatible = "raspberrypi,model-zero-w", "brcm,bcm2835"; + model = "Raspberry Pi Zero W"; + + chosen { -+ bootargs = "coherent_pool=1M 8250.nr_uarts=1 snd_bcm2835.enable_compat_alsa=0 snd_bcm2835.enable_hdmi=1"; ++ bootargs = "coherent_pool=1M 8250.nr_uarts=1 snd_bcm2835.enable_headphones=0"; + }; + + aliases { @@ -4895,6 +6351,72 @@ index 000000000000..e4c6c352f3aa +}; + +&gpio { ++ /* ++ * This is based on the official GPU firmware DT blob. ++ * ++ * Legend: ++ * "NC" = not connected (no rail from the SoC) ++ * "FOO" = GPIO line named "FOO" on the schematic ++ * "FOO_N" = GPIO line named "FOO" on schematic, active low ++ */ ++ gpio-line-names = "ID_SDA", ++ "ID_SCL", ++ "GPIO2", ++ "GPIO3", ++ "GPIO4", ++ "GPIO5", ++ "GPIO6", ++ "GPIO7", ++ "GPIO8", ++ "GPIO9", ++ "GPIO10", ++ "GPIO11", ++ "GPIO12", ++ "GPIO13", ++ "GPIO14", ++ "GPIO15", ++ "GPIO16", ++ "GPIO17", ++ "GPIO18", ++ "GPIO19", ++ "GPIO20", ++ "GPIO21", ++ "GPIO22", ++ "GPIO23", ++ "GPIO24", ++ "GPIO25", ++ "GPIO26", ++ "GPIO27", ++ "SDA0", ++ "SCL0", ++ /* Used by BT module */ ++ "CTS0", ++ "RTS0", ++ "TXD0", ++ "RXD0", ++ /* Used by Wifi */ ++ "SD1_CLK", ++ "SD1_CMD", ++ "SD1_DATA0", ++ "SD1_DATA1", ++ "SD1_DATA2", ++ "SD1_DATA3", ++ "CAM_GPIO1", /* GPIO40 */ ++ "WL_ON", /* GPIO41 */ ++ "NC", /* GPIO42 */ ++ "WIFI_CLK", /* GPIO43 */ ++ "CAM_GPIO0", /* GPIO44 */ ++ "BT_ON", /* GPIO45 */ ++ "HDMI_HPD_N", ++ "STATUS_LED_N", ++ /* Used by SD Card */ ++ "SD_CLK_R", ++ "SD_CMD_R", ++ "SD_DATA0_R", ++ "SD_DATA1_R", ++ "SD_DATA2_R", ++ "SD_DATA3_R"; ++ + spi0_pins: spi0_pins { + brcm,pins = <9 10 11>; + brcm,function = <4>; /* alt0 */ @@ -4944,6 +6466,12 @@ index 000000000000..e4c6c352f3aa + brcm,pull; + }; + ++ uart1_bt_pins: uart1_bt_pins { ++ brcm,pins = <32 33 30 31>; ++ brcm,function = ; /* alt5=UART1 */ ++ brcm,pull = <0 2 2 0>; ++ }; ++ + audio_pins: audio_pins { + brcm,pins = <>; + brcm,function = <>; @@ -5017,22 +6545,19 @@ index 000000000000..e4c6c352f3aa + pinctrl-0 = <&i2s_pins>; +}; + -+&leds { -+ act_led: led-act { -+ label = "led0"; -+ linux,default-trigger = "actpwr"; -+ gpios = <&gpio 47 GPIO_ACTIVE_LOW>; -+ }; ++&led_act { ++ gpios = <&gpio 47 GPIO_ACTIVE_LOW>; ++ default-state = "off"; ++ linux,default-trigger = "actpwr"; +}; + +&hdmi { + hpd-gpios = <&gpio 46 GPIO_ACTIVE_LOW>; +}; + -+&audio { ++&vchiq { + pinctrl-names = "default"; + pinctrl-0 = <&audio_pins>; -+ brcm,disable-headphones = <1>; +}; + +&cam1_reg { @@ -5042,36 +6567,103 @@ index 000000000000..e4c6c352f3aa +cam0_reg: &cam_dummy_reg { +}; + ++i2c_arm: &i2c1 {}; ++i2c_vc: &i2c0 {}; ++i2c_csi_dsi0: &i2c0 {}; ++ +/ { + __overrides__ { -+ act_led_gpio = <&act_led>,"gpios:4"; -+ act_led_activelow = <&act_led>,"gpios:8"; -+ act_led_trigger = <&act_led>,"linux,default-trigger"; ++ audio = <&chosen>,"bootargs{on='snd_bcm2835.enable_hdmi=1',off='snd_bcm2835.enable_hdmi=0'}"; ++ ++ act_led_gpio = <&led_act>,"gpios:4"; ++ act_led_activelow = <&led_act>,"gpios:8"; ++ act_led_trigger = <&led_act>,"linux,default-trigger"; + }; +}; -diff --git a/arch/arm/boot/dts/bcm2708-rpi-zero.dts b/arch/arm/boot/dts/bcm2708-rpi-zero.dts +diff --git a/arch/arm/boot/dts/broadcom/bcm2708-rpi-zero.dts b/arch/arm/boot/dts/broadcom/bcm2708-rpi-zero.dts new file mode 100644 -index 000000000000..19dae0d682ed +index 000000000000..1721be8dbe20 --- /dev/null -+++ b/arch/arm/boot/dts/bcm2708-rpi-zero.dts -@@ -0,0 +1,125 @@ ++++ b/arch/arm/boot/dts/broadcom/bcm2708-rpi-zero.dts +@@ -0,0 +1,189 @@ +/dts-v1/; + +#include "bcm2708.dtsi" +#include "bcm2708-rpi.dtsi" +#include "bcm283x-rpi-csi1-2lane.dtsi" +#include "bcm283x-rpi-i2c0mux_0_28.dtsi" ++#include "bcm283x-rpi-led-deprecated.dtsi" + +/ { + compatible = "raspberrypi,model-zero", "brcm,bcm2835"; + model = "Raspberry Pi Zero"; -+ -+ chosen { -+ bootargs = "coherent_pool=1M snd_bcm2835.enable_compat_alsa=0 snd_bcm2835.enable_hdmi=1"; -+ }; +}; + +&gpio { ++ /* ++ * This is based on the official GPU firmware DT blob. ++ * ++ * Legend: ++ * "NC" = not connected (no rail from the SoC) ++ * "FOO" = GPIO line named "FOO" on the schematic ++ * "FOO_N" = GPIO line named "FOO" on schematic, active low ++ */ ++ gpio-line-names = "ID_SDA", ++ "ID_SCL", ++ "GPIO2", ++ "GPIO3", ++ "GPIO4", ++ "GPIO5", ++ "GPIO6", ++ "GPIO7", ++ "GPIO8", ++ "GPIO9", ++ "GPIO10", ++ "GPIO11", ++ "GPIO12", ++ "GPIO13", ++ "GPIO14", ++ "GPIO15", ++ "GPIO16", ++ "GPIO17", ++ "GPIO18", ++ "GPIO19", ++ "GPIO20", ++ "GPIO21", ++ "GPIO22", ++ "GPIO23", ++ "GPIO24", ++ "GPIO25", ++ "GPIO26", ++ "GPIO27", ++ "SDA0", ++ "SCL0", ++ "NC", /* GPIO30 */ ++ "NC", /* GPIO31 */ ++ "CAM_GPIO1", /* GPIO32 */ ++ "NC", /* GPIO33 */ ++ "NC", /* GPIO34 */ ++ "NC", /* GPIO35 */ ++ "NC", /* GPIO36 */ ++ "NC", /* GPIO37 */ ++ "NC", /* GPIO38 */ ++ "NC", /* GPIO39 */ ++ "NC", /* GPIO40 */ ++ "CAM_GPIO0", /* GPIO41 */ ++ "NC", /* GPIO42 */ ++ "NC", /* GPIO43 */ ++ "NC", /* GPIO44 */ ++ "NC", /* GPIO45 */ ++ "HDMI_HPD_N", ++ "STATUS_LED_N", ++ /* Used by SD Card */ ++ "SD_CLK_R", ++ "SD_CMD_R", ++ "SD_DATA0_R", ++ "SD_DATA1_R", ++ "SD_DATA2_R", ++ "SD_DATA3_R"; ++ + spi0_pins: spi0_pins { + brcm,pins = <9 10 11>; + brcm,function = <4>; /* alt0 */ @@ -5148,22 +6740,19 @@ index 000000000000..19dae0d682ed + pinctrl-0 = <&i2s_pins>; +}; + -+&leds { -+ act_led: led-act { -+ label = "led0"; -+ linux,default-trigger = "actpwr"; -+ gpios = <&gpio 47 GPIO_ACTIVE_LOW>; -+ }; ++&led_act { ++ gpios = <&gpio 47 GPIO_ACTIVE_LOW>; ++ default-state = "off"; ++ linux,default-trigger = "actpwr"; +}; + +&hdmi { + hpd-gpios = <&gpio 46 GPIO_ACTIVE_LOW>; +}; + -+&audio { ++&vchiq { + pinctrl-names = "default"; + pinctrl-0 = <&audio_pins>; -+ brcm,disable-headphones = <1>; +}; + +&cam1_reg { @@ -5173,22 +6762,30 @@ index 000000000000..19dae0d682ed +cam0_reg: &cam_dummy_reg { +}; + ++i2c_arm: &i2c1 {}; ++i2c_vc: &i2c0 {}; ++i2c_csi_dsi0: &i2c0 {}; ++ +/ { + __overrides__ { -+ act_led_gpio = <&act_led>,"gpios:4"; -+ act_led_activelow = <&act_led>,"gpios:8"; -+ act_led_trigger = <&act_led>,"linux,default-trigger"; ++ audio = <&chosen>,"bootargs{on='snd_bcm2835.enable_hdmi=1',off='snd_bcm2835.enable_hdmi=0'}"; ++ ++ act_led_gpio = <&led_act>,"gpios:4"; ++ act_led_activelow = <&led_act>,"gpios:8"; ++ act_led_trigger = <&led_act>,"linux,default-trigger"; + }; +}; -diff --git a/arch/arm/boot/dts/bcm2708-rpi.dtsi b/arch/arm/boot/dts/bcm2708-rpi.dtsi +diff --git a/arch/arm/boot/dts/broadcom/bcm2708-rpi.dtsi b/arch/arm/boot/dts/broadcom/bcm2708-rpi.dtsi new file mode 100644 -index 000000000000..e2458b15d64a +index 000000000000..f4949a07272b --- /dev/null -+++ b/arch/arm/boot/dts/bcm2708-rpi.dtsi -@@ -0,0 +1,36 @@ ++++ b/arch/arm/boot/dts/broadcom/bcm2708-rpi.dtsi +@@ -0,0 +1,57 @@ +/* Downstream modifications common to bcm2835, bcm2836, bcm2837 */ + ++#define i2c0 i2c0mux +#include "bcm2835-rpi.dtsi" ++#undef i2c0 +#include "bcm270x-rpi.dtsi" + +/ { @@ -5202,12 +6799,31 @@ index 000000000000..e2458b15d64a + }; + + __overrides__ { ++ hdmi = <&hdmi>,"status"; + i2c2_iknowwhatimdoing = <&i2c2>,"status"; + i2c2_baudrate = <&i2c2>,"clock-frequency:0"; ++ nvmem_cust_rw = <&nvmem_cust>,"rw?"; ++ sd = <&sdhost>,"status"; + sd_poll_once = <&sdhost>,"non-removable?"; + }; +}; + ++&soc { ++ nvmem_otp: nvmem_otp { ++ compatible = "raspberrypi,rpi-otp"; ++ firmware = <&firmware>; ++ reg = <0 192>; ++ status = "okay"; ++ }; ++ ++ nvmem_cust: nvmem_cust { ++ compatible = "raspberrypi,rpi-otp"; ++ firmware = <&firmware>; ++ reg = <1 8>; ++ status = "okay"; ++ }; ++}; ++ +&sdhost { + pinctrl-names = "default"; + pinctrl-0 = <&sdhost_gpio48>; @@ -5222,13 +6838,15 @@ index 000000000000..e2458b15d64a +&i2c2 { + status = "disabled"; +}; -diff --git a/arch/arm/boot/dts/bcm2708.dtsi b/arch/arm/boot/dts/bcm2708.dtsi +diff --git a/arch/arm/boot/dts/broadcom/bcm2708.dtsi b/arch/arm/boot/dts/broadcom/bcm2708.dtsi new file mode 100644 -index 000000000000..36ec4989403f +index 000000000000..fdc7f2423bbe --- /dev/null -+++ b/arch/arm/boot/dts/bcm2708.dtsi -@@ -0,0 +1,12 @@ ++++ b/arch/arm/boot/dts/broadcom/bcm2708.dtsi +@@ -0,0 +1,19 @@ ++#define i2c0 i2c0if +#include "bcm2835.dtsi" ++#undef i2c0 +#include "bcm270x.dtsi" + +/ { @@ -5237,15 +6855,20 @@ index 000000000000..36ec4989403f + }; +}; + ++&soc { ++ dma-ranges = <0x80000000 0x00000000 0x20000000>, ++ <0x7e000000 0x20000000 0x02000000>; ++}; ++ +&vc4 { + status = "disabled"; +}; -diff --git a/arch/arm/boot/dts/bcm2709-rpi-2-b.dts b/arch/arm/boot/dts/bcm2709-rpi-2-b.dts +diff --git a/arch/arm/boot/dts/broadcom/bcm2709-rpi-2-b.dts b/arch/arm/boot/dts/broadcom/bcm2709-rpi-2-b.dts new file mode 100644 -index 000000000000..4c80d15981fe +index 000000000000..7796e545da43 --- /dev/null -+++ b/arch/arm/boot/dts/bcm2709-rpi-2-b.dts -@@ -0,0 +1,131 @@ ++++ b/arch/arm/boot/dts/broadcom/bcm2709-rpi-2-b.dts +@@ -0,0 +1,204 @@ +/dts-v1/; + +#include "bcm2709.dtsi" @@ -5253,6 +6876,7 @@ index 000000000000..4c80d15981fe +#include "bcm283x-rpi-smsc9514.dtsi" +#include "bcm283x-rpi-csi1-2lane.dtsi" +#include "bcm283x-rpi-i2c0mux_0_28.dtsi" ++#include "bcm283x-rpi-led-deprecated.dtsi" + +/ { + compatible = "raspberrypi,2-model-b", "brcm,bcm2836"; @@ -5260,6 +6884,71 @@ index 000000000000..4c80d15981fe +}; + +&gpio { ++ /* ++ * Taken from rpi_SCH_2b_1p2_reduced.pdf and ++ * the official GPU firmware DT blob. ++ * ++ * Legend: ++ * "NC" = not connected (no rail from the SoC) ++ * "FOO" = GPIO line named "FOO" on the schematic ++ * "FOO_N" = GPIO line named "FOO" on schematic, active low ++ */ ++ gpio-line-names = "ID_SDA", ++ "ID_SCL", ++ "GPIO2", ++ "GPIO3", ++ "GPIO4", ++ "GPIO5", ++ "GPIO6", ++ "GPIO7", ++ "GPIO8", ++ "GPIO9", ++ "GPIO10", ++ "GPIO11", ++ "GPIO12", ++ "GPIO13", ++ "GPIO14", ++ "GPIO15", ++ "GPIO16", ++ "GPIO17", ++ "GPIO18", ++ "GPIO19", ++ "GPIO20", ++ "GPIO21", ++ "GPIO22", ++ "GPIO23", ++ "GPIO24", ++ "GPIO25", ++ "GPIO26", ++ "GPIO27", ++ "SDA0", ++ "SCL0", ++ "NC", /* GPIO30 */ ++ "LAN_RUN", ++ "CAM_GPIO1", ++ "NC", /* GPIO33 */ ++ "NC", /* GPIO34 */ ++ "PWR_LOW_N", ++ "NC", /* GPIO36 */ ++ "NC", /* GPIO37 */ ++ "USB_LIMIT", ++ "NC", /* GPIO39 */ ++ "PWM0_OUT", ++ "CAM_GPIO0", ++ "SMPS_SCL", ++ "SMPS_SDA", ++ "ETH_CLK", ++ "PWM1_OUT", ++ "HDMI_HPD_N", ++ "STATUS_LED", ++ /* Used by SD Card */ ++ "SD_CLK_R", ++ "SD_CMD_R", ++ "SD_DATA0_R", ++ "SD_DATA1_R", ++ "SD_DATA2_R", ++ "SD_DATA3_R"; ++ + spi0_pins: spi0_pins { + brcm,pins = <9 10 11>; + brcm,function = <4>; /* alt0 */ @@ -5288,6 +6977,7 @@ index 000000000000..4c80d15981fe + audio_pins: audio_pins { + brcm,pins = <40 45>; + brcm,function = <4>; ++ brcm,pull = <0>; + }; +}; + @@ -5336,17 +7026,18 @@ index 000000000000..4c80d15981fe + pinctrl-0 = <&i2s_pins>; +}; + -+&leds { -+ act_led: led-act { -+ label = "led0"; -+ linux,default-trigger = "mmc0"; -+ gpios = <&gpio 47 0>; -+ }; ++&led_act { ++ gpios = <&gpio 47 GPIO_ACTIVE_HIGH>; ++ default-state = "off"; ++ linux,default-trigger = "mmc0"; ++}; + -+ pwr_led: led-pwr { -+ label = "led1"; ++&leds { ++ led_pwr: led-pwr { ++ label = "PWR"; ++ gpios = <&gpio 35 GPIO_ACTIVE_HIGH>; ++ default-state = "off"; + linux,default-trigger = "input"; -+ gpios = <&gpio 35 0>; + }; +}; + @@ -5354,7 +7045,7 @@ index 000000000000..4c80d15981fe + hpd-gpios = <&gpio 46 GPIO_ACTIVE_LOW>; +}; + -+&audio { ++&vchiq { + pinctrl-names = "default"; + pinctrl-0 = <&audio_pins>; +}; @@ -5366,35 +7057,274 @@ index 000000000000..4c80d15981fe +cam0_reg: &cam_dummy_reg { +}; + ++i2c_csi_dsi0: &i2c0 { ++}; ++ +/ { + __overrides__ { -+ act_led_gpio = <&act_led>,"gpios:4"; -+ act_led_activelow = <&act_led>,"gpios:8"; -+ act_led_trigger = <&act_led>,"linux,default-trigger"; ++ audio = <&chosen>,"bootargs{on='snd_bcm2835.enable_headphones=1 snd_bcm2835.enable_hdmi=1',off='snd_bcm2835.enable_headphones=0 snd_bcm2835.enable_hdmi=0'}"; + -+ pwr_led_gpio = <&pwr_led>,"gpios:4"; -+ pwr_led_activelow = <&pwr_led>,"gpios:8"; -+ pwr_led_trigger = <&pwr_led>,"linux,default-trigger"; ++ act_led_gpio = <&led_act>,"gpios:4"; ++ act_led_activelow = <&led_act>,"gpios:8"; ++ act_led_trigger = <&led_act>,"linux,default-trigger"; ++ ++ pwr_led_gpio = <&led_pwr>,"gpios:4"; ++ pwr_led_activelow = <&led_pwr>,"gpios:8"; ++ pwr_led_trigger = <&led_pwr>,"linux,default-trigger"; + }; +}; -diff --git a/arch/arm/boot/dts/bcm2709-rpi.dtsi b/arch/arm/boot/dts/bcm2709-rpi.dtsi +diff --git a/arch/arm/boot/dts/broadcom/bcm2709-rpi-cm2.dts b/arch/arm/boot/dts/broadcom/bcm2709-rpi-cm2.dts new file mode 100644 -index 000000000000..babfa41cd9f7 +index 000000000000..396771880798 --- /dev/null -+++ b/arch/arm/boot/dts/bcm2709-rpi.dtsi -@@ -0,0 +1,5 @@ ++++ b/arch/arm/boot/dts/broadcom/bcm2709-rpi-cm2.dts +@@ -0,0 +1,223 @@ ++/dts-v1/; ++ ++#include "bcm2709.dtsi" ++#include "bcm2709-rpi.dtsi" ++#include "bcm283x-rpi-csi0-2lane.dtsi" ++#include "bcm283x-rpi-csi1-4lane.dtsi" ++#include "bcm283x-rpi-i2c0mux_0_28.dtsi" ++#include "bcm283x-rpi-led-deprecated.dtsi" ++ ++/ { ++ compatible = "raspberrypi,2-compute-module", "brcm,bcm2836"; ++ model = "Raspberry Pi Compute Module 2"; ++}; ++ ++&cam1_reg { ++ gpio = <&gpio 2 GPIO_ACTIVE_HIGH>; ++ status = "disabled"; ++}; ++ ++cam0_reg: &cam0_regulator { ++ gpio = <&gpio 30 GPIO_ACTIVE_HIGH>; ++}; ++ ++i2c_csi_dsi0: &i2c0 { ++}; ++ ++&uart0 { ++ status = "okay"; ++}; ++ ++&gpio { ++ /* ++ * This is based on the official GPU firmware DT blob. ++ * ++ * Legend: ++ * "NC" = not connected (no rail from the SoC) ++ * "FOO" = GPIO line named "FOO" on the schematic ++ * "FOO_N" = GPIO line named "FOO" on schematic, active low ++ */ ++ gpio-line-names = "GPIO0", ++ "GPIO1", ++ "GPIO2", ++ "GPIO3", ++ "GPIO4", ++ "GPIO5", ++ "GPIO6", ++ "GPIO7", ++ "GPIO8", ++ "GPIO9", ++ "GPIO10", ++ "GPIO11", ++ "GPIO12", ++ "GPIO13", ++ "GPIO14", ++ "GPIO15", ++ "GPIO16", ++ "GPIO17", ++ "GPIO18", ++ "GPIO19", ++ "GPIO20", ++ "GPIO21", ++ "GPIO22", ++ "GPIO23", ++ "GPIO24", ++ "GPIO25", ++ "GPIO26", ++ "GPIO27", ++ "GPIO28", ++ "GPIO29", ++ "GPIO30", ++ "GPIO31", ++ "GPIO32", ++ "GPIO33", ++ "GPIO34", ++ "GPIO35", ++ "GPIO36", ++ "GPIO37", ++ "GPIO38", ++ "GPIO39", ++ "GPIO40", ++ "GPIO41", ++ "GPIO42", ++ "GPIO43", ++ "GPIO44", ++ "GPIO45", ++ "SMPS_SCL", ++ "SMPS_SDA", ++ /* Used by eMMC */ ++ "SD_CLK_R", ++ "SD_CMD_R", ++ "SD_DATA0_R", ++ "SD_DATA1_R", ++ "SD_DATA2_R", ++ "SD_DATA3_R"; ++ ++ spi0_pins: spi0_pins { ++ brcm,pins = <9 10 11>; ++ brcm,function = <4>; /* alt0 */ ++ }; ++ ++ spi0_cs_pins: spi0_cs_pins { ++ brcm,pins = <8 7>; ++ brcm,function = <1>; /* output */ ++ }; ++ ++ i2c0_pins: i2c0 { ++ brcm,pins = <0 1>; ++ brcm,function = <4>; ++ }; ++ ++ i2c1_pins: i2c1 { ++ brcm,pins = <2 3>; ++ brcm,function = <4>; ++ }; ++ ++ i2s_pins: i2s { ++ brcm,pins = <18 19 20 21>; ++ brcm,function = <4>; /* alt0 */ ++ }; ++ ++ audio_pins: audio_pins { ++ brcm,pins; ++ brcm,function; ++ }; ++}; ++ ++&soc { ++ virtgpio: virtgpio { ++ compatible = "brcm,bcm2835-virtgpio"; ++ gpio-controller; ++ #gpio-cells = <2>; ++ firmware = <&firmware>; ++ status = "okay"; ++ }; ++ ++}; ++ ++&firmware { ++ expgpio: expgpio { ++ compatible = "raspberrypi,firmware-gpio"; ++ gpio-controller; ++ #gpio-cells = <2>; ++ gpio-line-names = "HDMI_HPD_N", ++ "EMMC_EN_N", ++ "NC", ++ "NC", ++ "NC", ++ "NC", ++ "NC", ++ "NC"; ++ status = "okay"; ++ }; ++}; ++ ++&spi0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi0_pins &spi0_cs_pins>; ++ cs-gpios = <&gpio 8 1>, <&gpio 7 1>; ++ ++ spidev0: spidev@0{ ++ compatible = "spidev"; ++ reg = <0>; /* CE0 */ ++ #address-cells = <1>; ++ #size-cells = <0>; ++ spi-max-frequency = <125000000>; ++ }; ++ ++ spidev1: spidev@1{ ++ compatible = "spidev"; ++ reg = <1>; /* CE1 */ ++ #address-cells = <1>; ++ #size-cells = <0>; ++ spi-max-frequency = <125000000>; ++ }; ++}; ++ ++&i2c0if { ++ clock-frequency = <100000>; ++}; ++ ++&i2c1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c1_pins>; ++ clock-frequency = <100000>; ++}; ++ ++&i2c2 { ++ clock-frequency = <100000>; ++}; ++ ++&i2s { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2s_pins>; ++}; ++ ++&led_act { ++ gpios = <&virtgpio 0 GPIO_ACTIVE_HIGH>; ++ default-state = "off"; ++ linux,default-trigger = "mmc0"; ++}; ++ ++&hdmi { ++ hpd-gpios = <&expgpio 0 GPIO_ACTIVE_LOW>; ++}; ++ ++&vchiq { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&audio_pins>; ++}; ++ ++/ { ++ __overrides__ { ++ audio = <&chosen>,"bootargs{on='snd_bcm2835.enable_hdmi=1',off='snd_bcm2835.enable_hdmi=0'}"; ++ ++ act_led_gpio = <&led_act>,"gpios:4"; ++ act_led_activelow = <&led_act>,"gpios:8"; ++ act_led_trigger = <&led_act>,"linux,default-trigger"; ++ cam0_reg = <&cam0_reg>,"status"; ++ cam0_reg_gpio = <&cam0_reg>,"gpio:4"; ++ cam1_reg = <&cam1_reg>,"status"; ++ cam1_reg_gpio = <&cam1_reg>,"gpio:4"; ++ }; ++}; +diff --git a/arch/arm/boot/dts/broadcom/bcm2709-rpi.dtsi b/arch/arm/boot/dts/broadcom/bcm2709-rpi.dtsi +new file mode 100644 +index 000000000000..7335e7fbcb71 +--- /dev/null ++++ b/arch/arm/boot/dts/broadcom/bcm2709-rpi.dtsi +@@ -0,0 +1,8 @@ +#include "bcm2708-rpi.dtsi" + +&vchiq { + compatible = "brcm,bcm2836-vchiq", "brcm,bcm2835-vchiq"; +}; -diff --git a/arch/arm/boot/dts/bcm2709.dtsi b/arch/arm/boot/dts/bcm2709.dtsi ++ ++i2c_arm: &i2c1 {}; ++i2c_vc: &i2c0 {}; +diff --git a/arch/arm/boot/dts/broadcom/bcm2709.dtsi b/arch/arm/boot/dts/broadcom/bcm2709.dtsi new file mode 100644 -index 000000000000..68eafc1b281a +index 000000000000..868f65f922ff --- /dev/null -+++ b/arch/arm/boot/dts/bcm2709.dtsi -@@ -0,0 +1,22 @@ ++++ b/arch/arm/boot/dts/broadcom/bcm2709.dtsi +@@ -0,0 +1,29 @@ ++#define i2c0 i2c0if +#include "bcm2836.dtsi" ++#undef i2c0 +#include "bcm270x.dtsi" + +/ { @@ -5402,7 +7332,8 @@ index 000000000000..68eafc1b281a + ranges = <0x7e000000 0x3f000000 0x01000000>, + <0x40000000 0x40000000 0x00040000>; + -+ /delete-node/ timer@7e003000; ++ dma-ranges = <0xc0000000 0x00000000 0x3f000000>, ++ <0x7e000000 0x3f000000 0x01000000>; + }; + + __overrides__ { @@ -5413,20 +7344,23 @@ index 000000000000..68eafc1b281a + }; +}; + ++&system_timer { ++ status = "disabled"; ++}; ++ +&vc4 { + status = "disabled"; +}; -diff --git a/arch/arm/boot/dts/bcm270x-rpi.dtsi b/arch/arm/boot/dts/bcm270x-rpi.dtsi +diff --git a/arch/arm/boot/dts/broadcom/bcm270x-rpi.dtsi b/arch/arm/boot/dts/broadcom/bcm270x-rpi.dtsi new file mode 100644 -index 000000000000..57e7d5f60d3e +index 000000000000..360fb05fe80e --- /dev/null -+++ b/arch/arm/boot/dts/bcm270x-rpi.dtsi -@@ -0,0 +1,155 @@ ++++ b/arch/arm/boot/dts/broadcom/bcm270x-rpi.dtsi +@@ -0,0 +1,186 @@ +/* Downstream modifications to bcm2835-rpi.dtsi */ + +/ { -+ aliases { -+ audio = &audio; ++ aliases: aliases { + aux = &aux; + sound = &sound; + soc = &soc; @@ -5446,6 +7380,7 @@ index 000000000000..57e7d5f60d3e + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c10 = &i2c_csi_dsi; ++ i2c = &i2c_arm; + spi0 = &spi0; + spi1 = &spi1; + spi2 = &spi2; @@ -5473,10 +7408,6 @@ index 000000000000..57e7d5f60d3e + regulator-name = "5v0"; + }; + -+ leds: leds { -+ compatible = "gpio-leds"; -+ }; -+ + soc { + gpiomem { + compatible = "brcm,bcm2835-gpiomem"; @@ -5504,10 +7435,15 @@ index 000000000000..57e7d5f60d3e + spi = <&spi0>,"status"; + i2c0 = <&i2c0if>,"status",<&i2c0mux>,"status"; + i2c1 = <&i2c1>,"status"; ++ i2c = <&i2c1>,"status"; ++ i2c_arm = <&i2c1>,"status"; ++ i2c_vc = <&i2c0if>,"status",<&i2c0mux>,"status"; + i2c0_baudrate = <&i2c0if>,"clock-frequency:0"; + i2c1_baudrate = <&i2c1>,"clock-frequency:0"; ++ i2c_baudrate = <&i2c1>,"clock-frequency:0"; ++ i2c_arm_baudrate = <&i2c1>,"clock-frequency:0"; ++ i2c_vc_baudrate = <&i2c0if>,"clock-frequency:0"; + -+ audio = <&audio>,"status"; + watchdog = <&watchdog>,"status"; + random = <&random>,"status"; + sd_overclock = <&sdhost>,"brcm,overclock-50:0"; @@ -5517,6 +7453,9 @@ index 000000000000..57e7d5f60d3e + sdio_overclock = <&mmc>,"brcm,overclock-50:0", + <&mmcnr>,"brcm,overclock-50:0"; + axiperf = <&axiperf>,"status"; ++ drm_fb0_vc4 = <&aliases>, "drm-fb0=",&vc4; ++ drm_fb1_vc4 = <&aliases>, "drm-fb1=",&vc4; ++ drm_fb2_vc4 = <&aliases>, "drm-fb2=",&vc4; + }; +}; + @@ -5537,6 +7476,8 @@ index 000000000000..57e7d5f60d3e +}; + +&i2c0mux { ++ pinctrl-names = "i2c0", "i2c_csi_dsi"; ++ /delete-property/ clock-frequency; + status = "disabled"; +}; + @@ -5544,6 +7485,9 @@ index 000000000000..57e7d5f60d3e + status = "disabled"; +}; + ++i2s_clk_producer: &i2s {}; ++i2s_clk_consumer: &i2s {}; ++ +&clocks { + firmware = <&firmware>; +}; @@ -5555,45 +7499,67 @@ index 000000000000..57e7d5f60d3e +}; + +&cpu_thermal { -+ /delete-node/ trips; -+}; -+ -+&vec { -+ status = "disabled"; -+}; -+ -+&vchiq { -+ /* Onboard audio */ -+ audio: bcm2835_audio { -+ compatible = "brcm,bcm2835-audio"; -+ brcm,firmware = <&firmware>; -+ brcm,pwm-channels = <8>; -+ status = "disabled"; ++ // Add some labels ++ thermal_trips: trips { ++ cpu-crit { ++ // Raise upstream limit of 90C ++ temperature = <110000>; ++ }; ++ }; ++ cooling_maps: cooling-maps { + }; +}; + ++&vec { ++ clocks = <&firmware_clocks 15>; ++ status = "disabled"; ++}; ++ +&firmware { ++#ifndef BCM2711 ++ firmware_clocks: clocks { ++ compatible = "raspberrypi,firmware-clocks"; ++ #clock-cells = <1>; ++ }; ++#endif ++ + vcio: vcio { + compatible = "raspberrypi,vcio"; + }; +}; -diff --git a/arch/arm/boot/dts/bcm270x.dtsi b/arch/arm/boot/dts/bcm270x.dtsi ++ ++&vc4 { ++ raspberrypi,firmware = <&firmware>; ++}; ++ ++#ifndef BCM2711 ++ ++&hdmi { ++ reg-names = "hdmi", ++ "hd"; ++ clocks = <&firmware_clocks 9>, ++ <&firmware_clocks 13>; ++ dmas = <&dma (17|(1<<27)|(1<<24))>; ++}; ++ ++#endif +diff --git a/arch/arm/boot/dts/broadcom/bcm270x.dtsi b/arch/arm/boot/dts/broadcom/bcm270x.dtsi new file mode 100644 -index 000000000000..a5cabb5bc4a1 +index 000000000000..c318080eb883 --- /dev/null -+++ b/arch/arm/boot/dts/bcm270x.dtsi -@@ -0,0 +1,272 @@ ++++ b/arch/arm/boot/dts/broadcom/bcm270x.dtsi +@@ -0,0 +1,294 @@ +/* Downstream bcm283x.dtsi diff */ +#include + +/ { -+ chosen { -+ bootargs = "coherent_pool=1M snd_bcm2835.enable_compat_alsa=0 snd_bcm2835.enable_hdmi=1"; -+ /delete-property/ stdout-path; ++ chosen: chosen { ++ // Disable audio by default ++ bootargs = "coherent_pool=1M snd_bcm2835.enable_headphones=0"; ++ stdout-path = "serial0:115200n8"; + }; + + soc: soc { -+ + watchdog: watchdog@7e100000 { + /* Add label */ + }; @@ -5736,6 +7702,28 @@ index 000000000000..a5cabb5bc4a1 + firmware = <&firmware>; + status = "disabled"; + }; ++ ++ i2c0mux: i2c0mux { ++ compatible = "i2c-mux-pinctrl"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ i2c-parent = <&i2c0if>; ++ ++ status = "disabled"; ++ ++ i2c0: i2c@0 { ++ reg = <0>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ }; ++ ++ i2c_csi_dsi: i2c@1 { ++ reg = <1>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ }; ++ }; + }; + + cam1_reg: cam1_regulator { @@ -5855,12 +7843,12 @@ index 000000000000..a5cabb5bc4a1 + dmas = <&dma 6>, <&dma 7>; + dma-names = "tx", "rx"; +}; -diff --git a/arch/arm/boot/dts/bcm2710-rpi-2-b.dts b/arch/arm/boot/dts/bcm2710-rpi-2-b.dts +diff --git a/arch/arm/boot/dts/broadcom/bcm2710-rpi-2-b.dts b/arch/arm/boot/dts/broadcom/bcm2710-rpi-2-b.dts new file mode 100644 -index 000000000000..a8a18ef4d1bf +index 000000000000..ce48eb6073f0 --- /dev/null -+++ b/arch/arm/boot/dts/bcm2710-rpi-2-b.dts -@@ -0,0 +1,131 @@ ++++ b/arch/arm/boot/dts/broadcom/bcm2710-rpi-2-b.dts +@@ -0,0 +1,204 @@ +/dts-v1/; + +#include "bcm2710.dtsi" @@ -5868,6 +7856,7 @@ index 000000000000..a8a18ef4d1bf +#include "bcm283x-rpi-smsc9514.dtsi" +#include "bcm283x-rpi-csi1-2lane.dtsi" +#include "bcm283x-rpi-i2c0mux_0_28.dtsi" ++#include "bcm283x-rpi-led-deprecated.dtsi" + +/ { + compatible = "raspberrypi,2-model-b-rev2", "brcm,bcm2837"; @@ -5875,6 +7864,71 @@ index 000000000000..a8a18ef4d1bf +}; + +&gpio { ++ /* ++ * Taken from rpi_SCH_2b_1p2_reduced.pdf and ++ * the official GPU firmware DT blob. ++ * ++ * Legend: ++ * "NC" = not connected (no rail from the SoC) ++ * "FOO" = GPIO line named "FOO" on the schematic ++ * "FOO_N" = GPIO line named "FOO" on schematic, active low ++ */ ++ gpio-line-names = "ID_SDA", ++ "ID_SCL", ++ "GPIO2", ++ "GPIO3", ++ "GPIO4", ++ "GPIO5", ++ "GPIO6", ++ "GPIO7", ++ "GPIO8", ++ "GPIO9", ++ "GPIO10", ++ "GPIO11", ++ "GPIO12", ++ "GPIO13", ++ "GPIO14", ++ "GPIO15", ++ "GPIO16", ++ "GPIO17", ++ "GPIO18", ++ "GPIO19", ++ "GPIO20", ++ "GPIO21", ++ "GPIO22", ++ "GPIO23", ++ "GPIO24", ++ "GPIO25", ++ "GPIO26", ++ "GPIO27", ++ "SDA0", ++ "SCL0", ++ "NC", /* GPIO30 */ ++ "LAN_RUN", ++ "CAM_GPIO1", ++ "NC", /* GPIO33 */ ++ "NC", /* GPIO34 */ ++ "PWR_LOW_N", ++ "NC", /* GPIO36 */ ++ "NC", /* GPIO37 */ ++ "USB_LIMIT", ++ "NC", /* GPIO39 */ ++ "PWM0_OUT", ++ "CAM_GPIO0", ++ "SMPS_SCL", ++ "SMPS_SDA", ++ "ETH_CLK", ++ "PWM1_OUT", ++ "HDMI_HPD_N", ++ "STATUS_LED", ++ /* Used by SD Card */ ++ "SD_CLK_R", ++ "SD_CMD_R", ++ "SD_DATA0_R", ++ "SD_DATA1_R", ++ "SD_DATA2_R", ++ "SD_DATA3_R"; ++ + spi0_pins: spi0_pins { + brcm,pins = <9 10 11>; + brcm,function = <4>; /* alt0 */ @@ -5903,6 +7957,7 @@ index 000000000000..a8a18ef4d1bf + audio_pins: audio_pins { + brcm,pins = <40 45>; + brcm,function = <4>; ++ brcm,pull = <0>; + }; +}; + @@ -5951,17 +8006,18 @@ index 000000000000..a8a18ef4d1bf + pinctrl-0 = <&i2s_pins>; +}; + -+&leds { -+ act_led: led-act { -+ label = "led0"; -+ linux,default-trigger = "mmc0"; -+ gpios = <&gpio 47 0>; -+ }; ++&led_act { ++ gpios = <&gpio 47 GPIO_ACTIVE_HIGH>; ++ default-state = "off"; ++ linux,default-trigger = "mmc0"; ++}; + -+ pwr_led: led-pwr { -+ label = "led1"; ++&leds { ++ led_pwr: led-pwr { ++ label = "PWR"; ++ gpios = <&gpio 35 GPIO_ACTIVE_HIGH>; ++ default-state = "off"; + linux,default-trigger = "input"; -+ gpios = <&gpio 35 0>; + }; +}; + @@ -5969,7 +8025,7 @@ index 000000000000..a8a18ef4d1bf + hpd-gpios = <&gpio 46 GPIO_ACTIVE_LOW>; +}; + -+&audio { ++&vchiq { + pinctrl-names = "default"; + pinctrl-0 = <&audio_pins>; +}; @@ -5981,23 +8037,28 @@ index 000000000000..a8a18ef4d1bf +cam0_reg: &cam_dummy_reg { +}; + ++i2c_csi_dsi0: &i2c0 { ++}; ++ +/ { + __overrides__ { -+ act_led_gpio = <&act_led>,"gpios:4"; -+ act_led_activelow = <&act_led>,"gpios:8"; -+ act_led_trigger = <&act_led>,"linux,default-trigger"; ++ audio = <&chosen>,"bootargs{on='snd_bcm2835.enable_headphones=1 snd_bcm2835.enable_hdmi=1',off='snd_bcm2835.enable_headphones=0 snd_bcm2835.enable_hdmi=0'}"; + -+ pwr_led_gpio = <&pwr_led>,"gpios:4"; -+ pwr_led_activelow = <&pwr_led>,"gpios:8"; -+ pwr_led_trigger = <&pwr_led>,"linux,default-trigger"; ++ act_led_gpio = <&led_act>,"gpios:4"; ++ act_led_activelow = <&led_act>,"gpios:8"; ++ act_led_trigger = <&led_act>,"linux,default-trigger"; ++ ++ pwr_led_gpio = <&led_pwr>,"gpios:4"; ++ pwr_led_activelow = <&led_pwr>,"gpios:8"; ++ pwr_led_trigger = <&led_pwr>,"linux,default-trigger"; + }; +}; -diff --git a/arch/arm/boot/dts/bcm2710-rpi-3-b-plus.dts b/arch/arm/boot/dts/bcm2710-rpi-3-b-plus.dts +diff --git a/arch/arm/boot/dts/broadcom/bcm2710-rpi-3-b-plus.dts b/arch/arm/boot/dts/broadcom/bcm2710-rpi-3-b-plus.dts new file mode 100644 -index 000000000000..93f9c8dddbca +index 000000000000..1afbb9011702 --- /dev/null -+++ b/arch/arm/boot/dts/bcm2710-rpi-3-b-plus.dts -@@ -0,0 +1,210 @@ ++++ b/arch/arm/boot/dts/broadcom/bcm2710-rpi-3-b-plus.dts +@@ -0,0 +1,299 @@ +/dts-v1/; + +#include "bcm2710.dtsi" @@ -6006,13 +8067,14 @@ index 000000000000..93f9c8dddbca +#include "bcm283x-rpi-csi1-2lane.dtsi" +#include "bcm283x-rpi-i2c0mux_0_44.dtsi" +#include "bcm271x-rpi-bt.dtsi" ++#include "bcm283x-rpi-led-deprecated.dtsi" + +/ { + compatible = "raspberrypi,3-model-b-plus", "brcm,bcm2837"; + model = "Raspberry Pi 3 Model B+"; + + chosen { -+ bootargs = "coherent_pool=1M 8250.nr_uarts=1 snd_bcm2835.enable_compat_alsa=0 snd_bcm2835.enable_hdmi=1"; ++ bootargs = "coherent_pool=1M 8250.nr_uarts=1 snd_bcm2835.enable_headphones=0"; + }; + + aliases { @@ -6023,6 +8085,73 @@ index 000000000000..93f9c8dddbca +}; + +&gpio { ++ /* ++ * Taken from rpi_SCH_3bplus_1p0_reduced.pdf and ++ * the official GPU firmware DT blob. ++ * ++ * Legend: ++ * "NC" = not connected (no rail from the SoC) ++ * "FOO" = GPIO line named "FOO" on the schematic ++ * "FOO_N" = GPIO line named "FOO" on schematic, active low ++ */ ++ gpio-line-names = "ID_SDA", ++ "ID_SCL", ++ "GPIO2", ++ "GPIO3", ++ "GPIO4", ++ "GPIO5", ++ "GPIO6", ++ "GPIO7", ++ "GPIO8", ++ "GPIO9", ++ "GPIO10", ++ "GPIO11", ++ "GPIO12", ++ "GPIO13", ++ "GPIO14", ++ "GPIO15", ++ "GPIO16", ++ "GPIO17", ++ "GPIO18", ++ "GPIO19", ++ "GPIO20", ++ "GPIO21", ++ "GPIO22", ++ "GPIO23", ++ "GPIO24", ++ "GPIO25", ++ "GPIO26", ++ "GPIO27", ++ "HDMI_HPD_N", ++ "STATUS_LED_G", ++ /* Used by BT module */ ++ "CTS0", ++ "RTS0", ++ "TXD0", ++ "RXD0", ++ /* Used by Wifi */ ++ "SD1_CLK", ++ "SD1_CMD", ++ "SD1_DATA0", ++ "SD1_DATA1", ++ "SD1_DATA2", ++ "SD1_DATA3", ++ "PWM0_OUT", ++ "PWM1_OUT", ++ "ETH_CLK", ++ "WIFI_CLK", ++ "SDA0", ++ "SCL0", ++ "SMPS_SCL", ++ "SMPS_SDA", ++ /* Used by SD Card */ ++ "SD_CLK_R", ++ "SD_CMD_R", ++ "SD_DATA0_R", ++ "SD_DATA1_R", ++ "SD_DATA2_R", ++ "SD_DATA3_R"; ++ + spi0_pins: spi0_pins { + brcm,pins = <9 10 11>; + brcm,function = <4>; /* alt0 */ @@ -6072,9 +8201,16 @@ index 000000000000..93f9c8dddbca + brcm,pull; + }; + ++ uart1_bt_pins: uart1_bt_pins { ++ brcm,pins = <32 33 30 31>; ++ brcm,function = ; /* alt5=UART1 */ ++ brcm,pull = <0 2 2 0>; ++ }; ++ + audio_pins: audio_pins { + brcm,pins = <40 41>; + brcm,function = <4>; ++ brcm,pull = <0>; + }; +}; + @@ -6097,6 +8233,14 @@ index 000000000000..93f9c8dddbca + compatible = "raspberrypi,firmware-gpio"; + gpio-controller; + #gpio-cells = <2>; ++ gpio-line-names = "BT_ON", ++ "WL_ON", ++ "PWR_LED_R", ++ "LAN_RUN", ++ "NC", ++ "CAM_GPIO0", ++ "CAM_GPIO1", ++ "NC"; + status = "okay"; + }; +}; @@ -6154,17 +8298,18 @@ index 000000000000..93f9c8dddbca + pinctrl-0 = <&i2s_pins>; +}; + -+&leds { -+ act_led: led-act { -+ label = "led0"; -+ linux,default-trigger = "mmc0"; -+ gpios = <&gpio 29 0>; -+ }; ++&led_act { ++ gpios = <&gpio 29 GPIO_ACTIVE_HIGH>; ++ default-state = "off"; ++ linux,default-trigger = "mmc0"; ++}; + -+ pwr_led: led-pwr { -+ label = "led1"; -+ linux,default-trigger = "default-on"; ++&leds { ++ led_pwr: led-pwr { ++ label = "PWR"; + gpios = <&expgpio 2 GPIO_ACTIVE_LOW>; ++ default-state = "off"; ++ linux,default-trigger = "default-on"; + }; +}; + @@ -6172,7 +8317,7 @@ index 000000000000..93f9c8dddbca + hpd-gpios = <&gpio 28 GPIO_ACTIVE_LOW>; +}; + -+&audio { ++&vchiq { + pinctrl-names = "default"; + pinctrl-0 = <&audio_pins>; +}; @@ -6190,15 +8335,20 @@ index 000000000000..93f9c8dddbca +cam0_reg: &cam_dummy_reg { +}; + ++i2c_csi_dsi0: &i2c0 { ++}; ++ +/ { + __overrides__ { -+ act_led_gpio = <&act_led>,"gpios:4"; -+ act_led_activelow = <&act_led>,"gpios:8"; -+ act_led_trigger = <&act_led>,"linux,default-trigger"; ++ audio = <&chosen>,"bootargs{on='snd_bcm2835.enable_headphones=1 snd_bcm2835.enable_hdmi=1',off='snd_bcm2835.enable_headphones=0 snd_bcm2835.enable_hdmi=0'}"; + -+ pwr_led_gpio = <&pwr_led>,"gpios:4"; -+ pwr_led_activelow = <&pwr_led>,"gpios:8"; -+ pwr_led_trigger = <&pwr_led>,"linux,default-trigger"; ++ act_led_gpio = <&led_act>,"gpios:4"; ++ act_led_activelow = <&led_act>,"gpios:8"; ++ act_led_trigger = <&led_act>,"linux,default-trigger"; ++ ++ pwr_led_gpio = <&led_pwr>,"gpios:4"; ++ pwr_led_activelow = <&led_pwr>,"gpios:8"; ++ pwr_led_trigger = <&led_pwr>,"linux,default-trigger"; + + eee = <ð_phy>,"microchip,eee-enabled?"; + tx_lpi_timer = <ð_phy>,"microchip,tx-lpi-timer:0"; @@ -6208,12 +8358,12 @@ index 000000000000..93f9c8dddbca + eth_max_speed = <ð_phy>,"max-speed:0"; + }; +}; -diff --git a/arch/arm/boot/dts/bcm2710-rpi-3-b.dts b/arch/arm/boot/dts/bcm2710-rpi-3-b.dts +diff --git a/arch/arm/boot/dts/broadcom/bcm2710-rpi-3-b.dts b/arch/arm/boot/dts/broadcom/bcm2710-rpi-3-b.dts new file mode 100644 -index 000000000000..bc5d086beb93 +index 000000000000..b893affe6997 --- /dev/null -+++ b/arch/arm/boot/dts/bcm2710-rpi-3-b.dts -@@ -0,0 +1,212 @@ ++++ b/arch/arm/boot/dts/broadcom/bcm2710-rpi-3-b.dts +@@ -0,0 +1,297 @@ +/dts-v1/; + +#include "bcm2710.dtsi" @@ -6222,13 +8372,14 @@ index 000000000000..bc5d086beb93 +#include "bcm283x-rpi-csi1-2lane.dtsi" +#include "bcm283x-rpi-i2c0mux_0_44.dtsi" +#include "bcm271x-rpi-bt.dtsi" ++#include "bcm283x-rpi-led-deprecated.dtsi" + +/ { + compatible = "raspberrypi,3-model-b", "brcm,bcm2837"; + model = "Raspberry Pi 3 Model B"; + + chosen { -+ bootargs = "coherent_pool=1M 8250.nr_uarts=1 snd_bcm2835.enable_compat_alsa=0 snd_bcm2835.enable_hdmi=1"; ++ bootargs = "coherent_pool=1M 8250.nr_uarts=1 snd_bcm2835.enable_headphones=0"; + }; + + aliases { @@ -6239,6 +8390,73 @@ index 000000000000..bc5d086beb93 +}; + +&gpio { ++ /* ++ * Taken from rpi_SCH_3b_1p2_reduced.pdf and ++ * the official GPU firmware DT blob. ++ * ++ * Legend: ++ * "NC" = not connected (no rail from the SoC) ++ * "FOO" = GPIO line named "FOO" on the schematic ++ * "FOO_N" = GPIO line named "FOO" on schematic, active low ++ */ ++ gpio-line-names = "ID_SDA", ++ "ID_SCL", ++ "GPIO2", ++ "GPIO3", ++ "GPIO4", ++ "GPIO5", ++ "GPIO6", ++ "GPIO7", ++ "GPIO8", ++ "GPIO9", ++ "GPIO10", ++ "GPIO11", ++ "GPIO12", ++ "GPIO13", ++ "GPIO14", ++ "GPIO15", ++ "GPIO16", ++ "GPIO17", ++ "GPIO18", ++ "GPIO19", ++ "GPIO20", ++ "GPIO21", ++ "GPIO22", ++ "GPIO23", ++ "GPIO24", ++ "GPIO25", ++ "GPIO26", ++ "GPIO27", ++ "NC", /* GPIO 28 */ ++ "LAN_RUN_BOOT", ++ /* Used by BT module */ ++ "CTS0", ++ "RTS0", ++ "TXD0", ++ "RXD0", ++ /* Used by Wifi */ ++ "SD1_CLK", ++ "SD1_CMD", ++ "SD1_DATA0", ++ "SD1_DATA1", ++ "SD1_DATA2", ++ "SD1_DATA3", ++ "PWM0_OUT", ++ "PWM1_OUT", ++ "ETH_CLK", ++ "WIFI_CLK", ++ "SDA0", ++ "SCL0", ++ "SMPS_SCL", ++ "SMPS_SDA", ++ /* Used by SD Card */ ++ "SD_CLK_R", ++ "SD_CMD_R", ++ "SD_DATA0_R", ++ "SD_DATA1_R", ++ "SD_DATA2_R", ++ "SD_DATA3_R"; ++ + spi0_pins: spi0_pins { + brcm,pins = <9 10 11>; + brcm,function = <4>; /* alt0 */ @@ -6288,9 +8506,16 @@ index 000000000000..bc5d086beb93 + brcm,pull; + }; + ++ uart1_bt_pins: uart1_bt_pins { ++ brcm,pins = <32 33>; ++ brcm,function = ; /* alt5=UART1 */ ++ brcm,pull = <0 2>; ++ }; ++ + audio_pins: audio_pins { + brcm,pins = <40 41>; + brcm,function = <4>; ++ brcm,pull = <0>; + }; +}; + @@ -6308,22 +8533,26 @@ index 000000000000..bc5d086beb93 + }; +}; + -+&soc { -+ virtgpio: virtgpio { -+ compatible = "brcm,bcm2835-virtgpio"; -+ gpio-controller; -+ #gpio-cells = <2>; -+ firmware = <&firmware>; -+ status = "okay"; -+ }; -+ -+}; -+ +&firmware { + expgpio: expgpio { + compatible = "raspberrypi,firmware-gpio"; + gpio-controller; + #gpio-cells = <2>; ++ gpio-line-names = "BT_ON", ++ "WL_ON", ++ "STATUS_LED", ++ "LAN_RUN", ++ "HDMI_HPD_N", ++ "CAM_GPIO0", ++ "CAM_GPIO1", ++ "PWR_LOW_N"; ++ status = "okay"; ++ }; ++ ++ virtgpio: virtgpio { ++ compatible = "brcm,bcm2835-virtgpio"; ++ gpio-controller; ++ #gpio-cells = <2>; + status = "okay"; + }; +}; @@ -6385,17 +8614,18 @@ index 000000000000..bc5d086beb93 + pinctrl-0 = <&i2s_pins>; +}; + -+&leds { -+ act_led: led-act { -+ label = "led0"; -+ linux,default-trigger = "mmc0"; -+ gpios = <&virtgpio 0 0>; -+ }; ++&led_act { ++ gpios = <&virtgpio 0 GPIO_ACTIVE_HIGH>; ++ default-state = "off"; ++ linux,default-trigger = "mmc0"; ++}; + -+ pwr_led: led-pwr { -+ label = "led1"; ++&leds { ++ led_pwr: led-pwr { ++ label = "PWR"; ++ gpios = <&expgpio 7 GPIO_ACTIVE_HIGH>; ++ default-state = "off"; + linux,default-trigger = "input"; -+ gpios = <&expgpio 7 0>; + }; +}; + @@ -6403,7 +8633,7 @@ index 000000000000..bc5d086beb93 + hpd-gpios = <&expgpio 4 GPIO_ACTIVE_LOW>; +}; + -+&audio { ++&vchiq { + pinctrl-names = "default"; + pinctrl-0 = <&audio_pins>; +}; @@ -6415,23 +8645,28 @@ index 000000000000..bc5d086beb93 +cam0_reg: &cam_dummy_reg { +}; + ++i2c_csi_dsi0: &i2c0 { ++}; ++ +/ { + __overrides__ { -+ act_led_gpio = <&act_led>,"gpios:4"; -+ act_led_activelow = <&act_led>,"gpios:8"; -+ act_led_trigger = <&act_led>,"linux,default-trigger"; ++ audio = <&chosen>,"bootargs{on='snd_bcm2835.enable_headphones=1 snd_bcm2835.enable_hdmi=1',off='snd_bcm2835.enable_headphones=0 snd_bcm2835.enable_hdmi=0'}"; + -+ pwr_led_gpio = <&pwr_led>,"gpios:4"; -+ pwr_led_activelow = <&pwr_led>,"gpios:8"; -+ pwr_led_trigger = <&pwr_led>,"linux,default-trigger"; ++ act_led_gpio = <&led_act>,"gpios:4"; ++ act_led_activelow = <&led_act>,"gpios:8"; ++ act_led_trigger = <&led_act>,"linux,default-trigger"; ++ ++ pwr_led_gpio = <&led_pwr>,"gpios:4"; ++ pwr_led_activelow = <&led_pwr>,"gpios:8"; ++ pwr_led_trigger = <&led_pwr>,"linux,default-trigger"; + }; +}; -diff --git a/arch/arm/boot/dts/bcm2710-rpi-cm3.dts b/arch/arm/boot/dts/bcm2710-rpi-cm3.dts +diff --git a/arch/arm/boot/dts/broadcom/bcm2710-rpi-cm3.dts b/arch/arm/boot/dts/broadcom/bcm2710-rpi-cm3.dts new file mode 100644 -index 000000000000..517ed47c257d +index 000000000000..08a33038e3f5 --- /dev/null -+++ b/arch/arm/boot/dts/bcm2710-rpi-cm3.dts -@@ -0,0 +1,146 @@ ++++ b/arch/arm/boot/dts/broadcom/bcm2710-rpi-cm3.dts +@@ -0,0 +1,223 @@ +/dts-v1/; + +#include "bcm2710.dtsi" @@ -6439,18 +8674,23 @@ index 000000000000..517ed47c257d +#include "bcm283x-rpi-csi0-2lane.dtsi" +#include "bcm283x-rpi-csi1-4lane.dtsi" +#include "bcm283x-rpi-i2c0mux_0_28.dtsi" ++#include "bcm283x-rpi-led-deprecated.dtsi" ++ +/ { + compatible = "raspberrypi,3-compute-module", "brcm,bcm2837"; + model = "Raspberry Pi Compute Module 3"; +}; + +&cam1_reg { -+ gpio = <&gpio 2 GPIO_ACTIVE_HIGH>; ++ gpio = <&gpio 3 GPIO_ACTIVE_HIGH>; + status = "disabled"; +}; + +cam0_reg: &cam0_regulator { -+ gpio = <&gpio 30 GPIO_ACTIVE_HIGH>; ++ gpio = <&gpio 31 GPIO_ACTIVE_HIGH>; ++}; ++ ++i2c_csi_dsi0: &i2c0 { +}; + +&uart0 { @@ -6458,6 +8698,70 @@ index 000000000000..517ed47c257d +}; + +&gpio { ++ /* ++ * This is based on the official GPU firmware DT blob. ++ * ++ * Legend: ++ * "NC" = not connected (no rail from the SoC) ++ * "FOO" = GPIO line named "FOO" on the schematic ++ * "FOO_N" = GPIO line named "FOO" on schematic, active low ++ */ ++ gpio-line-names = "GPIO0", ++ "GPIO1", ++ "GPIO2", ++ "GPIO3", ++ "GPIO4", ++ "GPIO5", ++ "GPIO6", ++ "GPIO7", ++ "GPIO8", ++ "GPIO9", ++ "GPIO10", ++ "GPIO11", ++ "GPIO12", ++ "GPIO13", ++ "GPIO14", ++ "GPIO15", ++ "GPIO16", ++ "GPIO17", ++ "GPIO18", ++ "GPIO19", ++ "GPIO20", ++ "GPIO21", ++ "GPIO22", ++ "GPIO23", ++ "GPIO24", ++ "GPIO25", ++ "GPIO26", ++ "GPIO27", ++ "GPIO28", ++ "GPIO29", ++ "GPIO30", ++ "GPIO31", ++ "GPIO32", ++ "GPIO33", ++ "GPIO34", ++ "GPIO35", ++ "GPIO36", ++ "GPIO37", ++ "GPIO38", ++ "GPIO39", ++ "GPIO40", ++ "GPIO41", ++ "GPIO42", ++ "GPIO43", ++ "GPIO44", ++ "GPIO45", ++ "SMPS_SCL", ++ "SMPS_SDA", ++ /* Used by eMMC */ ++ "SD_CLK_R", ++ "SD_CMD_R", ++ "SD_DATA0_R", ++ "SD_DATA1_R", ++ "SD_DATA2_R", ++ "SD_DATA3_R"; ++ + spi0_pins: spi0_pins { + brcm,pins = <9 10 11>; + brcm,function = <4>; /* alt0 */ @@ -6505,6 +8809,14 @@ index 000000000000..517ed47c257d + compatible = "raspberrypi,firmware-gpio"; + gpio-controller; + #gpio-cells = <2>; ++ gpio-line-names = "HDMI_HPD_N", ++ "EMMC_EN_N", ++ "NC", ++ "NC", ++ "NC", ++ "NC", ++ "NC", ++ "NC"; + status = "okay"; + }; +}; @@ -6550,40 +8862,40 @@ index 000000000000..517ed47c257d + pinctrl-0 = <&i2s_pins>; +}; + -+&leds { -+ act_led: led-act { -+ label = "led0"; -+ linux,default-trigger = "mmc0"; -+ gpios = <&virtgpio 0 0>; -+ }; ++&led_act { ++ gpios = <&virtgpio 0 GPIO_ACTIVE_HIGH>; ++ default-state = "off"; ++ linux,default-trigger = "mmc0"; +}; + +&hdmi { + hpd-gpios = <&expgpio 0 GPIO_ACTIVE_LOW>; +}; + -+&audio { ++&vchiq { + pinctrl-names = "default"; + pinctrl-0 = <&audio_pins>; +}; + +/ { + __overrides__ { -+ act_led_gpio = <&act_led>,"gpios:4"; -+ act_led_activelow = <&act_led>,"gpios:8"; -+ act_led_trigger = <&act_led>,"linux,default-trigger"; ++ audio = <&chosen>,"bootargs{on='snd_bcm2835.enable_hdmi=1',off='snd_bcm2835.enable_hdmi=0'}"; ++ ++ act_led_gpio = <&led_act>,"gpios:4"; ++ act_led_activelow = <&led_act>,"gpios:8"; ++ act_led_trigger = <&led_act>,"linux,default-trigger"; + cam0_reg = <&cam0_reg>,"status"; -+ cam0_reg_gpio = <&cam0_reg>,"gpios:4"; ++ cam0_reg_gpio = <&cam0_reg>,"gpio:4"; + cam1_reg = <&cam1_reg>,"status"; -+ cam1_reg_gpio = <&cam1_reg>,"gpios:4"; ++ cam1_reg_gpio = <&cam1_reg>,"gpio:4"; + }; +}; -diff --git a/arch/arm/boot/dts/bcm2710-rpi-zero-2-w.dts b/arch/arm/boot/dts/bcm2710-rpi-zero-2-w.dts +diff --git a/arch/arm/boot/dts/broadcom/bcm2710-rpi-zero-2-w.dts b/arch/arm/boot/dts/broadcom/bcm2710-rpi-zero-2-w.dts new file mode 100644 -index 000000000000..38629ebfa47f +index 000000000000..25182d73f244 --- /dev/null -+++ b/arch/arm/boot/dts/bcm2710-rpi-zero-2-w.dts -@@ -0,0 +1,199 @@ ++++ b/arch/arm/boot/dts/broadcom/bcm2710-rpi-zero-2-w.dts +@@ -0,0 +1,261 @@ +/dts-v1/; + +#include "bcm2710.dtsi" @@ -6591,13 +8903,14 @@ index 000000000000..38629ebfa47f +#include "bcm283x-rpi-csi1-2lane.dtsi" +#include "bcm283x-rpi-i2c0mux_0_44.dtsi" +#include "bcm2708-rpi-bt.dtsi" ++#include "bcm283x-rpi-led-deprecated.dtsi" + +/ { + compatible = "raspberrypi,model-zero-2-w", "brcm,bcm2837"; + model = "Raspberry Pi Zero 2 W"; + + chosen { -+ bootargs = "coherent_pool=1M 8250.nr_uarts=1 snd_bcm2835.enable_compat_alsa=0 snd_bcm2835.enable_hdmi=1"; ++ bootargs = "coherent_pool=1M 8250.nr_uarts=1 snd_bcm2835.enable_headphones=0"; + }; + + aliases { @@ -6608,6 +8921,72 @@ index 000000000000..38629ebfa47f +}; + +&gpio { ++ /* ++ * This is based on the official GPU firmware DT blob. ++ * ++ * Legend: ++ * "NC" = not connected (no rail from the SoC) ++ * "FOO" = GPIO line named "FOO" on the schematic ++ * "FOO_N" = GPIO line named "FOO" on schematic, active low ++ */ ++ gpio-line-names = "ID_SDA", ++ "ID_SCL", ++ "GPIO2", ++ "GPIO3", ++ "GPIO4", ++ "GPIO5", ++ "GPIO6", ++ "GPIO7", ++ "GPIO8", ++ "GPIO9", ++ "GPIO10", ++ "GPIO11", ++ "GPIO12", ++ "GPIO13", ++ "GPIO14", ++ "GPIO15", ++ "GPIO16", ++ "GPIO17", ++ "GPIO18", ++ "GPIO19", ++ "GPIO20", ++ "GPIO21", ++ "GPIO22", ++ "GPIO23", ++ "GPIO24", ++ "GPIO25", ++ "GPIO26", ++ "GPIO27", ++ "HDMI_HPD_N", ++ "STATUS_LED_N", ++ /* Used by BT module */ ++ "CTS0", ++ "RTS0", ++ "TXD0", ++ "RXD0", ++ /* Used by Wifi */ ++ "SD1_CLK", ++ "SD1_CMD", ++ "SD1_DATA0", ++ "SD1_DATA1", ++ "SD1_DATA2", ++ "SD1_DATA3", ++ "CAM_GPIO1", /* GPIO40 */ ++ "WL_ON", /* GPIO41 */ ++ "BT_ON", /* GPIO42 */ ++ "WIFI_CLK", /* GPIO43 */ ++ "SDA0", /* GPIO44 */ ++ "SCL0", /* GPIO45 */ ++ "SMPS_SCL", /* GPIO46 */ ++ "SMPS_SDA", /* GPIO47 */ ++ /* Used by SD Card */ ++ "SD_CLK_R", ++ "SD_CMD_R", ++ "SD_DATA0_R", ++ "SD_DATA1_R", ++ "SD_DATA2_R", ++ "SD_DATA3_R"; ++ + spi0_pins: spi0_pins { + brcm,pins = <9 10 11>; + brcm,function = <4>; /* alt0 */ @@ -6657,6 +9036,12 @@ index 000000000000..38629ebfa47f + brcm,pull; + }; + ++ uart1_bt_pins: uart1_bt_pins { ++ brcm,pins = <32 33 30 31>; ++ brcm,function = ; /* alt5=UART1 */ ++ brcm,pull = <0 2 2 0>; ++ }; ++ + audio_pins: audio_pins { + brcm,pins = <>; + brcm,function = <>; @@ -6674,19 +9059,6 @@ index 000000000000..38629ebfa47f + brcmf: wifi@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; -+ -+ firmwares { -+ fw_43436p { -+ chipid = <43430>; -+ revmask = <4>; -+ fw_base = "brcm/brcmfmac43436-sdio"; -+ }; -+ fw_43436s { -+ chipid = <43430>; -+ revmask = <2>; -+ fw_base = "brcm/brcmfmac43436s-sdio"; -+ }; -+ }; + }; +}; + @@ -6743,22 +9115,19 @@ index 000000000000..38629ebfa47f + pinctrl-0 = <&i2s_pins>; +}; + -+&leds { -+ act_led: led-act { -+ label = "led0"; -+ linux,default-trigger = "actpwr"; -+ gpios = <&gpio 29 GPIO_ACTIVE_LOW>; -+ }; ++&led_act { ++ gpios = <&gpio 29 GPIO_ACTIVE_LOW>; ++ default-state = "off"; ++ linux,default-trigger = "actpwr"; +}; + +&hdmi { + hpd-gpios = <&gpio 28 GPIO_ACTIVE_LOW>; +}; + -+&audio { ++&vchiq { + pinctrl-names = "default"; + pinctrl-0 = <&audio_pins>; -+ brcm,disable-headphones = <1>; +}; + +&bt { @@ -6776,27 +9145,34 @@ index 000000000000..38629ebfa47f +cam0_reg: &cam_dummy_reg { +}; + ++i2c_csi_dsi0: &i2c0 { ++}; ++ +/ { + __overrides__ { -+ act_led_gpio = <&act_led>,"gpios:4"; -+ act_led_activelow = <&act_led>,"gpios:8"; -+ act_led_trigger = <&act_led>,"linux,default-trigger"; ++ audio = <&chosen>,"bootargs{on='snd_bcm2835.enable_hdmi=1',off='snd_bcm2835.enable_hdmi=0'}"; ++ ++ act_led_gpio = <&led_act>,"gpios:4"; ++ act_led_activelow = <&led_act>,"gpios:8"; ++ act_led_trigger = <&led_act>,"linux,default-trigger"; + }; +}; -diff --git a/arch/arm/boot/dts/bcm2710-rpi-zero-2.dts b/arch/arm/boot/dts/bcm2710-rpi-zero-2.dts +diff --git a/arch/arm/boot/dts/broadcom/bcm2710-rpi-zero-2.dts b/arch/arm/boot/dts/broadcom/bcm2710-rpi-zero-2.dts new file mode 100644 index 000000000000..daa12bd30d6b --- /dev/null -+++ b/arch/arm/boot/dts/bcm2710-rpi-zero-2.dts ++++ b/arch/arm/boot/dts/broadcom/bcm2710-rpi-zero-2.dts @@ -0,0 +1 @@ +#include "bcm2710-rpi-zero-2-w.dts" -diff --git a/arch/arm/boot/dts/bcm2710.dtsi b/arch/arm/boot/dts/bcm2710.dtsi +diff --git a/arch/arm/boot/dts/broadcom/bcm2710.dtsi b/arch/arm/boot/dts/broadcom/bcm2710.dtsi new file mode 100644 -index 000000000000..e7e5c913f1d1 +index 000000000000..bdcdbb51fab8 --- /dev/null -+++ b/arch/arm/boot/dts/bcm2710.dtsi -@@ -0,0 +1,25 @@ ++++ b/arch/arm/boot/dts/broadcom/bcm2710.dtsi +@@ -0,0 +1,32 @@ ++#define i2c0 i2c0if +#include "bcm2837.dtsi" ++#undef i2c0 +#include "bcm270x.dtsi" + +/ { @@ -6807,7 +9183,8 @@ index 000000000000..e7e5c913f1d1 + }; + + soc { -+ /delete-node/ timer@7e003000; ++ dma-ranges = <0xc0000000 0x00000000 0x3f000000>, ++ <0x7e000000 0x3f000000 0x01000000>; + }; + + __overrides__ { @@ -6818,87 +9195,85 @@ index 000000000000..e7e5c913f1d1 + }; +}; + ++&system_timer { ++ status = "disabled"; ++}; ++ +&vc4 { + status = "disabled"; +}; -diff --git a/arch/arm/boot/dts/bcm2711-rpi-4-b.dts b/arch/arm/boot/dts/bcm2711-rpi-4-b.dts -index 167538518a1e..fb44c89f3b0c 100644 ---- a/arch/arm/boot/dts/bcm2711-rpi-4-b.dts -+++ b/arch/arm/boot/dts/bcm2711-rpi-4-b.dts -@@ -2,7 +2,6 @@ +diff --git a/arch/arm/boot/dts/broadcom/bcm2711-rpi-4-b.dts b/arch/arm/boot/dts/broadcom/bcm2711-rpi-4-b.dts +index d5f8823230db..d3a3a1e4d4c6 100644 +--- a/arch/arm/boot/dts/broadcom/bcm2711-rpi-4-b.dts ++++ b/arch/arm/boot/dts/broadcom/bcm2711-rpi-4-b.dts +@@ -1,10 +1,16 @@ + // SPDX-License-Identifier: GPL-2.0 /dts-v1/; ++#define BCM2711 ++#define i2c0 i2c0if #include "bcm2711.dtsi" - #include "bcm2835-rpi.dtsi" ++#include "bcm283x-rpi-wifi-bt.dtsi" ++#undef i2c0 ++#include "bcm270x.dtsi" ++#define i2c0 i2c0mux + #include "bcm2711-rpi.dtsi" ++#undef i2c0 + #include "bcm283x-rpi-led-deprecated.dtsi" -#include "bcm283x-rpi-usb-peripheral.dtsi" +-#include "bcm283x-rpi-wifi-bt.dtsi" ++//#include "bcm283x-rpi-usb-peripheral.dtsi" - #include - -@@ -25,6 +24,7 @@ aliases { - emmc2bus = &emmc2bus; - ethernet0 = &genet; - pcie0 = &pcie0; -+ blconfig = &blconfig; - }; - - leds { -@@ -95,7 +95,7 @@ expgpio: gpio { - "VDD_SD_IO_SEL", - "CAM_GPIO", - "SD_PWR_ON", -- ""; -+ "SD_OC_N"; - status = "okay"; - }; - -@@ -181,12 +181,14 @@ &gpio { - &hdmi0 { - clocks = <&firmware_clocks 13>, <&firmware_clocks 14>, <&dvp 0>, <&clk_27MHz>; - clock-names = "hdmi", "bvb", "audio", "cec"; -+ wifi-2.4ghz-coexistence; - status = "okay"; + / { + compatible = "raspberrypi,4-model-b", "brcm,bcm2711"; +@@ -60,7 +66,7 @@ &expgpio { + "VDD_SD_IO_SEL", + "CAM_GPIO", /* 5 */ + "SD_PWR_ON", +- ""; ++ "SD_OC_N"; }; - &hdmi1 { - clocks = <&firmware_clocks 13>, <&firmware_clocks 14>, <&dvp 1>, <&clk_27MHz>; - clock-names = "hdmi", "bvb", "audio", "cec"; -+ wifi-2.4ghz-coexistence; - status = "okay"; - }; - -@@ -216,6 +218,22 @@ &pwm1 { - status = "okay"; - }; - -+&rmem { -+ /* -+ * RPi4's co-processor will copy the board's bootloader configuration -+ * into memory for the OS to consume. It'll also update this node with -+ * its placement information. -+ */ -+ blconfig: nvram@0 { -+ compatible = "raspberrypi,bootloader-config", "nvmem-rmem"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ reg = <0x0 0x0 0x0>; -+ no-map; -+ status = "disabled"; -+ }; -+}; -+ - /* SDHCI is used to control the SDIO for wireless */ - &sdhci { - #address-cells = <1>; -@@ -302,3 +320,311 @@ &vc4 { - &vec { - status = "disabled"; + &gpio { +@@ -74,21 +80,21 @@ &gpio { + */ + gpio-line-names = "ID_SDA", /* 0 */ + "ID_SCL", +- "SDA1", +- "SCL1", +- "GPIO_GCLK", ++ "GPIO2", ++ "GPIO3", ++ "GPIO4", + "GPIO5", /* 5 */ + "GPIO6", +- "SPI_CE1_N", +- "SPI_CE0_N", +- "SPI_MISO", +- "SPI_MOSI", /* 10 */ +- "SPI_SCLK", ++ "GPIO7", ++ "GPIO8", ++ "GPIO9", ++ "GPIO10", /* 10 */ ++ "GPIO11", + "GPIO12", + "GPIO13", + /* Serial port */ +- "TXD1", +- "RXD1", /* 15 */ ++ "GPIO14", ++ "GPIO15", /* 15 */ + "GPIO16", + "GPIO17", + "GPIO18", +@@ -241,3 +247,233 @@ &vec { + &wifi_pwrseq { + reset-gpios = <&expgpio 1 GPIO_ACTIVE_LOW>; }; + +// ============================================= +// Downstream rpi- changes + -+#define BCM2711 -+ -+#include "bcm270x.dtsi" +#include "bcm271x-rpi-bt.dtsi" + +/ { @@ -6908,32 +9283,13 @@ index 167538518a1e..fb44c89f3b0c 100644 + }; +}; + -+#include "bcm2711-rpi.dtsi" ++#include "bcm2711-rpi-ds.dtsi" +#include "bcm283x-rpi-csi1-2lane.dtsi" +#include "bcm283x-rpi-i2c0mux_0_44.dtsi" + +/ { + chosen { -+ bootargs = "coherent_pool=1M 8250.nr_uarts=1 snd_bcm2835.enable_compat_alsa=0 snd_bcm2835.enable_hdmi=1"; -+ }; -+ -+ aliases { -+ serial0 = &uart1; -+ serial1 = &uart0; -+ mmc0 = &emmc2; -+ mmc1 = &mmcnr; -+ mmc2 = &sdhost; -+ i2c3 = &i2c3; -+ i2c4 = &i2c4; -+ i2c5 = &i2c5; -+ i2c6 = &i2c6; -+ i2c20 = &ddc0; -+ i2c21 = &ddc1; -+ spi3 = &spi3; -+ spi4 = &spi4; -+ spi5 = &spi5; -+ spi6 = &spi6; -+ /delete-property/ intc; ++ bootargs = "coherent_pool=1M 8250.nr_uarts=1 snd_bcm2835.enable_headphones=0"; + }; + + /delete-node/ wifi-pwrseq; @@ -6978,102 +9334,67 @@ index 167538518a1e..fb44c89f3b0c 100644 +}; + +&gpio { -+ spi0_pins: spi0_pins { -+ brcm,pins = <9 10 11>; -+ brcm,function = ; -+ }; -+ -+ spi0_cs_pins: spi0_cs_pins { -+ brcm,pins = <8 7>; -+ brcm,function = ; -+ }; -+ -+ spi3_pins: spi3_pins { -+ brcm,pins = <1 2 3>; -+ brcm,function = ; -+ }; -+ -+ spi3_cs_pins: spi3_cs_pins { -+ brcm,pins = <0 24>; -+ brcm,function = ; -+ }; -+ -+ spi4_pins: spi4_pins { -+ brcm,pins = <5 6 7>; -+ brcm,function = ; -+ }; -+ -+ spi4_cs_pins: spi4_cs_pins { -+ brcm,pins = <4 25>; -+ brcm,function = ; -+ }; -+ -+ spi5_pins: spi5_pins { -+ brcm,pins = <13 14 15>; -+ brcm,function = ; -+ }; -+ -+ spi5_cs_pins: spi5_cs_pins { -+ brcm,pins = <12 26>; -+ brcm,function = ; -+ }; -+ -+ spi6_pins: spi6_pins { -+ brcm,pins = <19 20 21>; -+ brcm,function = ; -+ }; -+ -+ spi6_cs_pins: spi6_cs_pins { -+ brcm,pins = <18 27>; -+ brcm,function = ; -+ }; -+ -+ i2c0_pins: i2c0 { -+ brcm,pins = <0 1>; -+ brcm,function = ; -+ brcm,pull = ; -+ }; -+ -+ i2c1_pins: i2c1 { -+ brcm,pins = <2 3>; -+ brcm,function = ; -+ brcm,pull = ; -+ }; -+ -+ i2c3_pins: i2c3 { -+ brcm,pins = <4 5>; -+ brcm,function = ; -+ brcm,pull = ; -+ }; -+ -+ i2c4_pins: i2c4 { -+ brcm,pins = <8 9>; -+ brcm,function = ; -+ brcm,pull = ; -+ }; -+ -+ i2c5_pins: i2c5 { -+ brcm,pins = <12 13>; -+ brcm,function = ; -+ brcm,pull = ; -+ }; -+ -+ i2c6_pins: i2c6 { -+ brcm,pins = <22 23>; -+ brcm,function = ; -+ brcm,pull = ; -+ }; -+ -+ i2s_pins: i2s { -+ brcm,pins = <18 19 20 21>; -+ brcm,function = ; -+ }; -+ -+ sdio_pins: sdio_pins { -+ brcm,pins = <34 35 36 37 38 39>; -+ brcm,function = ; // alt3 = SD1 -+ brcm,pull = <0 2 2 2 2 2>; -+ }; ++ gpio-line-names = "ID_SDA", ++ "ID_SCL", ++ "GPIO2", ++ "GPIO3", ++ "GPIO4", ++ "GPIO5", ++ "GPIO6", ++ "GPIO7", ++ "GPIO8", ++ "GPIO9", ++ "GPIO10", ++ "GPIO11", ++ "GPIO12", ++ "GPIO13", ++ "GPIO14", ++ "GPIO15", ++ "GPIO16", ++ "GPIO17", ++ "GPIO18", ++ "GPIO19", ++ "GPIO20", ++ "GPIO21", ++ "GPIO22", ++ "GPIO23", ++ "GPIO24", ++ "GPIO25", ++ "GPIO26", ++ "GPIO27", ++ "RGMII_MDIO", ++ "RGMIO_MDC", ++ /* Used by BT module */ ++ "CTS0", /* 30 */ ++ "RTS0", ++ "TXD0", ++ "RXD0", ++ /* Used by Wifi */ ++ "SD1_CLK", ++ "SD1_CMD", /* 35 */ ++ "SD1_DATA0", ++ "SD1_DATA1", ++ "SD1_DATA2", ++ "SD1_DATA3", ++ /* Shared with SPI flash */ ++ "PWM0_MISO", /* 40 */ ++ "PWM1_MOSI", ++ "STATUS_LED_G_CLK", ++ "SPIFLASH_CE_N", ++ "SDA0", ++ "SCL0", /* 45 */ ++ "RGMII_RXCLK", ++ "RGMII_RXCTL", ++ "RGMII_RXD0", ++ "RGMII_RXD1", ++ "RGMII_RXD2", /* 50 */ ++ "RGMII_RXD3", ++ "RGMII_TXCLK", ++ "RGMII_TXCTL", ++ "RGMII_TXD0", ++ "RGMII_TXD1", /* 55 */ ++ "RGMII_TXD2", ++ "RGMII_TXD3"; + + bt_pins: bt_pins { + brcm,pins = "-"; // non-empty to keep btuart happy, //4 = 0 @@ -7094,28 +9415,10 @@ index 167538518a1e..fb44c89f3b0c 100644 + brcm,pull; + }; + -+ uart2_pins: uart2_pins { -+ brcm,pins = <0 1>; -+ brcm,function = ; -+ brcm,pull = <0 2>; -+ }; -+ -+ uart3_pins: uart3_pins { -+ brcm,pins = <4 5>; -+ brcm,function = ; -+ brcm,pull = <0 2>; -+ }; -+ -+ uart4_pins: uart4_pins { -+ brcm,pins = <8 9>; -+ brcm,function = ; -+ brcm,pull = <0 2>; -+ }; -+ -+ uart5_pins: uart5_pins { -+ brcm,pins = <12 13>; -+ brcm,function = ; -+ brcm,pull = <0 2>; ++ uart1_bt_pins: uart1_bt_pins { ++ brcm,pins = <32 33 30 31>; ++ brcm,function = ; /* alt5=UART1 */ ++ brcm,pull = <0 2 2 0>; + }; +}; + @@ -7149,28 +9452,24 @@ index 167538518a1e..fb44c89f3b0c 100644 + audio_pins: audio_pins { + brcm,pins = <40 41>; + brcm,function = <4>; ++ brcm,pull = <0>; + }; +}; + -+&leds { -+ act_led: led-act { -+ label = "led0"; -+ linux,default-trigger = "mmc0"; -+ gpios = <&gpio 42 GPIO_ACTIVE_HIGH>; -+ }; ++&led_act { ++ default-state = "off"; ++ linux,default-trigger = "mmc0"; ++}; + -+ pwr_led: led-pwr { -+ label = "led1"; -+ linux,default-trigger = "default-on"; -+ gpios = <&expgpio 2 GPIO_ACTIVE_LOW>; -+ }; ++&led_pwr { ++ default-state = "off"; +}; + +&pwm1 { + status = "disabled"; +}; + -+&audio { ++&vchiq { + pinctrl-names = "default"; + pinctrl-0 = <&audio_pins>; +}; @@ -7182,677 +9481,104 @@ index 167538518a1e..fb44c89f3b0c 100644 +cam0_reg: &cam_dummy_reg { +}; + ++i2c_csi_dsi0: &i2c0 { ++}; ++ +/ { + __overrides__ { -+ act_led_gpio = <&act_led>,"gpios:4"; -+ act_led_activelow = <&act_led>,"gpios:8"; -+ act_led_trigger = <&act_led>,"linux,default-trigger"; ++ audio = <&chosen>,"bootargs{on='snd_bcm2835.enable_headphones=1 snd_bcm2835.enable_hdmi=1',off='snd_bcm2835.enable_headphones=0 snd_bcm2835.enable_hdmi=0'}"; + -+ pwr_led_gpio = <&pwr_led>,"gpios:4"; -+ pwr_led_activelow = <&pwr_led>,"gpios:8"; -+ pwr_led_trigger = <&pwr_led>,"linux,default-trigger"; ++ act_led_gpio = <&led_act>,"gpios:4"; ++ act_led_activelow = <&led_act>,"gpios:8"; ++ act_led_trigger = <&led_act>,"linux,default-trigger"; ++ ++ pwr_led_gpio = <&led_pwr>,"gpios:4"; ++ pwr_led_activelow = <&led_pwr>,"gpios:8"; ++ pwr_led_trigger = <&led_pwr>,"linux,default-trigger"; + + eth_led0 = <&phy1>,"led-modes:0"; + eth_led1 = <&phy1>,"led-modes:4"; -+ -+ sd_poll_once = <&emmc2>, "non-removable?"; -+ spi_dma4 = <&spi0>, "dmas:0=", <&dma40>, -+ <&spi0>, "dmas:8=", <&dma40>; + }; +}; -diff --git a/arch/arm/boot/dts/bcm2711-rpi-400.dts b/arch/arm/boot/dts/bcm2711-rpi-400.dts -new file mode 100644 -index 000000000000..ec0c75810754 ---- /dev/null -+++ b/arch/arm/boot/dts/bcm2711-rpi-400.dts -@@ -0,0 +1,637 @@ -+// SPDX-License-Identifier: GPL-2.0 -+/dts-v1/; -+#include "bcm2711.dtsi" -+#include "bcm2835-rpi.dtsi" -+ -+#include -+ -+/ { -+ compatible = "raspberrypi,400", "brcm,bcm2711"; -+ model = "Raspberry Pi 400"; -+ -+ chosen { -+ /* 8250 auxiliary UART instead of pl011 */ -+ stdout-path = "serial1:115200n8"; -+ }; -+ -+ /* Will be filled by the bootloader */ -+ memory@0 { -+ device_type = "memory"; -+ reg = <0 0 0>; -+ }; -+ -+ aliases { -+ emmc2bus = &emmc2bus; -+ ethernet0 = &genet; -+ pcie0 = &pcie0; -+ blconfig = &blconfig; -+ }; -+ -+ leds { -+ led-act { -+ gpios = <&gpio 42 GPIO_ACTIVE_HIGH>; -+ }; -+ -+ led-pwr { -+ label = "PWR"; -+ gpios = <&expgpio 2 GPIO_ACTIVE_LOW>; -+ default-state = "keep"; -+ linux,default-trigger = "default-on"; -+ }; -+ }; -+ -+ wifi_pwrseq: wifi-pwrseq { -+ compatible = "mmc-pwrseq-simple"; -+ reset-gpios = <&expgpio 1 GPIO_ACTIVE_LOW>; -+ }; -+ -+ sd_io_1v8_reg: sd_io_1v8_reg { -+ compatible = "regulator-gpio"; -+ regulator-name = "vdd-sd-io"; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-boot-on; -+ regulator-always-on; -+ regulator-settling-time-us = <5000>; -+ gpios = <&expgpio 4 GPIO_ACTIVE_HIGH>; -+ states = <1800000 0x1 -+ 3300000 0x0>; -+ status = "okay"; -+ }; -+ -+ sd_vcc_reg: sd_vcc_reg { -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc-sd"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-boot-on; -+ enable-active-high; -+ gpio = <&expgpio 6 GPIO_ACTIVE_HIGH>; -+ }; -+}; -+ -+&ddc0 { -+ status = "okay"; -+}; -+ -+&ddc1 { -+ status = "okay"; -+}; -+ -+&firmware { -+ firmware_clocks: clocks { -+ compatible = "raspberrypi,firmware-clocks"; -+ #clock-cells = <1>; -+ }; -+ -+ expgpio: gpio { -+ compatible = "raspberrypi,firmware-gpio"; -+ gpio-controller; -+ #gpio-cells = <2>; -+ gpio-line-names = "BT_ON", -+ "WL_ON", -+ "PWR_LED_OFF", -+ "GLOBAL_RESET", -+ "VDD_SD_IO_SEL", -+ "GLOBAL_SHUTDOWN", -+ "SD_PWR_ON", -+ "SHUTDOWN_REQUEST"; -+ status = "okay"; -+ }; -+ -+ reset: reset { -+ compatible = "raspberrypi,firmware-reset"; -+ #reset-cells = <1>; -+ }; -+}; -+ -+&gpio { -+ /* -+ * Parts taken from rpi_SCH_4b_4p0_reduced.pdf and -+ * the official GPU firmware DT blob. -+ * -+ * Legend: -+ * "FOO" = GPIO line named "FOO" on the schematic -+ * "FOO_N" = GPIO line named "FOO" on schematic, active low -+ */ -+ gpio-line-names = "ID_SDA", -+ "ID_SCL", -+ "SDA1", -+ "SCL1", -+ "GPIO_GCLK", -+ "GPIO5", -+ "GPIO6", -+ "SPI_CE1_N", -+ "SPI_CE0_N", -+ "SPI_MISO", -+ "SPI_MOSI", -+ "SPI_SCLK", -+ "GPIO12", -+ "GPIO13", -+ /* Serial port */ -+ "TXD1", -+ "RXD1", -+ "GPIO16", -+ "GPIO17", -+ "GPIO18", -+ "GPIO19", -+ "GPIO20", -+ "GPIO21", -+ "GPIO22", -+ "GPIO23", -+ "GPIO24", -+ "GPIO25", -+ "GPIO26", -+ "GPIO27", -+ "RGMII_MDIO", -+ "RGMIO_MDC", -+ /* Used by BT module */ -+ "CTS0", -+ "RTS0", -+ "TXD0", -+ "RXD0", -+ /* Used by Wifi */ -+ "SD1_CLK", -+ "SD1_CMD", -+ "SD1_DATA0", -+ "SD1_DATA1", -+ "SD1_DATA2", -+ "SD1_DATA3", -+ /* Shared with SPI flash */ -+ "PWM0_MISO", -+ "PWM1_MOSI", -+ "STATUS_LED_G_CLK", -+ "SPIFLASH_CE_N", -+ "SDA0", -+ "SCL0", -+ "RGMII_RXCLK", -+ "RGMII_RXCTL", -+ "RGMII_RXD0", -+ "RGMII_RXD1", -+ "RGMII_RXD2", -+ "RGMII_RXD3", -+ "RGMII_TXCLK", -+ "RGMII_TXCTL", -+ "RGMII_TXD0", -+ "RGMII_TXD1", -+ "RGMII_TXD2", -+ "RGMII_TXD3"; -+}; -+ -+&hdmi0 { -+ clocks = <&firmware_clocks 13>, <&firmware_clocks 14>, <&dvp 0>, <&clk_27MHz>; -+ clock-names = "hdmi", "bvb", "audio", "cec"; -+ wifi-2.4ghz-coexistence; -+ status = "okay"; -+}; -+ -+&hdmi1 { -+ clocks = <&firmware_clocks 13>, <&firmware_clocks 14>, <&dvp 1>, <&clk_27MHz>; -+ clock-names = "hdmi", "bvb", "audio", "cec"; -+ wifi-2.4ghz-coexistence; -+ status = "okay"; -+}; -+ -+&hvs { -+ clocks = <&firmware_clocks 4>; -+}; -+ -+&pixelvalve0 { -+ status = "okay"; -+}; -+ -+&pixelvalve1 { -+ status = "okay"; -+}; -+ -+&pixelvalve2 { -+ status = "okay"; -+}; -+ -+&pixelvalve4 { -+ status = "okay"; -+}; -+ -+&pwm1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pwm1_0_gpio40 &pwm1_1_gpio41>; -+ status = "okay"; -+}; -+ -+&rmem { -+ /* -+ * RPi4's co-processor will copy the board's bootloader configuration -+ * into memory for the OS to consume. It'll also update this node with -+ * its placement information. -+ */ -+ blconfig: nvram@0 { -+ compatible = "raspberrypi,bootloader-config", "nvmem-rmem"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ reg = <0x0 0x0 0x0>; -+ no-map; -+ status = "disabled"; -+ }; -+}; -+ -+/* SDHCI is used to control the SDIO for wireless */ -+&sdhci { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&emmc_gpio34>; -+ bus-width = <4>; -+ non-removable; -+ mmc-pwrseq = <&wifi_pwrseq>; -+ status = "okay"; -+ -+ brcmf: wifi@1 { -+ reg = <1>; -+ compatible = "brcm,bcm4329-fmac"; -+ }; -+}; -+ -+/* EMMC2 is used to drive the SD card */ -+&emmc2 { -+ vqmmc-supply = <&sd_io_1v8_reg>; -+ vmmc-supply = <&sd_vcc_reg>; -+ broken-cd; -+ status = "okay"; -+}; -+ -+&genet { -+ phy-handle = <&phy1>; -+ phy-mode = "rgmii-rxid"; -+ status = "okay"; -+}; -+ -+&genet_mdio { -+ phy1: ethernet-phy@1 { -+ /* No PHY interrupt */ -+ reg = <0x1>; -+ }; -+}; -+ -+&pcie0 { -+ pci@0,0 { -+ device_type = "pci"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ ranges; -+ -+ reg = <0 0 0 0 0>; -+ -+ usb@0,0 { -+ reg = <0 0 0 0 0>; -+ resets = <&reset RASPBERRYPI_FIRMWARE_RESET_ID_USB>; -+ }; -+ }; -+}; -+ -+/* uart0 communicates with the BT module */ -+&uart0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&uart0_ctsrts_gpio30 &uart0_gpio32>; -+ uart-has-rtscts; -+ status = "okay"; -+ -+ bluetooth { -+ compatible = "brcm,bcm43438-bt"; -+ max-speed = <2000000>; -+ shutdown-gpios = <&expgpio 0 GPIO_ACTIVE_HIGH>; -+ }; -+}; -+ -+/* uart1 is mapped to the pin header */ -+&uart1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&uart1_gpio14>; -+ status = "okay"; -+}; -+ -+&vchiq { -+ interrupts = ; -+}; -+ -+&vc4 { -+ status = "okay"; -+}; -+ -+&vec { -+ status = "disabled"; -+}; +diff --git a/arch/arm/boot/dts/broadcom/bcm2711-rpi-400.dts b/arch/arm/boot/dts/broadcom/bcm2711-rpi-400.dts +index 5a2869a18bd5..d5b81b889018 100644 +--- a/arch/arm/boot/dts/broadcom/bcm2711-rpi-400.dts ++++ b/arch/arm/boot/dts/broadcom/bcm2711-rpi-400.dts +@@ -36,8 +36,53 @@ &led_pwr { + gpios = <&gpio 42 GPIO_ACTIVE_HIGH>; + }; + +-/delete-node/ &led_act; +- + &pm { + /delete-property/ system-power-controller; + }; + +// ============================================= +// Downstream rpi- changes + -+#define BCM2711 -+ -+#include "bcm270x.dtsi" -+#include "bcm271x-rpi-bt.dtsi" -+ -+/ { -+ soc { -+ /delete-node/ pixelvalve@7e807000; -+ /delete-node/ hdmi@7e902000; -+ }; -+}; -+ -+#include "bcm2711-rpi.dtsi" -+#include "bcm283x-rpi-csi1-2lane.dtsi" -+#include "bcm283x-rpi-i2c0mux_0_44.dtsi" -+ +/ { + chosen { -+ bootargs = "coherent_pool=1M 8250.nr_uarts=1 snd_bcm2835.enable_compat_alsa=0 snd_bcm2835.enable_hdmi=1"; -+ }; -+ -+ aliases { -+ serial0 = &uart1; -+ serial1 = &uart0; -+ mmc0 = &emmc2; -+ mmc1 = &mmcnr; -+ mmc2 = &sdhost; -+ i2c3 = &i2c3; -+ i2c4 = &i2c4; -+ i2c5 = &i2c5; -+ i2c6 = &i2c6; -+ i2c20 = &ddc0; -+ i2c21 = &ddc1; -+ spi3 = &spi3; -+ spi4 = &spi4; -+ spi5 = &spi5; -+ spi6 = &spi6; -+ /delete-property/ intc; -+ }; -+ -+ /delete-node/ wifi-pwrseq; -+}; -+ -+&mmcnr { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&sdio_pins>; -+ bus-width = <4>; -+ status = "okay"; -+}; -+ -+&uart0 { -+ pinctrl-0 = <&uart0_pins &bt_pins>; -+ status = "okay"; -+}; -+ -+&uart1 { -+ pinctrl-0 = <&uart1_pins>; -+}; -+ -+&spi0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&spi0_pins &spi0_cs_pins>; -+ cs-gpios = <&gpio 8 1>, <&gpio 7 1>; -+ -+ spidev0: spidev@0{ -+ compatible = "spidev"; -+ reg = <0>; /* CE0 */ -+ #address-cells = <1>; -+ #size-cells = <0>; -+ spi-max-frequency = <125000000>; -+ }; -+ -+ spidev1: spidev@1{ -+ compatible = "spidev"; -+ reg = <1>; /* CE1 */ -+ #address-cells = <1>; -+ #size-cells = <0>; -+ spi-max-frequency = <125000000>; ++ stdout-path = "serial0:115200n8"; + }; +}; + -+&gpio { -+ spi0_pins: spi0_pins { -+ brcm,pins = <9 10 11>; -+ brcm,function = ; -+ }; -+ -+ spi0_cs_pins: spi0_cs_pins { -+ brcm,pins = <8 7>; -+ brcm,function = ; -+ }; -+ -+ spi3_pins: spi3_pins { -+ brcm,pins = <1 2 3>; -+ brcm,function = ; -+ }; -+ -+ spi3_cs_pins: spi3_cs_pins { -+ brcm,pins = <0 24>; -+ brcm,function = ; -+ }; -+ -+ spi4_pins: spi4_pins { -+ brcm,pins = <5 6 7>; -+ brcm,function = ; -+ }; -+ -+ spi4_cs_pins: spi4_cs_pins { -+ brcm,pins = <4 25>; -+ brcm,function = ; -+ }; -+ -+ spi5_pins: spi5_pins { -+ brcm,pins = <13 14 15>; -+ brcm,function = ; -+ }; -+ -+ spi5_cs_pins: spi5_cs_pins { -+ brcm,pins = <12 26>; -+ brcm,function = ; -+ }; -+ -+ spi6_pins: spi6_pins { -+ brcm,pins = <19 20 21>; -+ brcm,function = ; -+ }; -+ -+ spi6_cs_pins: spi6_cs_pins { -+ brcm,pins = <18 27>; -+ brcm,function = ; -+ }; -+ -+ i2c0_pins: i2c0 { -+ brcm,pins = <0 1>; -+ brcm,function = ; -+ brcm,pull = ; -+ }; -+ -+ i2c1_pins: i2c1 { -+ brcm,pins = <2 3>; -+ brcm,function = ; -+ brcm,pull = ; -+ }; -+ -+ i2c3_pins: i2c3 { -+ brcm,pins = <4 5>; -+ brcm,function = ; -+ brcm,pull = ; -+ }; -+ -+ i2c4_pins: i2c4 { -+ brcm,pins = <8 9>; -+ brcm,function = ; -+ brcm,pull = ; -+ }; -+ -+ i2c5_pins: i2c5 { -+ brcm,pins = <12 13>; -+ brcm,function = ; -+ brcm,pull = ; -+ }; -+ -+ i2c6_pins: i2c6 { -+ brcm,pins = <22 23>; -+ brcm,function = ; -+ brcm,pull = ; -+ }; -+ -+ i2s_pins: i2s { -+ brcm,pins = <18 19 20 21>; -+ brcm,function = ; -+ }; -+ -+ sdio_pins: sdio_pins { -+ brcm,pins = <34 35 36 37 38 39>; -+ brcm,function = ; // alt3 = SD1 -+ brcm,pull = <0 2 2 2 2 2>; -+ }; -+ -+ bt_pins: bt_pins { -+ brcm,pins = "-"; // non-empty to keep btuart happy, //4 = 0 -+ // to fool pinctrl -+ brcm,function = <0>; -+ brcm,pull = <2>; -+ }; -+ -+ uart0_pins: uart0_pins { -+ brcm,pins = <32 33>; -+ brcm,function = ; -+ brcm,pull = <0 2>; -+ }; -+ -+ uart1_pins: uart1_pins { -+ brcm,pins; -+ brcm,function; -+ brcm,pull; -+ }; -+ -+ uart2_pins: uart2_pins { -+ brcm,pins = <0 1>; -+ brcm,function = ; -+ brcm,pull = <0 2>; -+ }; -+ -+ uart3_pins: uart3_pins { -+ brcm,pins = <4 5>; -+ brcm,function = ; -+ brcm,pull = <0 2>; -+ }; -+ -+ uart4_pins: uart4_pins { -+ brcm,pins = <8 9>; -+ brcm,function = ; -+ brcm,pull = <0 2>; -+ }; -+ -+ uart5_pins: uart5_pins { -+ brcm,pins = <12 13>; -+ brcm,function = ; -+ brcm,pull = <0 2>; -+ }; ++&audio_pins { ++ brcm,pins = <>; ++ brcm,function = <>; +}; + -+&i2c0if { -+ clock-frequency = <100000>; -+}; -+ -+&i2c1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c1_pins>; -+ clock-frequency = <100000>; -+}; -+ -+&i2s { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2s_pins>; -+}; -+ -+// ============================================= -+// Board specific stuff here -+ -+/ { -+ power_ctrl: power_ctrl { -+ compatible = "gpio-poweroff"; -+ gpios = <&expgpio 5 0>; -+ force; -+ }; -+}; -+ -+&sdhost { ++// Declare the LED but leave it disabled, in case a user wants to map it ++// to a GPIO on the header ++&led_act { ++ default-state = "off"; ++ gpios = <&gpio 0 GPIO_ACTIVE_HIGH>; + status = "disabled"; +}; + -+&phy1 { -+ led-modes = <0x00 0x08>; /* link/activity link */ ++&led_pwr { ++ default-state = "off"; +}; + -+&gpio { -+ audio_pins: audio_pins { -+ brcm,pins = <>; -+ brcm,function = <>; -+ }; ++&cam1_reg { ++ /delete-property/ gpio; +}; + -+&leds { -+ act_led: led-act { -+ label = "led0"; -+ linux,default-trigger = "default-on"; -+ default-state = "on"; -+ gpios = <&gpio 42 GPIO_ACTIVE_HIGH>; -+ }; -+ -+ pwr_led: led-pwr { -+ label = "led1"; -+ linux,default-trigger = "default-on"; -+ gpios = <&expgpio 2 GPIO_ACTIVE_LOW>; -+ }; -+}; -+ -+&pwm1 { -+ status = "disabled"; -+}; -+ -+&audio { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&audio_pins>; -+ brcm,disable-headphones = <1>; -+}; -+ -+&genet_mdio { -+ clock-frequency = <1950000>; ++cam0_reg: &cam_dummy_reg { +}; + +/ { + __overrides__ { -+ act_led_gpio = <&act_led>,"gpios:4"; -+ act_led_activelow = <&act_led>,"gpios:8"; -+ act_led_trigger = <&act_led>,"linux,default-trigger"; ++ audio = <&chosen>,"bootargs{on='snd_bcm2835.enable_hdmi=1',off='snd_bcm2835.enable_hdmi=0'}"; + -+ pwr_led_gpio = <&pwr_led>,"gpios:4"; -+ pwr_led_activelow = <&pwr_led>,"gpios:8"; -+ pwr_led_trigger = <&pwr_led>,"linux,default-trigger"; -+ -+ eth_led0 = <&phy1>,"led-modes:0"; -+ eth_led1 = <&phy1>,"led-modes:4"; -+ -+ sd_poll_once = <&emmc2>, "non-removable?"; -+ spi_dma4 = <&spi0>, "dmas:0=", <&dma40>, -+ <&spi0>, "dmas:8=", <&dma40>; ++ act_led_gpio = <&led_act>,"gpios:4", ++ <&led_act>,"status=okay"; ++ act_led_activelow = <&led_act>,"gpios:8"; ++ act_led_trigger = <&led_act>,"linux,default-trigger"; ++ pwr_led_gpio = <&led_pwr>,"gpios:4"; ++ pwr_led_activelow = <&led_pwr>,"gpios:8"; ++ pwr_led_trigger = <&led_pwr>,"linux,default-trigger"; + }; +}; -diff --git a/arch/arm/boot/dts/bcm2711-rpi-cm4.dts b/arch/arm/boot/dts/bcm2711-rpi-cm4.dts +diff --git a/arch/arm/boot/dts/broadcom/bcm2711-rpi-cm4.dts b/arch/arm/boot/dts/broadcom/bcm2711-rpi-cm4.dts new file mode 100644 -index 000000000000..5dbd1b77260b +index 000000000000..9fdb9278c5a2 --- /dev/null -+++ b/arch/arm/boot/dts/bcm2711-rpi-cm4.dts -@@ -0,0 +1,652 @@ ++++ b/arch/arm/boot/dts/broadcom/bcm2711-rpi-cm4.dts +@@ -0,0 +1,510 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; ++#define BCM2711 ++#define i2c0 i2c0if +#include "bcm2711.dtsi" -+#include "bcm2835-rpi.dtsi" ++#include "bcm283x-rpi-wifi-bt.dtsi" ++#undef i2c0 ++#include "bcm270x.dtsi" ++#define i2c0 i2c0mux ++#include "bcm2711-rpi.dtsi" ++#undef i2c0 ++#include "bcm283x-rpi-led-deprecated.dtsi" ++//#include "bcm283x-rpi-usb-peripheral.dtsi" + +/ { + compatible = "raspberrypi,4-compute-module", "brcm,bcm2711"; @@ -7863,37 +9589,6 @@ index 000000000000..5dbd1b77260b + stdout-path = "serial1:115200n8"; + }; + -+ /* Will be filled by the bootloader */ -+ memory@0 { -+ device_type = "memory"; -+ reg = <0 0 0>; -+ }; -+ -+ aliases { -+ emmc2bus = &emmc2bus; -+ ethernet0 = &genet; -+ pcie0 = &pcie0; -+ blconfig = &blconfig; -+ }; -+ -+ leds { -+ led-act { -+ gpios = <&gpio 42 GPIO_ACTIVE_HIGH>; -+ }; -+ -+ led-pwr { -+ label = "PWR"; -+ gpios = <&expgpio 2 GPIO_ACTIVE_LOW>; -+ default-state = "keep"; -+ linux,default-trigger = "default-on"; -+ }; -+ }; -+ -+ wifi_pwrseq: wifi-pwrseq { -+ compatible = "mmc-pwrseq-simple"; -+ reset-gpios = <&expgpio 1 GPIO_ACTIVE_LOW>; -+ }; -+ + sd_io_1v8_reg: sd_io_1v8_reg { + compatible = "regulator-gpio"; + regulator-name = "vdd-sd-io"; @@ -7903,8 +9598,8 @@ index 000000000000..5dbd1b77260b + regulator-always-on; + regulator-settling-time-us = <5000>; + gpios = <&expgpio 4 GPIO_ACTIVE_HIGH>; -+ states = <1800000 0x1 -+ 3300000 0x0>; ++ states = <1800000 0x1>, ++ <3300000 0x0>; + status = "okay"; + }; + @@ -7919,6 +9614,10 @@ index 000000000000..5dbd1b77260b + }; +}; + ++&bt { ++ shutdown-gpios = <&expgpio 0 GPIO_ACTIVE_HIGH>; ++}; ++ +&ddc0 { + status = "okay"; +}; @@ -7927,42 +9626,26 @@ index 000000000000..5dbd1b77260b + status = "okay"; +}; + -+&firmware { -+ firmware_clocks: clocks { -+ compatible = "raspberrypi,firmware-clocks"; -+ #clock-cells = <1>; ++&expgpio { ++ gpio-line-names = "BT_ON", ++ "WL_ON", ++ "PWR_LED_OFF", ++ "ANT1", ++ "VDD_SD_IO_SEL", ++ "CAM_GPIO", ++ "SD_PWR_ON", ++ "ANT2"; ++ ++ ant1: ant1 { ++ gpio-hog; ++ gpios = <3 GPIO_ACTIVE_HIGH>; ++ output-high; + }; + -+ expgpio: gpio { -+ compatible = "raspberrypi,firmware-gpio"; -+ gpio-controller; -+ #gpio-cells = <2>; -+ gpio-line-names = "BT_ON", -+ "WL_ON", -+ "PWR_LED_OFF", -+ "ANT1", -+ "VDD_SD_IO_SEL", -+ "CAM_GPIO", -+ "SD_PWR_ON", -+ "ANT2"; -+ status = "okay"; -+ -+ ant1: ant1 { -+ gpio-hog; -+ gpios = <3 GPIO_ACTIVE_HIGH>; -+ output-high; -+ }; -+ -+ ant2: ant2 { -+ gpio-hog; -+ gpios = <7 GPIO_ACTIVE_HIGH>; -+ output-low; -+ }; -+ }; -+ -+ reset: reset { -+ compatible = "raspberrypi,firmware-reset"; -+ #reset-cells = <1>; ++ ant2: ant2 { ++ gpio-hog; ++ gpios = <7 GPIO_ACTIVE_HIGH>; ++ output-low; + }; +}; + @@ -8040,21 +9723,24 @@ index 000000000000..5dbd1b77260b +}; + +&hdmi0 { -+ clocks = <&firmware_clocks 13>, <&firmware_clocks 14>, <&dvp 0>, <&clk_27MHz>; -+ clock-names = "hdmi", "bvb", "audio", "cec"; -+ wifi-2.4ghz-coexistence; + status = "okay"; +}; + +&hdmi1 { -+ clocks = <&firmware_clocks 13>, <&firmware_clocks 14>, <&dvp 1>, <&clk_27MHz>; -+ clock-names = "hdmi", "bvb", "audio", "cec"; -+ wifi-2.4ghz-coexistence; + status = "okay"; +}; + -+&hvs { -+ clocks = <&firmware_clocks 4>; ++&led_act { ++ gpios = <&gpio 42 GPIO_ACTIVE_HIGH>; ++}; ++ ++&leds { ++ led_pwr: led-pwr { ++ label = "PWR"; ++ gpios = <&expgpio 2 GPIO_ACTIVE_LOW>; ++ default-state = "keep"; ++ linux,default-trigger = "default-on"; ++ }; +}; + +&pixelvalve0 { @@ -8079,39 +9765,6 @@ index 000000000000..5dbd1b77260b + status = "okay"; +}; + -+&rmem { -+ /* -+ * RPi4's co-processor will copy the board's bootloader configuration -+ * into memory for the OS to consume. It'll also update this node with -+ * its placement information. -+ */ -+ blconfig: nvram@0 { -+ compatible = "raspberrypi,bootloader-config", "nvmem-rmem"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ reg = <0x0 0x0 0x0>; -+ no-map; -+ status = "disabled"; -+ }; -+}; -+ -+/* SDHCI is used to control the SDIO for wireless */ -+&sdhci { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&emmc_gpio34>; -+ bus-width = <4>; -+ non-removable; -+ mmc-pwrseq = <&wifi_pwrseq>; -+ status = "okay"; -+ -+ brcmf: wifi@1 { -+ reg = <1>; -+ compatible = "brcm,bcm4329-fmac"; -+ }; -+}; -+ +/* EMMC2 is used to drive the EMMC card */ +&emmc2 { + bus-width = <8>; @@ -8150,13 +9803,6 @@ index 000000000000..5dbd1b77260b + pinctrl-names = "default"; + pinctrl-0 = <&uart0_ctsrts_gpio30 &uart0_gpio32>; + uart-has-rtscts; -+ status = "okay"; -+ -+ bluetooth { -+ compatible = "brcm,bcm43438-bt"; -+ max-speed = <2000000>; -+ shutdown-gpios = <&expgpio 0 GPIO_ACTIVE_HIGH>; -+ }; +}; + +/* uart1 is mapped to the pin header */ @@ -8166,10 +9812,6 @@ index 000000000000..5dbd1b77260b + status = "okay"; +}; + -+&vchiq { -+ interrupts = ; -+}; -+ +&vc4 { + status = "okay"; +}; @@ -8178,12 +9820,13 @@ index 000000000000..5dbd1b77260b + status = "disabled"; +}; + ++&wifi_pwrseq { ++ reset-gpios = <&expgpio 1 GPIO_ACTIVE_LOW>; ++}; ++ +// ============================================= +// Downstream rpi- changes + -+#define BCM2711 -+ -+#include "bcm270x.dtsi" +#include "bcm271x-rpi-bt.dtsi" + +/ { @@ -8193,33 +9836,14 @@ index 000000000000..5dbd1b77260b + }; +}; + -+#include "bcm2711-rpi.dtsi" ++#include "bcm2711-rpi-ds.dtsi" +#include "bcm283x-rpi-csi0-2lane.dtsi" +#include "bcm283x-rpi-csi1-4lane.dtsi" +#include "bcm283x-rpi-i2c0mux_0_44.dtsi" + +/ { + chosen { -+ bootargs = "coherent_pool=1M 8250.nr_uarts=1 snd_bcm2835.enable_compat_alsa=0 snd_bcm2835.enable_hdmi=1"; -+ }; -+ -+ aliases { -+ serial0 = &uart1; -+ serial1 = &uart0; -+ mmc0 = &emmc2; -+ mmc1 = &mmcnr; -+ mmc2 = &sdhost; -+ i2c3 = &i2c3; -+ i2c4 = &i2c4; -+ i2c5 = &i2c5; -+ i2c6 = &i2c6; -+ i2c20 = &ddc0; -+ i2c21 = &ddc1; -+ spi3 = &spi3; -+ spi4 = &spi4; -+ spi5 = &spi5; -+ spi6 = &spi6; -+ /delete-property/ intc; ++ bootargs = "coherent_pool=1M 8250.nr_uarts=1 snd_bcm2835.enable_headphones=0"; + }; + + /delete-node/ wifi-pwrseq; @@ -8264,102 +9888,67 @@ index 000000000000..5dbd1b77260b +}; + +&gpio { -+ spi0_pins: spi0_pins { -+ brcm,pins = <9 10 11>; -+ brcm,function = ; -+ }; -+ -+ spi0_cs_pins: spi0_cs_pins { -+ brcm,pins = <8 7>; -+ brcm,function = ; -+ }; -+ -+ spi3_pins: spi3_pins { -+ brcm,pins = <1 2 3>; -+ brcm,function = ; -+ }; -+ -+ spi3_cs_pins: spi3_cs_pins { -+ brcm,pins = <0 24>; -+ brcm,function = ; -+ }; -+ -+ spi4_pins: spi4_pins { -+ brcm,pins = <5 6 7>; -+ brcm,function = ; -+ }; -+ -+ spi4_cs_pins: spi4_cs_pins { -+ brcm,pins = <4 25>; -+ brcm,function = ; -+ }; -+ -+ spi5_pins: spi5_pins { -+ brcm,pins = <13 14 15>; -+ brcm,function = ; -+ }; -+ -+ spi5_cs_pins: spi5_cs_pins { -+ brcm,pins = <12 26>; -+ brcm,function = ; -+ }; -+ -+ spi6_pins: spi6_pins { -+ brcm,pins = <19 20 21>; -+ brcm,function = ; -+ }; -+ -+ spi6_cs_pins: spi6_cs_pins { -+ brcm,pins = <18 27>; -+ brcm,function = ; -+ }; -+ -+ i2c0_pins: i2c0 { -+ brcm,pins = <0 1>; -+ brcm,function = ; -+ brcm,pull = ; -+ }; -+ -+ i2c1_pins: i2c1 { -+ brcm,pins = <2 3>; -+ brcm,function = ; -+ brcm,pull = ; -+ }; -+ -+ i2c3_pins: i2c3 { -+ brcm,pins = <4 5>; -+ brcm,function = ; -+ brcm,pull = ; -+ }; -+ -+ i2c4_pins: i2c4 { -+ brcm,pins = <8 9>; -+ brcm,function = ; -+ brcm,pull = ; -+ }; -+ -+ i2c5_pins: i2c5 { -+ brcm,pins = <12 13>; -+ brcm,function = ; -+ brcm,pull = ; -+ }; -+ -+ i2c6_pins: i2c6 { -+ brcm,pins = <22 23>; -+ brcm,function = ; -+ brcm,pull = ; -+ }; -+ -+ i2s_pins: i2s { -+ brcm,pins = <18 19 20 21>; -+ brcm,function = ; -+ }; -+ -+ sdio_pins: sdio_pins { -+ brcm,pins = <34 35 36 37 38 39>; -+ brcm,function = ; // alt3 = SD1 -+ brcm,pull = <0 2 2 2 2 2>; -+ }; ++ gpio-line-names = "ID_SDA", ++ "ID_SCL", ++ "GPIO2", ++ "GPIO3", ++ "GPIO4", ++ "GPIO5", ++ "GPIO6", ++ "GPIO7", ++ "GPIO8", ++ "GPIO9", ++ "GPIO10", ++ "GPIO11", ++ "GPIO12", ++ "GPIO13", ++ "GPIO14", ++ "GPIO15", ++ "GPIO16", ++ "GPIO17", ++ "GPIO18", ++ "GPIO19", ++ "GPIO20", ++ "GPIO21", ++ "GPIO22", ++ "GPIO23", ++ "GPIO24", ++ "GPIO25", ++ "GPIO26", ++ "GPIO27", ++ "RGMII_MDIO", ++ "RGMIO_MDC", ++ /* Used by BT module */ ++ "CTS0", ++ "RTS0", ++ "TXD0", ++ "RXD0", ++ /* Used by Wifi */ ++ "SD1_CLK", ++ "SD1_CMD", ++ "SD1_DATA0", ++ "SD1_DATA1", ++ "SD1_DATA2", ++ "SD1_DATA3", ++ /* Shared with SPI flash */ ++ "PWM0_MISO", ++ "PWM1_MOSI", ++ "STATUS_LED_G_CLK", ++ "SPIFLASH_CE_N", ++ "SDA0", ++ "SCL0", ++ "RGMII_RXCLK", ++ "RGMII_RXCTL", ++ "RGMII_RXD0", ++ "RGMII_RXD1", ++ "RGMII_RXD2", ++ "RGMII_RXD3", ++ "RGMII_TXCLK", ++ "RGMII_TXCTL", ++ "RGMII_TXD0", ++ "RGMII_TXD1", ++ "RGMII_TXD2", ++ "RGMII_TXD3"; + + bt_pins: bt_pins { + brcm,pins = "-"; // non-empty to keep btuart happy, //4 = 0 @@ -8380,28 +9969,10 @@ index 000000000000..5dbd1b77260b + brcm,pull; + }; + -+ uart2_pins: uart2_pins { -+ brcm,pins = <0 1>; -+ brcm,function = ; -+ brcm,pull = <0 2>; -+ }; -+ -+ uart3_pins: uart3_pins { -+ brcm,pins = <4 5>; -+ brcm,function = ; -+ brcm,pull = <0 2>; -+ }; -+ -+ uart4_pins: uart4_pins { -+ brcm,pins = <8 9>; -+ brcm,function = ; -+ brcm,pull = <0 2>; -+ }; -+ -+ uart5_pins: uart5_pins { -+ brcm,pins = <12 13>; -+ brcm,function = ; -+ brcm,pull = <0 2>; ++ uart1_bt_pins: uart1_bt_pins { ++ brcm,pins = <32 33 30 31>; ++ brcm,function = ; /* alt5=UART1 */ ++ brcm,pull = <0 2 2 0>; + }; +}; + @@ -8442,43 +10013,42 @@ index 000000000000..5dbd1b77260b + }; +}; + -+&leds { -+ act_led: led-act { -+ label = "led0"; -+ linux,default-trigger = "mmc0"; -+ gpios = <&gpio 42 GPIO_ACTIVE_HIGH>; -+ }; ++&led_act { ++ default-state = "off"; ++ linux,default-trigger = "mmc0"; ++}; + -+ pwr_led: led-pwr { -+ label = "led1"; -+ linux,default-trigger = "default-on"; -+ gpios = <&expgpio 2 GPIO_ACTIVE_LOW>; -+ }; ++&led_pwr { ++ default-state = "off"; +}; + +&pwm1 { + status = "disabled"; +}; + -+&audio { ++&vchiq { + pinctrl-names = "default"; + pinctrl-0 = <&audio_pins>; -+ brcm,disable-headphones = <1>; +}; + +cam0_reg: &cam1_reg { + gpio = <&expgpio 5 GPIO_ACTIVE_HIGH>; +}; + ++i2c_csi_dsi0: &i2c0 { ++}; ++ +/ { + __overrides__ { -+ act_led_gpio = <&act_led>,"gpios:4"; -+ act_led_activelow = <&act_led>,"gpios:8"; -+ act_led_trigger = <&act_led>,"linux,default-trigger"; ++ audio = <&chosen>,"bootargs{on='snd_bcm2835.enable_hdmi=1',off='snd_bcm2835.enable_hdmi=0'}"; + -+ pwr_led_gpio = <&pwr_led>,"gpios:4"; -+ pwr_led_activelow = <&pwr_led>,"gpios:8"; -+ pwr_led_trigger = <&pwr_led>,"linux,default-trigger"; ++ act_led_gpio = <&led_act>,"gpios:4"; ++ act_led_activelow = <&led_act>,"gpios:8"; ++ act_led_trigger = <&led_act>,"linux,default-trigger"; ++ ++ pwr_led_gpio = <&led_pwr>,"gpios:4"; ++ pwr_led_activelow = <&led_pwr>,"gpios:8"; ++ pwr_led_trigger = <&led_pwr>,"linux,default-trigger"; + + eth_led0 = <&phy1>,"led-modes:0"; + eth_led1 = <&phy1>,"led-modes:4"; @@ -8496,67 +10066,44 @@ index 000000000000..5dbd1b77260b + <&ant2>, "output-high?=off", + <&ant2>, "output-low?=on"; + -+ sd_poll_once = <&emmc2>, "non-removable?"; -+ spi_dma4 = <&spi0>, "dmas:0=", <&dma40>, -+ <&spi0>, "dmas:8=", <&dma40>; ++ cam0_reg = <&cam0_reg>,"status"; ++ cam0_reg_gpio = <&cam0_reg>,"gpio:4", ++ <&cam0_reg>,"gpio:0=", <&gpio>; ++ cam1_reg = <&cam1_reg>,"status"; ++ cam1_reg_gpio = <&cam1_reg>,"gpio:4", ++ <&cam1_reg>,"gpio:0=", <&gpio>; ++ ++ pcie_tperst_clk_ms = <&pcie0>,"brcm,tperst-clk-ms:0"; + }; +}; -diff --git a/arch/arm/boot/dts/bcm2711-rpi-cm4s.dts b/arch/arm/boot/dts/bcm2711-rpi-cm4s.dts +diff --git a/arch/arm/boot/dts/broadcom/bcm2711-rpi-cm4s.dts b/arch/arm/boot/dts/broadcom/bcm2711-rpi-cm4s.dts new file mode 100644 -index 000000000000..f90785abc92f +index 000000000000..4cabd53bf45d --- /dev/null -+++ b/arch/arm/boot/dts/bcm2711-rpi-cm4s.dts -@@ -0,0 +1,467 @@ ++++ b/arch/arm/boot/dts/broadcom/bcm2711-rpi-cm4s.dts +@@ -0,0 +1,297 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; ++#define BCM2711 ++#define i2c0 i2c0if +#include "bcm2711.dtsi" -+#include "bcm2835-rpi.dtsi" -+ -+#include ++//#include "bcm283x-rpi-wifi-bt.dtsi" ++#undef i2c0 ++#include "bcm270x.dtsi" ++#define i2c0 i2c0mux ++#include "bcm2711-rpi.dtsi" ++#undef i2c0 ++#include "bcm283x-rpi-led-deprecated.dtsi" + +/ { + compatible = "raspberrypi,4-compute-module-s", "brcm,bcm2711"; + model = "Raspberry Pi Compute Module 4S"; -+ -+ chosen { -+ /* 8250 auxiliary UART instead of pl011 */ -+ stdout-path = "serial1:115200n8"; -+ }; -+ -+ /* Will be filled by the bootloader */ -+ memory@0 { -+ device_type = "memory"; -+ reg = <0 0 0>; -+ }; -+ -+ aliases { -+ emmc2bus = &emmc2bus; -+ blconfig = &blconfig; -+ }; -+ -+ leds { -+ led-act { -+ gpios = <&virtgpio 0 0>; -+ }; -+ }; +}; + +&ddc0 { + status = "okay"; +}; + -+&firmware { -+ firmware_clocks: clocks { -+ compatible = "raspberrypi,firmware-clocks"; -+ #clock-cells = <1>; -+ }; -+ -+ reset: reset { -+ compatible = "raspberrypi,firmware-reset"; -+ #reset-cells = <1>; -+ }; -+}; -+ +&gpio { + /* + * Parts taken from rpi_SCH_4b_4p0_reduced.pdf and @@ -8568,21 +10115,20 @@ index 000000000000..f90785abc92f + */ + gpio-line-names = "ID_SDA", + "ID_SCL", -+ "SDA1", -+ "SCL1", -+ "GPIO_GCLK", ++ "GPIO2", ++ "GPIO3", ++ "GPIO4", + "GPIO5", + "GPIO6", -+ "SPI_CE1_N", -+ "SPI_CE0_N", -+ "SPI_MISO", -+ "SPI_MOSI", -+ "SPI_SCLK", ++ "GPIO7", ++ "GPIO8", ++ "GPIO9", ++ "GPIO10", ++ "GPIO11", + "GPIO12", + "GPIO13", -+ /* Serial port */ -+ "TXD1", -+ "RXD1", ++ "GPIO14", ++ "GPIO15", + "GPIO16", + "GPIO17", + "GPIO18", @@ -8616,15 +10162,11 @@ index 000000000000..f90785abc92f +}; + +&hdmi0 { -+ clocks = <&firmware_clocks 13>, <&firmware_clocks 14>, <&dvp 0>, <&clk_27MHz>; -+ clock-names = "hdmi", "bvb", "audio", "cec"; -+ wifi-2.4ghz-coexistence; + status = "okay"; +}; + -+ -+&hvs { -+ clocks = <&firmware_clocks 4>; ++&led_act { ++ gpios = <&virtgpio 0 GPIO_ACTIVE_HIGH>; +}; + +&pixelvalve0 { @@ -8649,22 +10191,6 @@ index 000000000000..f90785abc92f + status = "okay"; +}; + -+&rmem { -+ /* -+ * RPi4's co-processor will copy the board's bootloader configuration -+ * into memory for the OS to consume. It'll also update this node with -+ * its placement information. -+ */ -+ blconfig: nvram@0 { -+ compatible = "raspberrypi,bootloader-config", "nvmem-rmem"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ reg = <0x0 0x0 0x0>; -+ no-map; -+ status = "disabled"; -+ }; -+}; -+ +/* EMMC2 is used to drive the EMMC card */ +&emmc2 { + bus-width = <8>; @@ -8691,9 +10217,7 @@ index 000000000000..f90785abc92f +// ============================================= +// Downstream rpi- changes + -+#define BCM2711 -+ -+#include "bcm270x.dtsi" ++#include "bcm2711-rpi-ds.dtsi" + +/ { + soc { @@ -8710,30 +10234,20 @@ index 000000000000..f90785abc92f + }; +}; + -+#include "bcm2711-rpi.dtsi" +#include "bcm283x-rpi-csi0-2lane.dtsi" +#include "bcm283x-rpi-csi1-4lane.dtsi" +#include "bcm283x-rpi-i2c0mux_0_28.dtsi" + +/ { + chosen { -+ bootargs = "coherent_pool=1M 8250.nr_uarts=1 snd_bcm2835.enable_compat_alsa=0 snd_bcm2835.enable_hdmi=1"; ++ bootargs = "coherent_pool=1M snd_bcm2835.enable_headphones=0"; + }; + + aliases { + serial0 = &uart0; -+ mmc0 = &emmc2; -+ mmc1 = &mmcnr; -+ mmc2 = &sdhost; -+ i2c3 = &i2c3; -+ i2c4 = &i2c4; -+ i2c5 = &i2c5; -+ i2c6 = &i2c6; -+ spi3 = &spi3; -+ spi4 = &spi4; -+ spi5 = &spi5; -+ spi6 = &spi6; -+ /delete-property/ intc; ++ serial1 = &uart1; ++ /delete-property/ i2c20; ++ /delete-property/ i2c21; + }; + + /delete-node/ wifi-pwrseq; @@ -8768,132 +10282,11 @@ index 000000000000..f90785abc92f +}; + +&gpio { -+ spi0_pins: spi0_pins { -+ brcm,pins = <9 10 11>; -+ brcm,function = ; -+ }; -+ -+ spi0_cs_pins: spi0_cs_pins { -+ brcm,pins = <8 7>; -+ brcm,function = ; -+ }; -+ -+ spi3_pins: spi3_pins { -+ brcm,pins = <1 2 3>; -+ brcm,function = ; -+ }; -+ -+ spi3_cs_pins: spi3_cs_pins { -+ brcm,pins = <0 24>; -+ brcm,function = ; -+ }; -+ -+ spi4_pins: spi4_pins { -+ brcm,pins = <5 6 7>; -+ brcm,function = ; -+ }; -+ -+ spi4_cs_pins: spi4_cs_pins { -+ brcm,pins = <4 25>; -+ brcm,function = ; -+ }; -+ -+ spi5_pins: spi5_pins { -+ brcm,pins = <13 14 15>; -+ brcm,function = ; -+ }; -+ -+ spi5_cs_pins: spi5_cs_pins { -+ brcm,pins = <12 26>; -+ brcm,function = ; -+ }; -+ -+ spi6_pins: spi6_pins { -+ brcm,pins = <19 20 21>; -+ brcm,function = ; -+ }; -+ -+ spi6_cs_pins: spi6_cs_pins { -+ brcm,pins = <18 27>; -+ brcm,function = ; -+ }; -+ -+ i2c0_pins: i2c0 { -+ brcm,pins = <0 1>; -+ brcm,function = ; -+ brcm,pull = ; -+ }; -+ -+ i2c1_pins: i2c1 { -+ brcm,pins = <2 3>; -+ brcm,function = ; -+ brcm,pull = ; -+ }; -+ -+ i2c3_pins: i2c3 { -+ brcm,pins = <4 5>; -+ brcm,function = ; -+ brcm,pull = ; -+ }; -+ -+ i2c4_pins: i2c4 { -+ brcm,pins = <8 9>; -+ brcm,function = ; -+ brcm,pull = ; -+ }; -+ -+ i2c5_pins: i2c5 { -+ brcm,pins = <12 13>; -+ brcm,function = ; -+ brcm,pull = ; -+ }; -+ -+ i2c6_pins: i2c6 { -+ brcm,pins = <22 23>; -+ brcm,function = ; -+ brcm,pull = ; -+ }; -+ -+ i2s_pins: i2s { -+ brcm,pins = <18 19 20 21>; -+ brcm,function = ; -+ }; -+ -+ sdio_pins: sdio_pins { -+ brcm,pins = <34 35 36 37 38 39>; -+ brcm,function = ; // alt3 = SD1 -+ brcm,pull = <0 2 2 2 2 2>; -+ }; -+ + uart0_pins: uart0_pins { + brcm,pins; + brcm,function; + brcm,pull; + }; -+ -+ uart2_pins: uart2_pins { -+ brcm,pins = <0 1>; -+ brcm,function = ; -+ brcm,pull = <0 2>; -+ }; -+ -+ uart3_pins: uart3_pins { -+ brcm,pins = <4 5>; -+ brcm,function = ; -+ brcm,pull = <0 2>; -+ }; -+ -+ uart4_pins: uart4_pins { -+ brcm,pins = <8 9>; -+ brcm,function = ; -+ brcm,pull = <0 2>; -+ }; -+ -+ uart5_pins: uart5_pins { -+ brcm,pins = <12 13>; -+ brcm,function = ; -+ brcm,pull = <0 2>; -+ }; +}; + +&i2c0if { @@ -8914,6 +10307,16 @@ index 000000000000..f90785abc92f +// ============================================= +// Board specific stuff here + ++/* Enable USB in OTG-aware mode */ ++&usb { ++ compatible = "brcm,bcm2835-usb"; ++ dr_mode = "otg"; ++ g-np-tx-fifo-size = <32>; ++ g-rx-fifo-size = <558>; ++ g-tx-fifo-size = <512 512 512 512 512 256 256>; ++ status = "okay"; ++}; ++ +&sdhost { + status = "disabled"; +}; @@ -8935,86 +10338,130 @@ index 000000000000..f90785abc92f + compatible = "disabled"; +}; + -+&leds { -+ act_led: led-act { -+ label = "led0"; -+ linux,default-trigger = "mmc0"; -+ gpios = <&virtgpio 0 0>; -+ }; ++&led_act { ++ default-state = "off"; ++ linux,default-trigger = "mmc0"; +}; + +&pwm1 { + status = "disabled"; +}; + -+&audio { ++&vchiq { + pinctrl-names = "default"; + pinctrl-0 = <&audio_pins>; -+ brcm,disable-headphones = <1>; +}; + +&cam1_reg { -+ gpio = <&gpio 2 GPIO_ACTIVE_HIGH>; ++ gpio = <&gpio 3 GPIO_ACTIVE_HIGH>; + status = "disabled"; +}; + +cam0_reg: &cam0_regulator { -+ gpio = <&gpio 30 GPIO_ACTIVE_HIGH>; ++ gpio = <&gpio 31 GPIO_ACTIVE_HIGH>; + status = "disabled"; +}; + ++i2c_csi_dsi0: &i2c0 { ++}; ++ +/ { + __overrides__ { -+ act_led_gpio = <&act_led>,"gpios:4"; -+ act_led_activelow = <&act_led>,"gpios:8"; -+ act_led_trigger = <&act_led>,"linux,default-trigger"; ++ audio = <&chosen>,"bootargs{on='snd_bcm2835.enable_hdmi=1',off='snd_bcm2835.enable_hdmi=0'}"; + -+ sd_poll_once = <&emmc2>, "non-removable?"; -+ spi_dma4 = <&spi0>, "dmas:0=", <&dma40>, -+ <&spi0>, "dmas:8=", <&dma40>; ++ act_led_gpio = <&led_act>,"gpios:4"; ++ act_led_activelow = <&led_act>,"gpios:8"; ++ act_led_trigger = <&led_act>,"linux,default-trigger"; ++ ++ cam0_reg = <&cam0_reg>,"status"; ++ cam0_reg_gpio = <&cam0_reg>,"gpio:4"; ++ cam1_reg = <&cam1_reg>,"status"; ++ cam1_reg_gpio = <&cam1_reg>,"gpio:4"; + }; +}; -diff --git a/arch/arm/boot/dts/bcm2711-rpi.dtsi b/arch/arm/boot/dts/bcm2711-rpi.dtsi +diff --git a/arch/arm/boot/dts/broadcom/bcm2711-rpi-ds.dtsi b/arch/arm/boot/dts/broadcom/bcm2711-rpi-ds.dtsi new file mode 100644 -index 000000000000..ebf73b789b4a +index 000000000000..c45685339992 --- /dev/null -+++ b/arch/arm/boot/dts/bcm2711-rpi.dtsi -@@ -0,0 +1,205 @@ ++++ b/arch/arm/boot/dts/broadcom/bcm2711-rpi-ds.dtsi +@@ -0,0 +1,561 @@ +// SPDX-License-Identifier: GPL-2.0 +#include "bcm270x-rpi.dtsi" + +/ { -+ __overrides__ { -+ arm_freq; ++ chosen: chosen { + }; + -+ v3dbus: v3dbus { -+ compatible = "simple-bus"; -+ #address-cells = <1>; -+ #size-cells = <2>; -+ ranges = <0x7c500000 0x0 0xfc500000 0x0 0x03300000>, -+ <0x40000000 0x0 0xff800000 0x0 0x00800000>; -+ dma-ranges = <0x00000000 0x0 0x00000000 0x4 0x00000000>; ++ __overrides__ { ++ arm_freq; ++ eee = <&chosen>,"bootargs{on='',off='genet.eee=N'}"; ++ hdmi = <&hdmi0>,"status", ++ <&hdmi1>,"status"; ++ nvmem_cust_rw = <&nvmem_cust>,"rw?"; ++ nvmem_priv_rw = <&nvmem_priv>,"rw?"; ++ pcie = <&pcie0>,"status"; ++ sd = <&emmc2>,"status"; + -+ v3d: v3d@7ec04000 { -+ compatible = "brcm,2711-v3d"; -+ reg = -+ <0x7ec00000 0x0 0x4000>, -+ <0x7ec04000 0x0 0x4000>; -+ reg-names = "hub", "core0"; -+ -+ power-domains = <&pm BCM2835_POWER_DOMAIN_GRAFX_V3D>; -+ resets = <&pm BCM2835_RESET_V3D>; -+ clocks = <&firmware_clocks 5>; -+ clocks-names = "v3d"; -+ interrupts = ; -+ status = "disabled"; -+ }; ++ sd_poll_once = <&emmc2>, "non-removable?"; ++ spi_dma4 = <&spi0>, "dmas:0=", <&dma40>, ++ <&spi0>, "dmas:8=", <&dma40>; ++ i2s_dma4 = <&i2s>, "dmas:0=", <&dma40>, ++ <&i2s>, "dmas:8=", <&dma40>; + }; + + scb: scb { + /* Add a label */ + }; ++ ++ soc: soc { ++ /* Add a label */ ++ }; ++ ++ arm-pmu { ++ compatible = "arm,cortex-a72-pmu", "arm,armv8-pmuv3", "arm,cortex-a7-pmu"; ++ ++ }; ++ ++ chosen { ++ stdout-path = "serial0:115200n8"; ++ }; ++ ++ aliases { ++ uart2 = &uart2; ++ uart3 = &uart3; ++ uart4 = &uart4; ++ uart5 = &uart5; ++ serial0 = &uart1; ++ serial1 = &uart0; ++ serial2 = &uart2; ++ serial3 = &uart3; ++ serial4 = &uart4; ++ serial5 = &uart5; ++ mmc0 = &emmc2; ++ mmc1 = &mmcnr; ++ mmc2 = &sdhost; ++ i2c3 = &i2c3; ++ i2c4 = &i2c4; ++ i2c5 = &i2c5; ++ i2c6 = &i2c6; ++ i2c20 = &ddc0; ++ i2c21 = &ddc1; ++ spi3 = &spi3; ++ spi4 = &spi4; ++ spi5 = &spi5; ++ spi6 = &spi6; ++ /delete-property/ intc; ++ }; ++ ++ /* ++ * Add a node with a dma-ranges value that exists only to be found ++ * by of_dma_get_max_cpu_address, and hence limit the DMA zone. ++ */ ++ zone_dma { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ dma-ranges = <0x0 0x0 0x0 0x40000000>; ++ }; +}; + +&vc4 { @@ -9026,12 +10473,42 @@ index 000000000000..ebf73b789b4a + alloc-ranges = <0x0 0x00000000 0x30000000>; +}; + ++&soc { ++ /* Add the physical <-> DMA mapping for the I/O space */ ++ dma-ranges = <0xc0000000 0x0 0x00000000 0x40000000>, ++ <0x7c000000 0x0 0xfc000000 0x03800000>; ++ ++ nvmem_otp: nvmem_otp { ++ compatible = "raspberrypi,rpi-otp"; ++ firmware = <&firmware>; ++ reg = <0 166>; ++ status = "okay"; ++ }; ++ ++ nvmem_cust: nvmem_cust { ++ compatible = "raspberrypi,rpi-otp"; ++ firmware = <&firmware>; ++ reg = <1 8>; ++ status = "okay"; ++ }; ++ ++ nvmem_priv: nvmem_priv { ++ compatible = "raspberrypi,rpi-otp"; ++ firmware = <&firmware>; ++ reg = <3 8>; ++ status = "okay"; ++ }; ++}; ++ +&scb { ++ #size-cells = <2>; ++ + ranges = <0x0 0x7c000000 0x0 0xfc000000 0x0 0x03800000>, + <0x0 0x40000000 0x0 0xff800000 0x0 0x00800000>, + <0x6 0x00000000 0x6 0x00000000 0x0 0x40000000>, + <0x0 0x00000000 0x0 0x00000000 0x0 0xfc000000>; -+ dma-ranges = <0x0 0x00000000 0x0 0x00000000 0x4 0x00000000>; ++ dma-ranges = <0x4 0x7c000000 0x0 0xfc000000 0x0 0x03800000>, ++ <0x0 0x00000000 0x0 0x00000000 0x4 0x00000000>; + + dma40: dma@7e007b00 { + compatible = "brcm,bcm2711-dma"; @@ -9057,30 +10534,27 @@ index 000000000000..ebf73b789b4a + power-domains = <&power RPI_POWER_DOMAIN_USB>; + }; + -+ hevc-decoder@7eb00000 { -+ compatible = "raspberrypi,rpivid-hevc-decoder"; -+ reg = <0x0 0x7eb00000 0x0 0x10000>; -+ status = "okay"; -+ }; -+ -+ rpivid-local-intc@7eb10000 { -+ compatible = "raspberrypi,rpivid-local-intc"; -+ reg = <0x0 0x7eb10000 0x0 0x1000>; -+ status = "okay"; ++ codec@7eb10000 { ++ compatible = "raspberrypi,rpivid-vid-decoder"; ++ reg = <0x0 0x7eb10000 0x0 0x1000>, /* INTC */ ++ <0x0 0x7eb00000 0x0 0x10000>; /* HEVC */ ++ reg-names = "intc", ++ "hevc"; + interrupts = ; -+ }; + -+ h264-decoder@7eb20000 { -+ compatible = "raspberrypi,rpivid-h264-decoder"; -+ reg = <0x0 0x7eb20000 0x0 0x10000>; -+ status = "okay"; ++ clocks = <&firmware_clocks 11>; ++ clock-names = "hevc"; + }; ++}; + -+ vp9-decoder@7eb30000 { -+ compatible = "raspberrypi,rpivid-vp9-decoder"; -+ reg = <0x0 0x7eb30000 0x0 0x10000>; -+ status = "okay"; -+ }; ++&pcie0 { ++ reg = <0x0 0x7d500000 0x0 0x9310>; ++ ranges = <0x02000000 0x0 0xc0000000 0x6 0x00000000 ++ 0x0 0x40000000>; ++}; ++ ++&genet { ++ reg = <0x0 0x7d580000 0x0 0x10000>; +}; + +&dma40 { @@ -9134,6 +10608,127 @@ index 000000000000..ebf73b789b4a +&gpio { + interrupts = , + ; ++ ++ spi0_pins: spi0_pins { ++ brcm,pins = <9 10 11>; ++ brcm,function = ; ++ }; ++ ++ spi0_cs_pins: spi0_cs_pins { ++ brcm,pins = <8 7>; ++ brcm,function = ; ++ }; ++ ++ spi3_pins: spi3_pins { ++ brcm,pins = <1 2 3>; ++ brcm,function = ; ++ }; ++ ++ spi3_cs_pins: spi3_cs_pins { ++ brcm,pins = <0 24>; ++ brcm,function = ; ++ }; ++ ++ spi4_pins: spi4_pins { ++ brcm,pins = <5 6 7>; ++ brcm,function = ; ++ }; ++ ++ spi4_cs_pins: spi4_cs_pins { ++ brcm,pins = <4 25>; ++ brcm,function = ; ++ }; ++ ++ spi5_pins: spi5_pins { ++ brcm,pins = <13 14 15>; ++ brcm,function = ; ++ }; ++ ++ spi5_cs_pins: spi5_cs_pins { ++ brcm,pins = <12 26>; ++ brcm,function = ; ++ }; ++ ++ spi6_pins: spi6_pins { ++ brcm,pins = <19 20 21>; ++ brcm,function = ; ++ }; ++ ++ spi6_cs_pins: spi6_cs_pins { ++ brcm,pins = <18 27>; ++ brcm,function = ; ++ }; ++ ++ i2c0_pins: i2c0 { ++ brcm,pins = <0 1>; ++ brcm,function = ; ++ brcm,pull = ; ++ }; ++ ++ i2c1_pins: i2c1 { ++ brcm,pins = <2 3>; ++ brcm,function = ; ++ brcm,pull = ; ++ }; ++ ++ i2c3_pins: i2c3 { ++ brcm,pins = <4 5>; ++ brcm,function = ; ++ brcm,pull = ; ++ }; ++ ++ i2c4_pins: i2c4 { ++ brcm,pins = <8 9>; ++ brcm,function = ; ++ brcm,pull = ; ++ }; ++ ++ i2c5_pins: i2c5 { ++ brcm,pins = <12 13>; ++ brcm,function = ; ++ brcm,pull = ; ++ }; ++ ++ i2c6_pins: i2c6 { ++ brcm,pins = <22 23>; ++ brcm,function = ; ++ brcm,pull = ; ++ }; ++ ++ i2s_pins: i2s { ++ brcm,pins = <18 19 20 21>; ++ brcm,function = ; ++ }; ++ ++ sdio_pins: sdio_pins { ++ brcm,pins = <34 35 36 37 38 39>; ++ brcm,function = ; // alt3 = SD1 ++ brcm,pull = <0 2 2 2 2 2>; ++ }; ++ ++ uart2_pins: uart2_pins { ++ brcm,pins = <0 1>; ++ brcm,function = ; ++ brcm,pull = <0 2>; ++ }; ++ ++ uart3_pins: uart3_pins { ++ brcm,pins = <4 5>; ++ brcm,function = ; ++ brcm,pull = <0 2>; ++ }; ++ ++ uart4_pins: uart4_pins { ++ brcm,pins = <8 9>; ++ brcm,function = ; ++ brcm,pull = <0 2>; ++ }; ++ ++ uart5_pins: uart5_pins { ++ brcm,pins = <12 13>; ++ brcm,function = ; ++ brcm,pull = <0 2>; ++ }; +}; + +&emmc2 { @@ -9165,7 +10760,31 @@ index 000000000000..ebf73b789b4a +}; + +&hdmi0 { -+ dmas = <&dma (10|(1<<27)|(1<<24)|(10<<16)|(15<<20))>; ++ reg = <0x7ef00700 0x300>, ++ <0x7ef00300 0x200>, ++ <0x7ef00f00 0x80>, ++ <0x7ef00f80 0x80>, ++ <0x7ef01b00 0x200>, ++ <0x7ef01f00 0x400>, ++ <0x7ef00200 0x80>, ++ <0x7ef04300 0x100>, ++ <0x7ef20000 0x100>, ++ <0x7ef00100 0x30>; ++ reg-names = "hdmi", ++ "dvp", ++ "phy", ++ "rm", ++ "packet", ++ "metadata", ++ "csc", ++ "cec", ++ "hd", ++ "intr2"; ++ clocks = <&firmware_clocks 13>, ++ <&firmware_clocks 14>, ++ <&dvp 0>, ++ <&clk_27MHz>; ++ dmas = <&dma40 (10|(1<<30)|(1<<24)|(10<<16)|(15<<20))>; + status = "disabled"; +}; + @@ -9174,7 +10793,31 @@ index 000000000000..ebf73b789b4a +}; + +&hdmi1 { -+ dmas = <&dma (17|(1<<27)|(1<<24)|(10<<16)|(15<<20))>; ++ reg = <0x7ef05700 0x300>, ++ <0x7ef05300 0x200>, ++ <0x7ef05f00 0x80>, ++ <0x7ef05f80 0x80>, ++ <0x7ef06b00 0x200>, ++ <0x7ef06f00 0x400>, ++ <0x7ef00280 0x80>, ++ <0x7ef09300 0x100>, ++ <0x7ef20000 0x100>, ++ <0x7ef00100 0x30>; ++ reg-names = "hdmi", ++ "dvp", ++ "phy", ++ "rm", ++ "packet", ++ "metadata", ++ "csc", ++ "cec", ++ "hd", ++ "intr2"; ++ clocks = <&firmware_clocks 13>, ++ <&firmware_clocks 14>, ++ <&dvp 1>, ++ <&clk_27MHz>; ++ dmas = <&dma40 (17|(1<<30)|(1<<24)|(10<<16)|(15<<20))>; + status = "disabled"; +}; + @@ -9185,179 +10828,3716 @@ index 000000000000..ebf73b789b4a +&dvp { + status = "disabled"; +}; -diff --git a/arch/arm/boot/dts/bcm2711.dtsi b/arch/arm/boot/dts/bcm2711.dtsi -index 55ec83bde5a6..2b834efddc06 100644 ---- a/arch/arm/boot/dts/bcm2711.dtsi -+++ b/arch/arm/boot/dts/bcm2711.dtsi -@@ -300,6 +300,14 @@ pixelvalve3: pixelvalve@7ec12000 { ++ ++&vec { ++ clocks = <&firmware_clocks 15>; ++}; ++ ++&aon_intr { ++ interrupts = ; ++ status = "disabled"; ++}; ++ ++&system_timer { ++ status = "disabled"; ++}; ++ ++&i2c0 { ++ /delete-property/ compatible; ++ /delete-property/ interrupts; ++}; ++ ++&i2c0if { ++ compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c"; ++ interrupts = ; ++}; ++ ++i2c_arm: &i2c1 {}; ++i2c_vc: &i2c0 {}; ++ ++&i2c3 { ++ pinctrl-0 = <&i2c3_pins>; ++ pinctrl-names = "default"; ++}; ++ ++&i2c4 { ++ pinctrl-0 = <&i2c4_pins>; ++ pinctrl-names = "default"; ++}; ++ ++&i2c5 { ++ pinctrl-0 = <&i2c5_pins>; ++ pinctrl-names = "default"; ++}; ++ ++&i2c6 { ++ pinctrl-0 = <&i2c6_pins>; ++ pinctrl-names = "default"; ++}; ++ ++&spi3 { ++ pinctrl-0 = <&spi3_pins &spi3_cs_pins>; ++ pinctrl-names = "default"; ++}; ++ ++&spi4 { ++ pinctrl-0 = <&spi4_pins &spi4_cs_pins>; ++ pinctrl-names = "default"; ++}; ++ ++&spi5 { ++ pinctrl-0 = <&spi5_pins &spi5_cs_pins>; ++ pinctrl-names = "default"; ++}; ++ ++&spi6 { ++ pinctrl-0 = <&spi6_pins &spi6_cs_pins>; ++ pinctrl-names = "default"; ++}; ++ ++&uart2 { ++ pinctrl-0 = <&uart2_pins>; ++ pinctrl-names = "default"; ++}; ++ ++&uart3 { ++ pinctrl-0 = <&uart3_pins>; ++ pinctrl-names = "default"; ++}; ++ ++&uart4 { ++ pinctrl-0 = <&uart4_pins>; ++ pinctrl-names = "default"; ++}; ++ ++&uart5 { ++ pinctrl-0 = <&uart5_pins>; ++ pinctrl-names = "default"; ++}; ++ ++&axiperf { ++ compatible = "brcm,bcm2711-axiperf"; ++}; ++ ++/delete-node/ &v3d; ++ ++/ { ++ v3dbus: v3dbus { ++ compatible = "simple-bus"; ++ #address-cells = <1>; ++ #size-cells = <2>; ++ ranges = <0x7c500000 0x0 0xfc500000 0x0 0x03300000>, ++ <0x40000000 0x0 0xff800000 0x0 0x00800000>; ++ dma-ranges = <0x00000000 0x0 0x00000000 0x4 0x00000000>; ++ ++ v3d: v3d@7ec04000 { ++ compatible = "brcm,2711-v3d"; ++ reg = ++ <0x7ec00000 0x0 0x4000>, ++ <0x7ec04000 0x0 0x4000>; ++ reg-names = "hub", "core0"; ++ ++ power-domains = <&pm BCM2835_POWER_DOMAIN_GRAFX_V3D>; ++ resets = <&pm BCM2835_RESET_V3D>; ++ clocks = <&firmware_clocks 5>; ++ clocks-names = "v3d"; ++ interrupts = ; ++ status = "disabled"; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/broadcom/bcm2711-rpi.dtsi b/arch/arm/boot/dts/broadcom/bcm2711-rpi.dtsi +index 98817a6675b9..7b9e946db985 100644 +--- a/arch/arm/boot/dts/broadcom/bcm2711-rpi.dtsi ++++ b/arch/arm/boot/dts/broadcom/bcm2711-rpi.dtsi +@@ -15,6 +15,7 @@ aliases { + ethernet0 = &genet; + pcie0 = &pcie0; + blconfig = &blconfig; ++ blpubkey = &blpubkey; + }; + }; + +@@ -67,6 +68,18 @@ blconfig: nvram@0 { + no-map; + status = "disabled"; + }; ++ /* ++ * RPi4 will copy the binary public key blob (if present) from the bootloader ++ * into memory for use by the OS. ++ */ ++ blpubkey: nvram@1 { ++ compatible = "raspberrypi,bootloader-public-key", "nvmem-rmem"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ reg = <0x0 0x0 0x0>; ++ no-map; ++ status = "disabled"; ++ }; + }; + + &v3d { +diff --git a/arch/arm/boot/dts/broadcom/bcm2711.dtsi b/arch/arm/boot/dts/broadcom/bcm2711.dtsi +index 4a379a14966d..09dbe7b3ca39 100644 +--- a/arch/arm/boot/dts/broadcom/bcm2711.dtsi ++++ b/arch/arm/boot/dts/broadcom/bcm2711.dtsi +@@ -277,7 +277,7 @@ pwm1: pwm@7e20c800 { + reg = <0x7e20c800 0x28>; + clocks = <&clocks BCM2835_CLOCK_PWM>; + assigned-clocks = <&clocks BCM2835_CLOCK_PWM>; +- assigned-clock-rates = <10000000>; ++ assigned-clock-rates = <50000000>; + #pwm-cells = <3>; status = "disabled"; }; - -+ vec: vec@7ec13000 { -+ compatible = "brcm,bcm2711-vec"; -+ reg = <0x7ec13000 0x1000>; -+ clocks = <&firmware_clocks 15>; -+ interrupts = ; +diff --git a/arch/arm/boot/dts/broadcom/bcm2712-rpi-5-b.dts b/arch/arm/boot/dts/broadcom/bcm2712-rpi-5-b.dts +new file mode 100644 +index 000000000000..f0e752436b68 +--- /dev/null ++++ b/arch/arm/boot/dts/broadcom/bcm2712-rpi-5-b.dts +@@ -0,0 +1,863 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/dts-v1/; ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define i2c0 _i2c0 ++#define i2c3 _i2c3 ++#define i2c4 _i2c4 ++#define i2c5 _i2c5 ++#define i2c6 _i2c6 ++#define i2c8 _i2c8 ++#define i2s _i2s ++#define pwm0 _pwm0 ++#define pwm1 _pwm1 ++#define spi0 _spi0 ++#define spi3 _spi3 ++#define spi4 _spi4 ++#define spi5 _spi5 ++#define spi6 _spi6 ++#define uart0 _uart0 ++#define uart2 _uart2 ++#define uart5 _uart5 ++ ++#include "bcm2712.dtsi" ++ ++#undef i2c0 ++#undef i2c3 ++#undef i2c4 ++#undef i2c5 ++#undef i2c6 ++#undef i2c8 ++#undef i2s ++#undef pwm0 ++#undef pwm1 ++#undef spi0 ++#undef spi3 ++#undef spi4 ++#undef spi5 ++#undef spi6 ++#undef uart0 ++#undef uart2 ++#undef uart3 ++#undef uart4 ++#undef uart5 ++ ++/ { ++ compatible = "raspberrypi,5-model-b", "brcm,bcm2712"; ++ model = "Raspberry Pi 5"; ++ ++ /* Will be filled by the bootloader */ ++ memory@0 { ++ device_type = "memory"; ++ reg = <0 0 0x28000000>; ++ }; ++ ++ leds: leds { ++ compatible = "gpio-leds"; ++ ++ led_pwr: led-pwr { ++ label = "PWR"; ++ gpios = <&rp1_gpio 44 GPIO_ACTIVE_LOW>; ++ default-state = "off"; ++ linux,default-trigger = "none"; ++ }; ++ ++ led_act: led-act { ++ label = "ACT"; ++ gpios = <&gio_aon 9 GPIO_ACTIVE_LOW>; ++ default-state = "off"; ++ linux,default-trigger = "mmc0"; ++ }; ++ }; ++ ++ sd_io_1v8_reg: sd_io_1v8_reg { ++ compatible = "regulator-gpio"; ++ regulator-name = "vdd-sd-io"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-boot-on; ++ regulator-always-on; ++ regulator-settling-time-us = <5000>; ++ gpios = <&gio_aon 3 GPIO_ACTIVE_HIGH>; ++ states = <1800000 0x1 ++ 3300000 0x0>; ++ status = "okay"; ++ }; ++ ++ sd_vcc_reg: sd_vcc_reg { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc-sd"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-boot-on; ++ enable-active-high; ++ gpios = <&gio_aon 4 GPIO_ACTIVE_HIGH>; ++ status = "okay"; ++ }; ++ ++ wl_on_reg: wl_on_reg { ++ compatible = "regulator-fixed"; ++ regulator-name = "wl-on-regulator"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ pinctrl-0 = <&wl_on_pins>; ++ pinctrl-names = "default"; ++ ++ gpio = <&gio 28 GPIO_ACTIVE_HIGH>; ++ ++ startup-delay-us = <150000>; ++ enable-active-high; ++ }; ++ ++ clocks: clocks { ++ }; ++ ++ cam1_clk: cam1_clk { ++ compatible = "fixed-clock"; ++ #clock-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ cam0_clk: cam0_clk { ++ compatible = "fixed-clock"; ++ #clock-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ cam0_reg: cam0_reg { ++ compatible = "regulator-fixed"; ++ regulator-name = "cam0_reg"; ++ enable-active-high; ++ status = "okay"; ++ gpio = <&rp1_gpio 34 0>; // CD0_IO0_MICCLK, to MIPI 0 connector ++ }; ++ ++ cam1_reg: cam1_reg { ++ compatible = "regulator-fixed"; ++ regulator-name = "cam1_reg"; ++ enable-active-high; ++ status = "okay"; ++ gpio = <&rp1_gpio 46 0>; // CD1_IO0_MICCLK, to MIPI 1 connector ++ }; ++ ++ cam_dummy_reg: cam_dummy_reg { ++ compatible = "regulator-fixed"; ++ regulator-name = "cam-dummy-reg"; ++ status = "okay"; ++ }; ++ ++ dummy: dummy { ++ // A target for unwanted overlay fragments ++ }; ++ ++ ++ // A few extra labels to keep overlays happy ++ ++ i2c0if: i2c0if {}; ++ i2c0mux: i2c0mux {}; ++}; ++ ++rp1_target: &pcie2 { ++ brcm,enable-mps-rcb; ++ brcm,vdm-qos-map = <0xbbaa9888>; ++ aspm-no-l0s; ++ status = "okay"; ++}; ++ ++// Add some labels to 2712 device ++ ++// The system UART ++uart10: &_uart0 { status = "okay"; }; ++ ++// The system SPI for the bootloader EEPROM ++spi10: &_spi0 { status = "okay"; }; ++ ++i2c_rp1boot: &_i2c3 { }; ++ ++#include "rp1.dtsi" ++ ++&rp1 { ++ // PCIe address space layout: ++ // 00_00000000-00_00xxxxxx = RP1 peripherals ++ // 10_00000000-1x_xxxxxxxx = up to 64GB system RAM ++ ++ // outbound access aimed at PCIe 0_00xxxxxx -> RP1 c0_40xxxxxx ++ // This is the RP1 peripheral space ++ ranges = <0xc0 0x40000000 ++ 0x02000000 0x00 0x00000000 ++ 0x00 0x00400000>; ++ ++ dma-ranges = ++ // inbound RP1 1x_xxxxxxxx -> PCIe 1x_xxxxxxxx ++ <0x10 0x00000000 ++ 0x43000000 0x10 0x00000000 ++ 0x10 0x00000000>, ++ ++ // inbound RP1 c0_40xxxxxx -> PCIe 00_00xxxxxx ++ // This allows the RP1 DMA controller to address RP1 hardware ++ <0xc0 0x40000000 ++ 0x02000000 0x0 0x00000000 ++ 0x0 0x00400000>, ++ ++ // inbound RP1 0x_xxxxxxxx -> PCIe 1x_xxxxxxxx ++ <0x00 0x00000000 ++ 0x02000000 0x10 0x00000000 ++ 0x10 0x00000000>; ++}; ++ ++// Expose RP1 nodes as system nodes with labels ++ ++&rp1_dma { ++ status = "okay"; ++}; ++ ++&rp1_eth { ++ status = "okay"; ++ phy-handle = <&phy1>; ++ phy-reset-gpios = <&rp1_gpio 32 GPIO_ACTIVE_LOW>; ++ phy-reset-duration = <5>; ++ ++ phy1: ethernet-phy@1 { ++ reg = <0x1>; ++ brcm,powerdown-enable; ++ }; ++}; ++ ++gpio: &rp1_gpio { ++ status = "okay"; ++}; ++ ++aux: &dummy {}; ++ ++&rp1_usb0 { ++ pinctrl-0 = <&usb_vbus_pins>; ++ pinctrl-names = "default"; ++ status = "okay"; ++}; ++ ++&rp1_usb1 { ++ status = "okay"; ++}; ++ ++#include "bcm2712-rpi.dtsi" ++ ++i2c_csi_dsi0: &i2c6 { // Note: This is for MIPI0 connector only ++ pinctrl-0 = <&rp1_i2c6_38_39>; ++ pinctrl-names = "default"; ++ clock-frequency = <100000>; ++}; ++ ++i2c_csi_dsi1: &i2c4 { // Note: This is for MIPI1 connector only ++ pinctrl-0 = <&rp1_i2c4_40_41>; ++ pinctrl-names = "default"; ++ clock-frequency = <100000>; ++}; ++ ++i2c_csi_dsi: &i2c_csi_dsi1 { }; // An alias for compatibility ++ ++csi0: &rp1_csi0 { }; ++csi1: &rp1_csi1 { }; ++dsi0: &rp1_dsi0 { }; ++dsi1: &rp1_dsi1 { }; ++dpi: &rp1_dpi { }; ++vec: &rp1_vec { }; ++dpi_gpio0: &rp1_dpi_24bit_gpio0 { }; ++dpi_gpio1: &rp1_dpi_24bit_gpio2 { }; ++dpi_18bit_cpadhi_gpio0: &rp1_dpi_18bit_cpadhi_gpio0 { }; ++dpi_18bit_cpadhi_gpio2: &rp1_dpi_18bit_cpadhi_gpio2 { }; ++dpi_18bit_gpio0: &rp1_dpi_18bit_gpio0 { }; ++dpi_18bit_gpio2: &rp1_dpi_18bit_gpio2 { }; ++dpi_16bit_cpadhi_gpio0: &rp1_dpi_16bit_cpadhi_gpio0 { }; ++dpi_16bit_cpadhi_gpio2: &rp1_dpi_16bit_cpadhi_gpio2 { }; ++dpi_16bit_gpio0: &rp1_dpi_16bit_gpio0 { }; ++dpi_16bit_gpio2: &rp1_dpi_16bit_gpio2 { }; ++ ++/* Add the IOMMUs for some RP1 bus masters */ ++ ++&csi0 { ++ iommus = <&iommu5>; ++}; ++ ++&csi1 { ++ iommus = <&iommu5>; ++}; ++ ++&dsi0 { ++ iommus = <&iommu5>; ++}; ++ ++&dsi1 { ++ iommus = <&iommu5>; ++}; ++ ++&dpi { ++ iommus = <&iommu5>; ++}; ++ ++&vec { ++ iommus = <&iommu5>; ++}; ++ ++&ddc0 { ++ status = "disabled"; ++}; ++ ++&ddc1 { ++ status = "disabled"; ++}; ++ ++&hdmi0 { ++ clocks = <&firmware_clocks 13>, <&firmware_clocks 14>, <&dvp 0>, <&clk_27MHz>; ++ clock-names = "hdmi", "bvb", "audio", "cec"; ++ status = "disabled"; ++}; ++ ++&hdmi1 { ++ clocks = <&firmware_clocks 13>, <&firmware_clocks 14>, <&dvp 1>, <&clk_27MHz>; ++ clock-names = "hdmi", "bvb", "audio", "cec"; ++ status = "disabled"; ++}; ++ ++&hvs { ++ clocks = <&firmware_clocks 4>, <&firmware_clocks 16>; ++ clock-names = "core", "disp"; ++}; ++ ++&mop { ++ status = "disabled"; ++}; ++ ++&moplet { ++ status = "disabled"; ++}; ++ ++&pixelvalve0 { ++ status = "disabled"; ++}; ++ ++&pixelvalve1 { ++ status = "disabled"; ++}; ++ ++&disp_intr { ++ status = "disabled"; ++}; ++ ++/* SDIO1 is used to drive the SD card */ ++&sdio1 { ++ pinctrl-0 = <&emmc_sd_pulls>, <&emmc_aon_cd_pins>; ++ pinctrl-names = "default"; ++ vqmmc-supply = <&sd_io_1v8_reg>; ++ vmmc-supply = <&sd_vcc_reg>; ++ bus-width = <4>; ++ sd-uhs-sdr50; ++ sd-uhs-ddr50; ++ sd-uhs-sdr104; ++ cd-gpios = <&gio_aon 5 GPIO_ACTIVE_LOW>; ++ //no-1-8-v; ++ status = "okay"; ++}; ++ ++&pinctrl_aon { ++ emmc_aon_cd_pins: emmc_aon_cd_pins { ++ function = "sd_card_g"; ++ pins = "aon_gpio5"; ++ bias-pull-up; ++ }; ++ ++ /* Slight hack - only one PWM pin (status LED) is usable */ ++ aon_pwm_1pin: aon_pwm_1pin { ++ function = "aon_pwm"; ++ pins = "aon_gpio9"; ++ }; ++}; ++ ++&pinctrl { ++ pwr_button_pins: pwr_button_pins { ++ function = "gpio"; ++ pins = "gpio20"; ++ bias-pull-up; ++ }; ++ ++ wl_on_pins: wl_on_pins { ++ function = "gpio"; ++ pins = "gpio28"; ++ }; ++ ++ bt_shutdown_pins: bt_shutdown_pins { ++ function = "gpio"; ++ pins = "gpio29"; ++ }; ++ ++ emmc_sd_pulls: emmc_sd_pulls { ++ pins = "emmc_cmd", "emmc_dat0", "emmc_dat1", "emmc_dat2", "emmc_dat3"; ++ bias-pull-up; ++ }; ++}; ++ ++/* uarta communicates with the BT module */ ++&uarta { ++ uart-has-rtscts; ++ auto-flow-control; ++ status = "okay"; ++ clock-frequency = <96000000>; ++ pinctrl-0 = <&uarta_24_pins &bt_shutdown_pins>; ++ pinctrl-names = "default"; ++ ++ bluetooth: bluetooth { ++ compatible = "brcm,bcm43438-bt"; ++ max-speed = <3000000>; ++ shutdown-gpios = <&gio 29 GPIO_ACTIVE_HIGH>; ++ local-bd-address = [ 00 00 00 00 00 00 ]; ++ }; ++}; ++ ++&i2c_rp1boot { ++ clock-frequency = <400000>; ++ pinctrl-0 = <&i2c3_m4_agpio0_pins>; ++ pinctrl-names = "default"; ++}; ++ ++/ { ++ chosen: chosen { ++ bootargs = "reboot=w coherent_pool=1M 8250.nr_uarts=1 pci=pcie_bus_safe snd_bcm2835.enable_compat_alsa=0 snd_bcm2835.enable_hdmi=1"; ++ stdout-path = "serial10:115200n8"; ++ }; ++ ++ fan: cooling_fan { ++ status = "disabled"; ++ compatible = "pwm-fan"; ++ #cooling-cells = <2>; ++ cooling-min-state = <0>; ++ cooling-max-state = <3>; ++ cooling-levels = <0 75 125 175 250>; ++ pwms = <&rp1_pwm1 3 41566 PWM_POLARITY_INVERTED>; ++ rpm-regmap = <&rp1_pwm1>; ++ rpm-offset = <0x3c>; ++ }; ++ ++ pwr_button { ++ compatible = "gpio-keys"; ++ ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pwr_button_pins>; ++ status = "okay"; ++ ++ pwr_key: pwr { ++ label = "pwr_button"; ++ // linux,code = <205>; // KEY_SUSPEND ++ linux,code = <116>; // KEY_POWER ++ gpios = <&gio 20 GPIO_ACTIVE_LOW>; ++ debounce-interval = <50>; // ms ++ }; ++ }; ++}; ++ ++&usb { ++ power-domains = <&power RPI_POWER_DOMAIN_USB>; ++}; ++ ++/* SDIO2 drives the WLAN interface */ ++&sdio2 { ++ pinctrl-0 = <&sdio2_30_pins>; ++ pinctrl-names = "default"; ++ bus-width = <4>; ++ vmmc-supply = <&wl_on_reg>; ++ sd-uhs-ddr50; ++ non-removable; ++ status = "okay"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ wifi: wifi@1 { ++ reg = <1>; ++ compatible = "brcm,bcm4329-fmac"; ++ local-mac-address = [00 00 00 00 00 00]; ++ }; ++}; ++ ++&rpivid { ++ status = "okay"; ++}; ++ ++&pinctrl { ++ spi10_gpio2: spi10_gpio2 { ++ function = "vc_spi0"; ++ pins = "gpio2", "gpio3", "gpio4"; ++ bias-disable; ++ }; ++ ++ spi10_cs_gpio1: spi10_cs_gpio1 { ++ function = "gpio"; ++ pins = "gpio1"; ++ bias-pull-up; ++ }; ++}; ++ ++spi10_pins: &spi10_gpio2 {}; ++spi10_cs_pins: &spi10_cs_gpio1 {}; ++ ++&spi10 { ++ pinctrl-names = "default"; ++ cs-gpios = <&gio 1 1>; ++ pinctrl-0 = <&spi10_pins &spi10_cs_pins>; ++ ++ spidev10: spidev@0 { ++ compatible = "spidev"; ++ reg = <0>; /* CE0 */ ++ #address-cells = <1>; ++ #size-cells = <0>; ++ spi-max-frequency = <20000000>; ++ status = "okay"; ++ }; ++}; ++ ++// ============================================= ++// Board specific stuff here ++ ++&gio_aon { ++ // Don't use GIO_AON as an interrupt controller because it will ++ // clash with the firmware monitoring the PMIC interrupt via the VPU. ++ ++ /delete-property/ interrupt-controller; ++}; ++ ++&main_aon_irq { ++ // Don't use the MAIN_AON_IRQ interrupt controller because it will ++ // clash with the firmware monitoring the PMIC interrupt via the VPU. ++ ++ status = "disabled"; ++}; ++ ++&rp1_pwm1 { ++ status = "disabled"; ++ pinctrl-0 = <&rp1_pwm1_gpio45>; ++ pinctrl-names = "default"; ++}; ++ ++&thermal_trips { ++ cpu_tepid: cpu-tepid { ++ temperature = <50000>; ++ hysteresis = <5000>; ++ type = "active"; ++ }; ++ ++ cpu_warm: cpu-warm { ++ temperature = <60000>; ++ hysteresis = <5000>; ++ type = "active"; ++ }; ++ ++ cpu_hot: cpu-hot { ++ temperature = <67500>; ++ hysteresis = <5000>; ++ type = "active"; ++ }; ++ ++ cpu_vhot: cpu-vhot { ++ temperature = <75000>; ++ hysteresis = <5000>; ++ type = "active"; ++ }; ++}; ++ ++&cooling_maps { ++ tepid { ++ trip = <&cpu_tepid>; ++ cooling-device = <&fan 1 1>; ++ }; ++ ++ warm { ++ trip = <&cpu_warm>; ++ cooling-device = <&fan 2 2>; ++ }; ++ ++ hot { ++ trip = <&cpu_hot>; ++ cooling-device = <&fan 3 3>; ++ }; ++ ++ vhot { ++ trip = <&cpu_vhot>; ++ cooling-device = <&fan 4 4>; ++ }; ++ ++ melt { ++ trip = <&cpu_crit>; ++ cooling-device = <&fan 4 4>; ++ }; ++}; ++ ++&gio { ++ // The GPIOs above 35 are not used on Pi 5, so shrink the upper bank ++ // to reduce the clutter in gpioinfo/pinctrl ++ brcm,gpio-bank-widths = <32 4>; ++ ++ gpio-line-names = ++ "-", // GPIO_000 ++ "2712_BOOT_CS_N", // GPIO_001 ++ "2712_BOOT_MISO", // GPIO_002 ++ "2712_BOOT_MOSI", // GPIO_003 ++ "2712_BOOT_SCLK", // GPIO_004 ++ "-", // GPIO_005 ++ "-", // GPIO_006 ++ "-", // GPIO_007 ++ "-", // GPIO_008 ++ "-", // GPIO_009 ++ "-", // GPIO_010 ++ "-", // GPIO_011 ++ "-", // GPIO_012 ++ "-", // GPIO_013 ++ "PCIE_SDA", // GPIO_014 ++ "PCIE_SCL", // GPIO_015 ++ "-", // GPIO_016 ++ "-", // GPIO_017 ++ "-", // GPIO_018 ++ "-", // GPIO_019 ++ "PWR_GPIO", // GPIO_020 ++ "2712_G21_FS", // GPIO_021 ++ "-", // GPIO_022 ++ "-", // GPIO_023 ++ "BT_RTS", // GPIO_024 ++ "BT_CTS", // GPIO_025 ++ "BT_TXD", // GPIO_026 ++ "BT_RXD", // GPIO_027 ++ "WL_ON", // GPIO_028 ++ "BT_ON", // GPIO_029 ++ "WIFI_SDIO_CLK", // GPIO_030 ++ "WIFI_SDIO_CMD", // GPIO_031 ++ "WIFI_SDIO_D0", // GPIO_032 ++ "WIFI_SDIO_D1", // GPIO_033 ++ "WIFI_SDIO_D2", // GPIO_034 ++ "WIFI_SDIO_D3"; // GPIO_035 ++}; ++ ++&gio_aon { ++ gpio-line-names = ++ "RP1_SDA", // AON_GPIO_00 ++ "RP1_SCL", // AON_GPIO_01 ++ "RP1_RUN", // AON_GPIO_02 ++ "SD_IOVDD_SEL", // AON_GPIO_03 ++ "SD_PWR_ON", // AON_GPIO_04 ++ "SD_CDET_N", // AON_GPIO_05 ++ "SD_FLG_N", // AON_GPIO_06 ++ "-", // AON_GPIO_07 ++ "2712_WAKE", // AON_GPIO_08 ++ "2712_STAT_LED", // AON_GPIO_09 ++ "-", // AON_GPIO_10 ++ "-", // AON_GPIO_11 ++ "PMIC_INT", // AON_GPIO_12 ++ "UART_TX_FS", // AON_GPIO_13 ++ "UART_RX_FS", // AON_GPIO_14 ++ "-", // AON_GPIO_15 ++ "-", // AON_GPIO_16 ++ ++ // Pad bank0 out to 32 entries ++ "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", ++ ++ "HDMI0_SCL", // AON_SGPIO_00 ++ "HDMI0_SDA", // AON_SGPIO_01 ++ "HDMI1_SCL", // AON_SGPIO_02 ++ "HDMI1_SDA", // AON_SGPIO_03 ++ "PMIC_SCL", // AON_SGPIO_04 ++ "PMIC_SDA"; // AON_SGPIO_05 ++ ++ rp1_run_hog { ++ gpio-hog; ++ gpios = <2 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "RP1 RUN pin"; ++ }; ++}; ++ ++&rp1_gpio { ++ gpio-line-names = ++ "ID_SDA", // GPIO0 ++ "ID_SCL", // GPIO1 ++ "GPIO2", // GPIO2 ++ "GPIO3", // GPIO3 ++ "GPIO4", // GPIO4 ++ "GPIO5", // GPIO5 ++ "GPIO6", // GPIO6 ++ "GPIO7", // GPIO7 ++ "GPIO8", // GPIO8 ++ "GPIO9", // GPIO9 ++ "GPIO10", // GPIO10 ++ "GPIO11", // GPIO11 ++ "GPIO12", // GPIO12 ++ "GPIO13", // GPIO13 ++ "GPIO14", // GPIO14 ++ "GPIO15", // GPIO15 ++ "GPIO16", // GPIO16 ++ "GPIO17", // GPIO17 ++ "GPIO18", // GPIO18 ++ "GPIO19", // GPIO19 ++ "GPIO20", // GPIO20 ++ "GPIO21", // GPIO21 ++ "GPIO22", // GPIO22 ++ "GPIO23", // GPIO23 ++ "GPIO24", // GPIO24 ++ "GPIO25", // GPIO25 ++ "GPIO26", // GPIO26 ++ "GPIO27", // GPIO27 ++ ++ "PCIE_RP1_WAKE", // GPIO28 ++ "FAN_TACH", // GPIO29 ++ "HOST_SDA", // GPIO30 ++ "HOST_SCL", // GPIO31 ++ "ETH_RST_N", // GPIO32 ++ "-", // GPIO33 ++ ++ "CD0_IO0_MICCLK", // GPIO34 ++ "CD0_IO0_MICDAT0", // GPIO35 ++ "RP1_PCIE_CLKREQ_N", // GPIO36 ++ "-", // GPIO37 ++ "CD0_SDA", // GPIO38 ++ "CD0_SCL", // GPIO39 ++ "CD1_SDA", // GPIO40 ++ "CD1_SCL", // GPIO41 ++ "USB_VBUS_EN", // GPIO42 ++ "USB_OC_N", // GPIO43 ++ "RP1_STAT_LED", // GPIO44 ++ "FAN_PWM", // GPIO45 ++ "CD1_IO0_MICCLK", // GPIO46 ++ "2712_WAKE", // GPIO47 ++ "CD1_IO1_MICDAT1", // GPIO48 ++ "EN_MAX_USB_CUR", // GPIO49 ++ "-", // GPIO50 ++ "-", // GPIO51 ++ "-", // GPIO52 ++ "-"; // GPIO53 ++ ++ usb_vbus_pins: usb_vbus_pins { ++ function = "vbus1"; ++ pins = "gpio42", "gpio43"; ++ }; ++}; ++ ++/ { ++ aliases: aliases { ++ blconfig = &blconfig; ++ blpubkey = &blpubkey; ++ bluetooth = &bluetooth; ++ console = &uart10; ++ ethernet0 = &rp1_eth; ++ wifi0 = &wifi; ++ fb = &fb; ++ mailbox = &mailbox; ++ mmc0 = &sdio1; ++ uart0 = &uart0; ++ uart1 = &uart1; ++ uart2 = &uart2; ++ uart3 = &uart3; ++ uart4 = &uart4; ++ uart10 = &uart10; ++ serial0 = &uart0; ++ serial1 = &uart1; ++ serial2 = &uart2; ++ serial3 = &uart3; ++ serial4 = &uart4; ++ serial10 = &uart10; ++ i2c = &i2c_arm; ++ i2c0 = &i2c0; ++ i2c1 = &i2c1; ++ i2c2 = &i2c2; ++ i2c3 = &i2c3; ++ i2c4 = &i2c4; ++ i2c5 = &i2c5; ++ i2c6 = &i2c6; ++ i2c10 = &i2c_rp1boot; ++ // Bit-bashed i2c_gpios start at 10 ++ spi0 = &spi0; ++ spi1 = &spi1; ++ spi2 = &spi2; ++ spi3 = &spi3; ++ spi4 = &spi4; ++ spi5 = &spi5; ++ spi10 = &spi10; ++ gpio0 = &gpio; ++ gpio1 = &gio; ++ gpio2 = &gio_aon; ++ gpio3 = &pinctrl; ++ gpio4 = &pinctrl_aon; ++ usb0 = &rp1_usb0; ++ usb1 = &rp1_usb1; ++ drm-dsi1 = &dsi0; ++ drm-dsi2 = &dsi1; ++ }; ++ ++ __overrides__ { ++ bdaddr = <&bluetooth>, "local-bd-address["; ++ button_debounce = <&pwr_key>, "debounce-interval:0"; ++ cooling_fan = <&fan>, "status", <&rp1_pwm1>, "status"; ++ uart0_console = <&uart0>,"status", <&aliases>, "console=",&uart0; ++ i2c0 = <&i2c0>, "status"; ++ i2c1 = <&i2c1>, "status"; ++ i2c = <&i2c1>, "status"; ++ i2c_arm = <&i2c_arm>, "status"; ++ i2c_vc = <&i2c_vc>, "status"; ++ i2c_csi_dsi = <&i2c_csi_dsi>, "status"; ++ i2c_csi_dsi0 = <&i2c_csi_dsi0>, "status"; ++ i2c_csi_dsi1 = <&i2c_csi_dsi1>, "status"; ++ i2c0_baudrate = <&i2c0>, "clock-frequency:0"; ++ i2c1_baudrate = <&i2c1>, "clock-frequency:0"; ++ i2c_baudrate = <&i2c_arm>, "clock-frequency:0"; ++ i2c_arm_baudrate = <&i2c_arm>, "clock-frequency:0"; ++ i2c_vc_baudrate = <&i2c_vc>, "clock-frequency:0"; ++ krnbt = <&bluetooth>, "status"; ++ nvme = <&pciex1>, "status"; ++ pciex1 = <&pciex1>, "status"; ++ pciex1_gen = <&pciex1> , "max-link-speed:0"; ++ pciex1_no_l0s = <&pciex1>, "aspm-no-l0s?"; ++ pciex1_tperst_clk_ms = <&pciex1>, "brcm,tperst-clk-ms:0"; ++ pcie_tperst_clk_ms = <&pciex1>, "brcm,tperst-clk-ms:0"; ++ random = <&random>, "status"; ++ rtc = <&rpi_rtc>, "status"; ++ rtc_bbat_vchg = <&rpi_rtc>, "trickle-charge-microvolt:0"; ++ sd_cqe = <&sdio1>, "supports-cqe?"; ++ spi = <&spi0>, "status"; ++ suspend = <&pwr_key>, "linux,code:0=205"; ++ uart0 = <&uart0>, "status"; ++ wifiaddr = <&wifi>, "local-mac-address["; ++ ++ act_led_gpio = <&led_act>,"gpios:4",<&led_act>,"gpios:0=",<&gpio>; ++ act_led_activelow = <&led_act>,"gpios:8"; ++ act_led_trigger = <&led_act>, "linux,default-trigger"; ++ pwr_led_gpio = <&led_pwr>,"gpios:4"; ++ pwr_led_activelow = <&led_pwr>, "gpios:8"; ++ pwr_led_trigger = <&led_pwr>, "linux,default-trigger"; ++ eth_led0 = <&phy1>,"led-modes:0"; ++ eth_led1 = <&phy1>,"led-modes:4"; ++ drm_fb0_rp1_dsi0 = <&aliases>, "drm-fb0=",&dsi0; ++ drm_fb0_rp1_dsi1 = <&aliases>, "drm-fb0=",&dsi1; ++ drm_fb0_rp1_dpi = <&aliases>, "drm-fb0=",&dpi; ++ drm_fb0_vc4 = <&aliases>, "drm-fb0=",&vc4; ++ drm_fb1_rp1_dsi0 = <&aliases>, "drm-fb1=",&dsi0; ++ drm_fb1_rp1_dsi1 = <&aliases>, "drm-fb1=",&dsi1; ++ drm_fb1_rp1_dpi = <&aliases>, "drm-fb1=",&dpi; ++ drm_fb1_vc4 = <&aliases>, "drm-fb1=",&vc4; ++ drm_fb2_rp1_dsi0 = <&aliases>, "drm-fb2=",&dsi0; ++ drm_fb2_rp1_dsi1 = <&aliases>, "drm-fb2=",&dsi1; ++ drm_fb2_rp1_dpi = <&aliases>, "drm-fb2=",&dpi; ++ drm_fb2_vc4 = <&aliases>, "drm-fb2=",&vc4; ++ ++ fan_temp0 = <&cpu_tepid>,"temperature:0"; ++ fan_temp1 = <&cpu_warm>,"temperature:0"; ++ fan_temp2 = <&cpu_hot>,"temperature:0"; ++ fan_temp3 = <&cpu_vhot>,"temperature:0"; ++ fan_temp0_hyst = <&cpu_tepid>,"hysteresis:0"; ++ fan_temp1_hyst = <&cpu_warm>,"hysteresis:0"; ++ fan_temp2_hyst = <&cpu_hot>,"hysteresis:0"; ++ fan_temp3_hyst = <&cpu_vhot>,"hysteresis:0"; ++ fan_temp0_speed = <&fan>, "cooling-levels:4"; ++ fan_temp1_speed = <&fan>, "cooling-levels:8"; ++ fan_temp2_speed = <&fan>, "cooling-levels:12"; ++ fan_temp3_speed = <&fan>, "cooling-levels:16"; ++ }; ++}; +diff --git a/arch/arm/boot/dts/broadcom/bcm2712-rpi-cm5-cm4io.dts b/arch/arm/boot/dts/broadcom/bcm2712-rpi-cm5-cm4io.dts +new file mode 100644 +index 000000000000..f89321921f27 +--- /dev/null ++++ b/arch/arm/boot/dts/broadcom/bcm2712-rpi-cm5-cm4io.dts +@@ -0,0 +1,20 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/dts-v1/; ++ ++#include "bcm2712-rpi-cm5.dtsi" ++ ++// The RP1 USB3 interfaces are not usable on CM4IO ++ ++&rp1_usb0 { ++ status = "disabled"; ++}; ++ ++&rp1_usb1 { ++ status = "disabled"; ++}; ++ ++/ { ++ __overrides__ { ++ i2c_csi_dsi = <&i2c_csi_dsi>, "status"; ++ }; ++}; +diff --git a/arch/arm/boot/dts/broadcom/bcm2712-rpi-cm5-cm5io.dts b/arch/arm/boot/dts/broadcom/bcm2712-rpi-cm5-cm5io.dts +new file mode 100644 +index 000000000000..47ce4ff5049a +--- /dev/null ++++ b/arch/arm/boot/dts/broadcom/bcm2712-rpi-cm5-cm5io.dts +@@ -0,0 +1,10 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/dts-v1/; ++ ++#include "bcm2712-rpi-cm5.dtsi" ++ ++/ { ++ __overrides__ { ++ i2c_csi_dsi = <&i2c_csi_dsi>, "status"; ++ }; ++}; +diff --git a/arch/arm/boot/dts/broadcom/bcm2712-rpi-cm5.dtsi b/arch/arm/boot/dts/broadcom/bcm2712-rpi-cm5.dtsi +new file mode 100644 +index 000000000000..068138904695 +--- /dev/null ++++ b/arch/arm/boot/dts/broadcom/bcm2712-rpi-cm5.dtsi +@@ -0,0 +1,860 @@ ++// SPDX-License-Identifier: GPL-2.0 ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define i2c0 _i2c0 ++#define i2c3 _i2c3 ++#define i2c4 _i2c4 ++#define i2c5 _i2c5 ++#define i2c6 _i2c6 ++#define i2c8 _i2c8 ++#define i2s _i2s ++#define pwm0 _pwm0 ++#define pwm1 _pwm1 ++#define spi0 _spi0 ++#define spi3 _spi3 ++#define spi4 _spi4 ++#define spi5 _spi5 ++#define spi6 _spi6 ++#define uart0 _uart0 ++#define uart2 _uart2 ++#define uart5 _uart5 ++ ++#include "bcm2712.dtsi" ++ ++#undef i2c0 ++#undef i2c3 ++#undef i2c4 ++#undef i2c5 ++#undef i2c6 ++#undef i2c8 ++#undef i2s ++#undef pwm0 ++#undef pwm1 ++#undef spi0 ++#undef spi3 ++#undef spi4 ++#undef spi5 ++#undef spi6 ++#undef uart0 ++#undef uart2 ++#undef uart3 ++#undef uart4 ++#undef uart5 ++ ++/ { ++ compatible = "raspberrypi,5-compute-model", "brcm,bcm2712"; ++ model = "Raspberry Pi Compute Module 5"; ++ ++ /* Will be filled by the bootloader */ ++ memory@0 { ++ device_type = "memory"; ++ reg = <0 0 0x28000000>; ++ }; ++ ++ leds: leds { ++ compatible = "gpio-leds"; ++ ++ led_pwr: led-pwr { ++ label = "PWR"; ++ gpios = <&rp1_gpio 44 GPIO_ACTIVE_LOW>; ++ default-state = "off"; ++ linux,default-trigger = "none"; ++ }; ++ ++ led_act: led-act { ++ label = "ACT"; ++ gpios = <&gio_aon 9 GPIO_ACTIVE_LOW>; ++ default-state = "off"; ++ linux,default-trigger = "mmc0"; ++ }; ++ }; ++ ++ sd_io_1v8_reg: sd_io_1v8_reg { ++ compatible = "regulator-gpio"; ++ regulator-name = "vdd-sd-io"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-boot-on; ++ regulator-always-on; ++ regulator-settling-time-us = <5000>; ++ gpios = <&gio_aon 3 GPIO_ACTIVE_HIGH>; ++ states = <1800000 0x1 ++ 3300000 0x0>; ++ status = "okay"; ++ }; ++ ++ sd_vcc_reg: sd_vcc_reg { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc-sd"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-boot-on; ++ enable-active-high; ++ gpios = <&gio_aon 4 GPIO_ACTIVE_HIGH>; ++ status = "okay"; ++ }; ++ ++ wl_on_reg: wl_on_reg { ++ compatible = "regulator-fixed"; ++ regulator-name = "wl-on-regulator"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ pinctrl-0 = <&wl_on_pins>; ++ pinctrl-names = "default"; ++ ++ gpio = <&gio 28 GPIO_ACTIVE_HIGH>; ++ ++ startup-delay-us = <150000>; ++ enable-active-high; ++ }; ++ ++ clocks: clocks { ++ }; ++ ++ cam1_clk: cam1_clk { ++ compatible = "fixed-clock"; ++ #clock-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ cam0_clk: cam0_clk { ++ compatible = "fixed-clock"; ++ #clock-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ cam0_reg: cam0_reg { ++ compatible = "regulator-fixed"; ++ regulator-name = "cam0_reg"; ++ enable-active-high; ++ status = "okay"; ++ gpio = <&rp1_gpio 34 0>; // CD0_IO0_MICCLK, to CAM_GPIO on connector ++ }; ++ ++ cam_dummy_reg: cam_dummy_reg { ++ compatible = "regulator-fixed"; ++ regulator-name = "cam-dummy-reg"; ++ status = "okay"; ++ }; ++ ++ dummy: dummy { ++ // A target for unwanted overlay fragments ++ }; ++ ++ ++ // A few extra labels to keep overlays happy ++ ++ i2c0if: i2c0if {}; ++ i2c0mux: i2c0mux {}; ++}; ++ ++rp1_target: &pcie2 { ++ brcm,enable-mps-rcb; ++ brcm,vdm-qos-map = <0xbbaa9888>; ++ aspm-no-l0s; ++ status = "okay"; ++}; ++ ++// Add some labels to 2712 device ++ ++// The system UART ++uart10: &_uart0 { status = "okay"; }; ++ ++// The system SPI for the bootloader EEPROM ++spi10: &_spi0 { status = "okay"; }; ++ ++i2c_rp1boot: &_i2c3 { }; ++ ++#include "rp1.dtsi" ++ ++&rp1 { ++ // PCIe address space layout: ++ // 00_00000000-00_00xxxxxx = RP1 peripherals ++ // 10_00000000-1x_xxxxxxxx = up to 64GB system RAM ++ ++ // outbound access aimed at PCIe 0_00xxxxxx -> RP1 c0_40xxxxxx ++ // This is the RP1 peripheral space ++ ranges = <0xc0 0x40000000 ++ 0x02000000 0x00 0x00000000 ++ 0x00 0x00400000>; ++ ++ dma-ranges = ++ // inbound RP1 1x_xxxxxxxx -> PCIe 1x_xxxxxxxx ++ <0x10 0x00000000 ++ 0x43000000 0x10 0x00000000 ++ 0x10 0x00000000>, ++ ++ // inbound RP1 c0_40xxxxxx -> PCIe 00_00xxxxxx ++ // This allows the RP1 DMA controller to address RP1 hardware ++ <0xc0 0x40000000 ++ 0x02000000 0x0 0x00000000 ++ 0x0 0x00400000>, ++ ++ // inbound RP1 0x_xxxxxxxx -> PCIe 1x_xxxxxxxx ++ <0x00 0x00000000 ++ 0x02000000 0x10 0x00000000 ++ 0x10 0x00000000>; ++}; ++ ++// Expose RP1 nodes as system nodes with labels ++ ++&rp1_dma { ++ status = "okay"; ++}; ++ ++&rp1_eth { ++ status = "okay"; ++ phy-handle = <&phy1>; ++ phy-reset-gpios = <&rp1_gpio 32 GPIO_ACTIVE_LOW>; ++ phy-reset-duration = <5>; ++ ++ phy1: ethernet-phy@1 { ++ reg = <0x1>; ++ brcm,powerdown-enable; ++ interrupt-parent = <&gpio>; ++ interrupts = <37 IRQ_TYPE_LEVEL_LOW>; ++ }; ++}; ++ ++gpio: &rp1_gpio { ++ status = "okay"; ++}; ++ ++aux: &dummy {}; ++ ++&rp1_usb0 { ++ pinctrl-0 = <&usb_vbus_pins>; ++ pinctrl-names = "default"; ++ status = "okay"; ++}; ++ ++&rp1_usb1 { ++ status = "okay"; ++}; ++ ++#include "bcm2712-rpi.dtsi" ++ ++i2c_csi_dsi0: &i2c6 { // Note: This is for MIPI0 connector only ++ pinctrl-0 = <&rp1_i2c6_38_39>; ++ pinctrl-names = "default"; ++ clock-frequency = <100000>; ++}; ++ ++i2c_csi_dsi1: &i2c0 { // Note: This is for MIPI1 connector ++}; ++ ++i2c_csi_dsi: &i2c_csi_dsi1 { }; // An alias for compatibility ++ ++cam1_reg: &cam0_reg { // Shares CAM_GPIO with cam0_reg ++}; ++ ++csi0: &rp1_csi0 { }; ++csi1: &rp1_csi1 { }; ++dsi0: &rp1_dsi0 { }; ++dsi1: &rp1_dsi1 { }; ++dpi: &rp1_dpi { }; ++vec: &rp1_vec { }; ++dpi_gpio0: &rp1_dpi_24bit_gpio0 { }; ++dpi_gpio1: &rp1_dpi_24bit_gpio2 { }; ++dpi_18bit_cpadhi_gpio0: &rp1_dpi_18bit_cpadhi_gpio0 { }; ++dpi_18bit_cpadhi_gpio2: &rp1_dpi_18bit_cpadhi_gpio2 { }; ++dpi_18bit_gpio0: &rp1_dpi_18bit_gpio0 { }; ++dpi_18bit_gpio2: &rp1_dpi_18bit_gpio2 { }; ++dpi_16bit_cpadhi_gpio0: &rp1_dpi_16bit_cpadhi_gpio0 { }; ++dpi_16bit_cpadhi_gpio2: &rp1_dpi_16bit_cpadhi_gpio2 { }; ++dpi_16bit_gpio0: &rp1_dpi_16bit_gpio0 { }; ++dpi_16bit_gpio2: &rp1_dpi_16bit_gpio2 { }; ++ ++/* Add the IOMMUs for some RP1 bus masters */ ++ ++&csi0 { ++ iommus = <&iommu5>; ++}; ++ ++&csi1 { ++ iommus = <&iommu5>; ++}; ++ ++&dsi0 { ++ iommus = <&iommu5>; ++}; ++ ++&dsi1 { ++ iommus = <&iommu5>; ++}; ++ ++&dpi { ++ iommus = <&iommu5>; ++}; ++ ++&vec { ++ iommus = <&iommu5>; ++}; ++ ++&ddc0 { ++ status = "disabled"; ++}; ++ ++&ddc1 { ++ status = "disabled"; ++}; ++ ++&hdmi0 { ++ clocks = <&firmware_clocks 13>, <&firmware_clocks 14>, <&dvp 0>, <&clk_27MHz>; ++ clock-names = "hdmi", "bvb", "audio", "cec"; ++ status = "disabled"; ++}; ++ ++&hdmi1 { ++ clocks = <&firmware_clocks 13>, <&firmware_clocks 14>, <&dvp 1>, <&clk_27MHz>; ++ clock-names = "hdmi", "bvb", "audio", "cec"; ++ status = "disabled"; ++}; ++ ++&hvs { ++ clocks = <&firmware_clocks 4>, <&firmware_clocks 16>; ++ clock-names = "core", "disp"; ++}; ++ ++&mop { ++ status = "disabled"; ++}; ++ ++&moplet { ++ status = "disabled"; ++}; ++ ++&pixelvalve0 { ++ status = "disabled"; ++}; ++ ++&pixelvalve1 { ++ status = "disabled"; ++}; ++ ++&disp_intr { ++ status = "disabled"; ++}; ++ ++/* SDIO1 is used to drive the eMMC/SD card */ ++&sdio1 { ++ pinctrl-0 = <&emmc_cmddat_pulls>, <&emmc_ds_pull>, <&emmc_aon_cd_pins>; ++ pinctrl-names = "default"; ++ vqmmc-supply = <&sd_io_1v8_reg>; ++ vmmc-supply = <&sd_vcc_reg>; ++ bus-width = <8>; ++ sd-uhs-sdr50; ++ sd-uhs-ddr50; ++ sd-uhs-sdr104; ++ mmc-hs200-1_8v; ++ broken-cd; ++ supports-cqe; ++ status = "okay"; ++}; ++ ++&pinctrl_aon { ++ emmc_aon_cd_pins: emmc_aon_cd_pins { ++ function = "sd_card_g"; ++ pins = "aon_gpio5"; ++ bias-pull-up; ++ }; ++ ++ /* Slight hack - only one PWM pin (status LED) is usable */ ++ aon_pwm_1pin: aon_pwm_1pin { ++ function = "aon_pwm"; ++ pins = "aon_gpio9"; ++ }; ++}; ++ ++&pinctrl { ++ pwr_button_pins: pwr_button_pins { ++ function = "gpio"; ++ pins = "gpio20"; ++ bias-pull-up; ++ }; ++ ++ wl_on_pins: wl_on_pins { ++ function = "gpio"; ++ pins = "gpio28"; ++ }; ++ ++ bt_shutdown_pins: bt_shutdown_pins { ++ function = "gpio"; ++ pins = "gpio29"; ++ }; ++ ++ emmc_ds_pull: emmc_ds_pull { ++ pins = "emmc_ds"; ++ bias-pull-down; ++ }; ++ ++ emmc_cmddat_pulls: emmc_cmddat_pulls { ++ pins = "emmc_cmd", "emmc_dat0", "emmc_dat1", "emmc_dat2", "emmc_dat3", ++ "emmc_dat4", "emmc_dat5", "emmc_dat6", "emmc_dat7"; ++ bias-pull-up; ++ }; ++}; ++ ++/* uarta communicates with the BT module */ ++&uarta { ++ uart-has-rtscts; ++ auto-flow-control; ++ status = "okay"; ++ clock-frequency = <96000000>; ++ pinctrl-0 = <&uarta_24_pins &bt_shutdown_pins>; ++ pinctrl-names = "default"; ++ ++ bluetooth: bluetooth { ++ compatible = "brcm,bcm43438-bt"; ++ max-speed = <3000000>; ++ shutdown-gpios = <&gio 29 GPIO_ACTIVE_HIGH>; ++ local-bd-address = [ 00 00 00 00 00 00 ]; ++ }; ++}; ++ ++&i2c_rp1boot { ++ clock-frequency = <400000>; ++ pinctrl-0 = <&i2c3_m4_agpio0_pins>; ++ pinctrl-names = "default"; ++}; ++ ++/ { ++ chosen: chosen { ++ bootargs = "reboot=w coherent_pool=1M 8250.nr_uarts=1 pci=pcie_bus_safe snd_bcm2835.enable_compat_alsa=0 snd_bcm2835.enable_hdmi=1"; ++ stdout-path = "serial10:115200n8"; ++ }; ++ ++ fan: cooling_fan { ++ status = "disabled"; ++ compatible = "pwm-fan"; ++ #cooling-cells = <2>; ++ cooling-min-state = <0>; ++ cooling-max-state = <3>; ++ cooling-levels = <0 75 125 175 250>; ++ pwms = <&rp1_pwm1 3 41566 PWM_POLARITY_INVERTED>; ++ rpm-regmap = <&rp1_pwm1>; ++ rpm-offset = <0x3c>; ++ }; ++ ++ pwr_button { ++ compatible = "gpio-keys"; ++ ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pwr_button_pins>; ++ status = "okay"; ++ ++ pwr_key: pwr { ++ label = "pwr_button"; ++ // linux,code = <205>; // KEY_SUSPEND ++ linux,code = <116>; // KEY_POWER ++ gpios = <&gio 20 GPIO_ACTIVE_LOW>; ++ debounce-interval = <50>; // ms ++ }; ++ }; ++}; ++ ++&usb { ++ power-domains = <&power RPI_POWER_DOMAIN_USB>; ++}; ++ ++/* SDIO2 drives the WLAN interface */ ++&sdio2 { ++ pinctrl-0 = <&sdio2_30_pins>; ++ pinctrl-names = "default"; ++ bus-width = <4>; ++ vmmc-supply = <&wl_on_reg>; ++ sd-uhs-ddr50; ++ non-removable; ++ status = "okay"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ wifi: wifi@1 { ++ reg = <1>; ++ compatible = "brcm,bcm4329-fmac"; ++ local-mac-address = [00 00 00 00 00 00]; ++ }; ++}; ++ ++&rpivid { ++ status = "okay"; ++}; ++ ++&pinctrl { ++ spi10_gpio2: spi10_gpio2 { ++ function = "vc_spi0"; ++ pins = "gpio2", "gpio3", "gpio4"; ++ bias-disable; ++ }; ++ ++ spi10_cs_gpio1: spi10_cs_gpio1 { ++ function = "gpio"; ++ pins = "gpio1"; ++ bias-pull-up; ++ }; ++}; ++ ++spi10_pins: &spi10_gpio2 {}; ++spi10_cs_pins: &spi10_cs_gpio1 {}; ++ ++&spi10 { ++ pinctrl-names = "default"; ++ cs-gpios = <&gio 1 1>; ++ pinctrl-0 = <&spi10_pins &spi10_cs_pins>; ++ ++ spidev10: spidev@0 { ++ compatible = "spidev"; ++ reg = <0>; /* CE0 */ ++ #address-cells = <1>; ++ #size-cells = <0>; ++ spi-max-frequency = <20000000>; ++ status = "okay"; ++ }; ++}; ++ ++// ============================================= ++// Board specific stuff here ++ ++&gio_aon { ++ // Don't use GIO_AON as an interrupt controller because it will ++ // clash with the firmware monitoring the PMIC interrupt via the VPU. ++ ++ /delete-property/ interrupt-controller; ++}; ++ ++&main_aon_irq { ++ // Don't use the MAIN_AON_IRQ interrupt controller because it will ++ // clash with the firmware monitoring the PMIC interrupt via the VPU. ++ ++ status = "disabled"; ++}; ++ ++&rp1_pwm1 { ++ status = "disabled"; ++ pinctrl-0 = <&rp1_pwm1_gpio45>; ++ pinctrl-names = "default"; ++}; ++ ++&thermal_trips { ++ cpu_tepid: cpu-tepid { ++ temperature = <50000>; ++ hysteresis = <5000>; ++ type = "active"; ++ }; ++ ++ cpu_warm: cpu-warm { ++ temperature = <60000>; ++ hysteresis = <5000>; ++ type = "active"; ++ }; ++ ++ cpu_hot: cpu-hot { ++ temperature = <67500>; ++ hysteresis = <5000>; ++ type = "active"; ++ }; ++ ++ cpu_vhot: cpu-vhot { ++ temperature = <75000>; ++ hysteresis = <5000>; ++ type = "active"; ++ }; ++}; ++ ++&cooling_maps { ++ tepid { ++ trip = <&cpu_tepid>; ++ cooling-device = <&fan 1 1>; ++ }; ++ ++ warm { ++ trip = <&cpu_warm>; ++ cooling-device = <&fan 2 2>; ++ }; ++ ++ hot { ++ trip = <&cpu_hot>; ++ cooling-device = <&fan 3 3>; ++ }; ++ ++ vhot { ++ trip = <&cpu_vhot>; ++ cooling-device = <&fan 4 4>; ++ }; ++ ++ melt { ++ trip = <&cpu_crit>; ++ cooling-device = <&fan 4 4>; ++ }; ++}; ++ ++&gio { ++ // The GPIOs above 35 are not used on Pi 5, so shrink the upper bank ++ // to reduce the clutter in gpioinfo/pinctrl ++ brcm,gpio-bank-widths = <32 4>; ++ ++ gpio-line-names = ++ "-", // GPIO_000 ++ "2712_BOOT_CS_N", // GPIO_001 ++ "2712_BOOT_MISO", // GPIO_002 ++ "2712_BOOT_MOSI", // GPIO_003 ++ "2712_BOOT_SCLK", // GPIO_004 ++ "-", // GPIO_005 ++ "-", // GPIO_006 ++ "-", // GPIO_007 ++ "-", // GPIO_008 ++ "-", // GPIO_009 ++ "-", // GPIO_010 ++ "-", // GPIO_011 ++ "-", // GPIO_012 ++ "-", // GPIO_013 ++ "-", // GPIO_014 ++ "-", // GPIO_015 ++ "-", // GPIO_016 ++ "-", // GPIO_017 ++ "-", // GPIO_018 ++ "-", // GPIO_019 ++ "PWR_GPIO", // GPIO_020 ++ "2712_G21_FS", // GPIO_021 ++ "-", // GPIO_022 ++ "-", // GPIO_023 ++ "BT_RTS", // GPIO_024 ++ "BT_CTS", // GPIO_025 ++ "BT_TXD", // GPIO_026 ++ "BT_RXD", // GPIO_027 ++ "WL_ON", // GPIO_028 ++ "BT_ON", // GPIO_029 ++ "WIFI_SDIO_CLK", // GPIO_030 ++ "WIFI_SDIO_CMD", // GPIO_031 ++ "WIFI_SDIO_D0", // GPIO_032 ++ "WIFI_SDIO_D1", // GPIO_033 ++ "WIFI_SDIO_D2", // GPIO_034 ++ "WIFI_SDIO_D3"; // GPIO_035 ++}; ++ ++&gio_aon { ++ gpio-line-names = ++ "RP1_SDA", // AON_GPIO_00 ++ "RP1_SCL", // AON_GPIO_01 ++ "RP1_RUN", // AON_GPIO_02 ++ "SD_IOVDD_SEL", // AON_GPIO_03 ++ "SD_PWR_ON", // AON_GPIO_04 ++ "ANT1", // AON_GPIO_05 ++ "ANT2", // AON_GPIO_06 ++ "-", // AON_GPIO_07 ++ "2712_WAKE", // AON_GPIO_08 ++ "2712_STAT_LED", // AON_GPIO_09 ++ "-", // AON_GPIO_10 ++ "-", // AON_GPIO_11 ++ "PMIC_INT", // AON_GPIO_12 ++ "UART_TX_FS", // AON_GPIO_13 ++ "UART_RX_FS", // AON_GPIO_14 ++ "-", // AON_GPIO_15 ++ "-", // AON_GPIO_16 ++ ++ // Pad bank0 out to 32 entries ++ "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", ++ ++ "HDMI0_SCL", // AON_SGPIO_00 ++ "HDMI0_SDA", // AON_SGPIO_01 ++ "HDMI1_SCL", // AON_SGPIO_02 ++ "HDMI1_SDA", // AON_SGPIO_03 ++ "PMIC_SCL", // AON_SGPIO_04 ++ "PMIC_SDA"; // AON_SGPIO_05 ++ ++ rp1_run_hog { ++ gpio-hog; ++ gpios = <2 GPIO_ACTIVE_HIGH>; ++ output-high; ++ line-name = "RP1 RUN pin"; ++ }; ++}; ++ ++&rp1_gpio { ++ gpio-line-names = ++ "ID_SDA", // GPIO0 ++ "ID_SCL", // GPIO1 ++ "GPIO2", // GPIO2 ++ "GPIO3", // GPIO3 ++ "GPIO4", // GPIO4 ++ "GPIO5", // GPIO5 ++ "GPIO6", // GPIO6 ++ "GPIO7", // GPIO7 ++ "GPIO8", // GPIO8 ++ "GPIO9", // GPIO9 ++ "GPIO10", // GPIO10 ++ "GPIO11", // GPIO11 ++ "GPIO12", // GPIO12 ++ "GPIO13", // GPIO13 ++ "GPIO14", // GPIO14 ++ "GPIO15", // GPIO15 ++ "GPIO16", // GPIO16 ++ "GPIO17", // GPIO17 ++ "GPIO18", // GPIO18 ++ "GPIO19", // GPIO19 ++ "GPIO20", // GPIO20 ++ "GPIO21", // GPIO21 ++ "GPIO22", // GPIO22 ++ "GPIO23", // GPIO23 ++ "GPIO24", // GPIO24 ++ "GPIO25", // GPIO25 ++ "GPIO26", // GPIO26 ++ "GPIO27", // GPIO27 ++ ++ "PCIE_PWR_EN", // GPIO28 ++ "FAN_TACH", // GPIO29 ++ "HOST_SDA", // GPIO30 ++ "HOST_SCL", // GPIO31 ++ "ETH_RST_N", // GPIO32 ++ "PCIE_DET_WAKE", // GPIO33 ++ ++ "CD0_IO0_MICCLK", // GPIO34 ++ "CD0_IO0_MICDAT0", // GPIO35 ++ "RP1_PCIE_CLKREQ_N", // GPIO36 ++ "ETH_IRQ_N", // GPIO37 ++ "SDA0", // GPIO38 ++ "SCL0", // GPIO39 ++ "-", // GPIO40 ++ "-", // GPIO41 ++ "USB_VBUS_EN", // GPIO42 ++ "USB_OC_N", // GPIO43 ++ "RP1_STAT_LED", // GPIO44 ++ "FAN_PWM", // GPIO45 ++ "-", // GPIO46 ++ "2712_WAKE", // GPIO47 ++ "-", // GPIO48 ++ "-", // GPIO49 ++ "-", // GPIO50 ++ "-", // GPIO51 ++ "-", // GPIO52 ++ "-"; // GPIO53 ++ ++ usb_vbus_pins: usb_vbus_pins { ++ function = "vbus1"; ++ pins = "gpio42", "gpio43"; ++ }; ++}; ++ ++/ { ++ aliases: aliases { ++ blconfig = &blconfig; ++ blpubkey = &blpubkey; ++ bluetooth = &bluetooth; ++ console = &uart10; ++ ethernet0 = &rp1_eth; ++ wifi0 = &wifi; ++ fb = &fb; ++ mailbox = &mailbox; ++ mmc0 = &sdio1; ++ uart0 = &uart0; ++ uart1 = &uart1; ++ uart2 = &uart2; ++ uart3 = &uart3; ++ uart4 = &uart4; ++ uart10 = &uart10; ++ serial0 = &uart0; ++ serial1 = &uart1; ++ serial2 = &uart2; ++ serial3 = &uart3; ++ serial4 = &uart4; ++ serial10 = &uart10; ++ i2c = &i2c_arm; ++ i2c0 = &i2c0; ++ i2c1 = &i2c1; ++ i2c2 = &i2c2; ++ i2c3 = &i2c3; ++ i2c4 = &i2c4; ++ i2c5 = &i2c5; ++ i2c6 = &i2c6; ++ i2c10 = &i2c_rp1boot; ++ // Bit-bashed i2c_gpios start at 10 ++ spi0 = &spi0; ++ spi1 = &spi1; ++ spi2 = &spi2; ++ spi3 = &spi3; ++ spi4 = &spi4; ++ spi5 = &spi5; ++ spi10 = &spi10; ++ gpio0 = &gpio; ++ gpio1 = &gio; ++ gpio2 = &gio_aon; ++ gpio3 = &pinctrl; ++ gpio4 = &pinctrl_aon; ++ usb0 = &rp1_usb0; ++ usb1 = &rp1_usb1; ++ drm-dsi1 = &dsi0; ++ drm-dsi2 = &dsi1; ++ }; ++ ++ __overrides__ { ++ bdaddr = <&bluetooth>, "local-bd-address["; ++ button_debounce = <&pwr_key>, "debounce-interval:0"; ++ cooling_fan = <&fan>, "status", <&rp1_pwm1>, "status"; ++ uart0_console = <&uart0>,"status", <&aliases>, "console=",&uart0; ++ i2c0 = <&i2c0>, "status"; ++ i2c1 = <&i2c1>, "status"; ++ i2c = <&i2c1>, "status"; ++ i2c_arm = <&i2c_arm>, "status"; ++ i2c_vc = <&i2c_vc>, "status"; ++ i2c_csi_dsi = <&i2c_csi_dsi>, "status"; ++ i2c_csi_dsi0 = <&i2c_csi_dsi0>, "status"; ++ i2c_csi_dsi1 = <&i2c_csi_dsi1>, "status"; ++ i2c0_baudrate = <&i2c0>, "clock-frequency:0"; ++ i2c1_baudrate = <&i2c1>, "clock-frequency:0"; ++ i2c_baudrate = <&i2c_arm>, "clock-frequency:0"; ++ i2c_arm_baudrate = <&i2c_arm>, "clock-frequency:0"; ++ i2c_vc_baudrate = <&i2c_vc>, "clock-frequency:0"; ++ krnbt = <&bluetooth>, "status"; ++ nvme = <&pciex1>, "status"; ++ pciex1 = <&pciex1>, "status"; ++ pciex1_gen = <&pciex1> , "max-link-speed:0"; ++ pciex1_no_l0s = <&pciex1>, "aspm-no-l0s?"; ++ pciex1_tperst_clk_ms = <&pciex1>, "brcm,tperst-clk-ms:0"; ++ pcie_tperst_clk_ms = <&pciex1>, "brcm,tperst-clk-ms:0"; ++ random = <&random>, "status"; ++ rtc = <&rpi_rtc>, "status"; ++ rtc_bbat_vchg = <&rpi_rtc>, "trickle-charge-microvolt:0"; ++ spi = <&spi0>, "status"; ++ suspend = <&pwr_key>, "linux,code:0=205"; ++ uart0 = <&uart0>, "status"; ++ wifiaddr = <&wifi>, "local-mac-address["; ++ ++ act_led_activelow = <&led_act>, "active-low?"; ++ act_led_trigger = <&led_act>, "linux,default-trigger"; ++ pwr_led_activelow = <&led_pwr>, "gpios:8"; ++ pwr_led_trigger = <&led_pwr>, "linux,default-trigger"; ++ eth_led0 = <&phy1>,"led-modes:0"; ++ eth_led1 = <&phy1>,"led-modes:4"; ++ drm_fb0_rp1_dsi0 = <&aliases>, "drm-fb0=",&dsi0; ++ drm_fb0_rp1_dsi1 = <&aliases>, "drm-fb0=",&dsi1; ++ drm_fb0_rp1_dpi = <&aliases>, "drm-fb0=",&dpi; ++ drm_fb0_vc4 = <&aliases>, "drm-fb0=",&vc4; ++ drm_fb1_rp1_dsi0 = <&aliases>, "drm-fb1=",&dsi0; ++ drm_fb1_rp1_dsi1 = <&aliases>, "drm-fb1=",&dsi1; ++ drm_fb1_rp1_dpi = <&aliases>, "drm-fb1=",&dpi; ++ drm_fb1_vc4 = <&aliases>, "drm-fb1=",&vc4; ++ drm_fb2_rp1_dsi0 = <&aliases>, "drm-fb2=",&dsi0; ++ drm_fb2_rp1_dsi1 = <&aliases>, "drm-fb2=",&dsi1; ++ drm_fb2_rp1_dpi = <&aliases>, "drm-fb2=",&dpi; ++ drm_fb2_vc4 = <&aliases>, "drm-fb2=",&vc4; ++ ++ fan_temp0 = <&cpu_tepid>,"temperature:0"; ++ fan_temp1 = <&cpu_warm>,"temperature:0"; ++ fan_temp2 = <&cpu_hot>,"temperature:0"; ++ fan_temp3 = <&cpu_vhot>,"temperature:0"; ++ fan_temp0_hyst = <&cpu_tepid>,"hysteresis:0"; ++ fan_temp1_hyst = <&cpu_warm>,"hysteresis:0"; ++ fan_temp2_hyst = <&cpu_hot>,"hysteresis:0"; ++ fan_temp3_hyst = <&cpu_vhot>,"hysteresis:0"; ++ fan_temp0_speed = <&fan>, "cooling-levels:4"; ++ fan_temp1_speed = <&fan>, "cooling-levels:8"; ++ fan_temp2_speed = <&fan>, "cooling-levels:12"; ++ fan_temp3_speed = <&fan>, "cooling-levels:16"; ++ }; ++}; +diff --git a/arch/arm/boot/dts/broadcom/bcm2712-rpi.dtsi b/arch/arm/boot/dts/broadcom/bcm2712-rpi.dtsi +new file mode 100644 +index 000000000000..359a30d6ef5f +--- /dev/null ++++ b/arch/arm/boot/dts/broadcom/bcm2712-rpi.dtsi +@@ -0,0 +1,336 @@ ++// SPDX-License-Identifier: GPL-2.0 ++ ++#include ++ ++&soc { ++ firmware: firmware { ++ compatible = "raspberrypi,bcm2835-firmware", "simple-mfd"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ mboxes = <&mailbox>; ++ dma-ranges; ++ ++ firmware_clocks: clocks { ++ compatible = "raspberrypi,firmware-clocks"; ++ #clock-cells = <1>; ++ }; ++ ++ reset: reset { ++ compatible = "raspberrypi,firmware-reset"; ++ #reset-cells = <1>; ++ }; ++ ++ vcio: vcio { ++ compatible = "raspberrypi,vcio"; ++ }; ++ }; ++ ++ power: power { ++ compatible = "raspberrypi,bcm2835-power"; ++ firmware = <&firmware>; ++ #power-domain-cells = <1>; ++ }; ++ ++ fb: fb { ++ compatible = "brcm,bcm2708-fb"; ++ firmware = <&firmware>; ++ status = "okay"; ++ }; ++ ++ rpi_rtc: rpi_rtc { ++ compatible = "raspberrypi,rpi-rtc"; ++ firmware = <&firmware>; ++ status = "okay"; ++ trickle-charge-microvolt = <0>; ++ }; ++ ++ nvmem_otp: nvmem_otp { ++ compatible = "raspberrypi,rpi-otp"; ++ firmware = <&firmware>; ++ reg = <0 192>; ++ status = "okay"; ++ }; ++ ++ nvmem_cust: nvmem_cust { ++ compatible = "raspberrypi,rpi-otp"; ++ firmware = <&firmware>; ++ reg = <1 8>; ++ status = "okay"; ++ }; ++ ++ nvmem_mac: nvmem_mac { ++ compatible = "raspberrypi,rpi-otp"; ++ firmware = <&firmware>; ++ reg = <2 6>; ++ status = "okay"; ++ }; ++ ++ nvmem_priv: nvmem_priv { ++ compatible = "raspberrypi,rpi-otp"; ++ firmware = <&firmware>; ++ reg = <3 16>; ++ status = "okay"; ++ }; ++ ++ /* Define these notional regulators for use by overlays, etc. */ ++ vdd_3v3_reg: fixedregulator_3v3 { ++ compatible = "regulator-fixed"; ++ regulator-always-on; ++ regulator-max-microvolt = <3300000>; ++ regulator-min-microvolt = <3300000>; ++ regulator-name = "3v3"; ++ }; ++ ++ vdd_5v0_reg: fixedregulator_5v0 { ++ compatible = "regulator-fixed"; ++ regulator-always-on; ++ regulator-max-microvolt = <5000000>; ++ regulator-min-microvolt = <5000000>; ++ regulator-name = "5v0"; ++ }; ++}; ++ ++/ { ++ __overrides__ { ++ arm_freq; ++ axiperf = <&axiperf>,"status"; ++ ++ nvmem_cust_rw = <&nvmem_cust>,"rw?"; ++ nvmem_priv_rw = <&nvmem_priv>,"rw?"; ++ nvmem_mac_rw = <&nvmem_mac>,"rw?"; ++ }; ++}; ++ ++pciex1: &pcie1 { }; ++pciex4: &pcie2 { }; ++ ++&dma32 { ++ /* The VPU firmware uses DMA channel 11 for VCHIQ */ ++ brcm,dma-channel-mask = <0x03f>; ++}; ++ ++&dma40 { ++ /* The VPU firmware DMA channel 11 for VCHIQ */ ++ brcm,dma-channel-mask = <0x07c0>; ++}; ++ ++&hdmi0 { ++ dmas = <&dma40 (10|(1<<30)|(1<<24)|(10<<16)|(15<<20))>; ++}; ++ ++&hdmi1 { ++ dmas = <&dma40 (17|(1<<30)|(1<<24)|(10<<16)|(15<<20))>; ++}; ++ ++&spi10 { ++ dmas = <&dma40 6>, <&dma40 7>; ++ dma-names = "tx", "rx"; ++}; ++ ++&usb { ++ power-domains = <&power RPI_POWER_DOMAIN_USB>; ++}; ++ ++&rmem { ++ /* ++ * RPi5's co-processor will copy the board's bootloader configuration ++ * into memory for the OS to consume. It'll also update this node with ++ * its placement information. ++ */ ++ blconfig: nvram@0 { ++ compatible = "raspberrypi,bootloader-config", "nvmem-rmem"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ reg = <0x0 0x0 0x0>; ++ no-map; ++ status = "disabled"; ++ }; ++ /* ++ * RPi5 will copy the binary public key blob (if present) from the bootloader ++ * into memory for use by the OS. ++ */ ++ blpubkey: nvram@1 { ++ compatible = "raspberrypi,bootloader-public-key", "nvmem-rmem"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ reg = <0x0 0x0 0x0>; ++ no-map; ++ status = "disabled"; ++ }; ++}; ++ ++&rp1_adc { ++ status = "okay"; ++}; ++ ++/* Add some gpiomem nodes to make the devices accessible to userspace. ++ * /dev/gpiomem should expose the registers for the interface with DT alias ++ * gpio. ++ */ ++ ++&rp1 { ++ gpiomem@d0000 { ++ /* Export IO_BANKs, RIO_BANKs and PADS_BANKs to userspace */ ++ compatible = "raspberrypi,gpiomem"; ++ reg = <0xc0 0x400d0000 0x0 0x30000>; ++ chardev-name = "gpiomem0"; ++ }; ++}; ++ ++&soc { ++ gpiomem@7d508500 { ++ compatible = "raspberrypi,gpiomem"; ++ reg = <0x7d508500 0x40>; ++ chardev-name = "gpiomem1"; ++ }; ++ ++ gpiomem@7d517c00 { ++ compatible = "raspberrypi,gpiomem"; ++ reg = <0x7d517c00 0x40>; ++ chardev-name = "gpiomem2"; ++ }; ++ ++ gpiomem@7d504100 { ++ compatible = "raspberrypi,gpiomem"; ++ reg = <0x7d504100 0x20>; ++ chardev-name = "gpiomem3"; ++ }; ++ ++ gpiomem@7d510700 { ++ compatible = "raspberrypi,gpiomem"; ++ reg = <0x7d510700 0x20>; ++ chardev-name = "gpiomem4"; ++ }; ++ ++ sound: sound { ++ status = "disabled"; ++ }; ++}; ++ ++i2c0: &rp1_i2c0 { }; ++i2c1: &rp1_i2c1 { }; ++i2c2: &rp1_i2c2 { }; ++i2c3: &rp1_i2c3 { }; ++i2c4: &rp1_i2c4 { }; ++i2c5: &rp1_i2c5 { }; ++i2c6: &rp1_i2c6 { }; ++i2s: &rp1_i2s0 { }; ++i2s_clk_producer: &rp1_i2s0 { }; ++i2s_clk_consumer: &rp1_i2s1 { }; ++pwm0: &rp1_pwm0 { }; ++pwm1: &rp1_pwm1 { }; ++pwm: &pwm0 { }; ++spi0: &rp1_spi0 { }; ++spi1: &rp1_spi1 { }; ++spi2: &rp1_spi2 { }; ++spi3: &rp1_spi3 { }; ++spi4: &rp1_spi4 { }; ++spi5: &rp1_spi5 { }; ++ ++uart0_pins: &rp1_uart0_14_15 {}; ++uart0_ctsrts_pins: &rp1_uart0_ctsrts_16_17 {}; ++uart0: &rp1_uart0 { ++ pinctrl-0 = <&uart0_pins>; ++}; ++ ++uart1_pins: &rp1_uart1_0_1 {}; ++uart1_ctsrts_pins: &rp1_uart1_ctsrts_2_3 {}; ++uart1: &rp1_uart1 { }; ++ ++uart2_pins: &rp1_uart2_4_5 {}; ++uart2_ctsrts_pins: &rp1_uart2_ctsrts_6_7 {}; ++uart2: &rp1_uart2 { }; ++ ++uart3_pins: &rp1_uart3_8_9 {}; ++uart3_ctsrts_pins: &rp1_uart3_ctsrts_10_11 {}; ++uart3: &rp1_uart3 { }; ++ ++uart4_pins: &rp1_uart4_12_13 {}; ++uart4_ctsrts_pins: &rp1_uart4_ctsrts_14_15 {}; ++uart4: &rp1_uart4 { }; ++ ++i2c0_pins: &rp1_i2c0_0_1 {}; ++i2c_vc: &i2c0 { // This is pins 27,28 on the header (not MIPI) ++ pinctrl-0 = <&i2c0_pins>; ++ pinctrl-names = "default"; ++ clock-frequency = <100000>; ++}; ++ ++i2c1_pins: &rp1_i2c1_2_3 {}; ++i2c_arm: &i2c1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c1_pins>; ++ clock-frequency = <100000>; ++}; ++ ++i2c2_pins: &rp1_i2c2_4_5 {}; ++&i2c2 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c2_pins>; ++}; ++ ++i2c3_pins: &rp1_i2c3_6_7 {}; ++&i2c3 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c3_pins>; ++}; ++ ++&i2s_clk_producer { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&rp1_i2s0_18_21>; ++}; ++ ++&i2s_clk_consumer { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&rp1_i2s1_18_21>; ++}; ++ ++spi0_pins: &rp1_spi0_gpio9 {}; ++spi0_cs_pins: &rp1_spi0_cs_gpio7 {}; ++ ++&spi0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi0_pins &spi0_cs_pins>; ++ cs-gpios = <&gpio 8 1>, <&gpio 7 1>; ++ ++ spidev0: spidev@0 { ++ compatible = "spidev"; ++ reg = <0>; /* CE0 */ ++ #address-cells = <1>; ++ #size-cells = <0>; ++ spi-max-frequency = <125000000>; ++ }; ++ ++ spidev1: spidev@1 { ++ compatible = "spidev"; ++ reg = <1>; /* CE1 */ ++ #address-cells = <1>; ++ #size-cells = <0>; ++ spi-max-frequency = <125000000>; ++ }; ++}; ++ ++spi2_pins: &rp1_spi2_gpio1 {}; ++&spi2 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi2_pins>; ++}; ++ ++spi3_pins: &rp1_spi3_gpio5 {}; ++&spi3 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi3_pins>; ++}; ++ ++spi4_pins: &rp1_spi4_gpio9 {}; ++&spi4 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi4_pins>; ++}; ++ ++spi5_pins: &rp1_spi5_gpio13 {}; ++&spi5 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi5_pins>; ++}; +diff --git a/arch/arm/boot/dts/broadcom/bcm2712.dtsi b/arch/arm/boot/dts/broadcom/bcm2712.dtsi +new file mode 100644 +index 000000000000..ee389a9cf89b +--- /dev/null ++++ b/arch/arm/boot/dts/broadcom/bcm2712.dtsi +@@ -0,0 +1,1304 @@ ++// SPDX-License-Identifier: GPL-2.0 ++#include ++#include ++#include ++ ++/ { ++ compatible = "brcm,bcm2712", "brcm,bcm2711"; ++ model = "BCM2712"; ++ ++ #address-cells = <2>; ++ #size-cells = <1>; ++ ++ interrupt-parent = <&gicv2>; ++ ++ rmem: reserved-memory { ++ #address-cells = <2>; ++ #size-cells = <1>; ++ ranges; ++ ++ atf@0 { ++ reg = <0x0 0x0 0x80000>; ++ no-map; ++ }; ++ ++ cma: linux,cma { ++ compatible = "shared-dma-pool"; ++ size = <0x4000000>; /* 64MB */ ++ reusable; ++ linux,cma-default; ++ ++ /* ++ * arm64 reserves the CMA by default somewhere in ++ * ZONE_DMA32, that's not good enough for the BCM2711 ++ * as some devices can only address the lower 1G of ++ * memory (ZONE_DMA). ++ */ ++ alloc-ranges = <0x0 0x00000000 0x40000000>; ++ }; ++ }; ++ ++ thermal-zones { ++ cpu_thermal: cpu-thermal { ++ polling-delay-passive = <2000>; ++ polling-delay = <1000>; ++ coefficients = <(-550) 450000>; ++ thermal-sensors = <&thermal>; ++ ++ thermal_trips: trips { ++ cpu_crit: cpu-crit { ++ temperature = <110000>; ++ hysteresis = <0>; ++ type = "critical"; ++ }; ++ }; ++ ++ cooling_maps: cooling-maps { ++ }; ++ }; ++ }; ++ ++ clk_27MHz: clk-27M { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <27000000>; ++ clock-output-names = "27MHz-clock"; ++ }; ++ ++ clk_108MHz: clk-108M { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <108000000>; ++ clock-output-names = "108MHz-clock"; ++ }; ++ ++ hvs: hvs@107c580000 { ++ compatible = "brcm,bcm2712-hvs"; ++ reg = <0x10 0x7c580000 0x1a000>; ++ interrupt-parent = <&disp_intr>; ++ interrupts = <2>, <9>, <16>; ++ interrupt-names = "ch0-eof", "ch1-eof", "ch2-eof"; ++ //iommus = <&iommu4>; ++ status = "disabled"; ++ }; ++ ++ soc: soc { ++ compatible = "simple-bus"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ ranges = <0x7c000000 0x10 0x7c000000 0x04000000>; ++ /* Emulate a contiguous 30-bit address range for DMA */ ++ dma-ranges = <0xc0000000 0x00 0x00000000 0x40000000>, ++ <0x7c000000 0x10 0x7c000000 0x04000000>; ++ ++ system_timer: timer@7c003000 { ++ compatible = "brcm,bcm2835-system-timer"; ++ reg = <0x7c003000 0x1000>; ++ interrupts = , ++ , ++ , ++ ; ++ clock-frequency = <1000000>; ++ }; ++ ++ firmwarekms: firmwarekms@7d503000 { ++ compatible = "raspberrypi,rpi-firmware-kms-2712"; ++ /* SUN_L2 interrupt reg */ ++ reg = <0x7d503000 0x18>; ++ interrupt-parent = <&cpu_l2_irq>; ++ interrupts = <19>; ++ brcm,firmware = <&firmware>; + status = "disabled"; + }; + - dvp: clock@7ef00000 { - compatible = "brcm,brcm2711-dvp"; - reg = <0x7ef00000 0x10>; -@@ -308,6 +316,15 @@ dvp: clock@7ef00000 { - #reset-cells = <1>; - }; - -+ aon_intr: interrupt-controller@7ef00100 { ++ axiperf: axiperf { ++ compatible = "brcm,bcm2712-axiperf"; ++ reg = <0x7c012800 0x100>, ++ <0x7e000000 0x100>; ++ firmware = <&firmware>; ++ status = "disabled"; ++ }; ++ ++ mailbox: mailbox@7c013880 { ++ compatible = "brcm,bcm2835-mbox"; ++ reg = <0x7c013880 0x40>; ++ interrupts = ; ++ #mbox-cells = <0>; ++ }; ++ ++ pixelvalve0: pixelvalve@7c410000 { ++ compatible = "brcm,bcm2712-pixelvalve0"; ++ reg = <0x7c410000 0x100>; ++ interrupts = ; ++ status = "disabled"; ++ }; ++ ++ pixelvalve1: pixelvalve@7c411000 { ++ compatible = "brcm,bcm2712-pixelvalve1"; ++ reg = <0x7c411000 0x100>; ++ interrupts = ; ++ status = "disabled"; ++ }; ++ ++ mop: mop@7c500000 { ++ compatible = "brcm,bcm2712-mop"; ++ reg = <0x7c500000 0x28>; ++ interrupt-parent = <&disp_intr>; ++ interrupts = <1>; ++ status = "disabled"; ++ }; ++ ++ moplet: moplet@7c501000 { ++ compatible = "brcm,bcm2712-moplet"; ++ reg = <0x7c501000 0x20>; ++ interrupt-parent = <&disp_intr>; ++ interrupts = <0>; ++ status = "disabled"; ++ }; ++ ++ disp_intr: interrupt-controller@7c502000 { + compatible = "brcm,bcm2711-l2-intc", "brcm,l2-intc"; -+ reg = <0x7ef00100 0x30>; -+ interrupts = ; ++ reg = <0x7c502000 0x30>; ++ interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + status = "disabled"; + }; + - hdmi0: hdmi@7ef00700 { - compatible = "brcm,bcm2711-hdmi0"; - reg = <0x7ef00700 0x300>, -@@ -318,7 +335,8 @@ hdmi0: hdmi@7ef00700 { - <0x7ef01f00 0x400>, - <0x7ef00200 0x80>, - <0x7ef04300 0x100>, -- <0x7ef20000 0x100>; -+ <0x7ef20000 0x100>, -+ <0x7ef00100 0x30>; - reg-names = "hdmi", - "dvp", - "phy", -@@ -327,11 +345,21 @@ hdmi0: hdmi@7ef00700 { - "metadata", - "csc", - "cec", -- "hd"; -+ "hd", -+ "intr2"; -+ clocks = <&firmware_clocks 13>, -+ <&firmware_clocks 14>, -+ <&dvp 0>, -+ <&clk_27MHz>; - clock-names = "hdmi", "bvb", "audio", "cec"; - resets = <&dvp 0>; ++ dvp: clock@7c700000 { ++ compatible = "brcm,brcm2711-dvp"; ++ reg = <0x7c700000 0x10>; ++ clocks = <&clk_108MHz>; ++ #clock-cells = <1>; ++ #reset-cells = <1>; ++ }; ++ ++ /* ++ * This node is the provider for the enable-method for ++ * bringing up secondary cores. ++ */ ++ local_intc: local_intc@7cd00000 { ++ compatible = "brcm,bcm2836-l1-intc"; ++ reg = <0x7cd00000 0x100>; ++ }; ++ ++ uart0: serial@7d001000 { ++ compatible = "arm,pl011", "arm,primecell"; ++ reg = <0x7d001000 0x200>; ++ interrupts = ; ++ clocks = <&clk_uart>, ++ <&clk_vpu>; ++ clock-names = "uartclk", "apb_pclk"; ++ arm,primecell-periphid = <0x00241011>; ++ status = "disabled"; ++ }; ++ ++ uart2: serial@7d001400 { ++ compatible = "arm,pl011", "arm,primecell"; ++ reg = <0x7d001400 0x200>; ++ interrupts = ; ++ clocks = <&clk_uart>, ++ <&clk_vpu>; ++ clock-names = "uartclk", "apb_pclk"; ++ arm,primecell-periphid = <0x00241011>; ++ status = "disabled"; ++ }; ++ ++ uart5: serial@7d001a00 { ++ compatible = "arm,pl011", "arm,primecell"; ++ reg = <0x7d001a00 0x200>; ++ interrupts = ; ++ clocks = <&clk_uart>, ++ <&clk_vpu>; ++ clock-names = "uartclk", "apb_pclk"; ++ arm,primecell-periphid = <0x00241011>; ++ status = "disabled"; ++ }; ++ ++ sdhost: mmc@7d002000 { ++ compatible = "brcm,bcm2835-sdhost"; ++ reg = <0x7d002000 0x100>; ++ //interrupts = ; ++ clocks = <&clk_vpu>; ++ status = "disabled"; ++ }; ++ ++ i2s: i2s@7d003000 { ++ compatible = "brcm,bcm2835-i2s"; ++ reg = <0x7d003000 0x24>; ++ //clocks = <&cprman BCM2835_CLOCK_PCM>; ++ status = "disabled"; ++ }; ++ ++ spi0: spi@7d004000 { ++ compatible = "brcm,bcm2835-spi"; ++ reg = <0x7d004000 0x200>; ++ interrupts = ; ++ clocks = <&clk_vpu>; ++ num-cs = <1>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ spi3: spi@7d004600 { ++ compatible = "brcm,bcm2835-spi"; ++ reg = <0x7d004600 0x0200>; ++ interrupts = ; ++ clocks = <&clk_vpu>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ spi4: spi@7d004800 { ++ compatible = "brcm,bcm2835-spi"; ++ reg = <0x7d004800 0x0200>; ++ interrupts = ; ++ clocks = <&clk_vpu>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ spi5: spi@7d004a00 { ++ compatible = "brcm,bcm2835-spi"; ++ reg = <0x7d004a00 0x0200>; ++ interrupts = ; ++ clocks = <&clk_vpu>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ spi6: spi@7d004c00 { ++ compatible = "brcm,bcm2835-spi"; ++ reg = <0x7d004c00 0x0200>; ++ interrupts = ; ++ clocks = <&clk_vpu>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ i2c0: i2c@7d005000 { ++ compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c"; ++ reg = <0x7d005000 0x20>; ++ interrupts = ; ++ clocks = <&clk_vpu>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ i2c3: i2c@7d005600 { ++ compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c"; ++ reg = <0x7d005600 0x20>; ++ interrupts = ; ++ clocks = <&clk_vpu>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ i2c4: i2c@7d005800 { ++ compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c"; ++ reg = <0x7d005800 0x20>; ++ interrupts = ; ++ clocks = <&clk_vpu>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ i2c5: i2c@7d005a00 { ++ compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c"; ++ reg = <0x7d005a00 0x20>; ++ interrupts = ; ++ clocks = <&clk_vpu>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ i2c6: i2c@7d005c00 { ++ compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c"; ++ reg = <0x7d005c00 0x20>; ++ interrupts = ; ++ clocks = <&clk_vpu>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ i2c8: i2c@7d005e00 { ++ compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c"; ++ reg = <0x7d005e00 0x20>; ++ interrupts = ; ++ clocks = <&clk_vpu>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ pwm0: pwm@7d00c000 { ++ compatible = "brcm,bcm2835-pwm"; ++ reg = <0x7d00c000 0x28>; ++ assigned-clock-rates = <50000000>; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ ++ pwm1: pwm@7d00c800 { ++ compatible = "brcm,bcm2835-pwm"; ++ reg = <0x7d00c800 0x28>; ++ assigned-clock-rates = <50000000>; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ ++ pm: watchdog@7d200000 { ++ compatible = "brcm,bcm2712-pm"; ++ reg = <0x7d200000 0x308>; ++ reg-names = "pm"; ++ #power-domain-cells = <1>; ++ #reset-cells = <1>; ++ //clocks = <&cprman BCM2835_CLOCK_V3D>, ++ // <&cprman BCM2835_CLOCK_PERI_IMAGE>, ++ // <&cprman BCM2835_CLOCK_H264>, ++ // <&cprman BCM2835_CLOCK_ISP>; ++ clock-names = "v3d", "peri_image", "h264", "isp"; ++ system-power-controller; ++ }; ++ ++ cprman: cprman@7d202000 { ++ compatible = "brcm,bcm2711-cprman"; ++ reg = <0x7d202000 0x2000>; ++ #clock-cells = <1>; ++ ++ /* CPRMAN derives almost everything from the ++ * platform's oscillator. However, the DSI ++ * pixel clocks come from the DSI analog PHY. ++ */ ++ clocks = <&clk_osc>; ++ status = "disabled"; ++ }; ++ ++ random: rng@7d208000 { ++ compatible = "brcm,bcm2711-rng200"; ++ reg = <0x7d208000 0x28>; ++ status = "okay"; ++ }; ++ ++ cpu_l2_irq: intc@7d503000 { ++ compatible = "brcm,l2-intc"; ++ reg = <0x7d503000 0x18>; ++ interrupts = ; ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ }; ++ ++ pinctrl: pinctrl@7d504100 { ++ compatible = "brcm,bcm2712-pinctrl"; ++ reg = <0x7d504100 0x30>; ++ ++ uarta_24_pins: uarta_24_pins { ++ pin_rts { ++ function = "uart0"; ++ pins = "gpio24"; ++ bias-disable; ++ }; ++ pin_cts { ++ function = "uart0"; ++ pins = "gpio25"; ++ bias-pull-up; ++ }; ++ pin_txd { ++ function = "uart0"; ++ pins = "gpio26"; ++ bias-disable; ++ }; ++ pin_rxd { ++ function = "uart0"; ++ pins = "gpio27"; ++ bias-pull-up; ++ }; ++ }; ++ ++ sdio2_30_pins: sdio2_30_pins { ++ pin_clk { ++ function = "sd2"; ++ pins = "gpio30"; ++ bias-disable; ++ }; ++ pin_cmd { ++ function = "sd2"; ++ pins = "gpio31"; ++ bias-pull-up; ++ }; ++ pins_dat { ++ function = "sd2"; ++ pins = "gpio32", "gpio33", "gpio34", "gpio35"; ++ bias-pull-up; ++ }; ++ }; ++ }; ++ ++ ddc0: i2c@7d508200 { ++ compatible = "brcm,brcmstb-i2c"; ++ reg = <0x7d508200 0x58>; ++ interrupt-parent = <&bsc_irq>; ++ interrupts = <1>; ++ clock-frequency = <97500>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ ddc1: i2c@7d508280 { ++ compatible = "brcm,brcmstb-i2c"; ++ reg = <0x7d508280 0x58>; ++ interrupt-parent = <&bsc_irq>; ++ interrupts = <2>; ++ clock-frequency = <97500>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ bscd: i2c@7d508300 { ++ compatible = "brcm,brcmstb-i2c"; ++ reg = <0x7d508300 0x58>; ++ interrupt-parent = <&bsc_irq>; ++ interrupts = <0>; ++ clock-frequency = <200000>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ bsc_irq: intc@7d508380 { ++ compatible = "brcm,bcm7271-l2-intc"; ++ reg = <0x7d508380 0x10>; ++ interrupts = ; ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ }; ++ ++ main_irq: intc@7d508400 { ++ compatible = "brcm,bcm7271-l2-intc"; ++ reg = <0x7d508400 0x10>; ++ interrupts = ; ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ }; ++ ++ gio: gpio@7d508500 { ++ compatible = "brcm,brcmstb-gpio"; ++ reg = <0x7d508500 0x40>; ++ interrupt-parent = <&main_irq>; ++ interrupts = <0>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ interrupt-controller; ++ #interrupt-cells = <2>; ++ brcm,gpio-bank-widths = <32 22>; ++ brcm,gpio-direct; ++ }; ++ ++ uarta: serial@7d50c000 { ++ compatible = "brcm,bcm7271-uart"; ++ reg = <0x7d50c000 0x20>; ++ reg-names = "uart"; ++ reg-shift = <2>; ++ reg-io-width = <4>; ++ interrupts = ; ++ skip-init; ++ status = "disabled"; ++ }; ++ ++ uartb: serial@7d50d000 { ++ compatible = "brcm,bcm7271-uart"; ++ reg = <0x7d50d000 0x20>; ++ reg-names = "uart"; ++ reg-shift = <2>; ++ reg-io-width = <4>; ++ interrupts = ; ++ skip-init; ++ status = "disabled"; ++ }; ++ ++ aon_intr: interrupt-controller@7d510600 { ++ compatible = "brcm,bcm2711-l2-intc", "brcm,l2-intc"; ++ reg = <0x7d510600 0x30>; ++ interrupts = ; ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ status = "disabled"; ++ }; ++ ++ pinctrl_aon: pinctrl@7d510700 { ++ compatible = "brcm,bcm2712-aon-pinctrl"; ++ reg = <0x7d510700 0x20>; ++ ++ i2c3_m4_agpio0_pins: i2c3_m4_agpio0_pins { ++ function = "vc_i2c3"; ++ pins = "aon_gpio0", "aon_gpio1"; ++ bias-pull-up; ++ }; ++ ++ bsc_m1_agpio13_pins: bsc_m1_agpio13_pins { ++ function = "bsc_m1"; ++ pins = "aon_gpio13", "aon_gpio14"; ++ bias-pull-up; ++ }; ++ ++ bsc_pmu_sgpio4_pins: bsc_pmu_sgpio4_pins { ++ function = "avs_pmu_bsc"; ++ pins = "aon_sgpio4", "aon_sgpio5"; ++ }; ++ ++ bsc_m2_sgpio4_pins: bsc_m2_sgpio4_pins { ++ function = "bsc_m2"; ++ pins = "aon_sgpio4", "aon_sgpio5"; ++ }; ++ ++ pwm_aon_agpio1_pins: pwm_aon_agpio1_pins { ++ function = "aon_pwm"; ++ pins = "aon_gpio1", "aon_gpio2"; ++ }; ++ ++ pwm_aon_agpio4_pins: pwm_aon_agpio4_pins { ++ function = "vc_pwm0"; ++ pins = "aon_gpio4", "aon_gpio5"; ++ }; ++ ++ pwm_aon_agpio7_pins: pwm_aon_agpio7_pins { ++ function = "aon_pwm"; ++ pins = "aon_gpio7", "aon_gpio9"; ++ }; ++ }; ++ ++ intc@7d517000 { ++ compatible = "brcm,bcm7271-l2-intc"; ++ reg = <0x7d517000 0x10>; ++ interrupts = ; ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ status = "disabled"; ++ }; ++ ++ bscc: i2c@7d517a00 { ++ compatible = "brcm,brcmstb-i2c"; ++ reg = <0x7d517a00 0x58>; ++ interrupt-parent = <&bsc_aon_irq>; ++ interrupts = <0>; ++ clock-frequency = <200000>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ pwm_aon: pwm@7d517a80 { ++ compatible = "brcm,bcm7038-pwm"; ++ reg = <0x7d517a80 0x28>; ++ #pwm-cells = <3>; ++ clocks = <&clk_27MHz>; ++ }; ++ ++ main_aon_irq: intc@7d517ac0 { ++ compatible = "brcm,bcm7271-l2-intc"; ++ reg = <0x7d517ac0 0x10>; ++ interrupts = ; ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ }; ++ ++ bsc_aon_irq: intc@7d517b00 { ++ compatible = "brcm,bcm7271-l2-intc"; ++ reg = <0x7d517b00 0x10>; ++ interrupts = ; ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ }; ++ ++ gio_aon: gpio@7d517c00 { ++ compatible = "brcm,brcmstb-gpio"; ++ reg = <0x7d517c00 0x40>; ++ interrupt-parent = <&main_aon_irq>; ++ interrupts = <0>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ interrupt-controller; ++ #interrupt-cells = <2>; ++ brcm,gpio-bank-widths = <17 6>; ++ brcm,gpio-direct; ++ }; ++ ++ avs_monitor: avs-monitor@7d542000 { ++ compatible = "brcm,bcm2711-avs-monitor", ++ "syscon", "simple-mfd"; ++ reg = <0x7d542000 0xf00>; ++ status = "okay"; ++ ++ thermal: thermal { ++ compatible = "brcm,bcm2711-thermal"; ++ #thermal-sensor-cells = <0>; ++ }; ++ }; ++ ++ bsc_pmu: i2c@7d544000 { ++ compatible = "brcm,brcmstb-i2c"; ++ reg = <0x7d544000 0x58>; ++ interrupt-parent = <&bsc_aon_irq>; ++ interrupts = <1>; ++ clock-frequency = <200000>; ++ status = "disabled"; ++ }; ++ ++ hdmi0: hdmi@7ef00700 { ++ compatible = "brcm,bcm2712-hdmi0"; ++ reg = <0x7c701400 0x300>, ++ <0x7c701000 0x200>, ++ <0x7c701d00 0x300>, ++ <0x7c702000 0x80>, ++ <0x7c703800 0x200>, ++ <0x7c704000 0x800>, ++ <0x7c700100 0x80>, ++ <0x7d510800 0x100>, ++ <0x7c720000 0x100>; ++ reg-names = "hdmi", ++ "dvp", ++ "phy", ++ "rm", ++ "packet", ++ "metadata", ++ "csc", ++ "cec", ++ "hd"; ++ resets = <&dvp 1>; + interrupt-parent = <&aon_intr>; -+ interrupts = <0>, <1>, <2>, -+ <3>, <4>, <5>; ++ interrupts = <1>, <2>, <3>, ++ <7>, <8>; + interrupt-names = "cec-tx", "cec-rx", "cec-low", -+ "wakeup", "hpd-connected", "hpd-removed"; - ddc = <&ddc0>; -- dmas = <&dma 10>; -+ dmas = <&dma (10 | (1 << 27) | (1 << 24)| (15 << 20) | (10 << 16))>; - dma-names = "audio-rx"; - status = "disabled"; - }; -@@ -354,7 +382,8 @@ hdmi1: hdmi@7ef05700 { - <0x7ef06f00 0x400>, - <0x7ef00280 0x80>, - <0x7ef09300 0x100>, -- <0x7ef20000 0x100>; -+ <0x7ef20000 0x100>, -+ <0x7ef00100 0x30>; - reg-names = "hdmi", - "dvp", - "phy", -@@ -363,11 +392,21 @@ hdmi1: hdmi@7ef05700 { - "metadata", - "csc", - "cec", -- "hd"; -+ "hd", -+ "intr2"; - ddc = <&ddc1>; - clock-names = "hdmi", "bvb", "audio", "cec"; -+ clocks = <&firmware_clocks 13>, -+ <&firmware_clocks 14>, -+ <&dvp 0>, -+ <&clk_27MHz>; - resets = <&dvp 1>; -- dmas = <&dma 17>; ++ "hpd-connected", "hpd-removed"; ++ ddc = <&ddc0>; ++ dmas = <&dma32 10>; ++ dma-names = "audio-rx"; ++ status = "disabled"; ++ }; ++ ++ hdmi1: hdmi@7ef05700 { ++ compatible = "brcm,bcm2712-hdmi1"; ++ reg = <0x7c706400 0x300>, ++ <0x7c706000 0x200>, ++ <0x7c706d00 0x300>, ++ <0x7c707000 0x80>, ++ <0x7c708800 0x200>, ++ <0x7c709000 0x800>, ++ <0x7c700180 0x80>, ++ <0x7d511000 0x100>, ++ <0x7c720000 0x100>; ++ reg-names = "hdmi", ++ "dvp", ++ "phy", ++ "rm", ++ "packet", ++ "metadata", ++ "csc", ++ "cec", ++ "hd"; ++ ddc = <&ddc1>; ++ resets = <&dvp 2>; + interrupt-parent = <&aon_intr>; -+ interrupts = <8>, <7>, <6>, // This is correct -+ <9>, <10>, <11>; ++ interrupts = <11>, <12>, <13>, ++ <14>, <15>; + interrupt-names = "cec-tx", "cec-rx", "cec-low", -+ "wakeup", "hpd-connected", "hpd-removed"; -+ dmas = <&dma (17 | (1 << 27) | (1 << 24)| (15 << 20) | (10 << 16))>; - dma-names = "audio-rx"; - status = "disabled"; - }; -@@ -468,14 +507,14 @@ cpu3: cpu@3 { - scb { - compatible = "simple-bus"; - #address-cells = <2>; -- #size-cells = <1>; ++ "hpd-connected", "hpd-removed"; ++ dmas = <&dma32 17>; ++ dma-names = "audio-rx"; ++ status = "disabled"; ++ }; ++ }; ++ ++ arm-pmu { ++ compatible = "arm,cortex-a76-pmu"; ++ interrupts = , ++ , ++ , ++ ; ++ interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; ++ }; ++ ++ timer { ++ compatible = "arm,armv8-timer"; ++ interrupts = , ++ , ++ , ++ ; ++ /* This only applies to the ARMv7 stub */ ++ arm,cpu-registers-not-fw-configured; ++ }; ++ ++ cpus: cpus { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ enable-method = "brcm,bcm2836-smp"; // for ARM 32-bit ++ ++ /* Source for d/i cache-line-size, cache-sets, cache-size ++ * https://developer.arm.com/documentation/100798/0401 ++ * /L1-memory-system/About-the-L1-memory-system?lang=en ++ */ ++ cpu0: cpu@0 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a76"; ++ reg = <0x000>; ++ enable-method = "psci"; ++ d-cache-size = <0x10000>; ++ d-cache-line-size = <64>; ++ d-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set ++ i-cache-size = <0x10000>; ++ i-cache-line-size = <64>; ++ i-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set ++ next-level-cache = <&l2_cache_l0>; ++ }; ++ ++ cpu1: cpu@1 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a76"; ++ reg = <0x100>; ++ enable-method = "psci"; ++ d-cache-size = <0x10000>; ++ d-cache-line-size = <64>; ++ d-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set ++ i-cache-size = <0x10000>; ++ i-cache-line-size = <64>; ++ i-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set ++ next-level-cache = <&l2_cache_l1>; ++ }; ++ ++ cpu2: cpu@2 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a76"; ++ reg = <0x200>; ++ enable-method = "psci"; ++ d-cache-size = <0x10000>; ++ d-cache-line-size = <64>; ++ d-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set ++ i-cache-size = <0x10000>; ++ i-cache-line-size = <64>; ++ i-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set ++ next-level-cache = <&l2_cache_l2>; ++ }; ++ ++ cpu3: cpu@3 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a76"; ++ reg = <0x300>; ++ enable-method = "psci"; ++ d-cache-size = <0x10000>; ++ d-cache-line-size = <64>; ++ d-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set ++ i-cache-size = <0x10000>; ++ i-cache-line-size = <64>; ++ i-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set ++ next-level-cache = <&l2_cache_l3>; ++ }; ++ ++ /* Source for cache-line-size and cache-sets: ++ * https://developer.arm.com/documentation/100798/0401 ++ * /L2-memory-system/About-the-L2-memory-system?lang=en ++ * and for cache-size: ++ * https://www.raspberrypi.com/documentation/computers ++ * /processors.html#bcm2712 ++ */ ++ l2_cache_l0: l2-cache-l0 { ++ compatible = "cache"; ++ cache-size = <0x80000>; ++ cache-line-size = <128>; ++ cache-sets = <1024>; // 512KiB(size)/64(line-size)=8192ways/8-way set ++ cache-level = <2>; ++ cache-unified; ++ next-level-cache = <&l3_cache>; ++ }; ++ ++ l2_cache_l1: l2-cache-l1 { ++ compatible = "cache"; ++ cache-size = <0x80000>; ++ cache-line-size = <128>; ++ cache-sets = <1024>; // 512KiB(size)/64(line-size)=8192ways/8-way set ++ cache-level = <2>; ++ cache-unified; ++ next-level-cache = <&l3_cache>; ++ }; ++ ++ l2_cache_l2: l2-cache-l2 { ++ compatible = "cache"; ++ cache-size = <0x80000>; ++ cache-line-size = <128>; ++ cache-sets = <1024>; // 512KiB(size)/64(line-size)=8192ways/8-way set ++ cache-level = <2>; ++ cache-unified; ++ next-level-cache = <&l3_cache>; ++ }; ++ ++ l2_cache_l3: l2-cache-l3 { ++ compatible = "cache"; ++ cache-size = <0x80000>; ++ cache-line-size = <128>; ++ cache-sets = <1024>; // 512KiB(size)/64(line-size)=8192ways/8-way set ++ cache-level = <2>; ++ cache-unified; ++ next-level-cache = <&l3_cache>; ++ }; ++ ++ /* Source for cache-line-size and cache-sets: ++ * https://developer.arm.com/documentation/100453/0401/L3-cache?lang=en ++ * Source for cache-size: ++ * https://www.raspberrypi.com/documentation/computers/processors.html#bcm2712 ++ */ ++ l3_cache: l3-cache { ++ compatible = "cache"; ++ cache-size = <0x200000>; ++ cache-line-size = <64>; ++ cache-sets = <2048>; // 2MiB(size)/64(line-size)=32768ways/16-way set ++ cache-level = <3>; ++ }; ++ }; ++ ++ psci { ++ method = "smc"; ++ compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci"; ++ cpu_on = <0xc4000003>; ++ cpu_suspend = <0xc4000001>; ++ cpu_off = <0x84000002>; ++ }; ++ ++ axi: axi { ++ compatible = "simple-bus"; ++ #address-cells = <2>; + #size-cells = <2>; - -- ranges = <0x0 0x7c000000 0x0 0xfc000000 0x03800000>, -- <0x6 0x00000000 0x6 0x00000000 0x40000000>; -+ ranges = <0x0 0x7c000000 0x0 0xfc000000 0x0 0x03800000>, -+ <0x6 0x00000000 0x6 0x00000000 0x0 0x40000000>; - - pcie0: pcie@7d500000 { - compatible = "brcm,bcm2711-pcie"; -- reg = <0x0 0x7d500000 0x9310>; -+ reg = <0x0 0x7d500000 0x0 0x9310>; - device_type = "pci"; - #address-cells = <3>; - #interrupt-cells = <1>; -@@ -495,8 +534,8 @@ IRQ_TYPE_LEVEL_HIGH>, - msi-controller; - msi-parent = <&pcie0>; - -- ranges = <0x02000000 0x0 0xf8000000 0x6 0x00000000 -- 0x0 0x04000000>; -+ ranges = <0x02000000 0x0 0xc0000000 0x6 0x00000000 -+ 0x0 0x40000000>; - /* - * The wrapper around the PCIe block has a bug - * preventing it from accessing beyond the first 3GB of -@@ -509,7 +548,7 @@ IRQ_TYPE_LEVEL_HIGH>, - - genet: ethernet@7d580000 { - compatible = "brcm,bcm2711-genet-v5"; -- reg = <0x0 0x7d580000 0x10000>; -+ reg = <0x0 0x7d580000 0x0 0x10000>; - #address-cells = <0x1>; - #size-cells = <0x1>; - interrupts = , -@@ -546,6 +585,7 @@ &dsi0 { - - &dsi1 { - interrupts = ; -+ compatible = "brcm,bcm2711-dsi1"; - }; - - &gpio { -@@ -1018,7 +1058,7 @@ &cma { - alloc-ranges = <0x0 0x00000000 0x40000000>; - }; - --&i2c0 { -+&i2c0if { - compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c"; - interrupts = ; - }; -@@ -1074,7 +1114,3 @@ &uart1 { - &usb { - interrupts = ; - }; -- --&vec { -- interrupts = ; --}; -diff --git a/arch/arm/boot/dts/bcm271x-rpi-bt.dtsi b/arch/arm/boot/dts/bcm271x-rpi-bt.dtsi ++ ++ ranges = <0x00 0x00000000 0x00 0x00000000 0x10 0x00000000>, ++ <0x10 0x00000000 0x10 0x00000000 0x01 0x00000000>, ++ <0x14 0x00000000 0x14 0x00000000 0x04 0x00000000>, ++ <0x18 0x00000000 0x18 0x00000000 0x04 0x00000000>, ++ <0x1c 0x00000000 0x1c 0x00000000 0x04 0x00000000>; ++ ++ dma-ranges = <0x00 0x00000000 0x00 0x00000000 0x10 0x00000000>, ++ <0x10 0x00000000 0x10 0x00000000 0x01 0x00000000>, ++ <0x14 0x00000000 0x14 0x00000000 0x04 0x00000000>, ++ <0x18 0x00000000 0x18 0x00000000 0x04 0x00000000>, ++ <0x1c 0x00000000 0x1c 0x00000000 0x04 0x00000000>; ++ ++ vc4: gpu { ++ compatible = "brcm,bcm2712-vc6"; ++ }; ++ ++ iommu2: iommu@5100 { ++ /* IOMMU2 for PISP-BE, HEVC; and (unused) H264 accelerators */ ++ compatible = "brcm,bcm2712-iommu"; ++ reg = <0x10 0x5100 0x0 0x80>; ++ cache = <&iommuc>; ++ #iommu-cells = <0>; ++ }; ++ ++ iommu4: iommu@5200 { ++ /* IOMMU4 for HVS, MPL/TXP; and (unused) Unicam, PISP-FE, MiniBVN */ ++ compatible = "brcm,bcm2712-iommu"; ++ reg = <0x10 0x5200 0x0 0x80>; ++ cache = <&iommuc>; ++ #iommu-cells = <0>; ++ #interconnect-cells = <0>; ++ }; ++ ++ iommu5: iommu@5280 { ++ /* IOMMU5 for PCIe2 (RP1); and (unused) BSTM */ ++ compatible = "brcm,bcm2712-iommu"; ++ reg = <0x10 0x5280 0x0 0x80>; ++ cache = <&iommuc>; ++ #iommu-cells = <0>; ++ dma-iova-offset = <0x10 0x00000000>; // HACK for RP1 masters over PCIe ++ }; ++ ++ iommuc: iommuc@5b00 { ++ compatible = "brcm,bcm2712-iommuc"; ++ reg = <0x10 0x5b00 0x0 0x80>; ++ }; ++ ++ dma32: dma@10000 { ++ compatible = "brcm,bcm2712-dma"; ++ reg = <0x10 0x00010000 0 0x600>; ++ interrupts = , ++ , ++ , ++ , ++ , ++ ; ++ interrupt-names = "dma0", ++ "dma1", ++ "dma2", ++ "dma3", ++ "dma4", ++ "dma5"; ++ #dma-cells = <1>; ++ brcm,dma-channel-mask = <0x0035>; ++ }; ++ ++ dma40: dma@10600 { ++ compatible = "brcm,bcm2712-dma"; ++ reg = <0x10 0x00010600 0 0x600>; ++ interrupts = ++ , /* dma4 6 */ ++ , /* dma4 7 */ ++ , /* dma4 8 */ ++ , /* dma4 9 */ ++ , /* dma4 10 */ ++ ; /* dma4 11 */ ++ interrupt-names = "dma6", ++ "dma7", ++ "dma8", ++ "dma9", ++ "dma10", ++ "dma11"; ++ #dma-cells = <1>; ++ brcm,dma-channel-mask = <0x0fc0>; ++ }; ++ ++ // Single-lane Gen3 PCIe ++ // Outbound window at 0x14_000000-0x17_ffffff ++ pcie0: pcie@100000 { ++ compatible = "brcm,bcm2712-pcie"; ++ reg = <0x10 0x00100000 0x0 0x9310>; ++ device_type = "pci"; ++ max-link-speed = <2>; ++ #address-cells = <3>; ++ #interrupt-cells = <1>; ++ #size-cells = <2>; ++ /* ++ * Unused interrupts: ++ * 208: AER ++ * 215: NMI ++ * 216: PME ++ */ ++ interrupt-parent = <&gicv2>; ++ interrupts = , ++ ; ++ interrupt-names = "pcie", "msi"; ++ interrupt-map-mask = <0x0 0x0 0x0 0x7>; ++ interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 209 ++ IRQ_TYPE_LEVEL_HIGH>, ++ <0 0 0 2 &gicv2 GIC_SPI 210 ++ IRQ_TYPE_LEVEL_HIGH>, ++ <0 0 0 3 &gicv2 GIC_SPI 211 ++ IRQ_TYPE_LEVEL_HIGH>, ++ <0 0 0 4 &gicv2 GIC_SPI 212 ++ IRQ_TYPE_LEVEL_HIGH>; ++ resets = <&bcm_reset 5>, <&bcm_reset 42>, <&pcie_rescal>; ++ reset-names = "swinit", "bridge", "rescal"; ++ msi-controller; ++ msi-parent = <&pcie0>; ++ ++ ranges = <0x02000000 0x00 0x00000000 ++ 0x17 0x00000000 ++ 0x0 0xfffffffc>, ++ <0x43000000 0x04 0x00000000 ++ 0x14 0x00000000 ++ 0x3 0x00000000>; ++ ++ dma-ranges = <0x43000000 0x10 0x00000000 ++ 0x00 0x00000000 ++ 0x10 0x00000000>; ++ ++ status = "disabled"; ++ }; ++ ++ // Single-lane Gen3 PCIe ++ // Outbound window at 0x18_000000-0x1b_ffffff ++ pcie1: pcie@110000 { ++ compatible = "brcm,bcm2712-pcie"; ++ reg = <0x10 0x00110000 0x0 0x9310>; ++ device_type = "pci"; ++ max-link-speed = <2>; ++ #address-cells = <3>; ++ #interrupt-cells = <1>; ++ #size-cells = <2>; ++ /* ++ * Unused interrupts: ++ * 218: AER ++ * 225: NMI ++ * 226: PME ++ */ ++ interrupt-parent = <&gicv2>; ++ interrupts = , ++ ; ++ interrupt-names = "pcie", "msi"; ++ interrupt-map-mask = <0x0 0x0 0x0 0x7>; ++ interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 219 ++ IRQ_TYPE_LEVEL_HIGH>, ++ <0 0 0 2 &gicv2 GIC_SPI 220 ++ IRQ_TYPE_LEVEL_HIGH>, ++ <0 0 0 3 &gicv2 GIC_SPI 221 ++ IRQ_TYPE_LEVEL_HIGH>, ++ <0 0 0 4 &gicv2 GIC_SPI 222 ++ IRQ_TYPE_LEVEL_HIGH>; ++ resets = <&bcm_reset 7>, <&bcm_reset 43>, <&pcie_rescal>; ++ reset-names = "swinit", "bridge", "rescal"; ++ msi-controller; ++ msi-parent = <&mip1>; ++ ++ ranges = <0x02000000 0x00 0x00000000 ++ 0x1b 0x00000000 ++ 0x00 0xfffffffc>, ++ <0x43000000 0x04 0x00000000 ++ 0x18 0x00000000 ++ 0x03 0x00000000>; ++ ++ dma-ranges = <0x03000000 0x10 0x00000000 ++ 0x00 0x00000000 ++ 0x10 0x00000000>; ++ ++ brcm,enable-l1ss; ++ status = "disabled"; ++ }; ++ ++ pcie_rescal: reset-controller@119500 { ++ compatible = "brcm,bcm7216-pcie-sata-rescal"; ++ reg = <0x10 0x00119500 0x0 0x10>; ++ #reset-cells = <0>; ++ }; ++ ++ // Quad-lane Gen3 PCIe ++ // Outbound window at 0x1c_000000-0x1f_ffffff ++ pcie2: pcie@120000 { ++ compatible = "brcm,bcm2712-pcie"; ++ reg = <0x10 0x00120000 0x0 0x9310>; ++ device_type = "pci"; ++ max-link-speed = <2>; ++ #address-cells = <3>; ++ #interrupt-cells = <1>; ++ #size-cells = <2>; ++ /* ++ * Unused interrupts: ++ * 228: AER ++ * 235: NMI ++ * 236: PME ++ */ ++ interrupt-parent = <&gicv2>; ++ interrupts = , ++ ; ++ interrupt-names = "pcie", "msi"; ++ interrupt-map-mask = <0x0 0x0 0x0 0x7>; ++ interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 229 ++ IRQ_TYPE_LEVEL_HIGH>, ++ <0 0 0 2 &gicv2 GIC_SPI 230 ++ IRQ_TYPE_LEVEL_HIGH>, ++ <0 0 0 3 &gicv2 GIC_SPI 231 ++ IRQ_TYPE_LEVEL_HIGH>, ++ <0 0 0 4 &gicv2 GIC_SPI 232 ++ IRQ_TYPE_LEVEL_HIGH>; ++ resets = <&bcm_reset 32>, <&bcm_reset 44>, <&pcie_rescal>; ++ reset-names = "swinit", "bridge", "rescal"; ++ msi-controller; ++ msi-parent = <&mip0>; ++ ++ // ~4GB, 32-bit, not-prefetchable at PCIe 00_00000000 ++ ranges = <0x02000000 0x00 0x00000000 ++ 0x1f 0x00000000 ++ 0x0 0xfffffffc>, ++ // 12GB, 64-bit, prefetchable at PCIe 04_00000000 ++ <0x43000000 0x04 0x00000000 ++ 0x1c 0x00000000 ++ 0x03 0x00000000>; ++ ++ // 64GB system RAM space at PCIe 10_00000000 ++ dma-ranges = <0x02000000 0x00 0x00000000 ++ 0x1f 0x00000000 ++ 0x00 0x00400000>, ++ <0x43000000 0x10 0x00000000 ++ 0x00 0x00000000 ++ 0x10 0x00000000>; ++ ++ brcm,enable-l1ss; ++ status = "disabled"; ++ }; ++ ++ mip0: msi-controller@130000 { ++ compatible = "brcm,bcm2712-mip-intc"; ++ reg = <0x10 0x00130000 0x0 0xc0>; ++ msi-controller; ++ interrupt-controller; ++ #interrupt-cells = <2>; ++ brcm,msi-base-spi = <128>; ++ brcm,msi-num-spis = <64>; ++ brcm,msi-offset = <0>; ++ brcm,msi-pci-addr = <0xff 0xfffff000>; ++ }; ++ ++ mip1: msi-controller@131000 { ++ compatible = "brcm,bcm2712-mip-intc"; ++ reg = <0x10 0x00131000 0x0 0xc0>; ++ msi-controller; ++ interrupt-controller; ++ #interrupt-cells = <2>; ++ brcm,msi-base-spi = <247>; ++ /* Actually 20 total, but the others are ++ * both sparse and non-consecutive */ ++ brcm,msi-num-spis = <8>; ++ brcm,msi-offset = <8>; ++ brcm,msi-pci-addr = <0xff 0xffffe000>; ++ }; ++ ++ syscon_piarbctl: syscon@400018 { ++ compatible = "brcm,syscon-piarbctl", "syscon", "simple-mfd"; ++ reg = <0x10 0x00400018 0x0 0x18>; ++ }; ++ ++ usb: usb@480000 { ++ compatible = "brcm,bcm2835-usb"; ++ reg = <0x10 0x00480000 0x0 0x10000>; ++ interrupts = ; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ clocks = <&clk_usb>; ++ clock-names = "otg"; ++ phys = <&usbphy>; ++ phy-names = "usb2-phy"; ++ status = "disabled"; ++ }; ++ ++ rpivid: codec@800000 { ++ compatible = "raspberrypi,rpivid-vid-decoder"; ++ reg = <0x10 0x00800000 0x0 0x10000>, /* HEVC */ ++ <0x10 0x00840000 0x0 0x1000>; /* INTC */ ++ reg-names = "hevc", ++ "intc"; ++ ++ interrupts = ; ++ ++ clocks = <&firmware_clocks 11>; ++ clock-names = "hevc"; ++ iommus = <&iommu2>; ++ status = "disabled"; ++ }; ++ ++ sdio1: mmc@fff000 { ++ compatible = "brcm,bcm2712-sdhci"; ++ reg = <0x10 0x00fff000 0x0 0x260>, ++ <0x10 0x00fff400 0x0 0x200>, ++ <0x10 0x015040b0 0x0 0x4>, // Bus isolation control ++ <0x10 0x015200f0 0x0 0x24>; // LCPLL control misc0-8 ++ reg-names = "host", "cfg", "busisol", "lcpll"; ++ interrupts = ; ++ clocks = <&clk_emmc2>; ++ sdhci-caps-mask = <0x0000C000 0x0>; ++ sdhci-caps = <0x0 0x0>; ++ mmc-ddr-3_3v; ++ }; ++ ++ sdio2: mmc@1100000 { ++ compatible = "brcm,bcm2712-sdhci"; ++ reg = <0x10 0x01100000 0x0 0x260>, ++ <0x10 0x01100400 0x0 0x200>; ++ reg-names = "host", "cfg"; ++ interrupts = ; ++ clocks = <&clk_emmc2>; ++ sdhci-caps-mask = <0x0000C000 0x0>; ++ sdhci-caps = <0x0 0x0>; ++ supports-cqe; ++ mmc-ddr-3_3v; ++ status = "disabled"; ++ }; ++ ++ bcm_reset: reset-controller@1504318 { ++ compatible = "brcm,brcmstb-reset"; ++ reg = <0x10 0x01504318 0x0 0x30>; ++ #reset-cells = <1>; ++ }; ++ ++ v3d: v3d@2000000 { ++ compatible = "brcm,2712-v3d"; ++ reg = <0x10 0x02000000 0x0 0x4000>, ++ <0x10 0x02008000 0x0 0x6000>; ++ reg-names = "hub", "core0"; ++ ++ power-domains = <&pm BCM2835_POWER_DOMAIN_GRAFX_V3D>; ++ resets = <&pm BCM2835_RESET_V3D>; ++ clocks = <&firmware_clocks 5>; ++ clocks-names = "v3d"; ++ interrupts = , ++ ; ++ status = "disabled"; ++ }; ++ ++ gicv2: interrupt-controller@7fff9000 { ++ interrupt-controller; ++ #interrupt-cells = <3>; ++ compatible = "arm,gic-400"; ++ reg = <0x10 0x7fff9000 0x0 0x1000>, ++ <0x10 0x7fffa000 0x0 0x2000>, ++ <0x10 0x7fffc000 0x0 0x2000>, ++ <0x10 0x7fffe000 0x0 0x2000>; ++ interrupts = ; ++ }; ++ ++ pisp_be: pisp_be@880000 { ++ compatible = "raspberrypi,pispbe"; ++ reg = <0x10 0x00880000 0x0 0x4000>; ++ interrupts = ; ++ clocks = <&firmware_clocks 7>; ++ clocks-names = "isp_be"; ++ status = "okay"; ++ iommus = <&iommu2>; ++ }; ++ }; ++ ++ clocks { ++ /* The oscillator is the root of the clock tree. */ ++ clk_osc: clk-osc { ++ compatible = "fixed-clock"; ++ #clock-cells = <0>; ++ clock-output-names = "osc"; ++ clock-frequency = <54000000>; ++ }; ++ ++ clk_usb: clk-usb { ++ compatible = "fixed-clock"; ++ #clock-cells = <0>; ++ clock-output-names = "otg"; ++ clock-frequency = <480000000>; ++ }; ++ ++ clk_vpu: clk_vpu { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <750000000>; ++ clock-output-names = "vpu-clock"; ++ }; ++ ++ clk_uart: clk_uart { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <9216000>; ++ clock-output-names = "uart-clock"; ++ }; ++ ++ clk_emmc2: clk_emmc2 { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <200000000>; ++ clock-output-names = "emmc2-clock"; ++ }; ++ }; ++ ++ usbphy: phy { ++ compatible = "usb-nop-xceiv"; ++ #phy-cells = <0>; ++ }; ++}; +diff --git a/arch/arm/boot/dts/broadcom/bcm2712d0-rpi-5-b.dts b/arch/arm/boot/dts/broadcom/bcm2712d0-rpi-5-b.dts new file mode 100644 -index 000000000000..6b9b79f74cf3 +index 000000000000..32aab40524b3 --- /dev/null -+++ b/arch/arm/boot/dts/bcm271x-rpi-bt.dtsi -@@ -0,0 +1,26 @@ ++++ b/arch/arm/boot/dts/broadcom/bcm2712d0-rpi-5-b.dts +@@ -0,0 +1,107 @@ ++// SPDX-License-Identifier: GPL-2.0 ++#include "bcm2712-rpi-5-b.dts" ++ ++&gio { ++ brcm,gpio-bank-widths = <32 4>; ++ ++ gpio-line-names = ++ "", // GPIO_000 ++ "2712_BOOT_CS_N", // GPIO_001 ++ "2712_BOOT_MISO", // GPIO_002 ++ "2712_BOOT_MOSI", // GPIO_003 ++ "2712_BOOT_SCLK", // GPIO_004 ++ "", // GPIO_005 ++ "", // GPIO_006 ++ "", // GPIO_007 ++ "", // GPIO_008 ++ "", // GPIO_009 ++ "", // GPIO_010 ++ "", // GPIO_011 ++ "", // GPIO_012 ++ "", // GPIO_013 ++ "PCIE_SDA", // GPIO_014 ++ "PCIE_SCL", // GPIO_015 ++ "", // GPIO_016 ++ "", // GPIO_017 ++ "-", // GPIO_018 ++ "-", // GPIO_019 ++ "PWR_GPIO", // GPIO_020 ++ "2712_G21_FS", // GPIO_021 ++ "-", // GPIO_022 ++ "-", // GPIO_023 ++ "BT_RTS", // GPIO_024 ++ "BT_CTS", // GPIO_025 ++ "BT_TXD", // GPIO_026 ++ "BT_RXD", // GPIO_027 ++ "WL_ON", // GPIO_028 ++ "BT_ON", // GPIO_029 ++ "WIFI_SDIO_CLK", // GPIO_030 ++ "WIFI_SDIO_CMD", // GPIO_031 ++ "WIFI_SDIO_D0", // GPIO_032 ++ "WIFI_SDIO_D1", // GPIO_033 ++ "WIFI_SDIO_D2", // GPIO_034 ++ "WIFI_SDIO_D3"; // GPIO_035 ++}; ++ ++&gio_aon { ++ brcm,gpio-bank-widths = <15 6>; ++ ++ gpio-line-names = ++ "RP1_SDA", // AON_GPIO_00 ++ "RP1_SCL", // AON_GPIO_01 ++ "RP1_RUN", // AON_GPIO_02 ++ "SD_IOVDD_SEL", // AON_GPIO_03 ++ "SD_PWR_ON", // AON_GPIO_04 ++ "SD_CDET_N", // AON_GPIO_05 ++ "SD_FLG_N", // AON_GPIO_06 ++ "", // AON_GPIO_07 ++ "2712_WAKE", // AON_GPIO_08 ++ "2712_STAT_LED", // AON_GPIO_09 ++ "", // AON_GPIO_10 ++ "", // AON_GPIO_11 ++ "PMIC_INT", // AON_GPIO_12 ++ "UART_TX_FS", // AON_GPIO_13 ++ "UART_RX_FS", // AON_GPIO_14 ++ "", // AON_GPIO_15 ++ "", // AON_GPIO_16 ++ ++ // Pad bank0 out to 32 entries ++ "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", ++ ++ "HDMI0_SCL", // AON_SGPIO_00 ++ "HDMI0_SDA", // AON_SGPIO_01 ++ "HDMI1_SCL", // AON_SGPIO_02 ++ "HDMI1_SDA", // AON_SGPIO_03 ++ "PMIC_SCL", // AON_SGPIO_04 ++ "PMIC_SDA"; // AON_SGPIO_05 ++}; ++ ++&pinctrl { ++ compatible = "brcm,bcm2712d0-pinctrl"; ++ reg = <0x7d504100 0x20>; ++}; ++ ++&pinctrl_aon { ++ compatible = "brcm,bcm2712d0-aon-pinctrl"; ++ reg = <0x7d510700 0x1c>; ++}; ++ ++&vc4 { ++ compatible = "brcm,bcm2712d0-vc6"; ++}; ++ ++&uart10 { ++ interrupts = ; ++}; ++ ++&spi10 { ++ dmas = <&dma40 3>, <&dma40 4>; ++}; ++ ++&hdmi0 { ++ dmas = <&dma40 (12|(1<<30)|(1<<24)|(10<<16)|(15<<20))>; ++}; ++ ++&hdmi1 { ++ dmas = <&dma40 (13|(1<<30)|(1<<24)|(10<<16)|(15<<20))>; ++}; +diff --git a/arch/arm/boot/dts/broadcom/bcm271x-rpi-bt.dtsi b/arch/arm/boot/dts/broadcom/bcm271x-rpi-bt.dtsi +new file mode 100644 +index 000000000000..400efdc5f03c +--- /dev/null ++++ b/arch/arm/boot/dts/broadcom/bcm271x-rpi-bt.dtsi +@@ -0,0 +1,38 @@ +// SPDX-License-Identifier: GPL-2.0 + +&uart0 { @@ -9365,428 +14545,1421 @@ index 000000000000..6b9b79f74cf3 + compatible = "brcm,bcm43438-bt"; + max-speed = <3000000>; + shutdown-gpios = <&expgpio 0 GPIO_ACTIVE_HIGH>; -+ status = "disabled"; ++ local-bd-address = [ 00 00 00 00 00 00 ]; ++ fallback-bd-address; // Don't override a valid address ++ status = "okay"; + }; +}; + +&uart1 { + minibt: bluetooth { + compatible = "brcm,bcm43438-bt"; -+ max-speed = <460800>; ++ max-speed = <230400>; + shutdown-gpios = <&expgpio 0 GPIO_ACTIVE_HIGH>; ++ local-bd-address = [ 00 00 00 00 00 00 ]; ++ fallback-bd-address; // Don't override a valid address + status = "disabled"; + }; +}; + +/ { ++ aliases { ++ bluetooth = &bt; ++ }; ++ + __overrides__ { ++ bdaddr = <&bt>,"local-bd-address[", ++ <&bt>,"fallback-bd-address?=0", ++ <&minibt>,"local-bd-address[", ++ <&minibt>,"fallback-bd-address?=0"; + krnbt = <&bt>,"status"; -+ krnbt_baudrate = <&bt>,"max-speed:0"; ++ krnbt_baudrate = <&bt>,"max-speed:0", <&minibt>,"max-speed:0"; + }; +}; -diff --git a/arch/arm/boot/dts/bcm2835-common.dtsi b/arch/arm/boot/dts/bcm2835-common.dtsi -index 4119271c979d..7f46a6ec512c 100644 ---- a/arch/arm/boot/dts/bcm2835-common.dtsi -+++ b/arch/arm/boot/dts/bcm2835-common.dtsi -@@ -106,6 +106,14 @@ i2c2: i2c@7e805000 { - status = "okay"; - }; - -+ vec: vec@7e806000 { -+ compatible = "brcm,bcm2835-vec"; -+ reg = <0x7e806000 0x1000>; -+ clocks = <&firmware_clocks 15>; -+ interrupts = <2 27>; -+ status = "disabled"; -+ }; -+ - pixelvalve@7e807000 { - compatible = "brcm,bcm2835-pixelvalve2"; - reg = <0x7e807000 0x100>; -@@ -116,12 +124,14 @@ hdmi: hdmi@7e902000 { - compatible = "brcm,bcm2835-hdmi"; - reg = <0x7e902000 0x600>, - <0x7e808000 0x100>; -+ reg-names = "hdmi", -+ "hd"; - interrupts = <2 8>, <2 9>; - ddc = <&i2c2>; -- clocks = <&clocks BCM2835_PLLH_PIX>, -+ clocks = <&firmware_clocks 9>, - <&clocks BCM2835_CLOCK_HSM>; - clock-names = "pixel", "hdmi"; -- dmas = <&dma 17>; -+ dmas = <&dma (17|(1<<27)|(1<<24))>; - dma-names = "audio-rx"; - status = "disabled"; - }; -diff --git a/arch/arm/boot/dts/bcm2835-rpi-a-plus.dts b/arch/arm/boot/dts/bcm2835-rpi-a-plus.dts -index 40b9405f1a8e..d2384d8e8555 100644 ---- a/arch/arm/boot/dts/bcm2835-rpi-a-plus.dts -+++ b/arch/arm/boot/dts/bcm2835-rpi-a-plus.dts -@@ -126,3 +126,8 @@ &uart0 { - pinctrl-0 = <&uart0_gpio14>; - status = "okay"; - }; -+ -+/* i2c on camera/display connector is gpio 28&29 */ -+&i2c0mux { -+ pinctrl-1 = <&i2c0_gpio28>; -+}; -diff --git a/arch/arm/boot/dts/bcm2835-rpi-a.dts b/arch/arm/boot/dts/bcm2835-rpi-a.dts -index 11edb581dbaf..4ceca674b752 100644 ---- a/arch/arm/boot/dts/bcm2835-rpi-a.dts -+++ b/arch/arm/boot/dts/bcm2835-rpi-a.dts -@@ -121,3 +121,10 @@ &uart0 { - pinctrl-0 = <&uart0_gpio14>; - status = "okay"; - }; -+ -+/* i2c0 on camera/display connector is gpio 0&1. Not exposed on header. -+ * To avoid having to remap everything, map both ports to gpios 0&1 -+ */ -+&i2c0mux { -+ pinctrl-1 = <&i2c0_gpio0>; -+}; -diff --git a/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts b/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts -index 1b435c64bd9c..8f2d10d82fa1 100644 ---- a/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts -+++ b/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts -@@ -128,3 +128,8 @@ &uart0 { - pinctrl-0 = <&uart0_gpio14>; - status = "okay"; - }; -+ -+/* i2c on camera/display connector is gpio 28&29 */ -+&i2c0mux { -+ pinctrl-1 = <&i2c0_gpio28>; -+}; -diff --git a/arch/arm/boot/dts/bcm2835-rpi-b-rev2.dts b/arch/arm/boot/dts/bcm2835-rpi-b-rev2.dts -index a23c25c00eea..547c88a3ae9f 100644 ---- a/arch/arm/boot/dts/bcm2835-rpi-b-rev2.dts -+++ b/arch/arm/boot/dts/bcm2835-rpi-b-rev2.dts -@@ -121,3 +121,10 @@ &uart0 { - pinctrl-0 = <&uart0_gpio14>; - status = "okay"; - }; -+ -+/* i2c0 on camera/display connector is gpio 0&1. Not exposed on header. -+ * To avoid having to remap everything, map both ports to gpios 0&1 -+ */ -+&i2c0mux { -+ pinctrl-1 = <&i2c0_gpio0>; -+}; -diff --git a/arch/arm/boot/dts/bcm2835-rpi-b.dts b/arch/arm/boot/dts/bcm2835-rpi-b.dts -index 1b63d6b19750..073fc99ef8a2 100644 ---- a/arch/arm/boot/dts/bcm2835-rpi-b.dts -+++ b/arch/arm/boot/dts/bcm2835-rpi-b.dts -@@ -116,3 +116,10 @@ &uart0 { - pinctrl-0 = <&uart0_gpio14>; - status = "okay"; - }; -+ -+/* camera/display connector use BSC1 on GPIOS 2&3. -+ * To avoid having to remap everything, map both ports to gpios 0&1 -+ */ -+&i2c0mux { -+ pinctrl-1 = <&i2c0_gpio0>; -+}; -diff --git a/arch/arm/boot/dts/bcm2835-rpi-cm1-io1.dts b/arch/arm/boot/dts/bcm2835-rpi-cm1-io1.dts -index a75c882e6575..95564c93a645 100644 ---- a/arch/arm/boot/dts/bcm2835-rpi-cm1-io1.dts -+++ b/arch/arm/boot/dts/bcm2835-rpi-cm1-io1.dts -@@ -95,3 +95,8 @@ &uart0 { - pinctrl-0 = <&uart0_gpio14>; - status = "okay"; - }; -+ -+/* WHAT TO DO HERE? */ -+&i2c0mux { -+ pinctrl-1 = <&i2c0_gpio28>; -+}; -diff --git a/arch/arm/boot/dts/bcm2835-rpi-zero-w.dts b/arch/arm/boot/dts/bcm2835-rpi-zero-w.dts -index 33b2b77aa47d..3ea5c7e6be54 100644 ---- a/arch/arm/boot/dts/bcm2835-rpi-zero-w.dts -+++ b/arch/arm/boot/dts/bcm2835-rpi-zero-w.dts -@@ -149,3 +149,8 @@ &uart1 { - pinctrl-0 = <&uart1_gpio14>; - status = "okay"; - }; -+ -+/* i2c on camera/display connector is gpio 28&29 */ -+&i2c0mux { -+ pinctrl-1 = <&i2c0_gpio28>; -+}; -diff --git a/arch/arm/boot/dts/bcm2835-rpi-zero.dts b/arch/arm/boot/dts/bcm2835-rpi-zero.dts -index 6f9b3a908f28..a0eabab12c99 100644 ---- a/arch/arm/boot/dts/bcm2835-rpi-zero.dts -+++ b/arch/arm/boot/dts/bcm2835-rpi-zero.dts -@@ -117,3 +117,8 @@ &uart0 { - pinctrl-0 = <&uart0_gpio14>; - status = "okay"; - }; -+ -+/* i2c on camera/display connector is gpio 28&29 */ -+&i2c0mux { -+ pinctrl-1 = <&i2c0_gpio28>; -+}; -diff --git a/arch/arm/boot/dts/bcm2835-rpi.dtsi b/arch/arm/boot/dts/bcm2835-rpi.dtsi -index 87ddcad76083..edc55bba5ff4 100644 ---- a/arch/arm/boot/dts/bcm2835-rpi.dtsi -+++ b/arch/arm/boot/dts/bcm2835-rpi.dtsi -@@ -19,6 +19,11 @@ firmware: firmware { - - mboxes = <&mailbox>; - dma-ranges; -+ -+ firmware_clocks: clocks { -+ compatible = "raspberrypi,firmware-clocks"; -+ #clock-cells = <1>; -+ }; - }; - - power: power { -@@ -49,13 +54,17 @@ alt0: alt0 { - }; - }; - --&i2c0 { -- pinctrl-names = "default"; -- pinctrl-0 = <&i2c0_gpio0>; -+&i2c0if { - status = "okay"; - clock-frequency = <100000>; - }; - -+&i2c0mux { -+ pinctrl-0 = <&i2c0_gpio0>; -+ /* pinctrl-1 varies based on platform */ -+ status = "okay"; -+}; -+ - &i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_gpio2>; -@@ -67,6 +76,10 @@ &usb { - power-domains = <&power RPI_POWER_DOMAIN_USB>; - }; - -+&vc4 { -+ raspberrypi,firmware = <&firmware>; -+}; -+ - &vec { - power-domains = <&power RPI_POWER_DOMAIN_VEC>; - status = "okay"; -diff --git a/arch/arm/boot/dts/bcm2835.dtsi b/arch/arm/boot/dts/bcm2835.dtsi -index 0549686134ea..2ea891228ea0 100644 ---- a/arch/arm/boot/dts/bcm2835.dtsi -+++ b/arch/arm/boot/dts/bcm2835.dtsi -@@ -19,7 +19,7 @@ cpu@0 { - - soc { - ranges = <0x7e000000 0x20000000 0x02000000>; -- dma-ranges = <0x40000000 0x00000000 0x20000000>; -+ dma-ranges = <0x80000000 0x00000000 0x20000000>; - }; - - arm-pmu { -diff --git a/arch/arm/boot/dts/bcm2836-rpi-2-b.dts b/arch/arm/boot/dts/bcm2836-rpi-2-b.dts -index d8af8eeac7b6..bf22b74359d8 100644 ---- a/arch/arm/boot/dts/bcm2836-rpi-2-b.dts -+++ b/arch/arm/boot/dts/bcm2836-rpi-2-b.dts -@@ -128,3 +128,8 @@ &uart0 { - pinctrl-0 = <&uart0_gpio14>; - status = "okay"; - }; -+ -+/* i2c on camera/display connector is gpio 28&29 */ -+&i2c0mux { -+ pinctrl-1 = <&i2c0_gpio28>; -+}; -diff --git a/arch/arm/boot/dts/bcm2837-rpi-3-a-plus.dts b/arch/arm/boot/dts/bcm2837-rpi-3-a-plus.dts -index 77099a7871b0..9529c0475673 100644 ---- a/arch/arm/boot/dts/bcm2837-rpi-3-a-plus.dts -+++ b/arch/arm/boot/dts/bcm2837-rpi-3-a-plus.dts -@@ -178,3 +178,8 @@ &uart1 { - pinctrl-0 = <&uart1_gpio14>; - status = "okay"; - }; -+ -+/* i2c on camera/display connector is gpio 44&45 */ -+&i2c0mux { -+ pinctrl-1 = <&i2c0_gpio44>; -+}; -diff --git a/arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts b/arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts -index 61010266ca9a..40cb269aed0f 100644 ---- a/arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts -+++ b/arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts -@@ -181,3 +181,8 @@ &uart1 { - pinctrl-0 = <&uart1_gpio14>; - status = "okay"; - }; -+ -+/* i2c on camera/display connector is gpio 44&45 */ -+&i2c0mux { -+ pinctrl-1 = <&i2c0_gpio44>; -+}; -diff --git a/arch/arm/boot/dts/bcm2837-rpi-3-b.dts b/arch/arm/boot/dts/bcm2837-rpi-3-b.dts -index dd4a48604097..8f16b6b3fe08 100644 ---- a/arch/arm/boot/dts/bcm2837-rpi-3-b.dts -+++ b/arch/arm/boot/dts/bcm2837-rpi-3-b.dts -@@ -174,3 +174,8 @@ &sdhost { - status = "okay"; - bus-width = <4>; - }; -+ -+/* i2c on camera/display connector is gpio 44&45 */ -+&i2c0mux { -+ pinctrl-1 = <&i2c0_gpio44>; -+}; -diff --git a/arch/arm/boot/dts/bcm2837-rpi-cm3-io3.dts b/arch/arm/boot/dts/bcm2837-rpi-cm3-io3.dts -index 588d9411ceb6..dde209ade51b 100644 ---- a/arch/arm/boot/dts/bcm2837-rpi-cm3-io3.dts -+++ b/arch/arm/boot/dts/bcm2837-rpi-cm3-io3.dts -@@ -94,3 +94,8 @@ &uart0 { - pinctrl-0 = <&uart0_gpio14>; - status = "okay"; - }; -+ -+/* WHAT TO DO HERE? */ -+&i2c0mux { -+ pinctrl-1 = <&i2c0_gpio28>; -+}; -diff --git a/arch/arm/boot/dts/bcm283x-rpi-csi0-2lane.dtsi b/arch/arm/boot/dts/bcm283x-rpi-csi0-2lane.dtsi +diff --git a/arch/arm/boot/dts/broadcom/bcm283x-rpi-csi0-2lane.dtsi b/arch/arm/boot/dts/broadcom/bcm283x-rpi-csi0-2lane.dtsi new file mode 100644 index 000000000000..6e4ce8622b47 --- /dev/null -+++ b/arch/arm/boot/dts/bcm283x-rpi-csi0-2lane.dtsi ++++ b/arch/arm/boot/dts/broadcom/bcm283x-rpi-csi0-2lane.dtsi @@ -0,0 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0-only +&csi0 { + brcm,num-data-lanes = <2>; +}; -diff --git a/arch/arm/boot/dts/bcm283x-rpi-csi1-2lane.dtsi b/arch/arm/boot/dts/bcm283x-rpi-csi1-2lane.dtsi +diff --git a/arch/arm/boot/dts/broadcom/bcm283x-rpi-csi1-2lane.dtsi b/arch/arm/boot/dts/broadcom/bcm283x-rpi-csi1-2lane.dtsi new file mode 100644 index 000000000000..6938f4daacdc --- /dev/null -+++ b/arch/arm/boot/dts/bcm283x-rpi-csi1-2lane.dtsi ++++ b/arch/arm/boot/dts/broadcom/bcm283x-rpi-csi1-2lane.dtsi @@ -0,0 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0-only +&csi1 { + brcm,num-data-lanes = <2>; +}; -diff --git a/arch/arm/boot/dts/bcm283x-rpi-csi1-4lane.dtsi b/arch/arm/boot/dts/bcm283x-rpi-csi1-4lane.dtsi +diff --git a/arch/arm/boot/dts/broadcom/bcm283x-rpi-csi1-4lane.dtsi b/arch/arm/boot/dts/broadcom/bcm283x-rpi-csi1-4lane.dtsi new file mode 100644 index 000000000000..b37037437bee --- /dev/null -+++ b/arch/arm/boot/dts/bcm283x-rpi-csi1-4lane.dtsi ++++ b/arch/arm/boot/dts/broadcom/bcm283x-rpi-csi1-4lane.dtsi @@ -0,0 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0-only +&csi1 { + brcm,num-data-lanes = <4>; +}; -diff --git a/arch/arm/boot/dts/bcm283x-rpi-i2c0mux_0_28.dtsi b/arch/arm/boot/dts/bcm283x-rpi-i2c0mux_0_28.dtsi +diff --git a/arch/arm/boot/dts/broadcom/bcm283x-rpi-i2c0mux_0_28.dtsi b/arch/arm/boot/dts/broadcom/bcm283x-rpi-i2c0mux_0_28.dtsi new file mode 100644 index 000000000000..38f0074bce3f --- /dev/null -+++ b/arch/arm/boot/dts/bcm283x-rpi-i2c0mux_0_28.dtsi ++++ b/arch/arm/boot/dts/broadcom/bcm283x-rpi-i2c0mux_0_28.dtsi @@ -0,0 +1,4 @@ +&i2c0mux { + pinctrl-0 = <&i2c0_gpio0>; + pinctrl-1 = <&i2c0_gpio28>; +}; -diff --git a/arch/arm/boot/dts/bcm283x-rpi-i2c0mux_0_44.dtsi b/arch/arm/boot/dts/bcm283x-rpi-i2c0mux_0_44.dtsi +diff --git a/arch/arm/boot/dts/broadcom/bcm283x-rpi-i2c0mux_0_44.dtsi b/arch/arm/boot/dts/broadcom/bcm283x-rpi-i2c0mux_0_44.dtsi new file mode 100644 index 000000000000..119946d878db --- /dev/null -+++ b/arch/arm/boot/dts/bcm283x-rpi-i2c0mux_0_44.dtsi ++++ b/arch/arm/boot/dts/broadcom/bcm283x-rpi-i2c0mux_0_44.dtsi @@ -0,0 +1,4 @@ +&i2c0mux { + pinctrl-0 = <&i2c0_gpio0>; + pinctrl-1 = <&i2c0_gpio44>; +}; -diff --git a/arch/arm/boot/dts/bcm283x-rpi-usb-peripheral.dtsi b/arch/arm/boot/dts/bcm283x-rpi-usb-peripheral.dtsi -deleted file mode 100644 -index 0ff0e9e25327..000000000000 ---- a/arch/arm/boot/dts/bcm283x-rpi-usb-peripheral.dtsi -+++ /dev/null -@@ -1,7 +0,0 @@ --// SPDX-License-Identifier: GPL-2.0 --&usb { -- dr_mode = "peripheral"; -- g-rx-fifo-size = <256>; -- g-np-tx-fifo-size = <32>; -- g-tx-fifo-size = <256 256 512 512 512 768 768>; --}; -diff --git a/arch/arm/boot/dts/bcm283x.dtsi b/arch/arm/boot/dts/bcm283x.dtsi -index ffdf7c4fba46..62d7ee513549 100644 ---- a/arch/arm/boot/dts/bcm283x.dtsi -+++ b/arch/arm/boot/dts/bcm283x.dtsi -@@ -336,7 +336,7 @@ spi: spi@7e204000 { +diff --git a/arch/arm/boot/dts/broadcom/bcm283x.dtsi b/arch/arm/boot/dts/broadcom/bcm283x.dtsi +index 2ca8a2505a4d..8ac38cdb9ffc 100644 +--- a/arch/arm/boot/dts/broadcom/bcm283x.dtsi ++++ b/arch/arm/boot/dts/broadcom/bcm283x.dtsi +@@ -415,7 +415,7 @@ pwm: pwm@7e20c000 { + reg = <0x7e20c000 0x28>; + clocks = <&clocks BCM2835_CLOCK_PWM>; + assigned-clocks = <&clocks BCM2835_CLOCK_PWM>; +- assigned-clock-rates = <10000000>; ++ assigned-clock-rates = <50000000>; + #pwm-cells = <3>; status = "disabled"; }; - -- i2c0: i2c@7e205000 { -+ i2c0if: i2c@7e205000 { - compatible = "brcm,bcm2835-i2c"; - reg = <0x7e205000 0x200>; - interrupts = <2 21>; -@@ -346,6 +346,30 @@ i2c0: i2c@7e205000 { - status = "disabled"; - }; - -+ i2c0mux: i2c0mux { -+ compatible = "i2c-mux-pinctrl"; +diff --git a/arch/arm/boot/dts/broadcom/rp1.dtsi b/arch/arm/boot/dts/broadcom/rp1.dtsi +new file mode 100644 +index 000000000000..551a02a955a1 +--- /dev/null ++++ b/arch/arm/boot/dts/broadcom/rp1.dtsi +@@ -0,0 +1,1306 @@ ++#include ++#include ++#include ++ ++&rp1_target { ++ rp1: rp1 { ++ compatible = "simple-bus"; ++ #address-cells = <2>; ++ #size-cells = <2>; ++ #interrupt-cells = <2>; ++ interrupt-controller; ++ interrupt-parent = <&rp1>; ++ ++ // ranges and dma-ranges must be provided by the includer ++ ++ rp1_clocks: clocks@18000 { ++ compatible = "raspberrypi,rp1-clocks"; ++ #clock-cells = <1>; ++ reg = <0xc0 0x40018000 0x0 0x10038>; ++ clocks = <&clk_xosc>; ++ ++ assigned-clocks = <&rp1_clocks RP1_PLL_SYS_CORE>, ++ <&rp1_clocks RP1_PLL_AUDIO_CORE>, ++ // RP1_PLL_VIDEO_CORE and dividers are now managed by VEC,DPI drivers ++ <&rp1_clocks RP1_PLL_SYS>, ++ <&rp1_clocks RP1_PLL_SYS_SEC>, ++ <&rp1_clocks RP1_PLL_AUDIO>, ++ <&rp1_clocks RP1_PLL_AUDIO_SEC>, ++ <&rp1_clocks RP1_CLK_SYS>, ++ <&rp1_clocks RP1_PLL_SYS_PRI_PH>, ++ // RP1_CLK_SLOW_SYS is used for the frequency counter (FC0) ++ <&rp1_clocks RP1_CLK_SLOW_SYS>, ++ <&rp1_clocks RP1_CLK_SDIO_TIMER>, ++ <&rp1_clocks RP1_CLK_SDIO_ALT_SRC>, ++ <&rp1_clocks RP1_CLK_ETH_TSU>; ++ ++ assigned-clock-rates = <1000000000>, // RP1_PLL_SYS_CORE ++ <1536000000>, // RP1_PLL_AUDIO_CORE ++ <200000000>, // RP1_PLL_SYS ++ <125000000>, // RP1_PLL_SYS_SEC ++ <61440000>, // RP1_PLL_AUDIO ++ <192000000>, // RP1_PLL_AUDIO_SEC ++ <200000000>, // RP1_CLK_SYS ++ <100000000>, // RP1_PLL_SYS_PRI_PH ++ // Must match the XOSC frequency ++ <50000000>, // RP1_CLK_SLOW_SYS ++ <1000000>, // RP1_CLK_SDIO_TIMER ++ <200000000>, // RP1_CLK_SDIO_ALT_SRC ++ <50000000>; // RP1_CLK_ETH_TSU ++ }; ++ ++ rp1_uart0: serial@30000 { ++ compatible = "arm,pl011-axi"; ++ reg = <0xc0 0x40030000 0x0 0x100>; ++ interrupts = ; ++ clocks = <&rp1_clocks RP1_CLK_UART &rp1_clocks RP1_PLL_SYS_PRI_PH>; ++ clock-names = "uartclk", "apb_pclk"; ++ dmas = <&rp1_dma RP1_DMA_UART0_TX>, ++ <&rp1_dma RP1_DMA_UART0_RX>; ++ dma-names = "tx", "rx"; ++ pinctrl-names = "default"; ++ arm,primecell-periphid = <0x00541011>; ++ uart-has-rtscts; ++ cts-event-workaround; ++ skip-init; ++ status = "disabled"; ++ }; ++ ++ rp1_uart1: serial@34000 { ++ compatible = "arm,pl011-axi"; ++ reg = <0xc0 0x40034000 0x0 0x100>; ++ interrupts = ; ++ clocks = <&rp1_clocks RP1_CLK_UART &rp1_clocks RP1_PLL_SYS_PRI_PH>; ++ clock-names = "uartclk", "apb_pclk"; ++ // dmas = <&rp1_dma RP1_DMA_UART1_TX>, ++ // <&rp1_dma RP1_DMA_UART1_RX>; ++ // dma-names = "tx", "rx"; ++ pinctrl-names = "default"; ++ arm,primecell-periphid = <0x00541011>; ++ uart-has-rtscts; ++ cts-event-workaround; ++ skip-init; ++ status = "disabled"; ++ }; ++ ++ rp1_uart2: serial@38000 { ++ compatible = "arm,pl011-axi"; ++ reg = <0xc0 0x40038000 0x0 0x100>; ++ interrupts = ; ++ clocks = <&rp1_clocks RP1_CLK_UART &rp1_clocks RP1_PLL_SYS_PRI_PH>; ++ clock-names = "uartclk", "apb_pclk"; ++ // dmas = <&rp1_dma RP1_DMA_UART2_TX>, ++ // <&rp1_dma RP1_DMA_UART2_RX>; ++ // dma-names = "tx", "rx"; ++ pinctrl-names = "default"; ++ arm,primecell-periphid = <0x00541011>; ++ uart-has-rtscts; ++ cts-event-workaround; ++ skip-init; ++ status = "disabled"; ++ }; ++ ++ rp1_uart3: serial@3c000 { ++ compatible = "arm,pl011-axi"; ++ reg = <0xc0 0x4003c000 0x0 0x100>; ++ interrupts = ; ++ clocks = <&rp1_clocks RP1_CLK_UART &rp1_clocks RP1_PLL_SYS_PRI_PH>; ++ clock-names = "uartclk", "apb_pclk"; ++ // dmas = <&rp1_dma RP1_DMA_UART3_TX>, ++ // <&rp1_dma RP1_DMA_UART3_RX>; ++ // dma-names = "tx", "rx"; ++ pinctrl-names = "default"; ++ arm,primecell-periphid = <0x00541011>; ++ uart-has-rtscts; ++ cts-event-workaround; ++ skip-init; ++ status = "disabled"; ++ }; ++ ++ rp1_uart4: serial@40000 { ++ compatible = "arm,pl011-axi"; ++ reg = <0xc0 0x40040000 0x0 0x100>; ++ interrupts = ; ++ clocks = <&rp1_clocks RP1_CLK_UART &rp1_clocks RP1_PLL_SYS_PRI_PH>; ++ clock-names = "uartclk", "apb_pclk"; ++ // dmas = <&rp1_dma RP1_DMA_UART4_TX>, ++ // <&rp1_dma RP1_DMA_UART4_RX>; ++ // dma-names = "tx", "rx"; ++ pinctrl-names = "default"; ++ arm,primecell-periphid = <0x00541011>; ++ uart-has-rtscts; ++ cts-event-workaround; ++ skip-init; ++ status = "disabled"; ++ }; ++ ++ rp1_uart5: serial@44000 { ++ compatible = "arm,pl011-axi"; ++ reg = <0xc0 0x40044000 0x0 0x100>; ++ interrupts = ; ++ clocks = <&rp1_clocks RP1_CLK_UART &rp1_clocks RP1_PLL_SYS_PRI_PH>; ++ clock-names = "uartclk", "apb_pclk"; ++ // dmas = <&rp1_dma RP1_DMA_UART5_TX>, ++ // <&rp1_dma RP1_DMA_UART5_RX>; ++ // dma-names = "tx", "rx"; ++ pinctrl-names = "default"; ++ arm,primecell-periphid = <0x00541011>; ++ uart-has-rtscts; ++ cts-event-workaround; ++ skip-init; ++ status = "disabled"; ++ }; ++ ++ rp1_spi8: spi@4c000 { ++ reg = <0xc0 0x4004c000 0x0 0x130>; ++ compatible = "snps,dw-apb-ssi"; ++ interrupts = ; ++ clocks = <&rp1_clocks RP1_CLK_SYS>; ++ clock-names = "ssi_clk"; + #address-cells = <1>; + #size-cells = <0>; ++ num-cs = <2>; ++ dmas = <&rp1_dma RP1_DMA_SPI8_TX>, ++ <&rp1_dma RP1_DMA_SPI8_RX>; ++ dma-names = "tx", "rx"; ++ status = "disabled"; ++ }; + -+ i2c-parent = <&i2c0if>; ++ rp1_spi0: spi@50000 { ++ reg = <0xc0 0x40050000 0x0 0x130>; ++ compatible = "snps,dw-apb-ssi"; ++ interrupts = ; ++ clocks = <&rp1_clocks RP1_CLK_SYS>; ++ clock-names = "ssi_clk"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ num-cs = <2>; ++ dmas = <&rp1_dma RP1_DMA_SPI0_TX>, ++ <&rp1_dma RP1_DMA_SPI0_RX>; ++ dma-names = "tx", "rx"; ++ status = "disabled"; ++ }; + -+ pinctrl-names = "i2c0", "i2c_csi_dsi"; ++ rp1_spi1: spi@54000 { ++ reg = <0xc0 0x40054000 0x0 0x130>; ++ compatible = "snps,dw-apb-ssi"; ++ interrupts = ; ++ clocks = <&rp1_clocks RP1_CLK_SYS>; ++ clock-names = "ssi_clk"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ num-cs = <2>; ++ dmas = <&rp1_dma RP1_DMA_SPI1_TX>, ++ <&rp1_dma RP1_DMA_SPI1_RX>; ++ dma-names = "tx", "rx"; ++ status = "disabled"; ++ }; + ++ rp1_spi2: spi@58000 { ++ reg = <0xc0 0x40058000 0x0 0x130>; ++ compatible = "snps,dw-apb-ssi"; ++ interrupts = ; ++ clocks = <&rp1_clocks RP1_CLK_SYS>; ++ clock-names = "ssi_clk"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ num-cs = <2>; ++ dmas = <&rp1_dma RP1_DMA_SPI2_TX>, ++ <&rp1_dma RP1_DMA_SPI2_RX>; ++ dma-names = "tx", "rx"; ++ status = "disabled"; ++ }; ++ ++ rp1_spi3: spi@5c000 { ++ reg = <0xc0 0x4005c000 0x0 0x130>; ++ compatible = "snps,dw-apb-ssi"; ++ interrupts = ; ++ clocks = <&rp1_clocks RP1_CLK_SYS>; ++ clock-names = "ssi_clk"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ num-cs = <2>; ++ dmas = <&rp1_dma RP1_DMA_SPI3_TX>, ++ <&rp1_dma RP1_DMA_SPI3_RX>; ++ dma-names = "tx", "rx"; ++ status = "disabled"; ++ }; ++ ++ // SPI4 is a target/slave interface ++ rp1_spi4: spi@60000 { ++ reg = <0xc0 0x40060000 0x0 0x130>; ++ compatible = "snps,dw-apb-ssi"; ++ interrupts = ; ++ clocks = <&rp1_clocks RP1_CLK_SYS>; ++ clock-names = "ssi_clk"; ++ #address-cells = <0>; ++ #size-cells = <0>; ++ num-cs = <1>; ++ spi-slave; ++ dmas = <&rp1_dma RP1_DMA_SPI4_TX>, ++ <&rp1_dma RP1_DMA_SPI4_RX>; ++ dma-names = "tx", "rx"; + status = "disabled"; + -+ i2c0: i2c@0 { -+ reg = <0>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ }; -+ -+ i2c_csi_dsi: i2c@1 { -+ reg = <1>; -+ #address-cells = <1>; -+ #size-cells = <0>; ++ slave { ++ compatible = "spidev"; ++ spi-max-frequency = <1000000>; + }; + }; + - dpi: dpi@7e208000 { - compatible = "brcm,bcm2835-dpi"; - reg = <0x7e208000 0x8c>; -@@ -466,14 +490,6 @@ i2c1: i2c@7e804000 { - status = "disabled"; - }; - -- vec: vec@7e806000 { -- compatible = "brcm,bcm2835-vec"; -- reg = <0x7e806000 0x1000>; -- clocks = <&clocks BCM2835_CLOCK_VEC>; -- interrupts = <2 27>; -- status = "disabled"; -- }; -- - usb: usb@7e980000 { - compatible = "brcm,bcm2835-usb"; - reg = <0x7e980000 0x10000>; ++ rp1_spi5: spi@64000 { ++ reg = <0xc0 0x40064000 0x0 0x130>; ++ compatible = "snps,dw-apb-ssi"; ++ interrupts = ; ++ clocks = <&rp1_clocks RP1_CLK_SYS>; ++ clock-names = "ssi_clk"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ num-cs = <2>; ++ dmas = <&rp1_dma RP1_DMA_SPI5_TX>, ++ <&rp1_dma RP1_DMA_SPI5_RX>; ++ dma-names = "tx", "rx"; ++ status = "disabled"; ++ }; ++ ++ rp1_spi6: spi@68000 { ++ reg = <0xc0 0x40068000 0x0 0x130>; ++ compatible = "snps,dw-apb-ssi"; ++ interrupts = ; ++ clocks = <&rp1_clocks RP1_CLK_SYS>; ++ clock-names = "ssi_clk"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ num-cs = <2>; ++ dmas = <&rp1_dma RP1_DMA_SPI6_TX>, ++ <&rp1_dma RP1_DMA_SPI6_RX>; ++ dma-names = "tx", "rx"; ++ status = "disabled"; ++ }; ++ ++ // SPI7 is a target/slave interface ++ rp1_spi7: spi@6c000 { ++ reg = <0xc0 0x4006c000 0x0 0x130>; ++ compatible = "snps,dw-apb-ssi"; ++ interrupts = ; ++ clocks = <&rp1_clocks RP1_CLK_SYS>; ++ clock-names = "ssi_clk"; ++ #address-cells = <0>; ++ #size-cells = <0>; ++ num-cs = <1>; ++ spi-slave; ++ dmas = <&rp1_dma RP1_DMA_SPI7_TX>, ++ <&rp1_dma RP1_DMA_SPI7_RX>; ++ dma-names = "tx", "rx"; ++ status = "disabled"; ++ ++ slave { ++ compatible = "spidev"; ++ spi-max-frequency = <1000000>; ++ }; ++ }; ++ ++ rp1_i2c0: i2c@70000 { ++ reg = <0xc0 0x40070000 0x0 0x1000>; ++ compatible = "snps,designware-i2c"; ++ interrupts = ; ++ clocks = <&rp1_clocks RP1_CLK_SYS>; ++ i2c-scl-rising-time-ns = <65>; ++ i2c-scl-falling-time-ns = <100>; ++ status = "disabled"; ++ }; ++ ++ rp1_i2c1: i2c@74000 { ++ reg = <0xc0 0x40074000 0x0 0x1000>; ++ compatible = "snps,designware-i2c"; ++ interrupts = ; ++ clocks = <&rp1_clocks RP1_CLK_SYS>; ++ i2c-scl-rising-time-ns = <65>; ++ i2c-scl-falling-time-ns = <100>; ++ status = "disabled"; ++ }; ++ ++ rp1_i2c2: i2c@78000 { ++ reg = <0xc0 0x40078000 0x0 0x1000>; ++ compatible = "snps,designware-i2c"; ++ interrupts = ; ++ clocks = <&rp1_clocks RP1_CLK_SYS>; ++ i2c-scl-rising-time-ns = <65>; ++ i2c-scl-falling-time-ns = <100>; ++ status = "disabled"; ++ }; ++ ++ rp1_i2c3: i2c@7c000 { ++ reg = <0xc0 0x4007c000 0x0 0x1000>; ++ compatible = "snps,designware-i2c"; ++ interrupts = ; ++ clocks = <&rp1_clocks RP1_CLK_SYS>; ++ i2c-scl-rising-time-ns = <65>; ++ i2c-scl-falling-time-ns = <100>; ++ status = "disabled"; ++ }; ++ ++ rp1_i2c4: i2c@80000 { ++ reg = <0xc0 0x40080000 0x0 0x1000>; ++ compatible = "snps,designware-i2c"; ++ interrupts = ; ++ clocks = <&rp1_clocks RP1_CLK_SYS>; ++ i2c-scl-rising-time-ns = <65>; ++ i2c-scl-falling-time-ns = <100>; ++ status = "disabled"; ++ }; ++ ++ rp1_i2c5: i2c@84000 { ++ reg = <0xc0 0x40084000 0x0 0x1000>; ++ compatible = "snps,designware-i2c"; ++ interrupts = ; ++ clocks = <&rp1_clocks RP1_CLK_SYS>; ++ i2c-scl-rising-time-ns = <65>; ++ i2c-scl-falling-time-ns = <100>; ++ status = "disabled"; ++ }; ++ ++ rp1_i2c6: i2c@88000 { ++ reg = <0xc0 0x40088000 0x0 0x1000>; ++ compatible = "snps,designware-i2c"; ++ interrupts = ; ++ clocks = <&rp1_clocks RP1_CLK_SYS>; ++ i2c-scl-rising-time-ns = <65>; ++ i2c-scl-falling-time-ns = <100>; ++ status = "disabled"; ++ }; ++ ++ rp1_pwm0: pwm@98000 { ++ compatible = "raspberrypi,rp1-pwm"; ++ reg = <0xc0 0x40098000 0x0 0x100>; ++ #pwm-cells = <3>; ++ clocks = <&rp1_clocks RP1_CLK_PWM0>; ++ assigned-clocks = <&rp1_clocks RP1_CLK_PWM0>; ++ assigned-clock-rates = <50000000>; ++ status = "disabled"; ++ }; ++ ++ rp1_pwm1: pwm@9c000 { ++ compatible = "raspberrypi,rp1-pwm"; ++ reg = <0xc0 0x4009c000 0x0 0x100>; ++ #pwm-cells = <3>; ++ clocks = <&rp1_clocks RP1_CLK_PWM1>; ++ assigned-clocks = <&rp1_clocks RP1_CLK_PWM1>; ++ assigned-clock-rates = <50000000>; ++ status = "disabled"; ++ }; ++ ++ rp1_i2s0: i2s@a0000 { ++ reg = <0xc0 0x400a0000 0x0 0x1000>; ++ compatible = "snps,designware-i2s"; ++ // Providing an interrupt disables DMA ++ // interrupts = ; ++ clocks = <&rp1_clocks RP1_CLK_I2S>; ++ clock-names = "i2sclk"; ++ #sound-dai-cells = <0>; ++ dmas = <&rp1_dma RP1_DMA_I2S0_TX>,<&rp1_dma RP1_DMA_I2S0_RX>; ++ dma-names = "tx", "rx"; ++ status = "disabled"; ++ }; ++ ++ rp1_i2s1: i2s@a4000 { ++ reg = <0xc0 0x400a4000 0x0 0x1000>; ++ compatible = "snps,designware-i2s"; ++ // Providing an interrupt disables DMA ++ // interrupts = ; ++ clocks = <&rp1_clocks RP1_CLK_I2S>; ++ clock-names = "i2sclk"; ++ #sound-dai-cells = <0>; ++ dmas = <&rp1_dma RP1_DMA_I2S1_TX>,<&rp1_dma RP1_DMA_I2S1_RX>; ++ dma-names = "tx", "rx"; ++ status = "disabled"; ++ }; ++ ++ rp1_i2s2: i2s@a8000 { ++ reg = <0xc0 0x400a8000 0x0 0x1000>; ++ compatible = "snps,designware-i2s"; ++ // Providing an interrupt disables DMA ++ // interrupts = ; ++ clocks = <&rp1_clocks RP1_CLK_I2S>; ++ status = "disabled"; ++ }; ++ ++ rp1_sdio_clk0: sdio_clk0@b0004 { ++ compatible = "raspberrypi,rp1-sdio-clk"; ++ reg = <0xc0 0x400b0004 0x0 0x1c>; ++ clocks = <&sdio_src &sdhci_core>; ++ clock-names = "src", "base"; ++ #clock-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ rp1_sdio_clk1: sdio_clk1@b4004 { ++ compatible = "raspberrypi,rp1-sdio-clk"; ++ reg = <0xc0 0x400b4004 0x0 0x1c>; ++ clocks = <&sdio_src &sdhci_core>; ++ clock-names = "src", "base"; ++ #clock-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ rp1_adc: adc@c8000 { ++ compatible = "raspberrypi,rp1-adc"; ++ reg = <0xc0 0x400c8000 0x0 0x4000>; ++ clocks = <&rp1_clocks RP1_CLK_ADC>; ++ clock-names = "adcclk"; ++ #clock-cells = <0>; ++ vref-supply = <&rp1_vdd_3v3>; ++ status = "disabled"; ++ }; ++ ++ rp1_gpio: gpio@d0000 { ++ reg = <0xc0 0x400d0000 0x0 0xc000>, ++ <0xc0 0x400e0000 0x0 0xc000>, ++ <0xc0 0x400f0000 0x0 0xc000>; ++ compatible = "raspberrypi,rp1-gpio"; ++ interrupts = , ++ , ++ ; ++ gpio-controller; ++ #gpio-cells = <2>; ++ interrupt-controller; ++ #interrupt-cells = <2>; ++ ++ rp1_uart0_14_15: rp1_uart0_14_15 { ++ pin_txd { ++ function = "uart0"; ++ pins = "gpio14"; ++ bias-disable; ++ }; ++ pin_rxd { ++ function = "uart0"; ++ pins = "gpio15"; ++ bias-pull-up; ++ }; ++ }; ++ rp1_uart0_ctsrts_16_17: rp1_uart0_ctsrts_16_17 { ++ pin_cts { ++ function = "uart0"; ++ pins = "gpio16"; ++ bias-pull-up; ++ }; ++ pin_rts { ++ function = "uart0"; ++ pins = "gpio17"; ++ bias-disable; ++ }; ++ }; ++ rp1_uart1_0_1: rp1_uart1_0_1 { ++ pin_txd { ++ function = "uart1"; ++ pins = "gpio0"; ++ bias-disable; ++ }; ++ pin_rxd { ++ function = "uart1"; ++ pins = "gpio1"; ++ bias-pull-up; ++ }; ++ }; ++ rp1_uart1_ctsrts_2_3: rp1_uart1_ctsrts_2_3 { ++ pin_cts { ++ function = "uart1"; ++ pins = "gpio2"; ++ bias-pull-up; ++ }; ++ pin_rts { ++ function = "uart1"; ++ pins = "gpio3"; ++ bias-disable; ++ }; ++ }; ++ rp1_uart2_4_5: rp1_uart2_4_5 { ++ pin_txd { ++ function = "uart2"; ++ pins = "gpio4"; ++ bias-disable; ++ }; ++ pin_rxd { ++ function = "uart2"; ++ pins = "gpio5"; ++ bias-pull-up; ++ }; ++ }; ++ rp1_uart2_ctsrts_6_7: rp1_uart2_ctsrts_6_7 { ++ pin_cts { ++ function = "uart2"; ++ pins = "gpio6"; ++ bias-pull-up; ++ }; ++ pin_rts { ++ function = "uart2"; ++ pins = "gpio7"; ++ bias-disable; ++ }; ++ }; ++ rp1_uart3_8_9: rp1_uart3_8_9 { ++ pin_txd { ++ function = "uart3"; ++ pins = "gpio8"; ++ bias-disable; ++ }; ++ pin_rxd { ++ function = "uart3"; ++ pins = "gpio9"; ++ bias-pull-up; ++ }; ++ }; ++ rp1_uart3_ctsrts_10_11: rp1_uart3_ctsrts_10_11 { ++ pin_cts { ++ function = "uart3"; ++ pins = "gpio10"; ++ bias-pull-up; ++ }; ++ pin_rts { ++ function = "uart3"; ++ pins = "gpio11"; ++ bias-disable; ++ }; ++ }; ++ rp1_uart4_12_13: rp1_uart4_12_13 { ++ pin_txd { ++ function = "uart4"; ++ pins = "gpio12"; ++ bias-disable; ++ }; ++ pin_rxd { ++ function = "uart4"; ++ pins = "gpio13"; ++ bias-pull-up; ++ }; ++ }; ++ rp1_uart4_ctsrts_14_15: rp1_uart4_ctsrts_14_15 { ++ pin_cts { ++ function = "uart4"; ++ pins = "gpio14"; ++ bias-pull-up; ++ }; ++ pin_rts { ++ function = "uart4"; ++ pins = "gpio15"; ++ bias-disable; ++ }; ++ }; ++ ++ rp1_sdio0_22_27: rp1_sdio0_22_27 { ++ pin_clk { ++ function = "sd0"; ++ pins = "gpio22"; ++ bias-disable; ++ drive-strength = <12>; ++ slew-rate = <1>; ++ }; ++ pin_cmd { ++ function = "sd0"; ++ pins = "gpio23"; ++ bias-pull-up; ++ drive-strength = <12>; ++ slew-rate = <1>; ++ }; ++ pins_dat { ++ function = "sd0"; ++ pins = "gpio24", "gpio25", "gpio26", "gpio27"; ++ bias-pull-up; ++ drive-strength = <12>; ++ slew-rate = <1>; ++ }; ++ }; ++ ++ rp1_sdio1_28_33: rp1_sdio1_28_33 { ++ pin_clk { ++ function = "sd1"; ++ pins = "gpio28"; ++ bias-disable; ++ drive-strength = <12>; ++ slew-rate = <1>; ++ }; ++ pin_cmd { ++ function = "sd1"; ++ pins = "gpio29"; ++ bias-pull-up; ++ drive-strength = <12>; ++ slew-rate = <1>; ++ }; ++ pins_dat { ++ function = "sd1"; ++ pins = "gpio30", "gpio31", "gpio32", "gpio33"; ++ bias-pull-up; ++ drive-strength = <12>; ++ slew-rate = <1>; ++ }; ++ }; ++ ++ rp1_i2s0_18_21: rp1_i2s0_18_21 { ++ function = "i2s0"; ++ pins = "gpio18", "gpio19", "gpio20", "gpio21"; ++ bias-disable; ++ }; ++ ++ rp1_i2s1_18_21: rp1_i2s1_18_21 { ++ function = "i2s1"; ++ pins = "gpio18", "gpio19", "gpio20", "gpio21"; ++ bias-disable; ++ }; ++ ++ rp1_i2c4_34_35: rp1_i2c4_34_35 { ++ function = "i2c4"; ++ pins = "gpio34", "gpio35"; ++ drive-strength = <12>; ++ bias-pull-up; ++ }; ++ rp1_i2c6_38_39: rp1_i2c6_38_39 { ++ function = "i2c6"; ++ pins = "gpio38", "gpio39"; ++ drive-strength = <12>; ++ bias-pull-up; ++ }; ++ rp1_i2c4_40_41: rp1_i2c4_40_41 { ++ function = "i2c4"; ++ pins = "gpio40", "gpio41"; ++ drive-strength = <12>; ++ bias-pull-up; ++ }; ++ rp1_i2c5_44_45: rp1_i2c5_44_45 { ++ function = "i2c5"; ++ pins = "gpio44", "gpio45"; ++ drive-strength = <12>; ++ bias-pull-up; ++ }; ++ rp1_i2c0_0_1: rp1_i2c0_0_1 { ++ function = "i2c0"; ++ pins = "gpio0", "gpio1"; ++ drive-strength = <12>; ++ bias-pull-up; ++ }; ++ rp1_i2c0_8_9: rp1_i2c0_8_9 { ++ function = "i2c0"; ++ pins = "gpio8", "gpio9"; ++ drive-strength = <12>; ++ bias-pull-up; ++ }; ++ rp1_i2c1_2_3: rp1_i2c1_2_3 { ++ function = "i2c1"; ++ pins = "gpio2", "gpio3"; ++ drive-strength = <12>; ++ bias-pull-up; ++ }; ++ rp1_i2c1_10_11: rp1_i2c1_10_11 { ++ function = "i2c1"; ++ pins = "gpio10", "gpio11"; ++ drive-strength = <12>; ++ bias-pull-up; ++ }; ++ rp1_i2c2_4_5: rp1_i2c2_4_5 { ++ function = "i2c2"; ++ pins = "gpio4", "gpio5"; ++ drive-strength = <12>; ++ bias-pull-up; ++ }; ++ rp1_i2c2_12_13: rp1_i2c2_12_13 { ++ function = "i2c2"; ++ pins = "gpio12", "gpio13"; ++ drive-strength = <12>; ++ bias-pull-up; ++ }; ++ rp1_i2c3_6_7: rp1_i2c3_6_7 { ++ function = "i2c3"; ++ pins = "gpio6", "gpio7"; ++ drive-strength = <12>; ++ bias-pull-up; ++ }; ++ rp1_i2c3_14_15: rp1_i2c3_14_15 { ++ function = "i2c3"; ++ pins = "gpio14", "gpio15"; ++ drive-strength = <12>; ++ bias-pull-up; ++ }; ++ rp1_i2c3_22_23: rp1_i2c3_22_23 { ++ function = "i2c3"; ++ pins = "gpio22", "gpio23"; ++ drive-strength = <12>; ++ bias-pull-up; ++ }; ++ ++ // DPI mappings with HSYNC,VSYNC but without PIXCLK,DE ++ rp1_dpi_16bit_gpio2: rp1_dpi_16bit_gpio2 { /* Mode 2, not fully supported by RP1 */ ++ function = "dpi"; ++ pins = "gpio2", "gpio3", "gpio4", "gpio5", ++ "gpio6", "gpio7", "gpio8", "gpio9", ++ "gpio10", "gpio11", "gpio12", "gpio13", ++ "gpio14", "gpio15", "gpio16", "gpio17", ++ "gpio18", "gpio19"; ++ bias-disable; ++ }; ++ rp1_dpi_16bit_cpadhi_gpio2: rp1_dpi_16bit_cpadhi_gpio2 { /* Mode 3 */ ++ function = "dpi"; ++ pins = "gpio2", "gpio3", "gpio4", "gpio5", ++ "gpio6", "gpio7", "gpio8", ++ "gpio12", "gpio13", "gpio14", "gpio15", ++ "gpio16", "gpio17", ++ "gpio20", "gpio21", "gpio22", "gpio23", ++ "gpio24"; ++ bias-disable; ++ }; ++ rp1_dpi_16bit_pad666_gpio2: rp1_dpi_16bit_pad666_gpio2 { /* Mode 4 */ ++ function = "dpi"; ++ pins = "gpio2", "gpio3", ++ "gpio5", "gpio6", "gpio7", "gpio8", ++ "gpio9", ++ "gpio12", "gpio13", "gpio14", "gpio15", ++ "gpio16", "gpio17", ++ "gpio21", "gpio22", "gpio23", "gpio24", ++ "gpio25"; ++ bias-disable; ++ }; ++ rp1_dpi_18bit_gpio2: rp1_dpi_18bit_gpio2 { /* Mode 5, not fully supported by RP1 */ ++ function = "dpi"; ++ pins = "gpio2", "gpio3", "gpio4", "gpio5", ++ "gpio6", "gpio7", "gpio8", "gpio9", ++ "gpio10", "gpio11", "gpio12", "gpio13", ++ "gpio14", "gpio15", "gpio16", "gpio17", ++ "gpio18", "gpio19", "gpio20", "gpio21"; ++ bias-disable; ++ }; ++ rp1_dpi_18bit_cpadhi_gpio2: rp1_dpi_18bit_cpadhi_gpio2 { /* Mode 6 */ ++ function = "dpi"; ++ pins = "gpio2", "gpio3", "gpio4", "gpio5", ++ "gpio6", "gpio7", "gpio8", "gpio9", ++ "gpio12", "gpio13", "gpio14", "gpio15", ++ "gpio16", "gpio17", ++ "gpio20", "gpio21", "gpio22", "gpio23", ++ "gpio24", "gpio25"; ++ bias-disable; ++ }; ++ rp1_dpi_24bit_gpio2: rp1_dpi_24bit_gpio2 { /* Mode 7 */ ++ function = "dpi"; ++ pins = "gpio2", "gpio3", "gpio4", "gpio5", ++ "gpio6", "gpio7", "gpio8", "gpio9", ++ "gpio10", "gpio11", "gpio12", "gpio13", ++ "gpio14", "gpio15", "gpio16", "gpio17", ++ "gpio18", "gpio19", "gpio20", "gpio21", ++ "gpio22", "gpio23", "gpio24", "gpio25", ++ "gpio26", "gpio27"; ++ bias-disable; ++ }; ++ rp1_dpi_hvsync: rp1_dpi_hvsync { /* Sync only, for use with int VDAC */ ++ function = "dpi"; ++ pins = "gpio2", "gpio3"; ++ bias-disable; ++ }; ++ ++ // More DPI mappings, including PIXCLK,DE on GPIOs 0,1 ++ rp1_dpi_16bit_gpio0: rp1_dpi_16bit_gpio0 { /* Mode 2, not fully supported by RP1 */ ++ function = "dpi"; ++ pins = "gpio0", "gpio1", "gpio2", "gpio3", ++ "gpio4", "gpio5", "gpio6", "gpio7", ++ "gpio8", "gpio9", "gpio10", "gpio11", ++ "gpio12", "gpio13", "gpio14", "gpio15", ++ "gpio16", "gpio17", "gpio18", "gpio19"; ++ bias-disable; ++ }; ++ rp1_dpi_16bit_cpadhi_gpio0: rp1_dpi_16bit_cpadhi_gpio0 { /* Mode 3 */ ++ function = "dpi"; ++ pins = "gpio0", "gpio1", "gpio2", "gpio3", ++ "gpio4", "gpio5", "gpio6", "gpio7", ++ "gpio8", ++ "gpio12", "gpio13", "gpio14", "gpio15", ++ "gpio16", "gpio17", ++ "gpio20", "gpio21", "gpio22", "gpio23", ++ "gpio24"; ++ bias-disable; ++ }; ++ rp1_dpi_16bit_pad666_gpio0: rp1_dpi_16bit_pad666_gpio0 { /* Mode 4 */ ++ function = "dpi"; ++ pins = "gpio0", "gpio1", "gpio2", "gpio3", ++ "gpio5", "gpio6", "gpio7", "gpio8", ++ "gpio9", ++ "gpio12", "gpio13", "gpio14", "gpio15", ++ "gpio16", "gpio17", ++ "gpio21", "gpio22", "gpio23", "gpio24", ++ "gpio25"; ++ bias-disable; ++ }; ++ rp1_dpi_18bit_gpio0: rp1_dpi_18bit_gpio0 { /* Mode 5, not fully supported by RP1 */ ++ function = "dpi"; ++ pins = "gpio0", "gpio1", "gpio2", "gpio3", ++ "gpio4", "gpio5", "gpio6", "gpio7", ++ "gpio8", "gpio9", "gpio10", "gpio11", ++ "gpio12", "gpio13", "gpio14", "gpio15", ++ "gpio16", "gpio17", "gpio18", "gpio19", ++ "gpio20", "gpio21"; ++ bias-disable; ++ }; ++ rp1_dpi_18bit_cpadhi_gpio0: rp1_dpi_18bit_cpadhi_gpio0 { /* Mode 6 */ ++ function = "dpi"; ++ pins = "gpio0", "gpio1", "gpio2", "gpio3", ++ "gpio4", "gpio5", "gpio6", "gpio7", ++ "gpio8", "gpio9", ++ "gpio12", "gpio13", "gpio14", "gpio15", ++ "gpio16", "gpio17", ++ "gpio20", "gpio21", "gpio22", "gpio23", ++ "gpio24", "gpio25"; ++ bias-disable; ++ }; ++ rp1_dpi_24bit_gpio0: rp1_dpi_24bit_gpio0 { /* Mode 7 -- All GPIOs used! */ ++ function = "dpi"; ++ pins = "gpio0", "gpio1", "gpio2", "gpio3", ++ "gpio4", "gpio5", "gpio6", "gpio7", ++ "gpio8", "gpio9", "gpio10", "gpio11", ++ "gpio12", "gpio13", "gpio14", "gpio15", ++ "gpio16", "gpio17", "gpio18", "gpio19", ++ "gpio20", "gpio21", "gpio22", "gpio23", ++ "gpio24", "gpio25", "gpio26", "gpio27"; ++ bias-disable; ++ }; ++ ++ rp1_gpclksrc0_gpio4: rp1_gpclksrc0_gpio4 { ++ function = "gpclk0"; ++ pins = "gpio4"; ++ bias-disable; ++ }; ++ ++ rp1_gpclksrc0_gpio20: rp1_gpclksrc0_gpio20 { ++ function = "gpclk0"; ++ pins = "gpio20"; ++ bias-disable; ++ }; ++ ++ rp1_gpclksrc1_gpio5: rp1_gpclksrc1_gpio5 { ++ function = "gpclk1"; ++ pins = "gpio5"; ++ bias-disable; ++ }; ++ ++ rp1_gpclksrc1_gpio18: rp1_gpclksrc1_gpio18 { ++ function = "gpclk1"; ++ pins = "gpio18"; ++ bias-disable; ++ }; ++ ++ rp1_gpclksrc1_gpio21: rp1_gpclksrc1_gpio21 { ++ function = "gpclk1"; ++ pins = "gpio21"; ++ bias-disable; ++ }; ++ ++ rp1_pwm1_gpio45: rp1_pwm1_gpio45 { ++ function = "pwm1"; ++ pins = "gpio45"; ++ bias-pull-down; ++ }; ++ ++ rp1_spi0_gpio9: rp1_spi0_gpio9 { ++ function = "spi0"; ++ pins = "gpio9", "gpio10", "gpio11"; ++ bias-disable; ++ drive-strength = <12>; ++ slew-rate = <1>; ++ }; ++ ++ rp1_spi0_cs_gpio7: rp1_spi0_cs_gpio7 { ++ function = "spi0"; ++ pins = "gpio7", "gpio8"; ++ bias-pull-up; ++ }; ++ ++ rp1_spi1_gpio19: rp1_spi1_gpio19 { ++ function = "spi1"; ++ pins = "gpio19", "gpio20", "gpio21"; ++ bias-disable; ++ drive-strength = <12>; ++ slew-rate = <1>; ++ }; ++ ++ rp1_spi2_gpio1: rp1_spi2_gpio1 { ++ function = "spi2"; ++ pins = "gpio1", "gpio2", "gpio3"; ++ bias-disable; ++ drive-strength = <12>; ++ slew-rate = <1>; ++ }; ++ ++ rp1_spi3_gpio5: rp1_spi3_gpio5 { ++ function = "spi3"; ++ pins = "gpio5", "gpio6", "gpio7"; ++ bias-disable; ++ drive-strength = <12>; ++ slew-rate = <1>; ++ }; ++ ++ rp1_spi4_gpio9: rp1_spi4_gpio9 { ++ function = "spi4"; ++ pins = "gpio9", "gpio10", "gpio11"; ++ bias-disable; ++ drive-strength = <12>; ++ slew-rate = <1>; ++ }; ++ ++ rp1_spi5_gpio13: rp1_spi5_gpio13 { ++ function = "spi5"; ++ pins = "gpio13", "gpio14", "gpio15"; ++ bias-disable; ++ drive-strength = <12>; ++ slew-rate = <1>; ++ }; ++ ++ rp1_spi8_gpio49: rp1_spi8_gpio49 { ++ function = "spi8"; ++ pins = "gpio49", "gpio50", "gpio51"; ++ bias-disable; ++ drive-strength = <12>; ++ slew-rate = <1>; ++ }; ++ ++ rp1_spi8_cs_gpio52: rp1_spi8_cs_gpio52 { ++ function = "spi0"; ++ pins = "gpio52", "gpio53"; ++ bias-pull-up; ++ }; ++ }; ++ ++ rp1_eth: ethernet@100000 { ++ reg = <0xc0 0x40100000 0x0 0x4000>; ++ compatible = "cdns,macb"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ interrupts = ; ++ clocks = <&macb_pclk &macb_hclk &rp1_clocks RP1_CLK_ETH_TSU>; ++ clock-names = "pclk", "hclk", "tsu_clk"; ++ phy-mode = "rgmii-id"; ++ cdns,aw2w-max-pipe = /bits/ 8 <8>; ++ cdns,ar2r-max-pipe = /bits/ 8 <8>; ++ cdns,use-aw2b-fill; ++ local-mac-address = [00 00 00 00 00 00]; ++ status = "disabled"; ++ }; ++ ++ rp1_csi0: csi@110000 { ++ compatible = "raspberrypi,rp1-cfe"; ++ reg = <0xc0 0x40110000 0x0 0x100>, // CSI2 DMA address ++ <0xc0 0x40114000 0x0 0x100>, // PHY/CSI Host address ++ <0xc0 0x40120000 0x0 0x100>, // MIPI CFG address ++ <0xc0 0x40124000 0x0 0x1000>; // PiSP FE address ++ ++ // interrupts must match rp1_pisp_fe setup ++ interrupts = ; ++ ++ clocks = <&rp1_clocks RP1_CLK_MIPI0_CFG>; ++ assigned-clocks = <&rp1_clocks RP1_CLK_MIPI0_CFG>; ++ assigned-clock-rates = <25000000>; ++ ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ rp1_csi1: csi@128000 { ++ compatible = "raspberrypi,rp1-cfe"; ++ reg = <0xc0 0x40128000 0x0 0x100>, // CSI2 DMA address ++ <0xc0 0x4012c000 0x0 0x100>, // PHY/CSI Host address ++ <0xc0 0x40138000 0x0 0x100>, // MIPI CFG address ++ <0xc0 0x4013c000 0x0 0x1000>; // PiSP FE address ++ ++ // interrupts must match rp1_pisp_fe setup ++ interrupts = ; ++ ++ clocks = <&rp1_clocks RP1_CLK_MIPI1_CFG>; ++ assigned-clocks = <&rp1_clocks RP1_CLK_MIPI1_CFG>; ++ assigned-clock-rates = <25000000>; ++ ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; ++ ++ rp1_mmc0: mmc@180000 { ++ reg = <0xc0 0x40180000 0x0 0x100>; ++ compatible = "raspberrypi,rp1-dwcmshc"; ++ interrupts = ; ++ clocks = <&rp1_clocks RP1_CLK_SYS &sdhci_core ++ &rp1_clocks RP1_CLK_SDIO_TIMER ++ &rp1_sdio_clk0>; ++ clock-names = "bus", "core", "timeout", "sdio"; ++ /* Bank 0 VDDIO is fixed */ ++ no-1-8-v; ++ bus-width = <4>; ++ vmmc-supply = <&rp1_vdd_3v3>; ++ broken-cd; ++ status = "disabled"; ++ }; ++ ++ rp1_mmc1: mmc@184000 { ++ reg = <0xc0 0x40184000 0x0 0x100>; ++ compatible = "raspberrypi,rp1-dwcmshc"; ++ interrupts = ; ++ clocks = <&rp1_clocks RP1_CLK_SYS &sdhci_core ++ &rp1_clocks RP1_CLK_SDIO_TIMER ++ &rp1_sdio_clk1>; ++ clock-names = "bus", "core", "timeout", "sdio"; ++ bus-width = <4>; ++ vmmc-supply = <&rp1_vdd_3v3>; ++ /* Nerf SDR speeds */ ++ sdhci-caps-mask = <0x3 0x0>; ++ broken-cd; ++ status = "disabled"; ++ }; ++ ++ rp1_dma: dma@188000 { ++ reg = <0xc0 0x40188000 0x0 0x1000>; ++ compatible = "snps,axi-dma-1.01a"; ++ interrupts = ; ++ clocks = <&sdhci_core &rp1_clocks RP1_CLK_SYS>; ++ clock-names = "core-clk", "cfgr-clk"; ++ ++ #dma-cells = <1>; ++ dma-channels = <8>; ++ snps,dma-masters = <1>; ++ snps,dma-targets = <64>; ++ snps,data-width = <4>; // (8 << 4) == 128 bits ++ snps,block-size = <0x40000 0x40000 0x40000 0x40000 0x40000 0x40000 0x40000 0x40000>; ++ snps,priority = <0 1 2 3 4 5 6 7>; ++ snps,axi-max-burst-len = <8>; ++ status = "disabled"; ++ }; ++ ++ rp1_usb0: usb@200000 { ++ reg = <0xc0 0x40200000 0x0 0x100000>; ++ compatible = "snps,dwc3"; ++ dr_mode = "host"; ++ usb3-lpm-capable; ++ snps,axi-pipe-limit = /bits/ 8 <8>; ++ snps,dis_rxdet_inp3_quirk; ++ snps,parkmode-disable-ss-quirk; ++ snps,parkmode-disable-hs-quirk; ++ snps,parkmode-disable-fsls-quirk; ++ snps,tx-max-burst-prd = <8>; ++ snps,tx-thr-num-pkt-prd = <2>; ++ interrupts = ; ++ status = "disabled"; ++ }; ++ ++ rp1_usb1: usb@300000 { ++ reg = <0xc0 0x40300000 0x0 0x100000>; ++ compatible = "snps,dwc3"; ++ dr_mode = "host"; ++ usb3-lpm-capable; ++ snps,axi-pipe-limit = /bits/ 8 <8>; ++ snps,dis_rxdet_inp3_quirk; ++ snps,parkmode-disable-ss-quirk; ++ snps,parkmode-disable-hs-quirk; ++ snps,parkmode-disable-fsls-quirk; ++ snps,tx-max-burst-prd = <8>; ++ snps,tx-thr-num-pkt-prd = <2>; ++ interrupts = ; ++ status = "disabled"; ++ }; ++ ++ rp1_dsi0: dsi@110000 { ++ compatible = "raspberrypi,rp1dsi"; ++ status = "disabled"; ++ reg = <0xc0 0x40118000 0x0 0x1000>, // MIPI0 DSI DMA (ArgonDPI) ++ <0xc0 0x4011c000 0x0 0x1000>, // MIPI0 DSI Host (SNPS) ++ <0xc0 0x40120000 0x0 0x1000>; // MIPI0 CFG ++ ++ interrupts = ; ++ ++ clocks = <&rp1_clocks RP1_CLK_MIPI0_CFG>, // required, config bus clock ++ <&rp1_clocks RP1_CLK_MIPI0_DPI>, // required, pixel clock ++ <&clksrc_mipi0_dsi_byteclk>, // internal, parent for divide ++ <&clk_xosc>; // hardwired to DSI "refclk" ++ clock-names = "cfgclk", "dpiclk", "byteclk", "refclk"; ++ ++ assigned-clocks = <&rp1_clocks RP1_CLK_MIPI0_CFG>, ++ <&rp1_clocks RP1_CLK_MIPI0_DPI>; ++ assigned-clock-rates = <25000000>; ++ assigned-clock-parents = <0>, <&clksrc_mipi0_dsi_byteclk>; ++ }; ++ ++ rp1_dsi1: dsi@128000 { ++ compatible = "raspberrypi,rp1dsi"; ++ status = "disabled"; ++ reg = <0xc0 0x40130000 0x0 0x1000>, // MIPI1 DSI DMA (ArgonDPI) ++ <0xc0 0x40134000 0x0 0x1000>, // MIPI1 DSI Host (SNPS) ++ <0xc0 0x40138000 0x0 0x1000>; // MIPI1 CFG ++ ++ interrupts = ; ++ ++ clocks = <&rp1_clocks RP1_CLK_MIPI1_CFG>, // required, config bus clock ++ <&rp1_clocks RP1_CLK_MIPI1_DPI>, // required, pixel clock ++ <&clksrc_mipi1_dsi_byteclk>, // internal, parent for divide ++ <&clk_xosc>; // hardwired to DSI "refclk" ++ clock-names = "cfgclk", "dpiclk", "byteclk", "refclk"; ++ ++ assigned-clocks = <&rp1_clocks RP1_CLK_MIPI1_CFG>, ++ <&rp1_clocks RP1_CLK_MIPI1_DPI>; ++ assigned-clock-rates = <25000000>; ++ assigned-clock-parents = <0>, <&clksrc_mipi1_dsi_byteclk>; ++ }; ++ ++ /* VEC and DPI both need to control PLL_VIDEO and cannot work together; */ ++ /* config.txt should enable one or other using dtparam=vec or an overlay. */ ++ rp1_vec: vec@144000 { ++ compatible = "raspberrypi,rp1vec"; ++ status = "disabled"; ++ reg = <0xc0 0x40144000 0x0 0x1000>, // VIDEO_OUT_VEC ++ <0xc0 0x40140000 0x0 0x1000>; // VIDEO_OUT_CFG ++ ++ interrupts = ; ++ ++ clocks = <&rp1_clocks RP1_CLK_VEC>; ++ ++ assigned-clocks = <&rp1_clocks RP1_PLL_VIDEO_CORE>, ++ <&rp1_clocks RP1_PLL_VIDEO_SEC>, ++ <&rp1_clocks RP1_CLK_VEC>; ++ assigned-clock-rates = <1188000000>, ++ <108000000>, ++ <108000000>; ++ assigned-clock-parents = <0>, ++ <&rp1_clocks RP1_PLL_VIDEO_CORE>, ++ <&rp1_clocks RP1_PLL_VIDEO_SEC>; ++ }; ++ ++ rp1_dpi: dpi@148000 { ++ compatible = "raspberrypi,rp1dpi"; ++ status = "disabled"; ++ reg = <0xc0 0x40148000 0x0 0x1000>, // VIDEO_OUT DPI ++ <0xc0 0x40140000 0x0 0x1000>; // VIDEO_OUT_CFG ++ ++ interrupts = ; ++ ++ clocks = <&rp1_clocks RP1_CLK_DPI>, // DPI pixel clock ++ <&rp1_clocks RP1_PLL_VIDEO>, // PLL primary divider, and ++ <&rp1_clocks RP1_PLL_VIDEO_CORE>; // VCO, which we also control ++ clock-names = "dpiclk", "plldiv", "pllcore"; ++ ++ assigned-clocks = <&rp1_clocks RP1_CLK_DPI>; ++ assigned-clock-parents = <&rp1_clocks RP1_PLL_VIDEO>; ++ }; ++ }; ++}; ++ ++&clocks { ++ clk_xosc: clk_xosc { ++ compatible = "fixed-clock"; ++ #clock-cells = <0>; ++ clock-output-names = "xosc"; ++ clock-frequency = <50000000>; ++ }; ++ macb_pclk: macb_pclk { ++ compatible = "fixed-clock"; ++ #clock-cells = <0>; ++ clock-output-names = "pclk"; ++ clock-frequency = <200000000>; ++ }; ++ macb_hclk: macb_hclk { ++ compatible = "fixed-clock"; ++ #clock-cells = <0>; ++ clock-output-names = "hclk"; ++ clock-frequency = <200000000>; ++ }; ++ sdio_src: sdio_src { ++ // 400 MHz on FPGA. PLL sys VCO on asic ++ compatible = "fixed-clock"; ++ #clock-cells = <0>; ++ clock-output-names = "src"; ++ clock-frequency = <1000000000>; ++ }; ++ sdhci_core: sdhci_core { ++ compatible = "fixed-clock"; ++ #clock-cells = <0>; ++ clock-output-names = "core"; ++ clock-frequency = <50000000>; ++ }; ++ clksrc_mipi0_dsi_byteclk: clksrc_mipi0_dsi_byteclk { ++ // This clock is synthesized by MIPI0 D-PHY, when DSI is running. ++ // Its frequency is not known a priori (until a panel driver attaches) ++ // so assign a made-up frequency of 72MHz so it can be divided for DPI. ++ compatible = "fixed-clock"; ++ #clock-cells = <0>; ++ clock-output-names = "clksrc_mipi0_dsi_byteclk"; ++ clock-frequency = <72000000>; ++ }; ++ clksrc_mipi1_dsi_byteclk: clksrc_mipi1_dsi_byteclk { ++ // This clock is synthesized by MIPI1 D-PHY, when DSI is running. ++ // Its frequency is not known a priori (until a panel driver attaches) ++ // so assign a made-up frequency of 72MHz so it can be divided for DPI. ++ compatible = "fixed-clock"; ++ #clock-cells = <0>; ++ clock-output-names = "clksrc_mipi1_dsi_byteclk"; ++ clock-frequency = <72000000>; ++ }; ++ /* GPIO derived clock sources. Each GPIO with a GPCLK function ++ * can drive its output from the respective GPCLK ++ * generator, and provide a clock source to other internal ++ * dividers. Add dummy sources here so that they can be overridden ++ * with overlays. ++ */ ++ clksrc_gp0: clksrc_gp0 { ++ status = "disabled"; ++ compatible = "fixed-factor-clock"; ++ #clock-cells = <0>; ++ clock-div = <1>; ++ clock-mult = <1>; ++ clocks = <&rp1_clocks RP1_CLK_GP0>; ++ clock-output-names = "clksrc_gp0"; ++ }; ++ clksrc_gp1: clksrc_gp1 { ++ status = "disabled"; ++ compatible = "fixed-factor-clock"; ++ #clock-cells = <0>; ++ clock-div = <1>; ++ clock-mult = <1>; ++ clocks = <&rp1_clocks RP1_CLK_GP1>; ++ clock-output-names = "clksrc_gp1"; ++ }; ++ clksrc_gp2: clksrc_gp2 { ++ status = "disabled"; ++ compatible = "fixed-factor-clock"; ++ clock-div = <1>; ++ clock-mult = <1>; ++ #clock-cells = <0>; ++ clocks = <&rp1_clocks RP1_CLK_GP2>; ++ clock-output-names = "clksrc_gp2"; ++ }; ++ clksrc_gp3: clksrc_gp3 { ++ status = "disabled"; ++ compatible = "fixed-factor-clock"; ++ clock-div = <1>; ++ clock-mult = <1>; ++ #clock-cells = <0>; ++ clocks = <&rp1_clocks RP1_CLK_GP3>; ++ clock-output-names = "clksrc_gp3"; ++ }; ++ clksrc_gp4: clksrc_gp4 { ++ status = "disabled"; ++ compatible = "fixed-factor-clock"; ++ #clock-cells = <0>; ++ clock-div = <1>; ++ clock-mult = <1>; ++ clocks = <&rp1_clocks RP1_CLK_GP4>; ++ clock-output-names = "clksrc_gp4"; ++ }; ++ clksrc_gp5: clksrc_gp5 { ++ status = "disabled"; ++ compatible = "fixed-factor-clock"; ++ #clock-cells = <0>; ++ clock-div = <1>; ++ clock-mult = <1>; ++ clocks = <&rp1_clocks RP1_CLK_GP5>; ++ clock-output-names = "clksrc_gp5"; ++ }; ++}; ++ ++/ { ++ rp1_vdd_3v3: rp1_vdd_3v3 { ++ compatible = "regulator-fixed"; ++ regulator-name = "vdd-3v3"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-always-on; ++ }; ++}; diff --git a/arch/arm/boot/dts/overlays/Makefile b/arch/arm/boot/dts/overlays/Makefile new file mode 100644 -index 000000000000..6fcacdccb608 +index 000000000000..bdd02b8c6f0f --- /dev/null +++ b/arch/arm/boot/dts/overlays/Makefile -@@ -0,0 +1,257 @@ +@@ -0,0 +1,333 @@ +# Overlays for the Raspberry Pi platform + -+dtb-$(CONFIG_ARCH_BCM2835) += overlay_map.dtb ++dtb-$(CONFIG_ARCH_BCM2835) += overlay_map.dtb hat_map.dtb + +dtbo-$(CONFIG_ARCH_BCM2835) += \ + act-led.dtbo \ @@ -9809,23 +15982,37 @@ index 000000000000..6fcacdccb608 + anyspi.dtbo \ + apds9960.dtbo \ + applepi-dac.dtbo \ ++ arducam-64mp.dtbo \ ++ arducam-pivariety.dtbo \ + at86rf233.dtbo \ + audioinjector-addons.dtbo \ ++ audioinjector-bare-i2s.dtbo \ + audioinjector-isolated-soundcard.dtbo \ + audioinjector-ultra.dtbo \ + audioinjector-wm8731-audio.dtbo \ + audiosense-pi.dtbo \ + audremap.dtbo \ + balena-fin.dtbo \ ++ bcm2712d0.dtbo \ ++ camera-mux-2port.dtbo \ ++ camera-mux-4port.dtbo \ + cap1106.dtbo \ + chipdip-dac.dtbo \ ++ cirrus-wm5102.dtbo \ ++ cm-swap-i2c0.dtbo \ + cma.dtbo \ ++ crystalfontz-cfa050_pi_m.dtbo \ + cutiepi-panel.dtbo \ ++ dacberry400.dtbo \ + dht11.dtbo \ ++ dionaudio-kiwi.dtbo \ + dionaudio-loco.dtbo \ + dionaudio-loco-v2.dtbo \ + disable-bt.dtbo \ ++ disable-bt-pi5.dtbo \ ++ disable-emmc2.dtbo \ + disable-wifi.dtbo \ ++ disable-wifi-pi5.dtbo \ + dpi18.dtbo \ + dpi18cpadhi.dtbo \ + dpi24.dtbo \ @@ -9839,10 +16026,13 @@ index 000000000000..6fcacdccb608 + fbtft.dtbo \ + fe-pi-audio.dtbo \ + fsm-demo.dtbo \ ++ gc9a01.dtbo \ + ghost-amp.dtbo \ + goodix.dtbo \ + googlevoicehat-soundcard.dtbo \ ++ gpio-charger.dtbo \ + gpio-fan.dtbo \ ++ gpio-hog.dtbo \ + gpio-ir.dtbo \ + gpio-ir-tx.dtbo \ + gpio-key.dtbo \ @@ -9855,8 +16045,13 @@ index 000000000000..6fcacdccb608 + hdmi-backlight-hwhack-gpio.dtbo \ + hifiberry-amp.dtbo \ + hifiberry-amp100.dtbo \ ++ hifiberry-amp3.dtbo \ ++ hifiberry-amp4pro.dtbo \ + hifiberry-dac.dtbo \ ++ hifiberry-dac8x.dtbo \ + hifiberry-dacplus.dtbo \ ++ hifiberry-dacplus-pro.dtbo \ ++ hifiberry-dacplus-std.dtbo \ + hifiberry-dacplusadc.dtbo \ + hifiberry-dacplusadcpro.dtbo \ + hifiberry-dacplusdsp.dtbo \ @@ -9869,6 +16064,7 @@ index 000000000000..6fcacdccb608 + hy28b-2017.dtbo \ + i-sabre-q2m.dtbo \ + i2c-bcm2708.dtbo \ ++ i2c-fan.dtbo \ + i2c-gpio.dtbo \ + i2c-mux.dtbo \ + i2c-pwm-pca9685a.dtbo \ @@ -9876,22 +16072,35 @@ index 000000000000..6fcacdccb608 + i2c-rtc-gpio.dtbo \ + i2c-sensor.dtbo \ + i2c0.dtbo \ ++ i2c0-pi5.dtbo \ + i2c1.dtbo \ ++ i2c1-pi5.dtbo \ ++ i2c2-pi5.dtbo \ + i2c3.dtbo \ ++ i2c3-pi5.dtbo \ + i2c4.dtbo \ + i2c5.dtbo \ + i2c6.dtbo \ ++ i2s-dac.dtbo \ + i2s-gpio28-31.dtbo \ + ilitek251x.dtbo \ + imx219.dtbo \ ++ imx258.dtbo \ + imx290.dtbo \ ++ imx296.dtbo \ ++ imx327.dtbo \ + imx378.dtbo \ ++ imx462.dtbo \ + imx477.dtbo \ + imx519.dtbo \ ++ imx708.dtbo \ ++ interludeaudio-analog.dtbo \ ++ interludeaudio-digital.dtbo \ + iqaudio-codec.dtbo \ + iqaudio-dac.dtbo \ + iqaudio-dacplus.dtbo \ + iqaudio-digi-wm8804-audio.dtbo \ ++ iqs550.dtbo \ + irs1125.dtbo \ + jedec-spi-nor.dtbo \ + justboom-both.dtbo \ @@ -9913,23 +16122,32 @@ index 000000000000..6fcacdccb608 + media-center.dtbo \ + merus-amp.dtbo \ + midi-uart0.dtbo \ ++ midi-uart0-pi5.dtbo \ + midi-uart1.dtbo \ ++ midi-uart1-pi5.dtbo \ + midi-uart2.dtbo \ ++ midi-uart2-pi5.dtbo \ + midi-uart3.dtbo \ ++ midi-uart3-pi5.dtbo \ + midi-uart4.dtbo \ ++ midi-uart4-pi5.dtbo \ + midi-uart5.dtbo \ + minipitft13.dtbo \ + miniuart-bt.dtbo \ ++ mipi-dbi-spi.dtbo \ + mlx90640.dtbo \ + mmc.dtbo \ -+ mpu6050.dtbo \ + mz61581.dtbo \ ++ ov2311.dtbo \ + ov5647.dtbo \ ++ ov64a40.dtbo \ + ov7251.dtbo \ + ov9281.dtbo \ + papirus.dtbo \ + pca953x.dtbo \ ++ pcf857x.dtbo \ + pcie-32bit-dma.dtbo \ ++ pcie-32bit-dma-pi5.dtbo \ + pibell.dtbo \ + pifacedigital.dtbo \ + pifi-40.dtbo \ @@ -9940,28 +16158,33 @@ index 000000000000..6fcacdccb608 + piscreen.dtbo \ + piscreen2r.dtbo \ + pisound.dtbo \ ++ pisound-pi5.dtbo \ + pitft22.dtbo \ + pitft28-capacitive.dtbo \ + pitft28-resistive.dtbo \ + pitft35-resistive.dtbo \ + pps-gpio.dtbo \ ++ proto-codec.dtbo \ + pwm.dtbo \ + pwm-2chan.dtbo \ + pwm-ir-tx.dtbo \ ++ pwm1.dtbo \ + qca7000.dtbo \ + qca7000-uart0.dtbo \ ++ ramoops.dtbo \ ++ ramoops-pi4.dtbo \ + rotary-encoder.dtbo \ + rpi-backlight.dtbo \ -+ rpi-cirrus-wm5102.dtbo \ -+ rpi-dac.dtbo \ -+ rpi-display.dtbo \ ++ rpi-codeczero.dtbo \ ++ rpi-dacplus.dtbo \ ++ rpi-dacpro.dtbo \ ++ rpi-digiampplus.dtbo \ + rpi-ft5406.dtbo \ + rpi-poe.dtbo \ + rpi-poe-plus.dtbo \ -+ rpi-proto.dtbo \ + rpi-sense.dtbo \ ++ rpi-sense-v2.dtbo \ + rpi-tv.dtbo \ -+ rpivid-v4l2.dtbo \ + rra-digidac1-wm8741-audio.dtbo \ + sainsmart18.dtbo \ + sc16is750-i2c.dtbo \ @@ -9970,6 +16193,7 @@ index 000000000000..6fcacdccb608 + sc16is752-spi1.dtbo \ + sdhost.dtbo \ + sdio.dtbo \ ++ sdio-pi5.dtbo \ + seeed-can-fd-hat-v1.dtbo \ + seeed-can-fd-hat-v2.dtbo \ + sh1106-spi.dtbo \ @@ -9987,14 +16211,20 @@ index 000000000000..6fcacdccb608 + spi1-2cs.dtbo \ + spi1-3cs.dtbo \ + spi2-1cs.dtbo \ ++ spi2-1cs-pi5.dtbo \ + spi2-2cs.dtbo \ ++ spi2-2cs-pi5.dtbo \ + spi2-3cs.dtbo \ + spi3-1cs.dtbo \ ++ spi3-1cs-pi5.dtbo \ + spi3-2cs.dtbo \ ++ spi3-2cs-pi5.dtbo \ + spi4-1cs.dtbo \ + spi4-2cs.dtbo \ + spi5-1cs.dtbo \ ++ spi5-1cs-pi5.dtbo \ + spi5-2cs.dtbo \ ++ spi5-2cs-pi5.dtbo \ + spi6-1cs.dtbo \ + spi6-2cs.dtbo \ + ssd1306.dtbo \ @@ -10007,11 +16237,17 @@ index 000000000000..6fcacdccb608 + tc358743-audio.dtbo \ + tinylcd35.dtbo \ + tpm-slb9670.dtbo \ ++ tpm-slb9673.dtbo \ + uart0.dtbo \ ++ uart0-pi5.dtbo \ + uart1.dtbo \ ++ uart1-pi5.dtbo \ + uart2.dtbo \ ++ uart2-pi5.dtbo \ + uart3.dtbo \ ++ uart3-pi5.dtbo \ + uart4.dtbo \ ++ uart4-pi5.dtbo \ + uart5.dtbo \ + udrc.dtbo \ + ugreen-dabboard.dtbo \ @@ -10020,19 +16256,32 @@ index 000000000000..6fcacdccb608 + vc4-fkms-v3d.dtbo \ + vc4-fkms-v3d-pi4.dtbo \ + vc4-kms-dpi-generic.dtbo \ ++ vc4-kms-dpi-hyperpixel2r.dtbo \ ++ vc4-kms-dpi-hyperpixel4.dtbo \ ++ vc4-kms-dpi-hyperpixel4sq.dtbo \ + vc4-kms-dpi-panel.dtbo \ + vc4-kms-dsi-7inch.dtbo \ ++ vc4-kms-dsi-generic.dtbo \ ++ vc4-kms-dsi-ili9881-5inch.dtbo \ ++ vc4-kms-dsi-ili9881-7inch.dtbo \ + vc4-kms-dsi-lt070me05000.dtbo \ + vc4-kms-dsi-lt070me05000-v2.dtbo \ ++ vc4-kms-dsi-waveshare-panel.dtbo \ + vc4-kms-kippah-7inch.dtbo \ + vc4-kms-v3d.dtbo \ + vc4-kms-v3d-pi4.dtbo \ ++ vc4-kms-v3d-pi5.dtbo \ + vc4-kms-vga666.dtbo \ + vga666.dtbo \ + vl805.dtbo \ + w1-gpio.dtbo \ ++ w1-gpio-pi5.dtbo \ + w1-gpio-pullup.dtbo \ ++ w1-gpio-pullup-pi5.dtbo \ + w5500.dtbo \ ++ watterott-display.dtbo \ ++ waveshare-can-fd-hat-mode-a.dtbo \ ++ waveshare-can-fd-hat-mode-b.dtbo \ + wittypi.dtbo \ + wm8960-soundcard.dtbo + @@ -10043,10 +16292,10 @@ index 000000000000..6fcacdccb608 +clean-files := *.dtbo diff --git a/arch/arm/boot/dts/overlays/README b/arch/arm/boot/dts/overlays/README new file mode 100644 -index 000000000000..3a0961540427 +index 000000000000..cca16ab81f9e --- /dev/null +++ b/arch/arm/boot/dts/overlays/README -@@ -0,0 +1,3861 @@ +@@ -0,0 +1,5346 @@ +Introduction +============ + @@ -10193,15 +16442,58 @@ index 000000000000..3a0961540427 + See /sys/kernel/debug/raspberrypi_axi_monitor + for the results. + -+ cam0_reg Enables CAM 0 regulator. CM1 & 3 only. ++ bdaddr Set an alternative Bluetooth address (BDADDR). ++ The value should be a 6-byte hexadecimal value, ++ with or without colon separators, written least- ++ significant-byte first. For example, ++ bdaddr=06:05:04:03:02:01 ++ will set the BDADDR to 01:02:03:04:05:06. + -+ cam0_reg_gpio Set GPIO for CAM 0 regulator. Default 30. -+ CM1 & 3 only. ++ button_debounce Set the debounce delay (in ms) on the power/ ++ shutdown button (default 50ms) + -+ cam1_reg Enables CAM 1 regulator. CM1 & 3 only. ++ cam0_reg Enables CAM 0 regulator. ++ Only required on CM1 & 3. + -+ cam1_reg_gpio Set GPIO for CAM 1 regulator. Default 2. -+ CM1 & 3 only. ++ cam0_reg_gpio Set GPIO for CAM 0 regulator. ++ Default 31 on CM1, 3, and 4S. ++ Default of GPIO expander 5 on CM4, but override ++ switches to normal GPIO. ++ ++ cam1_reg Enables CAM 1 regulator. ++ Only required on CM1 & 3. ++ ++ cam1_reg_gpio Set GPIO for CAM 1 regulator. ++ Default 3 on CM1, 3, and 4S. ++ Default of GPIO expander 5 on CM4, but override ++ switches to normal GPIO. ++ ++ cooling_fan Enables the Pi 5 cooling fan (enabled ++ automatically by the firmware) ++ ++ drm_fb0_rp1_dpi Assign /dev/fb0 to the RP1 DPI output ++ ++ drm_fb0_rp1_dsi0 Assign /dev/fb0 to the RP1 DSI0 output ++ ++ drm_fb0_rp1_dsi1 Assign /dev/fb0 to the RP1 DSI1 output ++ ++ drm_fb0_vc4 Assign /dev/fb0 to the vc4 outputs ++ ++ drm_fb1_rp1_dpi Assign /dev/fb1 to the RP1 DPI output ++ ++ drm_fb1_rp1_dsi0 Assign /dev/fb1 to the RP1 DSI0 output ++ ++ drm_fb1_rp1_dsi1 Assign /dev/fb1 to the RP1 DSI1 output ++ ++ drm_fb1_vc4 Assign /dev/fb1 to the vc4 outputs ++ ++ drm_fb2_rp1_dpi Assign /dev/fb2 to the RP1 DPI output ++ ++ drm_fb2_rp1_dsi0 Assign /dev/fb2 to the RP1 DSI0 output ++ ++ drm_fb2_rp1_dsi1 Assign /dev/fb2 to the RP1 DSI1 output ++ ++ drm_fb2_vc4 Assign /dev/fb2 to the vc4 outputs + + eee Enable Energy Efficient Ethernet support for + compatible devices (default "on"). See also @@ -10213,7 +16505,7 @@ index 000000000000..3a0961540427 + 0 means never downshift (default 2). Pi3B+ only. + + eth_led0 Set mode of LED0 - amber on Pi3B+ (default "1"), -+ green on Pi4 (default "0"). ++ green on Pi4/5 (default "0"). + The legal values are: + + Pi3B+ @@ -10223,7 +16515,7 @@ index 000000000000..3a0961540427 + 4=link100/1000/activity 5=link10/1000/activity + 6=link10/100/activity 14=off 15=on + -+ Pi4 ++ Pi4/5 + + 0=Speed/Activity 1=Speed + 2=Flash activity 3=FDX @@ -10232,40 +16524,108 @@ index 000000000000..3a0961540427 + 8=Link 9=Activity + + eth_led1 Set mode of LED1 - green on Pi3B+ (default "6"), -+ amber on Pi4 (default "8"). See eth_led0 for ++ amber on Pi4/5 (default "8"). See eth_led0 for + legal values. + + eth_max_speed Set the maximum speed a link is allowed + to negotiate. Legal values are 10, 100 and + 1000 (default 1000). Pi3B+ only. + ++ fan_temp0 Temperature threshold (in millicelcius) for ++ 1st cooling level (default 50000). Pi5 only. ++ fan_temp0_hyst Temperature hysteresis (in millicelcius) for ++ 1st cooling level (default 5000). Pi5 only. ++ fan_temp0_speed Fan PWM setting for 1st cooling level (0-255, ++ default 75). Pi5 only. ++ fan_temp1 Temperature threshold (in millicelcius) for ++ 2nd cooling level (default 60000). Pi5 only. ++ fan_temp1_hyst Temperature hysteresis (in millicelcius) for ++ 2nd cooling level (default 5000). Pi5 only. ++ fan_temp1_speed Fan PWM setting for 2nd cooling level (0-255, ++ default 125). Pi5 only. ++ fan_temp2 Temperature threshold (in millicelcius) for ++ 3rd cooling level (default 67500). Pi5 only. ++ fan_temp2_hyst Temperature hysteresis (in millicelcius) for ++ 3rd cooling level (default 5000). Pi5 only. ++ fan_temp2_speed Fan PWM setting for 3rd cooling level (0-255, ++ default 175). Pi5 only. ++ fan_temp3 Temperature threshold (in millicelcius) for ++ 4th cooling level (default 75000). Pi5 only. ++ fan_temp3_hyst Temperature hysteresis (in millicelcius) for ++ 4th cooling level (default 5000). Pi5 only. ++ fan_temp3_speed Fan PWM setting for 4th cooling level (0-255, ++ default 250). Pi5 only. ++ ++ hdmi Set to "off" to disable the HDMI interface ++ (default "on") ++ ++ i2c An alias for i2c_arm ++ + i2c_arm Set to "on" to enable the ARM's i2c interface + (default "off") + ++ i2c_arm_baudrate Set the baudrate of the ARM's i2c interface ++ (default "100000") ++ ++ i2c_baudrate An alias for i2c_arm_baudrate ++ ++ i2c_csi_dsi Set to "on" to enable the i2c_csi_dsi interface ++ ++ i2c_csi_dsi0 Set to "on" to enable the i2c_csi_dsi0 interface ++ ++ i2c_csi_dsi1 Set to "on" to enable the i2c_csi_dsi1 interface ++ + i2c_vc Set to "on" to enable the i2c interface + usually reserved for the VideoCore processor + (default "off") + -+ i2c An alias for i2c_arm -+ -+ i2c_arm_baudrate Set the baudrate of the ARM's i2c interface -+ (default "100000") -+ + i2c_vc_baudrate Set the baudrate of the VideoCore i2c interface + (default "100000") + -+ i2c_baudrate An alias for i2c_arm_baudrate -+ + i2s Set to "on" to enable the i2s interface + (default "off") + -+ krnbt Set to "on" to enable autoprobing of Bluetooth ++ i2s_dma4 Use to enable 40-bit DMA on the i2s interface ++ (the assigned value doesn't matter) ++ (2711 only) ++ ++ krnbt Set to "off" to disable autoprobing of Bluetooth + driver without need of hciattach/btattach -+ (default "off") ++ (default "on") + + krnbt_baudrate Set the baudrate of the PL011 UART when used + with krnbt=on + ++ nvme Alias for "pciex1" (2712 only) ++ ++ nvmem_cust_rw Allow read/write access to customer otp ++ ++ nvmem_mac_rw Allow read/write access to mac addresses otp ++ ++ nvmem_priv_rw Allow read/write access to customer private otp ++ ++ pcie Set to "off" to disable the PCIe interface ++ (default "on") ++ (2711 only, but not applicable on CM4S) ++ N.B. USB-A ports on 4B are subsequently disabled ++ ++ pcie_tperst_clk_ms Add N milliseconds between PCIe reference clock ++ activation and PERST# deassertion ++ (CM4 and 2712, default "0") ++ ++ pciex1 Set to "on" to enable the external PCIe link ++ (2712 only, default "off") ++ ++ pciex1_gen Sets the PCIe "GEN"/speed for the external PCIe ++ link (2712 only, default "2") ++ ++ pciex1_no_l0s Set to "on" to disable ASPM L0s on the external ++ PCIe link for devices that have broken ++ implementations (2712 only, default "off") ++ ++ pciex1_tperst_clk_ms Alias for pcie_tperst_clk_ms ++ (2712 only, default "0") ++ + spi Set to "on" to enable the spi interfaces + (default "off") + @@ -10276,6 +16636,22 @@ index 000000000000..3a0961540427 + random Set to "on" to enable the hardware random + number generator (default "on") + ++ rtc Set to "off" to disable the onboard Real Time ++ Clock (2712 only, default "on") ++ ++ rtc_bbat_vchg Set the RTC backup battery charging voltage in ++ microvolts. If set to 0 or not specified, the ++ trickle charger is disabled. ++ (2712 only, default "0") ++ ++ sd Set to "off" to disable the SD card (or eMMC on ++ non-lite SKU of CM4). ++ (default "on") ++ ++ sd_cqe Use to enable Command Queueing on the SD ++ interface for faster Class A2 card performance ++ (Pi 5 only, default "off") ++ + sd_overclock Clock (in MHz) to use when the MMC framework + requests 50MHz + @@ -10296,18 +16672,30 @@ index 000000000000..3a0961540427 + sdio_overclock Clock (in MHz) to use when the MMC framework + requests 50MHz for the SDIO/WLAN interface. + ++ suspend Make the power button trigger a suspend rather ++ than a power-off (2712 only, default "off") ++ + tx_lpi_timer Set the delay in microseconds between going idle + and entering the low power state (default 600). + Requires EEE to be enabled - see "eee". + + uart0 Set to "off" to disable uart0 (default "on") + ++ uart0_console Move the kernel boot console to UART0 on pins ++ 6, 8 and 10 of the 40-way header (2712 only, ++ default "off") ++ + uart1 Set to "on" or "off" to enable or disable uart1 + (default varies) + + watchdog Set to "on" to enable the hardware watchdog + (default "off") + ++ wifiaddr Set an alternative WiFi MAC address. ++ The value should be a 6-byte hexadecimal value, ++ with or without colon separators, written in the ++ natural (big-endian) order. ++ + act_led_trigger Choose which activity the LED tracks. + Use "heartbeat" for a nice load indicator. + (default "mmc") @@ -10437,6 +16825,16 @@ index 000000000000..3a0961540427 + cha_gain Set the gain of the Programmable Gain + Amplifier for this channel. (Default 1 sets the + full scale of the channel to 4.096 Volts) ++ i2c0 Choose the I2C0 bus on GPIOs 0&1 ++ i2c_csi_dsi Choose the I2C0 bus on GPIOs 44&45 ++ i2c3 Choose the I2C3 bus (configure with the i2c3 ++ overlay - BCM2711 only) ++ i2c4 Choose the I2C4 bus (configure with the i2c4 ++ overlay - BCM2711 only) ++ i2c5 Choose the I2C5 bus (configure with the i2c5 ++ overlay - BCM2711 only) ++ i2c6 Choose the I2C6 bus (configure with the i2c6 ++ overlay - BCM2711 only) + + Channel parameters can be set for each enabled channel. + A maximum of 4 channels can be enabled (letters a thru d). @@ -10631,6 +17029,38 @@ index 000000000000..3a0961540427 +Params: + + ++Name: arducam-64mp ++Info: Arducam 64MP camera module. ++ Uses Unicam 1, which is the standard camera connector on most Pi ++ variants. ++Load: dtoverlay=arducam-64mp,= ++Params: rotation Mounting rotation of the camera sensor (0 or ++ 180, default 0) ++ orientation Sensor orientation (0 = front, 1 = rear, ++ 2 = external, default external) ++ media-controller Configure use of Media Controller API for ++ configuring the sensor (default on) ++ cam0 Adopt the default configuration for CAM0 on a ++ Compute Module (CSI0, i2c_vc, and cam0_reg). ++ vcm Select lens driver state. Default is enabled, ++ but vcm=off will disable. ++ ++ ++Name: arducam-pivariety ++Info: Arducam Pivariety camera module. ++ Uses Unicam 1, which is the standard camera connector on most Pi ++ variants. ++Load: dtoverlay=arducam-pivariety,= ++Params: rotation Mounting rotation of the camera sensor (0 or ++ 180, default 0) ++ orientation Sensor orientation (0 = front, 1 = rear, ++ 2 = external, default external) ++ media-controller Configure use of Media Controller API for ++ configuring the sensor (default on) ++ cam0 Adopt the default configuration for CAM0 on a ++ Compute Module (CSI0, i2c_vc, and cam0_reg). ++ ++ +Name: at86rf233 +Info: Configures the Atmel AT86RF233 802.15.4 low-power WPAN transceiver, + connected to spi0.0 @@ -10650,6 +17080,12 @@ index 000000000000..3a0961540427 + is paused or stopped (default off) + + ++Name: audioinjector-bare-i2s ++Info: Configures the audioinjector.net audio bare i2s soundcard ++Load: dtoverlay=audioinjector-bare-i2s ++Params: ++ ++ +Name: audioinjector-isolated-soundcard +Info: Configures the audioinjector.net isolated soundcard +Load: dtoverlay=audioinjector-isolated-soundcard @@ -10681,10 +17117,14 @@ index 000000000000..3a0961540427 +Load: dtoverlay=audremap,= +Params: swap_lr Reverse the channel allocation, which will also + swap the audio jack outputs (default off) -+ enable_jack Don't switch off the audio jack output -+ (default off) ++ enable_jack Don't switch off the audio jack output. Does ++ nothing on BCM2711 (default off) + pins_12_13 Select GPIOs 12 & 13 (default) + pins_18_19 Select GPIOs 18 & 19 ++ pins_40_41 Select GPIOs 40 & 41 (not available on CM4, used ++ for other purposes) ++ pins_40_45 Select GPIOs 40 & 45 (don't use on BCM2711 - the ++ pins are on different controllers) + + +Name: balena-fin @@ -10694,11 +17134,125 @@ index 000000000000..3a0961540427 +Params: + + ++Name: bcm2712d0 ++Info: Overlay encapsulating the BCM2712 C0->D0 differences ++Load: dtoverlay=bcm2712d0 ++Params: ++ ++ +Name: bmp085_i2c-sensor +Info: This overlay is now deprecated - see i2c-sensor +Load: + + ++Name: camera-mux-2port ++Info: Configures a 2 port camera multiplexer ++ Note that currently ALL IMX290 modules share a common clock, therefore ++ all modules will need to have the same clock frequency. ++Load: dtoverlay=camera-mux-2port,= ++Params: cam0-arducam-64mp Select Arducam64MP for camera on port 0 ++ cam0-imx219 Select IMX219 for camera on port 0 ++ cam0-imx258 Select IMX258 for camera on port 0 ++ cam0-imx290 Select IMX290 for camera on port 0 ++ cam0-imx477 Select IMX477 for camera on port 0 ++ cam0-imx519 Select IMX519 for camera on port 0 ++ cam0-imx708 Select IMX708 for camera on port 0 ++ cam0-ov2311 Select OV2311 for camera on port 0 ++ cam0-ov5647 Select OV5647 for camera on port 0 ++ cam0-ov64a40 Select OV64A40 for camera on port 0 ++ cam0-ov7251 Select OV7251 for camera on port 0 ++ cam0-ov9281 Select OV9281 for camera on port 0 ++ cam0-imx290-clk-freq Set clock frequency for an IMX290 on port 0 ++ cam1-arducam-64mp Select Arducam64MP for camera on port 1 ++ cam1-imx219 Select IMX219 for camera on port 1 ++ cam1-imx258 Select IMX258 for camera on port 1 ++ cam1-imx290 Select IMX290 for camera on port 1 ++ cam1-imx477 Select IMX477 for camera on port 1 ++ cam1-imx519 Select IMX519 for camera on port 1 ++ cam1-imx708 Select IMX708 for camera on port 1 ++ cam1-ov2311 Select OV2311 for camera on port 1 ++ cam1-ov5647 Select OV5647 for camera on port 1 ++ cam1-ov64a40 Select OV64A40 for camera on port 1 ++ cam1-ov7251 Select OV7251 for camera on port 1 ++ cam1-ov9281 Select OV9281 for camera on port 1 ++ cam1-imx290-clk-freq Set clock frequency for an IMX290 on port 1 ++ cam0-sync-source Set camera on port 0 as vsync source ++ cam0-sync-sink Set camera on port 0 as vsync sink ++ cam1-sync-source Set camera on port 1 as vsync source ++ cam1-sync-sink Set camera on port 1 as vsync sink ++ ++ cam0 Connect the mux to CAM0 port (default is CAM1) ++ ++ ++Name: camera-mux-4port ++Info: Configures a 4 port camera multiplexer ++ Note that currently ALL IMX290 modules share a common clock, therefore ++ all modules will need to have the same clock frequency. ++Load: dtoverlay=camera-mux-4port,= ++Params: cam0-arducam-64mp Select Arducam64MP for camera on port 0 ++ cam0-imx219 Select IMX219 for camera on port 0 ++ cam0-imx258 Select IMX258 for camera on port 0 ++ cam0-imx290 Select IMX290 for camera on port 0 ++ cam0-imx477 Select IMX477 for camera on port 0 ++ cam0-imx519 Select IMX519 for camera on port 0 ++ cam0-imx708 Select IMX708 for camera on port 0 ++ cam0-ov2311 Select OV2311 for camera on port 0 ++ cam0-ov5647 Select OV5647 for camera on port 0 ++ cam0-ov64a40 Select OV64A40 for camera on port 0 ++ cam0-ov7251 Select OV7251 for camera on port 0 ++ cam0-ov9281 Select OV9281 for camera on port 0 ++ cam0-imx290-clk-freq Set clock frequency for an IMX290 on port 0 ++ cam1-arducam-64mp Select Arducam64MP for camera on port 1 ++ cam1-imx219 Select IMX219 for camera on port 1 ++ cam1-imx258 Select IMX258 for camera on port 1 ++ cam1-imx290 Select IMX290 for camera on port 1 ++ cam1-imx477 Select IMX477 for camera on port 1 ++ cam1-imx519 Select IMX519 for camera on port 1 ++ cam1-imx708 Select IMX708 for camera on port 1 ++ cam1-ov2311 Select OV2311 for camera on port 1 ++ cam1-ov5647 Select OV5647 for camera on port 1 ++ cam1-ov64a40 Select OV64A40 for camera on port 1 ++ cam1-ov7251 Select OV7251 for camera on port 1 ++ cam1-ov9281 Select OV9281 for camera on port 1 ++ cam1-imx290-clk-freq Set clock frequency for an IMX290 on port 1 ++ cam2-arducam-64mp Select Arducam64MP for camera on port 2 ++ cam2-imx219 Select IMX219 for camera on port 2 ++ cam2-imx258 Select IMX258 for camera on port 2 ++ cam2-imx290 Select IMX290 for camera on port 2 ++ cam2-imx477 Select IMX477 for camera on port 2 ++ cam2-imx519 Select IMX519 for camera on port 2 ++ cam2-imx708 Select IMX708 for camera on port 2 ++ cam2-ov2311 Select OV2311 for camera on port 2 ++ cam2-ov5647 Select OV5647 for camera on port 2 ++ cam2-ov64a40 Select OV64A40 for camera on port 2 ++ cam2-ov7251 Select OV7251 for camera on port 2 ++ cam2-ov9281 Select OV9281 for camera on port 2 ++ cam2-imx290-clk-freq Set clock frequency for an IMX290 on port 2 ++ cam3-arducam-64mp Select Arducam64MP for camera on port 3 ++ cam3-imx219 Select IMX219 for camera on port 3 ++ cam3-imx258 Select IMX258 for camera on port 3 ++ cam3-imx290 Select IMX290 for camera on port 3 ++ cam3-imx477 Select IMX477 for camera on port 3 ++ cam3-imx519 Select IMX519 for camera on port 3 ++ cam3-imx708 Select IMX708 for camera on port 3 ++ cam3-ov2311 Select OV2311 for camera on port 3 ++ cam3-ov5647 Select OV5647 for camera on port 3 ++ cam3-ov64a40 Select OV64A40 for camera on port 3 ++ cam3-ov7251 Select OV7251 for camera on port 3 ++ cam3-ov9281 Select OV9281 for camera on port 3 ++ cam3-imx290-clk-freq Set clock frequency for an IMX290 on port 3 ++ cam0-sync-source Set camera on port 0 as vsync source ++ cam0-sync-sink Set camera on port 0 as vsync sink ++ cam1-sync-source Set camera on port 1 as vsync source ++ cam1-sync-sink Set camera on port 1 as vsync sink ++ cam2-sync-source Set camera on port 2 as vsync source ++ cam2-sync-sink Set camera on port 2 as vsync sink ++ cam3-sync-source Set camera on port 3 as vsync source ++ cam3-sync-sink Set camera on port 3 as vsync sink ++ ++ cam0 Connect the mux to CAM0 port (default is CAM1) ++ ++ +Name: cap1106 +Info: Enables the ability to use the cap1106 touch sensor as a keyboard +Load: dtoverlay=cap1106,= @@ -10711,6 +17265,28 @@ index 000000000000..3a0961540427 +Params: + + ++Name: cirrus-wm5102 ++Info: Configures the Cirrus Logic Audio Card ++Load: dtoverlay=cirrus-wm5102 ++Params: ++ ++ ++Name: cm-swap-i2c0 ++Info: Largely for Compute Modules 1&3 where the original instructions for ++ adding a camera used GPIOs 0&1 for CAM1 and 28&29 for CAM0, whilst all ++ other platforms use 28&29 (or 44&45) for CAM1. ++ The default assignment through using this overlay is for ++ i2c0 to use 28&29, and i2c10 (aka i2c_csi_dsi) to use 28&29, but the ++ overrides allow this to be changed. ++Load: dtoverlay=cm-swap-i2c0,= ++Params: i2c0-gpio0 Use GPIOs 0&1 for i2c0 ++ i2c0-gpio28 Use GPIOs 28&29 for i2c0 (default) ++ i2c0-gpio44 Use GPIOs 44&45 for i2c0 ++ i2c10-gpio0 Use GPIOs 0&1 for i2c0 (default) ++ i2c10-gpio28 Use GPIOs 28&29 for i2c0 ++ i2c10-gpio44 Use GPIOs 44&45 for i2c0 ++ ++ +Name: cma +Info: Set custom CMA sizes, only use if you know what you are doing, might + clash with other overlays like vc4-fkms-v3d and vc4-kms-v3d. @@ -10728,12 +17304,27 @@ index 000000000000..3a0961540427 + cma-default Use upstream's default value + + ++Name: crystalfontz-cfa050_pi_m ++Info: Configures the Crystalfontz CFA050-PI-M series of Raspberry Pi CM4 ++ based modules using the CFA7201280A0_050Tx 7" TFT LCD displays, ++ with or without capacitive touch screen. ++ Requires use of vc4-kms-v3d. ++Load: dtoverlay=crystalfontz-cfa050_pi_m,= ++Params: captouch Enable capacitive touch display ++ ++ +Name: cutiepi-panel +Info: 8" TFT LCD display and touch panel used by cutiepi.io +Load: dtoverlay=cutiepi-panel +Params: + + ++Name: dacberry400 ++Info: Configures the dacberry400 add on soundcard ++Load: dtoverlay=dacberry400 ++Params: ++ ++ +Name: dht11 +Info: Overlay for the DHT11/DHT21/DHT22 humidity/temperature sensors + Also sometimes found with the part number(s) AM230x. @@ -10742,6 +17333,12 @@ index 000000000000..3a0961540427 + (default 4) + + ++Name: dionaudio-kiwi ++Info: Configures the Dion Audio KIWI STREAMER ++Load: dtoverlay=dionaudio-kiwi ++Params: ++ ++ +Name: dionaudio-loco +Info: Configures the Dion Audio LOCO DAC-AMP +Load: dtoverlay=dionaudio-loco @@ -10768,20 +17365,34 @@ index 000000000000..3a0961540427 + + +Name: disable-bt -+Info: Disable onboard Bluetooth on Pi 3B, 3B+, 3A+, 4B and Zero W, restoring -+ UART0/ttyAMA0 over GPIOs 14 & 15. -+ N.B. To disable the systemd service that initialises the modem so it -+ doesn't use the UART, use 'sudo systemctl disable hciuart'. ++Info: Disable onboard Bluetooth on Bluetooth-capable Raspberry Pis. On Pis ++ prior to Pi 5 this restores UART0/ttyAMA0 over GPIOs 14 & 15. +Load: dtoverlay=disable-bt +Params: + + ++Name: disable-bt-pi5 ++Info: See disable-bt ++ ++ ++Name: disable-emmc2 ++Info: Disable EMMC2 controller on BCM2711. ++ The allows the onboard EMMC storage on Compute Module 4 to be disabled ++ e.g. if a fault has occurred. ++Load: dtoverlay=disable-emmc2 ++Params: ++ ++ +Name: disable-wifi -+Info: Disable onboard WLAN on Pi 3B, 3B+, 3A+, 4B and Zero W. ++Info: Disable onboard WLAN on WiFi-capable Raspberry Pis. +Load: dtoverlay=disable-wifi +Params: + + ++Name: disable-wifi-pi5 ++Info: See disable-wifi ++ ++ +Name: dpi18 +Info: Overlay for a generic 18-bit DPI display + This uses GPIOs 0-21 (so no I2C, uart etc.), and activates the output @@ -10881,9 +17492,11 @@ index 000000000000..3a0961540427 + + +Name: edt-ft5406 -+Info: Overlay for the EDT FT5406 touchscreen on the CSI/DSI I2C interface. ++Info: Overlay for the EDT FT5406 touchscreen. + This works with the Raspberry Pi 7" touchscreen when not being polled + by the firmware. ++ By default the overlay uses the i2c_csi_dsi I2C interface, but this ++ can be overridden + You MUST use either "disable_touchscreen=1" or "ignore_lcd=1" in + config.txt to stop the firmware polling the touchscreen. +Load: dtoverlay=edt-ft5406,= @@ -10892,6 +17505,19 @@ index 000000000000..3a0961540427 + invx Touchscreen inverted x axis + invy Touchscreen inverted y axis + swapxy Touchscreen swapped x y axis ++ i2c0 Choose the I2C0 bus on GPIOs 0&1 ++ i2c1 Choose the I2C1 bus on GPIOs 2&3 ++ i2c3 Choose the I2C3 bus (configure with the i2c3 ++ overlay - BCM2711 only) ++ i2c4 Choose the I2C4 bus (configure with the i2c4 ++ overlay - BCM2711 only) ++ i2c5 Choose the I2C5 bus (configure with the i2c5 ++ overlay - BCM2711 only) ++ i2c6 Choose the I2C6 bus (configure with the i2c6 ++ overlay - BCM2711 only) ++ addr Sets the address for the touch controller. Note ++ that the device must be configured to use the ++ specified address. + + +Name: enc28j60 @@ -11060,6 +17686,26 @@ index 000000000000..3a0961540427 +Params: fsm_debug Enable debug logging (default off) + + ++Name: gc9a01 ++Info: Enables GalaxyCore's GC9A01 single chip driver based displays on ++ SPI0 as fb1, using GPIOs DC=25, RST=27 and BL=18 (physical ++ GPIO header pins 22, 13 and 12 respectively) in addition to the ++ SPI0 pins DIN=10, CLK=11 and CS=8 (physical GPIO header pins 19, ++ 23 and 24 respectively). ++Load: dtoverlay=gc9a01,= ++Params: speed Display SPI bus speed ++ ++ rotate Display rotation {0,90,180,270} ++ ++ width Width of the display ++ ++ height Height of the display ++ ++ fps Delay between frame updates ++ ++ debug Debug output level {0-7} ++ ++ +Name: ghost-amp +Info: An overlay for the Ghost amplifier. +Load: dtoverlay=ghost-amp,= @@ -11081,12 +17727,40 @@ index 000000000000..3a0961540427 +Params: + + ++Name: gpio-charger ++Info: This is a generic overlay for detecting charger with GPIO. ++Load: dtoverlay=gpio-charger,= ++Params: gpio GPIO pin to trigger on (default 4) ++ active_low When this is 1 (active low), a falling ++ edge generates a charging event and a ++ rising edge generates a discharging event. ++ When this is 0 (active high), this is ++ reversed. The default is 0 (active high) ++ gpio_pull Desired pull-up/down state (off, down, up) ++ Default is "down". ++ type Set a charger type for the pin. (Default: mains) ++ ++ +Name: gpio-fan +Info: Configure a GPIO pin to control a cooling fan. +Load: dtoverlay=gpio-fan,= +Params: gpiopin GPIO used to control the fan (default 12) + temp Temperature at which the fan switches on, in + millicelcius (default 55000) ++ hyst Temperature delta (in millicelcius) below ++ temp at which the fan will drop to minrpm ++ (default 10000) ++ ++ ++Name: gpio-hog ++Info: Activate a "hog" for a GPIO - request that the kernel configures it as ++ an output, driven low or high as indicated by the presence or absence ++ of the active_low parameter. Note that a hogged GPIO is not available ++ to other drivers or for gpioset/gpioget. ++Load: dtoverlay=gpio-hog,= ++Params: gpio GPIO pin to hog (default 26) ++ active_low If set, the hog drives the GPIO low (defaults ++ to off - the GPIO is driven high) + + +Name: gpio-ir @@ -11373,7 +18047,7 @@ index 000000000000..3a0961540427 + responsibility of the user to ensure that + the Digital volume control is set to a value + that does not result in clipping/distortion!) -+ slave Force DAC+ Pro into slave mode, using Pi as ++ slave Force AMP100 into slave mode, using Pi as + master for bit clock and frame clock. + leds_off If set to 'true' the onboard indicator LEDs + are switched off at all times. @@ -11384,12 +18058,52 @@ index 000000000000..3a0961540427 + Will be overwritten by ALSA user settings. + + ++Name: hifiberry-amp3 ++Info: Configures the HifiBerry Amp3 audio card ++Load: dtoverlay=hifiberry-amp3 ++Params: ++ ++ ++Name: hifiberry-amp4pro ++Info: Configures the HifiBerry AMP4 Pro audio card ++Load: dtoverlay=hifiberry-amp4pro,= ++Params: 24db_digital_gain Allow gain to be applied via the TAS5756 ++ Digital volume control. Enable with ++ "dtoverlay=hifiberry-amp4pro,24db_digital_gain" ++ (The default behaviour is that the Digital ++ volume control is limited to a maximum of ++ 0dB. ie. it can attenuate but not provide ++ gain. For most users, this will be desired ++ as it will prevent clipping. By appending ++ the 24dB_digital_gain parameter, the Digital ++ volume control will allow up to 24dB of ++ gain. If this parameter is enabled, it is the ++ responsibility of the user to ensure that ++ the Digital volume control is set to a value ++ that does not result in clipping/distortion!) ++ slave Force the amp into slave mode, using Pi as ++ master for bit clock and frame clock. ++ leds_off If set to 'true' the onboard indicator LEDs ++ are switched off at all times. ++ auto_mute If set to 'true' the amplifier is automatically ++ muted when it is not playing. ++ mute_ext_ctl The amplifier's HW mute control is enabled ++ in ALSA mixer and set to . ++ Will be overwritten by ALSA user settings. ++ ++ +Name: hifiberry-dac +Info: Configures the HifiBerry DAC audio cards +Load: dtoverlay=hifiberry-dac +Params: + + ++Name: hifiberry-dac8x ++Info: Configures the HifiBerry DAC8X audio cards (only on Pi5) ++Load: dtoverlay=hifiberry-dac8x ++Params: ++ ++ +Name: hifiberry-dacplus +Info: Configures the HifiBerry DAC+ audio card +Load: dtoverlay=hifiberry-dacplus,= @@ -11407,12 +18121,54 @@ index 000000000000..3a0961540427 + responsibility of the user to ensure that + the Digital volume control is set to a value + that does not result in clipping/distortion!) -+ slave Force DAC+ Pro into slave mode, using Pi as ++ slave Force DAC+ into slave mode, using Pi as + master for bit clock and frame clock. + leds_off If set to 'true' the onboard indicator LEDs + are switched off at all times. + + ++Name: hifiberry-dacplus-pro ++Info: Configures the HifiBerry DAC+ PRO audio card (onboard clocks) ++Load: dtoverlay=hifiberry-dacplus-pro,= ++Params: 24db_digital_gain Allow gain to be applied via the PCM512x codec ++ Digital volume control. Enable with ++ "dtoverlay=hifiberry-dacplus,24db_digital_gain" ++ (The default behaviour is that the Digital ++ volume control is limited to a maximum of ++ 0dB. ie. it can attenuate but not provide ++ gain. For most users, this will be desired ++ as it will prevent clipping. By appending ++ the 24dB_digital_gain parameter, the Digital ++ volume control will allow up to 24dB of ++ gain. If this parameter is enabled, it is the ++ responsibility of the user to ensure that ++ the Digital volume control is set to a value ++ that does not result in clipping/distortion!) ++ leds_off If set to 'true' the onboard indicator LEDs ++ are switched off at all times. ++ ++ ++Name: hifiberry-dacplus-std ++Info: Configures the HifiBerry DAC+ standard audio card (no onboard clocks) ++Load: dtoverlay=hifiberry-dacplus-std,= ++Params: 24db_digital_gain Allow gain to be applied via the PCM512x codec ++ Digital volume control. Enable with ++ "dtoverlay=hifiberry-dacplus,24db_digital_gain" ++ (The default behaviour is that the Digital ++ volume control is limited to a maximum of ++ 0dB. ie. it can attenuate but not provide ++ gain. For most users, this will be desired ++ as it will prevent clipping. By appending ++ the 24dB_digital_gain parameter, the Digital ++ volume control will allow up to 24dB of ++ gain. If this parameter is enabled, it is the ++ responsibility of the user to ensure that ++ the Digital volume control is set to a value ++ that does not result in clipping/distortion!) ++ leds_off If set to 'true' the onboard indicator LEDs ++ are switched off at all times. ++ ++ +Name: hifiberry-dacplusadc +Info: Configures the HifiBerry DAC+ADC audio card +Load: dtoverlay=hifiberry-dacplusadc,= @@ -11430,8 +18186,6 @@ index 000000000000..3a0961540427 + responsibility of the user to ensure that + the Digital volume control is set to a value + that does not result in clipping/distortion!) -+ slave Force DAC+ Pro into slave mode, using Pi as -+ master for bit clock and frame clock. + leds_off If set to 'true' the onboard indicator LEDs + are switched off at all times. + @@ -11478,7 +18232,7 @@ index 000000000000..3a0961540427 + + +Name: hifiberry-digi-pro -+Info: Configures the HifiBerry Digi+ Pro audio card ++Info: Configures the HifiBerry Digi+ Pro and Digi2 Pro audio card +Load: dtoverlay=hifiberry-digi-pro +Params: + @@ -11558,6 +18312,51 @@ index 000000000000..3a0961540427 +Params: + + ++Name: i2c-fan ++Info: Adds support for a number of I2C fan controllers ++Load: dtoverlay=i2c-fan,= ++Params: addr Sets the address for the fan controller. Note ++ that the device must be configured to use the ++ specified address. ++ ++ i2c0 Choose the I2C0 bus on GPIOs 0&1 ++ ++ i2c_csi_dsi Choose the I2C0 bus on GPIOs 44&45 ++ ++ i2c3 Choose the I2C3 bus (configure with the i2c3 ++ overlay - BCM2711 only) ++ ++ i2c4 Choose the I2C4 bus (configure with the i2c4 ++ overlay - BCM2711 only) ++ ++ i2c5 Choose the I2C5 bus (configure with the i2c5 ++ overlay - BCM2711 only) ++ ++ i2c6 Choose the I2C6 bus (configure with the i2c6 ++ overlay - BCM2711 only) ++ ++ minpwm PWM setting for the fan when the SoC is below ++ mintemp (range 0-255. default 0) ++ maxpwm PWM setting for the fan when the SoC is above ++ maxtemp (range 0-255. default 255) ++ midtemp Temperature (in millicelcius) at which the fan ++ begins to speed up (default 50000) ++ ++ midtemp_hyst Temperature delta (in millicelcius) below ++ mintemp at which the fan will drop to minrpm ++ (default 2000) ++ ++ maxtemp Temperature (in millicelcius) at which the fan ++ will be held at maxrpm (default 70000) ++ ++ maxtemp_hyst Temperature delta (in millicelcius) below ++ maxtemp at which the fan begins to slow down ++ (default 2000) ++ ++ emc2301 Select the Microchip EMC230x controller family ++ - EMC2301, EMC2302, EMC2303, EMC2305. ++ ++ +Name: i2c-gpio +Info: Adds support for software i2c controller on gpio pins +Load: dtoverlay=i2c-gpio,= @@ -11587,6 +18386,28 @@ index 000000000000..3a0961540427 + + addr Change I2C address of the device (default 0x70) + ++ base Set an explicit base value for the channel bus ++ numbers ++ ++ i2c0 Choose the I2C0 bus on GPIOs 0&1 ++ ++ i2c_csi_dsi Choose the I2C0 bus on GPIOs 44&45 ++ ++ i2c3 Choose the I2C3 bus (configure with the i2c3 ++ overlay - BCM2711 only) ++ ++ i2c4 Choose the I2C3 bus (configure with the i2c3 ++ overlay - BCM2711 only) ++ ++ i2c5 Choose the I2C5 bus (configure with the i2c4 ++ overlay - BCM2711 only) ++ ++ i2c6 Choose the I2C6 bus (configure with the i2c6 ++ overlay - BCM2711 only) ++ ++ disconnect_on_idle Force the mux to disconnect all child buses ++ after every transaction. ++ + +[ The i2c-mux-pca9548a overlay has been deleted. See i2c-mux. ] + @@ -11595,6 +18416,16 @@ index 000000000000..3a0961540427 +Info: Adds support for an NXP PCA9685A I2C PWM controller on i2c_arm +Load: dtoverlay=i2c-pwm-pca9685a,= +Params: addr I2C address of PCA9685A (default 0x40) ++ i2c0 Choose the I2C0 bus on GPIOs 0&1 ++ i2c_csi_dsi Choose the I2C0 bus on GPIOs 44&45 ++ i2c3 Choose the I2C3 bus (configure with the i2c3 ++ overlay - BCM2711 only) ++ i2c4 Choose the I2C3 bus (configure with the i2c3 ++ overlay - BCM2711 only) ++ i2c5 Choose the I2C5 bus (configure with the i2c4 ++ overlay - BCM2711 only) ++ i2c6 Choose the I2C6 bus (configure with the i2c6 ++ overlay - BCM2711 only) + + +Name: i2c-rtc @@ -11624,6 +18455,8 @@ index 000000000000..3a0961540427 + + pcf2129 Select the PCF2129 device + ++ pcf2131 Select the PCF2131 device ++ + pcf85063 Select the PCF85063 device + + pcf85063a Select the PCF85063A device @@ -11638,6 +18471,10 @@ index 000000000000..3a0961540427 + + rv3028 Select the Micro Crystal RV3028 device + ++ rv3032 Select the Micro Crystal RV3032 device ++ ++ rv8803 Select the Micro Crystal RV8803 device ++ + sd3078 Select the ZXW Shenzhen whwave SD3078 device + + s35390a Select the ABLIC S35390A device @@ -11646,6 +18483,18 @@ index 000000000000..3a0961540427 + + i2c_csi_dsi Choose the I2C0 bus on GPIOs 44&45 + ++ i2c3 Choose the I2C3 bus (configure with the i2c3 ++ overlay - BCM2711 only) ++ ++ i2c4 Choose the I2C3 bus (configure with the i2c3 ++ overlay - BCM2711 only) ++ ++ i2c5 Choose the I2C5 bus (configure with the i2c4 ++ overlay - BCM2711 only) ++ ++ i2c6 Choose the I2C6 bus (configure with the i2c6 ++ overlay - BCM2711 only) ++ + addr Sets the address for the RTC. Note that the + device must be configured to use the specified + address. @@ -11657,13 +18506,21 @@ index 000000000000..3a0961540427 + "schottky" (ABx80x and RV1805 only) + + trickle-resistor-ohms Resistor value for trickle charge (DS1339, -+ ABx80x, RV1805, RV3028) ++ ABx80x, BQ32000, RV1805, RV3028, RV3032) ++ ++ trickle-voltage-mv Charge pump voltage for trickle charge (RV3032) + + wakeup-source Specify that the RTC can be used as a wakeup + source + + backup-switchover-mode Backup power supply switch mode. Must be 0 for -+ off or 1 for Vdd < VBackup (RV3028 only) ++ "Switchover disabled", 1 for "Direct Switching" ++ (if Vdd < VBackup), 2 for "Standby ++ Mode" (if Vdd < Vbackup, ++ does not draw current) or 3 for ++ "Level Switching" (if Vdd < Vbackup ++ and Vdd < Vddsw and Vbackup > Vddsw) ++ (RV3028, RV3032) + + +Name: i2c-rtc-gpio @@ -11694,6 +18551,8 @@ index 000000000000..3a0961540427 + + pcf2129 Select the PCF2129 device + ++ pcf2131 Select the PCF2131 device ++ + pcf85063 Select the PCF85063 device + + pcf85063a Select the PCF85063A device @@ -11708,6 +18567,10 @@ index 000000000000..3a0961540427 + + rv3028 Select the Micro Crystal RV3028 device + ++ rv3032 Select the Micro Crystal RV3032 device ++ ++ rv8803 Select the Micro Crystal RV8803 device ++ + sd3078 Select the ZXW Shenzhen whwave SD3078 device + + s35390a Select the ABLIC S35390A device @@ -11723,13 +18586,21 @@ index 000000000000..3a0961540427 + "schottky" (ABx80x and RV1805 only) + + trickle-resistor-ohms Resistor value for trickle charge (DS1339, -+ ABx80x, RV1805, RV3028) ++ ABx80x, BQ32000, RV1805, RV3028, RV3032) ++ ++ trickle-voltage-mv Charge pump voltage for trickle charge (RV3032) + + wakeup-source Specify that the RTC can be used as a wakeup + source + + backup-switchover-mode Backup power supply switch mode. Must be 0 for -+ off or 1 for Vdd < VBackup (RV3028 only) ++ "Switchover disabled", 1 for "Direct Switching" ++ (if Vdd < VBackup), 2 for "Standby ++ Mode" (if Vdd < Vbackup, ++ does not draw current) or 3 for ++ "Level Switching" (if Vdd < Vbackup ++ and Vdd < Vddsw and Vbackup > Vddsw) ++ (RV3028, RV3032) + + i2c_gpio_sda GPIO used for I2C data (default "23") + @@ -11743,9 +18614,17 @@ index 000000000000..3a0961540427 +Info: Adds support for a number of I2C barometric pressure, temperature, + light level and chemical sensors on i2c_arm +Load: dtoverlay=i2c-sensor,= -+Params: addr Set the address for the BH1750, BME280, BME680, -+ BMP280, CCS811, DS1621, HDC100X, LM75, SHT3x or -+ TMP102 ++Params: addr Set the address for the ADT7410, BH1750, BME280, ++ BME680, BMP280, BMP380, CCS811, DS1621, HDC100X, ++ JC42, LM75, MCP980x, MPU6050, MPU9250, MS5637, ++ MS5803, MS5805, MS5837, MS8607, SHT3x or TMP102 ++ ++ adt7410 Select the Analog Devices ADT7410 and ADT7420 ++ temperature sensors ++ Valid address 0x48-0x4b, default 0x48 ++ ++ aht10 Select the Aosong AHT10 temperature and humidity ++ sensor + + bh1750 Select the Rohm BH1750 ambient light sensor + Valid addresses 0x23 or 0x5c, default 0x23 @@ -11763,6 +18642,12 @@ index 000000000000..3a0961540427 + bmp280 Select the Bosch Sensortronic BMP280 + Valid addresses 0x76-0x77, default 0x76 + ++ bmp380 Select the Bosch Sensortronic BMP380 ++ Valid addresses 0x76-0x77, default 0x76 ++ ++ bno055 Select the Bosch Sensortronic BNO055 IMU ++ Valid address 0x28-0x29, default 0x29 ++ + ccs811 Select the AMS CCS811 digital gas sensor + Valid addresses 0x5a-0x5b, default 0x5b + @@ -11774,8 +18659,17 @@ index 000000000000..3a0961540427 + + htu21 Select the HTU21 temperature and humidity sensor + -+ int_pin Set the GPIO to use for interrupts (max30102 -+ only) ++ int_pin Set the GPIO to use for interrupts (max30102, ++ mpu6050 and mpu9250 only) ++ ++ jc42 Select any of the many JEDEC JC42.4-compliant ++ temperature sensors, including: ++ ADT7408, AT30TS00, CAT34TS02, CAT6095, ++ MAX6604, MCP9804, MCP9805, MCP9808, ++ MCP98242, MCP98243, MCP98244, MCP9843, ++ SE97, SE98, STTS424(E), STTS2002, STTS3000, ++ TSE2002, TSE2004, TS3000, and TS3001. ++ The default address is 0x18. + + lm75 Select the Maxim LM75 temperature sensor + Valid addresses 0x48-0x4f, default 0x4f @@ -11788,8 +18682,47 @@ index 000000000000..3a0961540427 + max30102 Select the Maxim Integrated MAX30102 heart-rate + and blood-oxygen sensor + -+ sht3x Select the Sensiron SHT3x temperature and -+ humidity sensor. Valid addresses 0x44-0x45, ++ mcp980x Select the Maxim MCP980x range of temperature ++ sensors (i.e. MCP9800, MCP9801, MCP9802 and ++ MCP9803). N.B. For MCP9804, MCP9805 and MCP9808, ++ use the "jc42" option. ++ Valid addresses are 0x18-0x1f (default 0x18) ++ ++ mpu6050 Select the InvenSense MPU6050 IMU. Valid ++ valid addresses are 0x68 and 0x69 (default 0x68) ++ ++ mpu9250 Select the InvenSense MPU9250 IMU. Valid ++ valid addresses are 0x68 and 0x69 (default 0x68) ++ ++ ms5637 Select the Measurement Specialities MS5637 ++ pressure and temperature sensor. ++ ++ ms5803 Select the Measurement Specialities MS5803 ++ pressure and temperature sensor. ++ ++ ms5805 Select the Measurement Specialities MS5805 ++ pressure and temperature sensor. ++ ++ ms5837 Select the Measurement Specialities MS5837 ++ pressure and temperature sensor. ++ ++ ms8607 Select the Measurement Specialities MS8607 ++ pressure and temperature sensor. ++ ++ no_timeout Disable the SMBUS timeout. N.B. Only supported ++ by some jc42 devices - using with an ++ incompatible device can stop it from being ++ activated. ++ ++ reset_pin GPIO to be used to reset the device (bno055 ++ only, disabled by default) ++ ++ sht3x Select the Sensirion SHT3x temperature and ++ humidity sensors. Valid addresses 0x44-0x45, ++ default 0x44 ++ ++ sht4x Select the Sensirion SHT4x temperature and ++ humidity sensors. Valid addresses 0x44-0x45, + default 0x44 + + si7020 Select the Silicon Labs Si7013/20/21 humidity/ @@ -11810,6 +18743,22 @@ index 000000000000..3a0961540427 + veml6070 Select the Vishay VEML6070 ultraviolet light + sensor + ++ i2c0 Choose the I2C0 bus on GPIOs 0&1 ++ ++ i2c_csi_dsi Choose the I2C0 bus on GPIOs 44&45 ++ ++ i2c3 Choose the I2C3 bus (configure with the i2c3 ++ overlay - BCM2711 only) ++ ++ i2c4 Choose the I2C3 bus (configure with the i2c3 ++ overlay - BCM2711 only) ++ ++ i2c5 Choose the I2C5 bus (configure with the i2c4 ++ overlay - BCM2711 only) ++ ++ i2c6 Choose the I2C6 bus (configure with the i2c6 ++ overlay - BCM2711 only) ++ + +Name: i2c0 +Info: Change i2c0 pin usage. Not all pin combinations are usable on all @@ -11836,6 +18785,15 @@ index 000000000000..3a0961540427 +Load: + + ++Name: i2c0-pi5 ++Info: Enable i2c0 (Pi 5 only) ++Load: dtoverlay=i2c0-pi5,= ++Params: pins_0_1 Use GPIOs 0 and 1 (default) ++ pins_8_9 Use GPIOs 8 and 9 ++ baudrate Set the baudrate for the interface (default ++ "100000") ++ ++ +Name: i2c1 +Info: Change i2c1 pin usage. Not all pin combinations are usable on all + platforms - platforms other then Compute Modules can only use this @@ -11852,6 +18810,24 @@ index 000000000000..3a0961540427 +Load: + + ++Name: i2c1-pi5 ++Info: Enable i2c1 (Pi 5 only) ++Load: dtoverlay=i2c1-pi5,= ++Params: pins_2_3 Use GPIOs 2 and 3 (default) ++ pins_10_11 Use GPIOs 10 and 11 ++ baudrate Set the baudrate for the interface (default ++ "100000") ++ ++ ++Name: i2c2-pi5 ++Info: Enable i2c2 (Pi 5 only) ++Load: dtoverlay=i2c2-pi5,= ++Params: pins_4_5 Use GPIOs 4 and 5 (default) ++ pins_12_13 Use GPIOs 12 and 13 ++ baudrate Set the baudrate for the interface (default ++ "100000") ++ ++ +Name: i2c3 +Info: Enable the i2c3 bus. BCM2711 only. +Load: dtoverlay=i2c3, @@ -11861,6 +18837,16 @@ index 000000000000..3a0961540427 + "100000") + + ++Name: i2c3-pi5 ++Info: Enable i2c3 (Pi 5 only) ++Load: dtoverlay=i2c3-pi5,= ++Params: pins_6_7 Use GPIOs 6 and 7 (default) ++ pins_14_15 Use GPIOs 14 and 15 ++ pins_22_23 Use GPIOs 22 and 23 ++ baudrate Set the baudrate for the interface (default ++ "100000") ++ ++ +Name: i2c4 +Info: Enable the i2c4 bus. BCM2711 only. +Load: dtoverlay=i2c4, @@ -11888,6 +18874,12 @@ index 000000000000..3a0961540427 + "100000") + + ++Name: i2s-dac ++Info: Configures any passive I2S DAC soundcard. ++Load: dtoverlay=i2s-dac ++Params: ++ ++ +Name: i2s-gpio28-31 +Info: move I2S function block to GPIO 28 to 31 +Load: dtoverlay=i2s-gpio28-31 @@ -11918,13 +18910,31 @@ index 000000000000..3a0961540427 + configuring the sensor (default on) + cam0 Adopt the default configuration for CAM0 on a + Compute Module (CSI0, i2c_vc, and cam0_reg). ++ vcm Configure a VCM focus drive on the sensor. ++ ++ ++Name: imx258 ++Info: Sony IMX258 camera module. ++ Uses Unicam 1, which is the standard camera connector on most Pi ++ variants. ++Load: dtoverlay=imx258,= ++Params: rotation Mounting rotation of the camera sensor (0 or ++ 180, default 180) ++ orientation Sensor orientation (0 = front, 1 = rear, ++ 2 = external, default external) ++ media-controller Configure use of Media Controller API for ++ configuring the sensor (default on) ++ cam0 Adopt the default configuration for CAM0 on a ++ Compute Module (CSI0, i2c_vc, and cam0_reg). ++ vcm Configure a VCM focus drive on the sensor. ++ 4lane Enable 4 CSI2 lanes. This requires a Compute ++ Module (1, 3, or 4). + + +Name: imx290 +Info: Sony IMX290 camera module. + Uses Unicam 1, which is the standard camera connector on most Pi -+ variants. NB This currently uses 4 CSI2 data lanes and therefore will -+ only work on a CM. ++ variants. +Load: dtoverlay=imx290, +Params: 4lane Enable 4 CSI2 lanes. This requires a Compute + Module (1, 3, or 4). @@ -11944,6 +18954,49 @@ index 000000000000..3a0961540427 + Compute Module (CSI0, i2c_vc, and cam0_reg). + + ++Name: imx296 ++Info: Sony IMX296 camera module. ++ Uses Unicam 1, which is the standard camera connector on most Pi ++ variants. ++Load: dtoverlay=imx296,= ++Params: rotation Mounting rotation of the camera sensor (0 or ++ 180, default 180) ++ orientation Sensor orientation (0 = front, 1 = rear, ++ 2 = external, default external) ++ media-controller Configure use of Media Controller API for ++ configuring the sensor (default on) ++ cam0 Adopt the default configuration for CAM0 on a ++ Compute Module (CSI0, i2c_vc, and cam0_reg). ++ clock-frequency Sets the clock frequency to match that used on ++ the board, which should be one of 54000000 ++ (the default), 37125000 or 74250000. ++ always-on Leave the regulator powered up, to stop the ++ camera clamping I/Os such as XTRIG to 0V. ++ ++ ++Name: imx327 ++Info: Sony IMX327 camera module. ++ Uses Unicam 1, which is the standard camera connector on most Pi ++ variants. ++Load: dtoverlay=imx327, ++Params: 4lane Enable 4 CSI2 lanes. This requires a Compute ++ Module (1, 3, or 4). ++ clock-frequency Sets the clock frequency to match that used on ++ the board. ++ Modules from Vision Components use 37.125MHz ++ (the default), whilst those from Innomaker use ++ 74.25MHz. ++ mono Denote that the module is a mono sensor. ++ orientation Sensor orientation (0 = front, 1 = rear, ++ 2 = external, default external) ++ rotation Mounting rotation of the camera sensor (0 or ++ 180, default 0) ++ media-controller Configure use of Media Controller API for ++ configuring the sensor (default on) ++ cam0 Adopt the default configuration for CAM0 on a ++ Compute Module (CSI0, i2c_vc, and cam0_reg). ++ ++ +Name: imx378 +Info: Sony IMX378 camera module. + Uses Unicam 1, which is the standard camera connector on most Pi @@ -11957,6 +19010,33 @@ index 000000000000..3a0961540427 + configuring the sensor (default on) + cam0 Adopt the default configuration for CAM0 on a + Compute Module (CSI0, i2c_vc, and cam0_reg). ++ always-on Leave the regulator powered up, to stop the ++ camera clamping I/Os such as XVS to 0V. ++ sync-source Configure as vsync source ++ sync-sink Configure as vsync sink ++ ++ ++Name: imx462 ++Info: Sony IMX462 camera module. ++ Uses Unicam 1, which is the standard camera connector on most Pi ++ variants. ++Load: dtoverlay=imx462, ++Params: 4lane Enable 4 CSI2 lanes. This requires a Compute ++ Module (1, 3, or 4). ++ clock-frequency Sets the clock frequency to match that used on ++ the board. ++ Modules from Vision Components use 37.125MHz ++ (the default), whilst those from Innomaker use ++ 74.25MHz. ++ mono Denote that the module is a mono sensor. ++ orientation Sensor orientation (0 = front, 1 = rear, ++ 2 = external, default external) ++ rotation Mounting rotation of the camera sensor (0 or ++ 180, default 0) ++ media-controller Configure use of Media Controller API for ++ configuring the sensor (default on) ++ cam0 Adopt the default configuration for CAM0 on a ++ Compute Module (CSI0, i2c_vc, and cam0_reg). + + +Name: imx477 @@ -11972,6 +19052,10 @@ index 000000000000..3a0961540427 + configuring the sensor (default on) + cam0 Adopt the default configuration for CAM0 on a + Compute Module (CSI0, i2c_vc, and cam0_reg). ++ always-on Leave the regulator powered up, to stop the ++ camera clamping I/Os such as XVS to 0V. ++ sync-source Configure as vsync source ++ sync-sink Configure as vsync sink + + +Name: imx519 @@ -11987,6 +19071,39 @@ index 000000000000..3a0961540427 + configuring the sensor (default on) + cam0 Adopt the default configuration for CAM0 on a + Compute Module (CSI0, i2c_vc, and cam0_reg). ++ vcm Select lens driver state. Default is enabled, ++ but vcm=off will disable. ++ ++ ++Name: imx708 ++Info: Sony IMX708 camera module. ++ Uses Unicam 1, which is the standard camera connector on most Pi ++ variants. ++Load: dtoverlay=imx708,= ++Params: rotation Mounting rotation of the camera sensor (0 or ++ 180, default 180) ++ orientation Sensor orientation (0 = front, 1 = rear, ++ 2 = external, default external) ++ vcm Select lens driver state. Default is enabled, ++ but vcm=off will disable. ++ media-controller Configure use of Media Controller API for ++ configuring the sensor (default on) ++ cam0 Adopt the default configuration for CAM0 on a ++ Compute Module (CSI0, i2c_vc, and cam0_reg). ++ link-frequency Allowable link frequency values to use in Hz: ++ 450000000 (default), 447000000, 453000000. ++ ++ ++Name: interludeaudio-analog ++Info: Configures Interlude Audio Analog Hat audio card ++Load: dtoverlay=interludeaudio-analog,= ++Params: gpiopin GPIO pin for codec reset ++ ++ ++Name: interludeaudio-digital ++Info: Configures Interlude Audio Digital Hat audio card ++Load: dtoverlay=interludeaudio-digital ++Params: + + +Name: iqaudio-codec @@ -12046,6 +19163,19 @@ index 000000000000..3a0961540427 + dai stream name. + + ++Name: iqs550 ++Info: Enables I2C connected Azoteq IQS550 trackpad/touchscreen controller ++ using GPIO 4 (pin 7 on GPIO header) for interrupt. ++Load: dtoverlay=iqs550,= ++Params: interrupt GPIO used for interrupt (default 4) ++ reset GPIO used for reset (optional) ++ sizex Touchscreen size x (default 800) ++ sizey Touchscreen size y (default 480) ++ invx Touchscreen inverted x axis ++ invy Touchscreen inverted y axis ++ swapxy Touchscreen swapped x y axis ++ ++ +Name: irs1125 +Info: Infineon irs1125 TOF camera module. + Uses Unicam 1, which is the standard camera connector on most Pi @@ -12061,9 +19191,11 @@ index 000000000000..3a0961540427 +Info: Adds support for JEDEC-compliant SPI NOR flash devices. (Note: The + "jedec,spi-nor" kernel driver was formerly known as "m25p80".) +Load: dtoverlay=jedec-spi-nor,= -+Params: flash-spi- Enables flash device on SPI, CS#. -+ flash-fastr-spi- Enables flash device with fast read capability -+ on SPI, CS#. ++Params: spi- Enable flash device on SPI, CS# ++ fastr Add fast read capability to the flash device ++ speed Maximum SPI frequency (Hz) ++ flash-spi- Same as spi- (deprecated) ++ flash-fastr-spi- Same as spi->m>,fastr (deprecated) + + +Name: justboom-both @@ -12205,6 +19337,16 @@ index 000000000000..3a0961540427 + + mcp23008 Configure an MCP23008 instead. + noints Disable the interrupt GPIO line. ++ i2c0 Choose the I2C0 bus on GPIOs 0&1 ++ i2c_csi_dsi Choose the I2C0 bus on GPIOs 44&45 ++ i2c3 Choose the I2C3 bus (configure with the i2c3 ++ overlay - BCM2711 only) ++ i2c4 Choose the I2C4 bus (configure with the i2c4 ++ overlay - BCM2711 only) ++ i2c5 Choose the I2C5 bus (configure with the i2c5 ++ overlay - BCM2711 only) ++ i2c6 Choose the I2C6 bus (configure with the i2c6 ++ overlay - BCM2711 only) + + +Name: mcp23s17 @@ -12331,18 +19473,6 @@ index 000000000000..3a0961540427 + xohms Touchpanel sensitivity (X-plate resistance) + swapxy Swap x and y axis + backlight Change backlight GPIO pin {e.g. 12, 18} -+ gpio_out_pin GPIO for output (default "17") -+ gpio_in_pin GPIO for input (default "18") -+ gpio_in_pull Pull up/down/off on the input pin -+ (default "down") -+ sense Override the IR receive auto-detection logic: -+ "0" = force active-high -+ "1" = force active-low -+ "-1" = use auto-detection -+ (default "-1") -+ softcarrier Turn the software carrier "on" or "off" -+ (default "on") -+ invert "on" = invert the output pin (default "off") + debug "on" = enable additional debug messages + (default "off") + @@ -12360,6 +19490,10 @@ index 000000000000..3a0961540427 +Params: + + ++Name: midi-uart0-pi5 ++Info: See midi-uart0 (this is the Pi 5 version) ++ ++ +Name: midi-uart1 +Info: Configures UART1 (ttyS0) so that a requested 38.4kbaud actually gets + 31.25kbaud, the frequency required for MIDI @@ -12367,29 +19501,45 @@ index 000000000000..3a0961540427 +Params: + + ++Name: midi-uart1-pi5 ++Info: See midi-uart1 (this is the Pi 5 version) ++ ++ +Name: midi-uart2 -+Info: Configures UART2 (ttyAMA1) so that a requested 38.4kbaud actually gets ++Info: Configures UART2 (ttyAMA2) so that a requested 38.4kbaud actually gets + 31.25kbaud, the frequency required for MIDI +Load: dtoverlay=midi-uart2 +Params: + + ++Name: midi-uart2-pi5 ++Info: See midi-uart2 (this is the Pi 5 version) ++ ++ +Name: midi-uart3 -+Info: Configures UART3 (ttyAMA2) so that a requested 38.4kbaud actually gets ++Info: Configures UART3 (ttyAMA3) so that a requested 38.4kbaud actually gets + 31.25kbaud, the frequency required for MIDI +Load: dtoverlay=midi-uart3 +Params: + + ++Name: midi-uart3-pi5 ++Info: See midi-uart3 (this is the Pi 5 version) ++ ++ +Name: midi-uart4 -+Info: Configures UART4 (ttyAMA3) so that a requested 38.4kbaud actually gets ++Info: Configures UART4 (ttyAMA4) so that a requested 38.4kbaud actually gets + 31.25kbaud, the frequency required for MIDI +Load: dtoverlay=midi-uart4 +Params: + + ++Name: midi-uart4-pi5 ++Info: See midi-uart4 (this is the Pi 5 version) ++ ++ +Name: midi-uart5 -+Info: Configures UART5 (ttyAMA4) so that a requested 38.4kbaud actually gets ++Info: Configures UART5 (ttyAMA5) so that a requested 38.4kbaud actually gets + 31.25kbaud, the frequency required for MIDI +Load: dtoverlay=midi-uart5 +Params: @@ -12407,20 +19557,82 @@ index 000000000000..3a0961540427 + + +Name: miniuart-bt -+Info: Switch the onboard Bluetooth function on Pi 3B, 3B+, 3A+, 4B and Zero W ++Info: Switch the onboard Bluetooth function of a BT-equipped Raspberry Pi + to use the mini-UART (ttyS0) and restore UART0/ttyAMA0 over GPIOs 14 & -+ 15. Note that this may reduce the maximum usable baudrate. -+ N.B. It is also necessary to edit /lib/systemd/system/hciuart.service -+ and replace ttyAMA0 with ttyS0, unless using Raspbian or another -+ distribution with udev rules that create /dev/serial0 and /dev/serial1, -+ in which case use /dev/serial1 instead because it will always be -+ correct. Furthermore, you must also set core_freq and core_freq_min to -+ the same value in config.txt or the miniuart will not work. ++ 15. Note that this option uses a lower baudrate, and should only be used ++ with low-bandwidth peripherals. +Load: dtoverlay=miniuart-bt,= -+Params: krnbt Set to "on" to enable autoprobing of Bluetooth ++Params: krnbt Set to "off" to disable autoprobing of Bluetooth + driver without need of hciattach/btattach + + ++Name: mipi-dbi-spi ++Info: Overlay for SPI-connected MIPI DBI displays using the panel-mipi-dbi ++ driver. The driver will load a file /lib/firmware/panel.bin containing ++ the initialisation commands. ++ ++ Example: ++ dtoverlay=mipi-dbi-spi,spi0-0,speed=70000000 ++ dtparam=width=320,height=240 ++ dtparam=reset-gpio=23,dc-gpio=24 ++ dtparam=backlight-gpio=18 ++ ++ Compared to fbtft panel-mipi-dbi runs pixel data at spi-max-frequency ++ and init commands at 10MHz. This makes it possible to push the envelope ++ without messing up the controller configuration due to command ++ transmission errors. ++ ++ For devices on spi1 or spi2, the interfaces should be enabled ++ with one of the spi1-1/2/3cs and/or spi2-1/2/3cs overlays. ++ ++ See https://github.com/notro/panel-mipi-dbi/wiki for more info. ++ ++Load: dtoverlay=mipi-dbi-spi,= ++Params: ++ compatible Set the compatible string to load a different ++ firmware file. Both the panel compatible value ++ used to load the firmware file and the value ++ used to load the driver has to be set having a ++ NUL (\0) separator between them. ++ Example: ++ dtparam=compatible=mypanel\0panel-mipi-dbi-spi ++ spi- Configure device at spi, cs ++ (boolean, required) ++ speed SPI bus speed in Hz (default 32000000) ++ cpha Shifted SPI clock phase (CPHA) mode ++ cpol Inverse SPI clock polarity (CPOL) mode ++ write-only Controller is not readable ++ (ie. MISO is not wired up). ++ ++ width Panel width in pixels (required) ++ height Panel height in pixels (required) ++ width-mm Panel width in mm ++ height-mm Panel height in mm ++ x-offset Panel x-offset in controller RAM ++ y-offset Panel y-offset in controller RAM ++ ++ clock-frequency Panel clock frequency in Hz ++ (optional, just informational). ++ ++ reset-gpio GPIO pin to be used for RESET ++ dc-gpio GPIO pin to be used for D/C ++ ++ backlight-gpio GPIO pin to be used for backlight control ++ (default of none). ++ backlight-pwm PWM channel to be used for backlight control ++ (default of none). NB Disables audio headphone ++ output as that also uses PWM. ++ backlight-pwm-chan Choose channel on &pwm node for backlight ++ control (default 0). ++ backlight-pwm-gpio GPIO pin to be used for the PWM backlight. See ++ pwm-2chan for valid options (default 18). ++ backlight-pwm-func Pin function of GPIO used for the PWM backlight. ++ See pwm-2chan for valid options (default 2). ++ backlight-def-brightness ++ Set the default brightness. Normal range 1-16. ++ (default 16). ++ ++ +Name: mlx90640 +Info: Overlay for i2c connected mlx90640 thermal camera +Load: dtoverlay=mlx90640 @@ -12435,10 +19647,10 @@ index 000000000000..3a0961540427 + + +Name: mpu6050 -+Info: Overlay for i2c connected mpu6050 imu -+Load: dtoverlay=mpu6050,= -+Params: interrupt GPIO pin for interrupt (default 4) -+ addr I2C address of the device (default 0x68) ++Info: This overlay has been deprecated - use "dtoverlay=i2c-sensor,mpu6050" ++ instead. Note that "int_pin" is the new name for the "interrupt" ++ parameter. ++Load: + + +Name: mz61581 @@ -12457,6 +19669,21 @@ index 000000000000..3a0961540427 + xohms Touchpanel sensitivity (X-plate resistance) + + ++Name: ov2311 ++Info: Omnivision OV2311 camera module. ++ Uses Unicam 1, which is the standard camera connector on most Pi ++ variants. ++Load: dtoverlay=ov2311,= ++Params: rotation Mounting rotation of the camera sensor (0 or ++ 180, default 0) ++ orientation Sensor orientation (0 = front, 1 = rear, ++ 2 = external, default external) ++ media-controller Configure use of Media Controller API for ++ configuring the sensor (default on) ++ cam0 Adopt the default configuration for CAM0 on a ++ Compute Module (CSI0, i2c_vc, and cam0_reg). ++ ++ +Name: ov5647 +Info: Omnivision OV5647 camera module. + Uses Unicam 1, which is the standard camera connector on most Pi @@ -12470,6 +19697,26 @@ index 000000000000..3a0961540427 + configuring the sensor (default on) + cam0 Adopt the default configuration for CAM0 on a + Compute Module (CSI0, i2c_vc, and cam0_reg). ++ vcm Configure a VCM focus drive on the sensor. ++ ++ ++Name: ov64a40 ++Info: Arducam OV64A40 camera module. ++ Uses Unicam 1, which is the standard camera connector on most Pi ++ variants. ++Load: dtoverlay=ov64a40,= ++Params: rotation Mounting rotation of the camera sensor (0 or ++ 180, default 0) ++ orientation Sensor orientation (0 = front, 1 = rear, ++ 2 = external, default external) ++ media-controller Configure use of Media Controller API for ++ configuring the sensor (default on) ++ cam0 Adopt the default configuration for CAM0 on a ++ Compute Module (CSI0, i2c_vc, and cam0_reg). ++ vcm Select lens driver state. Default is enabled, ++ but vcm=off will disable. ++ link-frequency Allowable link frequency values to use in Hz: ++ 456000000 (default), 360000000 + + +Name: ov7251 @@ -12531,9 +19778,9 @@ index 000000000000..3a0961540427 + pca9574 Select the NXP PCA9574 (8 bit) + pca9575 Select the NXP PCA9575 (16 bit) + pca9698 Select the NXP PCA9698 (40 bit) -+ pca16416 Select the NXP PCA16416 (16 bit) -+ pca16524 Select the NXP PCA16524 (24 bit) -+ pca19555a Select the NXP PCA19555A (16 bit) ++ pcal6416 Select the NXP PCAL6416 (16 bit) ++ pcal6524 Select the NXP PCAL6524 (24 bit) ++ pcal9555a Select the NXP PCAL9555A (16 bit) + max7310 Select the Maxim MAX7310 (8 bit) + max7312 Select the Maxim MAX7312 (16 bit) + max7313 Select the Maxim MAX7313 (16 bit) @@ -12549,6 +19796,17 @@ index 000000000000..3a0961540427 + xra1202 Select the Exar XRA1202 (8 bit) + + ++Name: pcf857x ++Info: NXP PCF857x family of I2C GPIO expanders. ++Load: dtoverlay=pcf857x,= ++Params: addr I2C address of expander. Default ++ depends on model selected. ++ pcf8574 Select the NXP PCF8574 (8 bit) ++ pcf8574a Select the NXP PCF8574A (8 bit) ++ pcf8575 Select the NXP PCF8575 (16 bit) ++ pca8574 Select the NXP PCA8574 (8 bit) ++ ++ +Name: pcie-32bit-dma +Info: Force PCIe config to support 32bit DMA addresses at the expense of + having to bounce buffers. @@ -12556,6 +19814,12 @@ index 000000000000..3a0961540427 +Params: + + ++Name: pcie-32bit-dma-pi5 ++Info: Force PCIe config to support 32bit DMA addresses at the expense of ++ having to bounce buffers (on the Pi 5). ++Load: dtoverlay=pcie-32bit-dma-pi5 ++Params: ++ +[ The pcf2127-rtc overlay has been deleted. See i2c-rtc. ] + + @@ -12647,6 +19911,9 @@ index 000000000000..3a0961540427 + + xohms Touchpanel sensitivity (X-plate resistance) + ++ drm Select the DRM/KMS driver instead of the FBTFT ++ one ++ + +Name: piscreen2r +Info: PiScreen 2 with resistive TP display by OzzMaker.com @@ -12663,11 +19930,17 @@ index 000000000000..3a0961540427 + + +Name: pisound -+Info: Configures the Blokas Labs pisound card ++Info: Configures the Blokas Labs Pisound card +Load: dtoverlay=pisound +Params: + + ++Name: pisound-pi5 ++Info: Pi 5 specific overlay override for Blokas Labs Pisound card, see pisound ++Load: dtoverlay=pisound-pi5 ++Params: ++ ++ +Name: pitft22 +Info: Adafruit PiTFT 2.2" screen +Load: dtoverlay=pitft22,= @@ -12679,6 +19952,10 @@ index 000000000000..3a0961540427 + + debug Debug output level {0-7} + ++ drm Force the use of the mi0283qt DRM driver (by ++ default the ili9340 framebuffer driver will ++ be used in preference if available) ++ + +Name: pitft28-capacitive +Info: Adafruit PiTFT 2.8" capacitive touch screen @@ -12691,6 +19968,10 @@ index 000000000000..3a0961540427 + + debug Debug output level {0-7} + ++ drm Force the use of the mi0283qt DRM driver (by ++ default the ili9340 framebuffer driver will ++ be used in preference if available) ++ + touch-sizex Touchscreen size x (default 240) + + touch-sizey Touchscreen size y (default 320) @@ -12713,6 +19994,16 @@ index 000000000000..3a0961540427 + + debug Debug output level {0-7} + ++ drm Force the use of the mi0283qt DRM driver (by ++ default the ili9340 framebuffer driver will ++ be used in preference if available) ++ ++ touch-invx Touchscreen inverted x axis ++ ++ touch-invy Touchscreen inverted y axis ++ ++ touch-swapxy Touchscreen swapped x y axis ++ + +Name: pitft35-resistive +Info: Adafruit PiTFT 3.5" resistive touch screen @@ -12725,6 +20016,16 @@ index 000000000000..3a0961540427 + + debug Debug output level {0-7} + ++ drm Force the use of the hx8357d DRM driver (by ++ default the fb_hx8357d framebuffer driver will ++ be used in preference if available) ++ ++ touch-invx Touchscreen inverted x axis ++ ++ touch-invy Touchscreen inverted y axis ++ ++ touch-swapxy Touchscreen swapped x y axis ++ + +Name: pps-gpio +Info: Configures the pps-gpio (pulse-per-second time signal via GPIO). @@ -12735,6 +20036,14 @@ index 000000000000..3a0961540427 + off) + capture_clear Generate clear events on the trailing edge + (default off) ++ pull Desired pull-up/down state (off, down, up) ++ Default is "off". ++ ++ ++Name: proto-codec ++Info: Configures the PROTO Audio Codec card ++Load: dtoverlay=proto-codec ++Params: + + +Name: pwm @@ -12790,6 +20099,24 @@ index 000000000000..3a0961540427 + func Pin function (default 2 = Alt5) + + ++Name: pwm1 ++Info: Configures one or two PWM channel on PWM1 (BCM2711 only) ++ N.B.: ++ 1) The onboard analogue audio output uses both PWM channels. ++ 2) So be careful mixing audio and PWM. ++ Note that even when only one pin is enabled, both channels are available ++ from the PWM driver, so be careful to use the correct one. ++Load: dtoverlay=pwm1,= ++Params: clock PWM clock frequency (informational) ++ pins_40 Enable channel 0 (PWM1_0) on GPIO 40 ++ pins_41 Enable channel 1 (PWM1_1) on GPIO 41 ++ pins_40_41 Enable channels 0 (PWM1_0) and 1 (PW1_1) on ++ GPIOs 40 and 41 (default) ++ pull_up Enable pull-ups on the PWM pins (default) ++ pull_down Enable pull-downs on the PWM pins ++ pull_off Disable pulls on the PWM pins ++ ++ +Name: qca7000 +Info: in-tech's Evaluation Board for PLC Stamp micro + This uses spi0 and a separate GPIO interrupt to connect the QCA7000. @@ -12809,6 +20136,35 @@ index 000000000000..3a0961540427 + "115200") + + ++Name: ramoops ++Info: Enable the preservation of crash logs across a reboot. With ++ systemd-pstore enabled (as it is on Raspberry Pi OS) the crash logs ++ are moved to /var/lib/systemd/pstore/ on reboot. ++Load: dtoverlay=ramoops,= ++Params: base-addr Where to place the capture buffer (default ++ 0x0b000000) ++ total-size How much memory to allocate altogether (in ++ bytes - default 64kB) ++ record-size How much space to use for each capture, i.e. ++ total-size / record-size = number of captures ++ (default 16kB) ++ console-size Size of non-panic dmesg captures (default 0) ++ ++ ++Name: ramoops-pi4 ++Info: The version of the ramoops overlay for the Pi 4 family. It should be ++ loaded automatically if dtoverlay=ramoops is specified on a Pi 4. ++Load: dtoverlay=ramoops-pi4,= ++Params: base-addr Where to place the capture buffer (default ++ 0x0b000000) ++ total-size How much memory to allocate altogether (in ++ bytes - default 64kB) ++ record-size How much space to use for each capture, i.e. ++ total-size / record-size = number of captures ++ (default 16kB) ++ console-size Size of non-panic dmesg captures (default 0) ++ ++ +Name: rotary-encoder +Info: Overlay for GPIO connected rotary encoder. +Load: dtoverlay=rotary-encoder,= @@ -12848,34 +20204,95 @@ index 000000000000..3a0961540427 + + +Name: rpi-cirrus-wm5102 -+Info: Configures the Cirrus Logic Audio Card -+Load: dtoverlay=rpi-cirrus-wm5102 ++Info: This overlay has been renamed to cirrus-wm5102 ++Load: ++ ++ ++Name: rpi-codeczero ++Info: Configures the Raspberry Pi Codec Zero sound card ++Load: dtoverlay=rpi-codeczero +Params: + + +Name: rpi-dac -+Info: Configures the RPi DAC audio card -+Load: dtoverlay=rpi-dac -+Params: ++Info: This overlay has been renamed to i2s-dac. ++Load: ++ ++ ++Name: rpi-dacplus ++Info: Configures the Raspberry Pi DAC+ card ++Load: dtoverlay=rpi-dacplus,= ++Params: 24db_digital_gain Allow gain to be applied via the PCM512x codec ++ digital volume control. Enable by adding ++ "dtparam=24db_digital_gain" to config.txt ++ before any "dtoverlay" lines. ++ The default behaviour is that the digital ++ volume control is limited to a maximum of ++ 0dB. ie. it can attenuate but not provide ++ gain. For most users, this will be desired ++ as it will prevent clipping. By appending ++ the 24db_digital_gain parameter, the digital ++ volume control will allow up to 24dB of ++ gain. If this parameter is enabled, it is the ++ responsibility of the user to ensure that ++ the digital volume control is set to a value ++ that does not result in clipping/distortion! ++ ++ ++Name: rpi-dacpro ++Info: Configures the Raspberry Pi DAC Pro sound card ++Load: dtoverlay=rpi-dacpro,= ++Params: 24db_digital_gain Allow gain to be applied via the PCM512x codec ++ digital volume control. Enable by adding ++ "dtparam=24db_digital_gain" to config.txt ++ before any "dtoverlay" lines. ++ The default behaviour is that the digital ++ volume control is limited to a maximum of ++ 0dB. ie. it can attenuate but not provide ++ gain. For most users, this will be desired ++ as it will prevent clipping. By appending ++ the 24db_digital_gain parameter, the digital ++ volume control will allow up to 24dB of ++ gain. If this parameter is enabled, it is the ++ responsibility of the user to ensure that ++ the digital volume control is set to a value ++ that does not result in clipping/distortion! ++ ++ ++Name: rpi-digiampplus ++Info: Configures the Raspberry Pi DigiAMP+ sound card ++Load: dtoverlay=rpi-digiampplus,= ++Params: 24db_digital_gain Allow gain to be applied via the PCM512x codec ++ digital volume control. Enable by adding ++ "dtparam=24db_digital_gain" to config.txt ++ before any "dtoverlay" lines. ++ The default behaviour is that the digital ++ volume control is limited to a maximum of ++ 0dB. ie. it can attenuate but not provide ++ gain. For most users, this will be desired ++ as it will prevent clipping. By appending ++ the 24db_digital_gain parameter, the digital ++ volume control will allow up to 24dB of ++ gain. If this parameter is enabled, it is the ++ responsibility of the user to ensure that ++ the digital volume control is set to a value ++ that does not result in clipping/distortion! ++ auto_mute_amp If specified, unmute/mute the DigiAMP+ when ++ starting/stopping audio playback (default "on"). ++ unmute_amp If specified, unmute the DigiAMP+ amp once when ++ the DAC driver module loads (default "off"). + + +Name: rpi-display -+Info: RPi-Display - 2.8" Touch Display by Watterott -+Load: dtoverlay=rpi-display,= -+Params: speed Display SPI bus speed -+ rotate Display rotation {0,90,180,270} -+ fps Delay between frame updates -+ debug Debug output level {0-7} -+ xohms Touchpanel sensitivity (X-plate resistance) -+ swapxy Swap x and y axis -+ backlight Change backlight GPIO pin {e.g. 12, 18} ++Info: This overlay has been renamed to watterott-display ++Load: + + +Name: rpi-ft5406 +Info: Official Raspberry Pi display touchscreen +Load: dtoverlay=rpi-ft5406,= +Params: touchscreen-size-x Touchscreen X resolution (default 800) -+ touchscreen-size-y Touchscreen Y resolution (default 600); ++ touchscreen-size-y Touchscreen Y resolution (default 480); + touchscreen-inverted-x Invert touchscreen X coordinates (default 0); + touchscreen-inverted-y Invert touchscreen Y coordinates (default 0); + touchscreen-swapped-x-y Swap X and Y cordinates (default 0); @@ -12900,6 +20317,8 @@ index 000000000000..3a0961540427 + speeds up (default 55000) + poe_fan_temp3_hyst Temperature delta (in millicelcius) at which + the fan slows down (default 5000) ++ i2c Control the fan via Linux I2C drivers instead of ++ the firmware. + + +Name: rpi-poe-plus @@ -12921,12 +20340,13 @@ index 000000000000..3a0961540427 + speeds up (default 55000) + poe_fan_temp3_hyst Temperature delta (in millicelcius) at which + the fan slows down (default 5000) ++ i2c Control the fan via Linux I2C drivers instead of ++ the firmware. + + +Name: rpi-proto -+Info: Configures the RPi Proto audio card -+Load: dtoverlay=rpi-proto -+Params: ++Info: This overlay has been renamed to proto-codec. ++Load: + + +Name: rpi-sense @@ -12935,6 +20355,12 @@ index 000000000000..3a0961540427 +Params: + + ++Name: rpi-sense-v2 ++Info: Raspberry Pi Sense HAT v2 ++Load: dtoverlay=rpi-sense-v2 ++Params: ++ ++ +Name: rpi-tv +Info: Raspberry Pi TV HAT +Load: dtoverlay=rpi-tv @@ -12942,10 +20368,9 @@ index 000000000000..3a0961540427 + + +Name: rpivid-v4l2 -+Info: Load the V4L2 stateless video decoder driver for the HEVC block, -+ disabling the memory mapped devices in the process. -+Load: dtoverlay=rpivid-v4l2 -+Params: ++Info: This overlay has been deprecated and deleted as the V4L2 stateless ++ video decoder driver is enabled by default. ++Load: + + +Name: rra-digidac1-wm8741-audio @@ -13054,6 +20479,13 @@ index 000000000000..3a0961540427 +Load: + + ++Name: sdio-pi5 ++Info: Selects the rp1_mmc0 interface and enables it on GPIOs 22-27. ++ Pi 5 only. ++Load: dtoverlay=sdio-pi5 ++Params: ++ ++ +Name: sdtweak +Info: This overlay is now deprecated. Use the sd_* dtparams in the + base DTB, e.g. "dtoverlay=sdtweak,poll_once" becomes @@ -13188,105 +20620,131 @@ index 000000000000..3a0961540427 +Info: Enables spi1 with a single chip select (CS) line and associated spidev + dev node. The gpio pin number for the CS line and spidev device node + creation are configurable. -+ N.B.: spi1 is only accessible on devices with a 40pin header, eg: -+ A+, B+, Zero and PI2 B; as well as the Compute Module. ++ N.B.: spi1 is not accessible on old Pis without a 40-pin header. +Load: dtoverlay=spi1-1cs,= +Params: cs0_pin GPIO pin for CS0 (default 18 - BCM SPI1_CE0). -+ cs0_spidev Set to 'disabled' to stop the creation of a ++ cs0_spidev Set to 'off' to stop the creation of a + userspace device node /dev/spidev1.0 (default -+ is 'okay' or enabled). ++ is 'on' or enabled). + + +Name: spi1-2cs +Info: Enables spi1 with two chip select (CS) lines and associated spidev + dev nodes. The gpio pin numbers for the CS lines and spidev device node + creation are configurable. -+ N.B.: spi1 is only accessible on devices with a 40pin header, eg: -+ A+, B+, Zero and PI2 B; as well as the Compute Module. ++ N.B.: spi1 is not accessible on old Pis without a 40-pin header. +Load: dtoverlay=spi1-2cs,= +Params: cs0_pin GPIO pin for CS0 (default 18 - BCM SPI1_CE0). + cs1_pin GPIO pin for CS1 (default 17 - BCM SPI1_CE1). -+ cs0_spidev Set to 'disabled' to stop the creation of a ++ cs0_spidev Set to 'off' to stop the creation of a + userspace device node /dev/spidev1.0 (default -+ is 'okay' or enabled). -+ cs1_spidev Set to 'disabled' to stop the creation of a ++ is 'on' or enabled). ++ cs1_spidev Set to 'off' to stop the creation of a + userspace device node /dev/spidev1.1 (default -+ is 'okay' or enabled). ++ is 'on' or enabled). + + +Name: spi1-3cs +Info: Enables spi1 with three chip select (CS) lines and associated spidev + dev nodes. The gpio pin numbers for the CS lines and spidev device node + creation are configurable. -+ N.B.: spi1 is only accessible on devices with a 40pin header, eg: -+ A+, B+, Zero and PI2 B; as well as the Compute Module. ++ N.B.: spi1 is not accessible on old Pis without a 40-pin header. +Load: dtoverlay=spi1-3cs,= +Params: cs0_pin GPIO pin for CS0 (default 18 - BCM SPI1_CE0). + cs1_pin GPIO pin for CS1 (default 17 - BCM SPI1_CE1). + cs2_pin GPIO pin for CS2 (default 16 - BCM SPI1_CE2). -+ cs0_spidev Set to 'disabled' to stop the creation of a ++ cs0_spidev Set to 'off' to stop the creation of a + userspace device node /dev/spidev1.0 (default -+ is 'okay' or enabled). -+ cs1_spidev Set to 'disabled' to stop the creation of a ++ is 'on' or enabled). ++ cs1_spidev Set to 'off' to stop the creation of a + userspace device node /dev/spidev1.1 (default -+ is 'okay' or enabled). -+ cs2_spidev Set to 'disabled' to stop the creation of a ++ is 'on' or enabled). ++ cs2_spidev Set to 'off' to stop the creation of a + userspace device node /dev/spidev1.2 (default -+ is 'okay' or enabled). ++ is 'on' or enabled). + + +Name: spi2-1cs -+Info: Enables spi2 with a single chip select (CS) line and associated spidev -+ dev node. The gpio pin number for the CS line and spidev device node -+ creation are configurable. -+ N.B.: spi2 is only accessible with the Compute Module. ++Info: Enables spi2 on GPIOs 40-42 with a single chip select (CS) line and ++ associated spidev dev node. The gpio pin number for the CS line and ++ spidev device node creation are configurable. spi2-2cs-pi5 is ++ substituted on a Pi 5. ++ N.B.: spi2 is only accessible with the Compute Module or Pi 5. +Load: dtoverlay=spi2-1cs,= +Params: cs0_pin GPIO pin for CS0 (default 43 - BCM SPI2_CE0). -+ cs0_spidev Set to 'disabled' to stop the creation of a ++ cs0_spidev Set to 'off' to stop the creation of a + userspace device node /dev/spidev2.0 (default -+ is 'okay' or enabled). ++ is 'on' or enabled). ++ ++ ++Name: spi2-1cs-pi5 ++Info: Enables spi2 on GPIOs 1-3 with a single chip select (CS) line and ++ associated spidev dev node. The gpio pin number for the CS line and ++ spidev device node creation are configurable. Pi 5 only. ++Load: dtoverlay=spi2-1cs-pi5,= ++Params: cs0_pin GPIO pin for CS0 (default 0). ++ cs0_spidev Set to 'off' to stop the creation of a ++ userspace device node /dev/spidev2.0 (default ++ is 'on' or enabled). + + +Name: spi2-2cs -+Info: Enables spi2 with two chip select (CS) lines and associated spidev -+ dev nodes. The gpio pin numbers for the CS lines and spidev device node -+ creation are configurable. -+ N.B.: spi2 is only accessible with the Compute Module. ++Info: Enables spi2 on GPIOs 40-42 with two chip select (CS) lines and ++ associated spidev dev nodes. The gpio pin numbers for the CS lines and ++ spidev device node creation are configurable. spi2-2cs-pi5 is ++ substituted on a Pi 5. ++ N.B.: spi2 is only accessible with the Compute Module or Pi 5. +Load: dtoverlay=spi2-2cs,= +Params: cs0_pin GPIO pin for CS0 (default 43 - BCM SPI2_CE0). + cs1_pin GPIO pin for CS1 (default 44 - BCM SPI2_CE1). -+ cs0_spidev Set to 'disabled' to stop the creation of a ++ cs0_spidev Set to 'off' to stop the creation of a + userspace device node /dev/spidev2.0 (default -+ is 'okay' or enabled). -+ cs1_spidev Set to 'disabled' to stop the creation of a ++ is 'on' or enabled). ++ cs1_spidev Set to 'off' to stop the creation of a + userspace device node /dev/spidev2.1 (default -+ is 'okay' or enabled). ++ is 'on' or enabled). ++ ++ ++Name: spi2-2cs-pi5 ++Info: Enables spi2 on GPIOs 1-3 with two chip select (CS) lines and ++ associated spidev dev nodes. The gpio pin numbers for the CS lines and ++ spidev device node creation are configurable. Pi 5 only. ++Load: dtoverlay=spi2-2cs-pi5,= ++Params: cs0_pin GPIO pin for CS0 (default 0). ++ cs1_pin GPIO pin for CS1 (default 24). ++ cs0_spidev Set to 'off' to stop the creation of a ++ userspace device node /dev/spidev2.0 (default ++ is 'on' or enabled). ++ cs1_spidev Set to 'off' to stop the creation of a ++ userspace device node /dev/spidev2.1 (default ++ is 'on' or enabled). + + +Name: spi2-3cs -+Info: Enables spi2 with three chip select (CS) lines and associated spidev -+ dev nodes. The gpio pin numbers for the CS lines and spidev device node -+ creation are configurable. -+ N.B.: spi2 is only accessible with the Compute Module. ++Info: Enables spi2 on GPIOs 40-42 with three chip select (CS) lines and ++ associated spidev dev nodes. The gpio pin numbers for the CS lines and ++ spidev device node creation are configurable. ++ N.B.: spi2 is only accessible with the Compute Module or Pi 5. +Load: dtoverlay=spi2-3cs,= +Params: cs0_pin GPIO pin for CS0 (default 43 - BCM SPI2_CE0). + cs1_pin GPIO pin for CS1 (default 44 - BCM SPI2_CE1). + cs2_pin GPIO pin for CS2 (default 45 - BCM SPI2_CE2). -+ cs0_spidev Set to 'disabled' to stop the creation of a ++ cs0_spidev Set to 'off' to stop the creation of a + userspace device node /dev/spidev2.0 (default -+ is 'okay' or enabled). -+ cs1_spidev Set to 'disabled' to stop the creation of a ++ is 'on' or enabled). ++ cs1_spidev Set to 'off' to stop the creation of a + userspace device node /dev/spidev2.1 (default -+ is 'okay' or enabled). -+ cs2_spidev Set to 'disabled' to stop the creation of a ++ is 'on' or enabled). ++ cs2_spidev Set to 'off' to stop the creation of a + userspace device node /dev/spidev2.2 (default -+ is 'okay' or enabled). ++ is 'on' or enabled). + + +Name: spi3-1cs -+Info: Enables spi3 with a single chip select (CS) line and associated spidev -+ dev node. The gpio pin number for the CS line and spidev device node -+ creation are configurable. BCM2711 only. ++Info: Enables spi3 on GPIOs 1-3 with a single chip select (CS) line and ++ associated spidev dev node. The gpio pin number for the CS line and ++ spidev device node creation are configurable. BCM2711 only, ++ spi3-1cs-pi5 is substituted on Pi 5. +Load: dtoverlay=spi3-1cs,= +Params: cs0_pin GPIO pin for CS0 (default 0 - BCM SPI3_CE0). + cs0_spidev Set to 'off' to prevent the creation of a @@ -13294,10 +20752,22 @@ index 000000000000..3a0961540427 + is 'on' or enabled). + + ++Name: spi3-1cs-pi5 ++Info: Enables spi3 on GPIOs 5-7 with a single chip select (CS) line and ++ associated spidev dev node. The gpio pin number for the CS line and ++ spidev device node creation are configurable. Pi 5 only. ++Load: dtoverlay=spi3-1cs-pi5,= ++Params: cs0_pin GPIO pin for CS0 (default 4). ++ cs0_spidev Set to 'off' to prevent the creation of a ++ userspace device node /dev/spidev3.0 (default ++ is 'on' or enabled). ++ ++ +Name: spi3-2cs -+Info: Enables spi3 with two chip select (CS) lines and associated spidev -+ dev nodes. The gpio pin numbers for the CS lines and spidev device node -+ creation are configurable. BCM2711 only. ++Info: Enables spi3 on GPIO2 1-3 with two chip select (CS) lines and ++ associated spidev dev nodes. The gpio pin numbers for the CS lines and ++ spidev device node creation are configurable. BCM2711 only, ++ spi3-2cs-pi5 is substituted on Pi 5. +Load: dtoverlay=spi3-2cs,= +Params: cs0_pin GPIO pin for CS0 (default 0 - BCM SPI3_CE0). + cs1_pin GPIO pin for CS1 (default 24 - BCM SPI3_CE1). @@ -13309,10 +20779,25 @@ index 000000000000..3a0961540427 + is 'on' or enabled). + + ++Name: spi3-2cs-pi5 ++Info: Enables spi3 on GPIOs 5-7 with two chip select (CS) lines and ++ associated spidev dev nodes. The gpio pin numbers for the CS lines and ++ spidev device node creation are configurable. Pi 5 only. ++Load: dtoverlay=spi3-2cs-pi5,= ++Params: cs0_pin GPIO pin for CS0 (default 4). ++ cs1_pin GPIO pin for CS1 (default 25). ++ cs0_spidev Set to 'off' to prevent the creation of a ++ userspace device node /dev/spidev3.0 (default ++ is 'on' or enabled). ++ cs1_spidev Set to 'off' to prevent the creation of a ++ userspace device node /dev/spidev3.1 (default ++ is 'on' or enabled). ++ ++ +Name: spi4-1cs -+Info: Enables spi4 with a single chip select (CS) line and associated spidev -+ dev node. The gpio pin number for the CS line and spidev device node -+ creation are configurable. BCM2711 only. ++Info: Enables spi4 on GPIOs 5-7 with a single chip select (CS) line and ++ associated spidev dev node. The gpio pin number for the CS line and ++ spidev device node creation are configurable. BCM2711 only. +Load: dtoverlay=spi4-1cs,= +Params: cs0_pin GPIO pin for CS0 (default 4 - BCM SPI4_CE0). + cs0_spidev Set to 'off' to prevent the creation of a @@ -13321,9 +20806,9 @@ index 000000000000..3a0961540427 + + +Name: spi4-2cs -+Info: Enables spi4 with two chip select (CS) lines and associated spidev -+ dev nodes. The gpio pin numbers for the CS lines and spidev device node -+ creation are configurable. BCM2711 only. ++Info: Enables spi4 on GPIOs 5-6 with two chip select (CS) lines and ++ associated spidev dev nodes. The gpio pin numbers for the CS lines and ++ spidev device node creation are configurable. BCM2711 only. +Load: dtoverlay=spi4-2cs,= +Params: cs0_pin GPIO pin for CS0 (default 4 - BCM SPI4_CE0). + cs1_pin GPIO pin for CS1 (default 25 - BCM SPI4_CE1). @@ -13336,23 +20821,27 @@ index 000000000000..3a0961540427 + + +Name: spi5-1cs -+Info: Enables spi5 with a single chip select (CS) line and associated spidev -+ dev node. The gpio pin numbers for the CS lines and spidev device node -+ creation are configurable. BCM2711 only. ++Info: Enables spi5 on GPIOs 13-15 with a single chip select (CS) line and ++ associated spidev dev node. The gpio pin numbers for the CS lines and ++ spidev device node creation are configurable. BCM2711 and Pi 5. +Load: dtoverlay=spi5-1cs,= -+Params: cs0_pin GPIO pin for CS0 (default 12 - BCM SPI5_CE0). ++Params: cs0_pin GPIO pin for CS0 (default 12). + cs0_spidev Set to 'off' to prevent the creation of a + userspace device node /dev/spidev5.0 (default + is 'on' or enabled). + + ++Name: spi5-1cs-pi5 ++Info: See spi5-1cs ++ ++ +Name: spi5-2cs -+Info: Enables spi5 with two chip select (CS) lines and associated spidev -+ dev nodes. The gpio pin numbers for the CS lines and spidev device node -+ creation are configurable. BCM2711 only. ++Info: Enables spi5 on GPIOs 13-15 with two chip select (CS) lines and ++ associated spidev dev nodes. The gpio pin numbers for the CS lines and ++ spidev device node creation are configurable. BCM2711 and Pi 5. +Load: dtoverlay=spi5-2cs,= -+Params: cs0_pin GPIO pin for CS0 (default 12 - BCM SPI5_CE0). -+ cs1_pin GPIO pin for CS1 (default 26 - BCM SPI5_CE1). ++Params: cs0_pin GPIO pin for CS0 (default 12). ++ cs1_pin GPIO pin for CS1 (default 26). + cs0_spidev Set to 'off' to prevent the creation of a + userspace device node /dev/spidev5.0 (default + is 'on' or enabled). @@ -13361,6 +20850,10 @@ index 000000000000..3a0961540427 + is 'on' or enabled). + + ++Name: spi5-2cs-pi5 ++Info: See spi5-2cs ++ ++ +Name: spi6-1cs +Info: Enables spi6 with a single chip select (CS) line and associated spidev + dev node. The gpio pin number for the CS line and spidev device node @@ -13428,6 +20921,8 @@ index 000000000000..3a0961540427 + dc_pin GPIO pin for D/C (default 24) + reset_pin GPIO pin for RESET (default 25) + height Display height (32 or 64; default 64) ++ inverted Set this if display is inverted and mirrored. ++ (default=not set) + + +Name: ssd1331-spi @@ -13542,6 +21037,14 @@ index 000000000000..3a0961540427 +Params: + + ++Name: tpm-slb9673 ++Info: Enables support for Infineon SLB9673 Trusted Platform Module add-on ++ boards, which can be used as a secure key storage and hwrng ++ via the I2C protocol. ++Load: dtoverlay=tpm-slb9673 ++Params: ++ ++ +Name: uart0 +Info: Change the pin usage of uart0 +Load: dtoverlay=uart0,= @@ -13553,6 +21056,12 @@ index 000000000000..3a0961540427 + 7(Alt3) for 32&33, 6(Alt2) for 36&37 + + ++Name: uart0-pi5 ++Info: Enable uart 0 on GPIOs 14-15. Pi 5 only. ++Load: dtoverlay=uart0-pi5, ++Params: ctsrts Enable CTS/RTS on GPIOs 16-17 (default off) ++ ++ +Name: uart1 +Info: Change the pin usage of uart1 +Load: dtoverlay=uart1,= @@ -13561,24 +21070,48 @@ index 000000000000..3a0961540427 + rxd1_pin GPIO pin for RXD1 (15, 33 or 41 - default 15) + + ++Name: uart1-pi5 ++Info: Enable uart 1 on GPIOs 0-1. Pi 5 only. ++Load: dtoverlay=uart1-pi5, ++Params: ctsrts Enable CTS/RTS on GPIOs 2-3 (default off) ++ ++ +Name: uart2 +Info: Enable uart 2 on GPIOs 0-3. BCM2711 only. +Load: dtoverlay=uart2, +Params: ctsrts Enable CTS/RTS on GPIOs 2-3 (default off) + + ++Name: uart2-pi5 ++Info: Enable uart 2 on GPIOs 4-5. Pi 5 only. ++Load: dtoverlay=uart2-pi5, ++Params: ctsrts Enable CTS/RTS on GPIOs 6-7 (default off) ++ ++ +Name: uart3 +Info: Enable uart 3 on GPIOs 4-7. BCM2711 only. +Load: dtoverlay=uart3, +Params: ctsrts Enable CTS/RTS on GPIOs 6-7 (default off) + + ++Name: uart3-pi5 ++Info: Enable uart 3 on GPIOs 8-9. Pi 5 only. ++Load: dtoverlay=uart3-pi5, ++Params: ctsrts Enable CTS/RTS on GPIOs 10-11 (default off) ++ ++ +Name: uart4 +Info: Enable uart 4 on GPIOs 8-11. BCM2711 only. +Load: dtoverlay=uart4, +Params: ctsrts Enable CTS/RTS on GPIOs 10-11 (default off) + + ++Name: uart4-pi5 ++Info: Enable uart 4 on GPIOs 12-13. Pi 5 only. ++Load: dtoverlay=uart4-pi5, ++Params: ctsrts Enable CTS/RTS on GPIOs 14-15 (default off) ++ ++ +Name: uart5 +Info: Enable uart 5 on GPIOs 12-15. BCM2711 only. +Load: dtoverlay=uart5, @@ -13681,8 +21214,14 @@ index 000000000000..3a0961540427 + width-mm Define the screen width in mm + height-mm Define the screen height in mm + rgb565 Change to RGB565 output on GPIOs 0-19 ++ rgb565-padhi Change to RGB565 output on GPIOs 0-8, 12-17, and ++ 20-24 ++ bgr666 Change to BGR666 output on GPIOs 0-21. ++ bgr666-padhi Change to BGR666 output on GPIOs 0-9, 12-17, and ++ 20-25 + rgb666-padhi Change to RGB666 output on GPIOs 0-9, 12-17, and + 20-25 ++ bgr888 Change to BGR888 output on GPIOs 0-27 + rgb888 Change to RGB888 output on GPIOs 0-27 + bus-format Override the bus format for a MEDIA_BUS_FMT_* + value. NB also overridden by rgbXXX overrides. @@ -13708,6 +21247,39 @@ index 000000000000..3a0961540427 + rotate Display rotation {0,90,180,270} (default 0) + + ++Name: vc4-kms-dpi-hyperpixel2r ++Info: Enable the KMS drivers for the Pimoroni HyperPixel2 Round DPI display. ++ Requires vc4-kms-v3d to be loaded. ++Load: dtoverlay=vc4-kms-dpi-hyperpixel2r,= ++Params: disable-touch Disables the touch controller ++ touchscreen-inverted-x Inverts X direction of touch controller ++ touchscreen-inverted-y Inverts Y direction of touch controller ++ touchscreen-swapped-x-y Swaps X & Y axes of touch controller ++ rotate Display rotation {0,90,180,270} (default 0) ++ ++ ++Name: vc4-kms-dpi-hyperpixel4 ++Info: Enable the KMS drivers for the Pimoroni HyperPixel4 DPI display. ++ Requires vc4-kms-v3d to be loaded. ++Load: dtoverlay=vc4-kms-dpi-hyperpixel4,= ++Params: disable-touch Disables the touch controller ++ touchscreen-inverted-x Inverts X direction of touch controller ++ touchscreen-inverted-y Inverts Y direction of touch controller ++ touchscreen-swapped-x-y Swaps X & Y axes of touch controller ++ rotate Display rotation {0,90,180,270} (default 0) ++ ++ ++Name: vc4-kms-dpi-hyperpixel4sq ++Info: Enable the KMS drivers for the Pimoroni HyperPixel4 Square DPI display. ++ Requires vc4-kms-v3d to be loaded. ++Load: dtoverlay=vc4-kms-dpi-hyperpixel4sq,= ++Params: disable-touch Disables the touch controller ++ touchscreen-inverted-x Inverts X direction of touch controller ++ touchscreen-inverted-y Inverts Y direction of touch controller ++ touchscreen-swapped-x-y Swaps X & Y axes of touch controller ++ rotate Display rotation {0,90,180,270} (default 0) ++ ++ +Name: vc4-kms-dpi-panel +Info: Enable a preconfigured KMS DPI panel. + Requires vc4-kms-v3d to be loaded. @@ -13748,6 +21320,67 @@ index 000000000000..3a0961540427 + invy Touchscreen inverted y axis + swapxy Touchscreen swapped x y axis + disable_touch Disables the touch screen overlay driver ++ dsi0 Use DSI0 and i2c_csi_dsi0 (rather than ++ the default DSI1 and i2c_csi_dsi). ++ ++ ++Name: vc4-kms-dsi-generic ++Info: Enable a generic DSI display under KMS. ++ Default timings are for a 840x480 RGB888 panel. ++ Requires vc4-kms-v3d to be loaded. ++Load: dtoverlay=vc4-kms-dsi-generic,= ++Params: clock-frequency Display clock frequency (Hz) ++ hactive Horizontal active pixels ++ hfp Horizontal front porch ++ hsync Horizontal sync pulse width ++ hbp Horizontal back porch ++ vactive Vertical active lines ++ vfp Vertical front porch ++ vsync Vertical sync pulse width ++ vbp Vertical back porch ++ width-mm Define the screen width in mm ++ height-mm Define the screen height in mm ++ rgb565 Change to RGB565 output ++ rgb666 Change to RGB666 output ++ rgb666p Change to RGB666 output with pixel packing ++ rgb888 Change to RGB888 output, this is the default ++ one-lane Use one DSI lane for data transmission ++ This is the default ++ two-lane Use two DSI lanes for data transmission ++ three-lane Use three DSI lanes for data transmission ++ Only supported on Pi5 and CM ++ four-lane Use four DSI lanes for data transmission ++ Only supported on Pi5 and CM ++ dsi0 Switch DSI port to DSI0 ++ Only supported on Pi5 and CM ++ ++ ++Name: vc4-kms-dsi-ili9881-5inch ++Info: Enable the Raspberry Pi 5" ILI9881 based touchscreen panel. ++ Requires vc4-kms-v3d to be loaded. ++Load: dtoverlay=vc4-kms-dsi-ili9881-5inch, ++Params: sizex Touchscreen size x (default 720) ++ sizey Touchscreen size y (default 1280) ++ invx Touchscreen inverted x axis ++ invy Touchscreen inverted y axis ++ swapxy Touchscreen swapped x y axis ++ disable_touch Disables the touch screen overlay driver ++ dsi0 Use DSI0 and i2c_csi_dsi0 (rather than ++ the default DSI1 and i2c_csi_dsi). ++ ++ ++Name: vc4-kms-dsi-ili9881-7inch ++Info: Enable the Raspberry Pi 7" ILI9881 based touchscreen panel. ++ Requires vc4-kms-v3d to be loaded. ++Load: dtoverlay=vc4-kms-dsi-ili9881-7inch, ++Params: sizex Touchscreen size x (default 720) ++ sizey Touchscreen size y (default 1280) ++ invx Touchscreen inverted x axis ++ invy Touchscreen inverted y axis ++ swapxy Touchscreen swapped x y axis ++ disable_touch Disables the touch screen overlay driver ++ dsi0 Use DSI0 and i2c_csi_dsi0 (rather than ++ the default DSI1 and i2c_csi_dsi). + + +Name: vc4-kms-dsi-lt070me05000 @@ -13771,6 +21404,37 @@ index 000000000000..3a0961540427 +Params: + + ++Name: vc4-kms-dsi-waveshare-panel ++Info: Enable a Waveshare DSI touchscreen ++ Includes the Goodix driver for the touchscreen element. ++ The default is for the display to be using the I2C0 option for control. ++ Use the i2c1 override if using the I2C1 wiring with jumper wires from ++ GPIOs 2&3 (pins 3&5). ++ invx/invy/swapxy should be used with caution as the panel specifier will ++ set the default inversions for that panel. Always use them after the ++ panel specifier, and be aware that you may need to set them as =0, not ++ just adding it. ++ Requires vc4-kms-v3d to be loaded. ++Load: dtoverlay=vc4-kms-dsi-waveshare-panel,= ++Params: 2_8_inch 2.8" 480x640 ++ 3_4_inch 3.4" 800x800 round ++ 4_0_inch 4.0" 480x800 ++ 4_0_inchC 4.0" 720x720 ++ 7_0_inchC 7.0" C 1024x600 ++ 7_9_inch 7.9" 400x1280 ++ 8_0_inch 8.0" 1280x800 ++ 10_1_inch 10.1" 1280x800 ++ 11_9_inch 11.9" 320x1480 ++ i2c1 Use i2c-1 with jumper wires from GPIOs 2&3 ++ disable_touch Disable the touch controller ++ rotation Set the panel orientation property ++ invx Touchscreen inverted x axis ++ invy Touchscreen inverted y axis ++ swapxy Touchscreen swapped x y axis ++ dsi0 Use DSI0 and i2c_csi_dsi0 (rather than ++ the default DSI1 and i2c_csi_dsi). ++ ++ +Name: vc4-kms-kippah-7inch +Info: This overlay is now deprecated - see vc4-kms-dpi-panel,kippah-7inch +Load: @@ -13794,6 +21458,7 @@ index 000000000000..3a0961540427 + noaudio Disable all HDMI audio (default "off") + composite Enable the composite output (default "off") + N.B. Disables all other outputs on a Pi 4. ++ nohdmi Disable HDMI output + + +Name: vc4-kms-v3d-pi4 @@ -13817,6 +21482,13 @@ index 000000000000..3a0961540427 + noaudio Disable all HDMI audio (default "off") + composite Enable the composite output (disables all other + outputs) ++ nohdmi Disable both HDMI 0 & 1 outputs ++ nohdmi0 Disable HDMI 0 output ++ nohdmi1 Disable HDMI 1 output ++ ++ ++Name: vc4-kms-v3d-pi5 ++Info: See vc4-kms-v3d-pi4 (this is the Pi 5 version) + + +Name: vc4-kms-vga666 @@ -13853,6 +21525,10 @@ index 000000000000..3a0961540427 + pullup Now enabled by default (ignored) + + ++Name: w1-gpio-pi5 ++Info: See w1-gpio (this is the Pi 5 version) ++ ++ +Name: w1-gpio-pullup +Info: Configures the w1-gpio Onewire interface module. + Use this overlay if you *do* need a GPIO to drive an external pullup. @@ -13862,6 +21538,10 @@ index 000000000000..3a0961540427 + pullup Now enabled by default (ignored) + + ++Name: w1-gpio-pullup-pi5 ++Info: See w1-gpio-pullup (this is the Pi 5 version) ++ ++ +Name: w5500 +Info: Overlay for the Wiznet W5500 Ethernet Controller on SPI0 +Load: dtoverlay=w5500,= @@ -13872,6 +21552,60 @@ index 000000000000..3a0961540427 + cs SPI bus Chip Select (default 0) + + ++Name: watterott-display ++Info: Watterott RPi-Display - 2.8" Touch Display ++ Linux has 2 drivers that support this display and this overlay supports ++ both. ++ ++ Examples: ++ fbtft/fb_ili9341: dtoverlay=watterott-display ++ drm/mi0283qt: dtoverlay=watterott-display,drm,backlight-pwm,rotate=180 ++ ++ Some notable differences with the DRM driver compared to fbtft: ++ - The display is turned on when it's first used and not on driver load ++ as with fbtft. So if nothing uses the display it stays off. ++ - Can run with a higher SPI clock increasing framerate. This is possible ++ since the driver avoids messing up the controller configuration due to ++ transmission errors by running config commands at 10MHz and only pixel ++ data at full speed (occasional pixel glitch might occur). ++ - PWM backlight is supported. ++ ++Load: dtoverlay=watterott-display,= ++Params: speed Display SPI bus speed ++ rotate Display rotation {0,90,180,270} ++ fps Delay between frame updates (fbtft only) ++ debug Debug output level {0-7} (fbtft only) ++ xohms Touchpanel sensitivity (X-plate resistance) ++ swapxy Swap x and y axis ++ backlight Change backlight GPIO pin {e.g. 12, 18} ++ (fbtft only) ++ drm Use DRM/KMS driver mi0283qt instead of fbtft. ++ Set the SPI clock to 70MHz. ++ This has to be the first parameter. ++ backlight-pwm Use pwm for backlight (drm only). NB: Disables ++ audio headphone output as that also uses PWM. ++ ++ ++Name: waveshare-can-fd-hat-mode-a ++Info: Overlay for the Waveshare 2-Channel Isolated CAN FD Expansion HAT ++ for Raspberry Pi, Multi Protections. Use this overlay when the ++ HAT is configured in Mode A (Default), with can0 on spi0.0 ++ and can1 on spi1.0. ++ https://www.waveshare.com/2-ch-can-fd-hat.htm ++Load: dtoverlay=waveshare-can-fd-hat-mode-a ++Params: ++ ++ ++Name: waveshare-can-fd-hat-mode-b ++Info: Overlay for the Waveshare 2-Channel Isolated CAN FD Expansion HAT ++ for Raspberry Pi, Multi Protections. Use this overlay when the ++ HAT is configured in Mode B (requires hardware modification), with ++ can0 on spi0.0 and can1 on spi0.1. ++ https://www.waveshare.com/2-ch-can-fd-hat.htm ++Load: dtoverlay=waveshare-can-fd-hat-mode-b ++Params: ++ ++ +Name: wittypi +Info: Configures the wittypi RTC module. +Load: dtoverlay=wittypi,= @@ -13910,10 +21644,10 @@ index 000000000000..3a0961540427 +http://www.raspberrypi.org/documentation/configuration/device-tree.md diff --git a/arch/arm/boot/dts/overlays/act-led-overlay.dts b/arch/arm/boot/dts/overlays/act-led-overlay.dts new file mode 100644 -index 000000000000..2f4bbb407f89 +index 000000000000..685e354923a0 --- /dev/null +++ b/arch/arm/boot/dts/overlays/act-led-overlay.dts -@@ -0,0 +1,27 @@ +@@ -0,0 +1,28 @@ +/dts-v1/; +/plugin/; + @@ -13930,20 +21664,21 @@ index 000000000000..2f4bbb407f89 + compatible = "brcm,bcm2835"; + + fragment@0 { -+ target = <&act_led>; ++ target = <&led_act>; + frag0: __overlay__ { + gpios = <&gpio 0 0>; + }; + }; + + __overrides__ { -+ gpio = <&frag0>,"gpios:4"; ++ gpio = <&frag0>,"gpios:4", ++ <&frag0>,"status=okay"; + activelow = <&frag0>,"gpios:8"; + }; +}; diff --git a/arch/arm/boot/dts/overlays/adafruit-st7735r-overlay.dts b/arch/arm/boot/dts/overlays/adafruit-st7735r-overlay.dts new file mode 100644 -index 000000000000..bf186811ec5d +index 000000000000..6e69bd7fa031 --- /dev/null +++ b/arch/arm/boot/dts/overlays/adafruit-st7735r-overlay.dts @@ -0,0 +1,83 @@ @@ -14011,7 +21746,7 @@ index 000000000000..bf186811ec5d + spi-max-frequency = <32000000>; + dc-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>; -+ rotate = <90>; ++ rotation = <90>; + pinctrl-names = "default"; + pinctrl-0 = <&adafruit_pins>; + backlight = <&af18_backlight>; @@ -14022,7 +21757,7 @@ index 000000000000..bf186811ec5d + __overrides__ { + 128x128 = <&af18>, "compatible=okaya,rh128128t"; + speed = <&af18>,"spi-max-frequency:0"; -+ rotate = <&af18>,"rotate:0"; ++ rotate = <&af18>,"rotation:0"; + dc_pin = <&af18>,"dc-gpios:4", <&adafruit_pins>,"brcm,pins:4"; + reset_pin = <&af18>,"reset-gpios:4", + <&adafruit_pins>,"brcm,pins:0"; @@ -14093,7 +21828,7 @@ index 000000000000..e1ce94a8cd3e +}; diff --git a/arch/arm/boot/dts/overlays/adau1977-adc-overlay.dts b/arch/arm/boot/dts/overlays/adau1977-adc-overlay.dts new file mode 100644 -index 000000000000..298488e19156 +index 000000000000..cf6d1ef3bfff --- /dev/null +++ b/arch/arm/boot/dts/overlays/adau1977-adc-overlay.dts @@ -0,0 +1,40 @@ @@ -14105,7 +21840,7 @@ index 000000000000..298488e19156 + compatible = "brcm,bcm2835"; + + fragment@0 { -+ target = <&i2c>; ++ target = <&i2c1>; + + __overlay__ { + #address-cells = <1>; @@ -14122,7 +21857,7 @@ index 000000000000..298488e19156 + }; + + fragment@1 { -+ target = <&i2s>; ++ target = <&i2s_clk_consumer>; + __overlay__ { + status = "okay"; + }; @@ -14132,14 +21867,14 @@ index 000000000000..298488e19156 + target = <&sound>; + __overlay__ { + compatible = "adi,adau1977-adc"; -+ i2s-controller = <&i2s>; ++ i2s-controller = <&i2s_clk_consumer>; + status = "okay"; + }; + }; +}; diff --git a/arch/arm/boot/dts/overlays/adau7002-simple-overlay.dts b/arch/arm/boot/dts/overlays/adau7002-simple-overlay.dts new file mode 100644 -index 000000000000..5fed769d2526 +index 000000000000..62e92bd8f952 --- /dev/null +++ b/arch/arm/boot/dts/overlays/adau7002-simple-overlay.dts @@ -0,0 +1,52 @@ @@ -14150,7 +21885,7 @@ index 000000000000..5fed769d2526 + compatible = "brcm,bcm2835"; + + fragment@0 { -+ target = <&i2s>; ++ target = <&i2s_clk_producer>; + __overlay__ { + status = "okay"; + }; @@ -14182,7 +21917,7 @@ index 000000000000..5fed769d2526 + "PDM_DAT", "Microphone Jack"; + status = "okay"; + simple-audio-card,cpu { -+ sound-dai = <&i2s>; ++ sound-dai = <&i2s_clk_producer>; + }; + dailink0_slave: simple-audio-card,codec { + sound-dai = <&adau7002_codec>; @@ -14301,10 +22036,10 @@ index 000000000000..dc1764613a8b +}; diff --git a/arch/arm/boot/dts/overlays/ads1115-overlay.dts b/arch/arm/boot/dts/overlays/ads1115-overlay.dts new file mode 100644 -index 000000000000..e44ced704ee2 +index 000000000000..64ada16de9c7 --- /dev/null +++ b/arch/arm/boot/dts/overlays/ads1115-overlay.dts -@@ -0,0 +1,103 @@ +@@ -0,0 +1,135 @@ +/* + * TI ADS1115 multi-channel ADC overlay + */ @@ -14316,7 +22051,63 @@ index 000000000000..e44ced704ee2 + compatible = "brcm,bcm2835"; + + fragment@0 { -+ target = <&i2c_arm>; ++ target = <&ads1115>; ++ __dormant__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ channel_a: channel_a { ++ reg = <4>; ++ ti,gain = <1>; ++ ti,datarate = <7>; ++ }; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&ads1115>; ++ __dormant__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ channel_b: channel_b { ++ reg = <5>; ++ ti,gain = <1>; ++ ti,datarate = <7>; ++ }; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&ads1115>; ++ __dormant__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ channel_c: channel_c { ++ reg = <6>; ++ ti,gain = <1>; ++ ti,datarate = <7>; ++ }; ++ }; ++ }; ++ ++ fragment@3 { ++ target = <&ads1115>; ++ __dormant__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ channel_d: channel_d { ++ reg = <7>; ++ ti,gain = <1>; ++ ti,datarate = <7>; ++ }; ++ }; ++ }; ++ ++ fragment@4 { ++ target = <&i2cbus>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; @@ -14332,85 +22123,61 @@ index 000000000000..e44ced704ee2 + }; + }; + -+ fragment@1 { -+ target = <&ads1115>; -+ __dormant__ { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ channel_a: channel_a { -+ reg = <4>; -+ ti,gain = <1>; -+ ti,datarate = <7>; -+ }; ++ frag100: fragment@100 { ++ target = <&i2c1>; ++ i2cbus: __overlay__ { ++ status = "okay"; + }; + }; + -+ fragment@2 { -+ target = <&ads1115>; ++ fragment@101 { ++ target = <&i2c0if>; + __dormant__ { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ channel_b: channel_b { -+ reg = <5>; -+ ti,gain = <1>; -+ ti,datarate = <7>; -+ }; ++ status = "okay"; + }; + }; + -+ fragment@3 { -+ target = <&ads1115>; ++ fragment@102 { ++ target = <&i2c0mux>; + __dormant__ { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ channel_c: channel_c { -+ reg = <6>; -+ ti,gain = <1>; -+ ti,datarate = <7>; -+ }; -+ }; -+ }; -+ -+ fragment@4 { -+ target = <&ads1115>; -+ __dormant__ { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ channel_d: channel_d { -+ reg = <7>; -+ ti,gain = <1>; -+ ti,datarate = <7>; -+ }; ++ status = "okay"; + }; + }; + + __overrides__ { + addr = <&ads1115>,"reg:0"; -+ cha_enable = <0>,"=1"; ++ cha_enable = <0>,"=0"; + cha_cfg = <&channel_a>,"reg:0"; + cha_gain = <&channel_a>,"ti,gain:0"; + cha_datarate = <&channel_a>,"ti,datarate:0"; -+ chb_enable = <0>,"=2"; ++ chb_enable = <0>,"=1"; + chb_cfg = <&channel_b>,"reg:0"; + chb_gain = <&channel_b>,"ti,gain:0"; + chb_datarate = <&channel_b>,"ti,datarate:0"; -+ chc_enable = <0>,"=3"; ++ chc_enable = <0>,"=2"; + chc_cfg = <&channel_c>,"reg:0"; + chc_gain = <&channel_c>,"ti,gain:0"; + chc_datarate = <&channel_c>,"ti,datarate:0"; -+ chd_enable = <0>,"=4"; ++ chd_enable = <0>,"=3"; + chd_cfg = <&channel_d>,"reg:0"; + chd_gain = <&channel_d>,"ti,gain:0"; + chd_datarate = <&channel_d>,"ti,datarate:0"; ++ i2c0 = <&frag100>, "target:0=",<&i2c0>; ++ i2c_csi_dsi = <&frag100>, "target:0=",<&i2c_csi_dsi>, ++ <0>,"+101+102"; ++ i2c3 = <&frag100>, "target?=0", ++ <&frag100>, "target-path=i2c3"; ++ i2c4 = <&frag100>, "target?=0", ++ <&frag100>, "target-path=i2c4"; ++ i2c5 = <&frag100>, "target?=0", ++ <&frag100>, "target-path=i2c5"; ++ i2c6 = <&frag100>, "target?=0", ++ <&frag100>, "target-path=i2c6"; + }; +}; diff --git a/arch/arm/boot/dts/overlays/ads7846-overlay.dts b/arch/arm/boot/dts/overlays/ads7846-overlay.dts new file mode 100644 -index 000000000000..1c5c9b6bb6ff +index 000000000000..211a002c0b34 --- /dev/null +++ b/arch/arm/boot/dts/overlays/ads7846-overlay.dts @@ -0,0 +1,89 @@ @@ -14473,7 +22240,7 @@ index 000000000000..1c5c9b6bb6ff + spi-max-frequency = <2000000>; + interrupts = <255 2>; /* high-to-low edge triggered */ + interrupt-parent = <&gpio>; -+ pendown-gpio = <&gpio 255 0>; ++ pendown-gpio = <&gpio 255 1>; + + /* driver defaults */ + ti,x-min = /bits/ 16 <0>; @@ -14627,7 +22394,7 @@ index 000000000000..ea392e886984 +}; diff --git a/arch/arm/boot/dts/overlays/akkordion-iqdacplus-overlay.dts b/arch/arm/boot/dts/overlays/akkordion-iqdacplus-overlay.dts new file mode 100644 -index 000000000000..82f9b3734fb1 +index 000000000000..d867146bcb8f --- /dev/null +++ b/arch/arm/boot/dts/overlays/akkordion-iqdacplus-overlay.dts @@ -0,0 +1,49 @@ @@ -14639,7 +22406,7 @@ index 000000000000..82f9b3734fb1 + compatible = "brcm,bcm2835"; + + fragment@0 { -+ target = <&i2s>; ++ target = <&i2s_clk_producer>; + __overlay__ { + status = "okay"; + }; @@ -14671,7 +22438,7 @@ index 000000000000..82f9b3734fb1 + card_name = "Akkordion"; + dai_name = "IQaudIO DAC"; + dai_stream_name = "IQaudIO DAC HiFi"; -+ i2s-controller = <&i2s>; ++ i2s-controller = <&i2s_clk_producer>; + status = "okay"; + }; + }; @@ -14682,10 +22449,10 @@ index 000000000000..82f9b3734fb1 +}; diff --git a/arch/arm/boot/dts/overlays/allo-boss-dac-pcm512x-audio-overlay.dts b/arch/arm/boot/dts/overlays/allo-boss-dac-pcm512x-audio-overlay.dts new file mode 100644 -index 000000000000..873cb2fab52b +index 000000000000..16806945890b --- /dev/null +++ b/arch/arm/boot/dts/overlays/allo-boss-dac-pcm512x-audio-overlay.dts -@@ -0,0 +1,59 @@ +@@ -0,0 +1,61 @@ +/* + * Definitions for Allo Boss DAC board + */ @@ -14706,8 +22473,8 @@ index 000000000000..873cb2fab52b + }; + }; + -+ fragment@1 { -+ target = <&i2s>; ++ frag1: fragment@1 { ++ target = <&i2s_clk_consumer>; + __overlay__ { + status = "okay"; + }; @@ -14734,7 +22501,7 @@ index 000000000000..873cb2fab52b + target = <&sound>; + boss_dac: __overlay__ { + compatible = "allo,boss-dac"; -+ i2s-controller = <&i2s>; ++ i2s-controller = <&i2s_clk_consumer>; + mute-gpios = <&gpio 6 1>; + status = "okay"; + }; @@ -14742,12 +22509,14 @@ index 000000000000..873cb2fab52b + + __overrides__ { + 24db_digital_gain = <&boss_dac>,"allo,24db_digital_gain?"; -+ slave = <&boss_dac>,"allo,slave?"; ++ slave = <&boss_dac>,"allo,slave?", ++ <&frag1>,"target:0=",<&i2s_clk_producer>, ++ <&boss_dac>,"i2s-controller:0=",<&i2s_clk_producer>; + }; +}; diff --git a/arch/arm/boot/dts/overlays/allo-boss2-dac-audio-overlay.dts b/arch/arm/boot/dts/overlays/allo-boss2-dac-audio-overlay.dts new file mode 100644 -index 000000000000..a6adfb495eb9 +index 000000000000..feac2b091b36 --- /dev/null +++ b/arch/arm/boot/dts/overlays/allo-boss2-dac-audio-overlay.dts @@ -0,0 +1,57 @@ @@ -14761,7 +22530,7 @@ index 000000000000..a6adfb495eb9 + compatible = "brcm,bcm2835"; + + fragment@0 { -+ target = <&i2s>; ++ target = <&i2s_clk_consumer>; + __overlay__ { + #sound-dai-cells = <0>; + status = "okay"; @@ -14810,7 +22579,7 @@ index 000000000000..a6adfb495eb9 + diff --git a/arch/arm/boot/dts/overlays/allo-digione-overlay.dts b/arch/arm/boot/dts/overlays/allo-digione-overlay.dts new file mode 100644 -index 000000000000..ea018ace34d4 +index 000000000000..61c3c2e9fbd8 --- /dev/null +++ b/arch/arm/boot/dts/overlays/allo-digione-overlay.dts @@ -0,0 +1,44 @@ @@ -14822,7 +22591,7 @@ index 000000000000..ea018ace34d4 + compatible = "brcm,bcm2835"; + + fragment@0 { -+ target = <&i2s>; ++ target = <&i2s_clk_consumer>; + __overlay__ { + status = "okay"; + }; @@ -14851,7 +22620,7 @@ index 000000000000..ea018ace34d4 + target = <&sound>; + __overlay__ { + compatible = "allo,allo-digione"; -+ i2s-controller = <&i2s>; ++ i2s-controller = <&i2s_clk_consumer>; + status = "okay"; + clock44-gpio = <&gpio 5 0>; + clock48-gpio = <&gpio 6 0>; @@ -14860,10 +22629,10 @@ index 000000000000..ea018ace34d4 +}; diff --git a/arch/arm/boot/dts/overlays/allo-katana-dac-audio-overlay.dts b/arch/arm/boot/dts/overlays/allo-katana-dac-audio-overlay.dts new file mode 100644 -index 000000000000..b25fd681f09f +index 000000000000..1ebb6bc6b907 --- /dev/null +++ b/arch/arm/boot/dts/overlays/allo-katana-dac-audio-overlay.dts -@@ -0,0 +1,57 @@ +@@ -0,0 +1,58 @@ +/* + * Definitions for Allo Katana DAC boards + */ @@ -14875,7 +22644,7 @@ index 000000000000..b25fd681f09f + compatible = "brcm,bcm2835"; + + fragment@0 { -+ target = <&i2s>; ++ target = <&i2s_clk_consumer>; + __overlay__ { + #sound-dai-cells = <0>; + status = "okay"; @@ -14896,6 +22665,7 @@ index 000000000000..b25fd681f09f + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; ++ clock-frequency = <50000>; + + allo-katana-codec@30 { + #sound-dai-cells = <0>; @@ -14923,7 +22693,7 @@ index 000000000000..b25fd681f09f + diff --git a/arch/arm/boot/dts/overlays/allo-piano-dac-pcm512x-audio-overlay.dts b/arch/arm/boot/dts/overlays/allo-piano-dac-pcm512x-audio-overlay.dts new file mode 100644 -index 000000000000..bfc66da6295a +index 000000000000..1b79ef1df2a1 --- /dev/null +++ b/arch/arm/boot/dts/overlays/allo-piano-dac-pcm512x-audio-overlay.dts @@ -0,0 +1,54 @@ @@ -14945,7 +22715,7 @@ index 000000000000..bfc66da6295a + compatible = "brcm,bcm2835"; + + fragment@0 { -+ target = <&i2s>; ++ target = <&i2s_clk_producer>; + __overlay__ { + status = "okay"; + }; @@ -14971,7 +22741,7 @@ index 000000000000..bfc66da6295a + target = <&sound>; + piano_dac: __overlay__ { + compatible = "allo,piano-dac"; -+ i2s-controller = <&i2s>; ++ i2s-controller = <&i2s_clk_producer>; + status = "okay"; + }; + }; @@ -14983,7 +22753,7 @@ index 000000000000..bfc66da6295a +}; diff --git a/arch/arm/boot/dts/overlays/allo-piano-dac-plus-pcm512x-audio-overlay.dts b/arch/arm/boot/dts/overlays/allo-piano-dac-plus-pcm512x-audio-overlay.dts new file mode 100644 -index 000000000000..d47a35def4f7 +index 000000000000..d17c9c10df39 --- /dev/null +++ b/arch/arm/boot/dts/overlays/allo-piano-dac-plus-pcm512x-audio-overlay.dts @@ -0,0 +1,57 @@ @@ -14995,7 +22765,7 @@ index 000000000000..d47a35def4f7 + compatible = "brcm,bcm2835"; + + fragment@0 { -+ target = <&i2s>; ++ target = <&i2s_clk_producer>; + __overlay__ { + status = "okay"; + }; @@ -15030,7 +22800,7 @@ index 000000000000..d47a35def4f7 + piano_dac: __overlay__ { + compatible = "allo,piano-dac-plus"; + audio-codec = <&allo_pcm5122_4c &allo_pcm5122_4d>; -+ i2s-controller = <&i2s>; ++ i2s-controller = <&i2s_clk_producer>; + mute1-gpios = <&gpio 6 1>; + mute2-gpios = <&gpio 25 1>; + status = "okay"; @@ -15257,10 +23027,10 @@ index 000000000000..87523dcca318 +}; diff --git a/arch/arm/boot/dts/overlays/apds9960-overlay.dts b/arch/arm/boot/dts/overlays/apds9960-overlay.dts new file mode 100644 -index 000000000000..c216932278ab +index 000000000000..bb18cca1ac66 --- /dev/null +++ b/arch/arm/boot/dts/overlays/apds9960-overlay.dts -@@ -0,0 +1,57 @@ +@@ -0,0 +1,55 @@ +// Definitions for APDS-9960 ambient light and gesture sensor + +/dts-v1/; @@ -15287,6 +23057,15 @@ index 000000000000..c216932278ab + }; + + fragment@2 { ++ target = <&apds9960>; ++ apds9960_irq: __overlay__ { ++ #interrupt-cells = <2>; ++ interrupt-parent = <&gpio>; ++ interrupts = <4 1>; ++ }; ++ }; ++ ++ fragment@3 { + target = <&i2c1>; + __overlay__ { + #address-cells = <1>; @@ -15300,27 +23079,16 @@ index 000000000000..c216932278ab + }; + }; + -+ fragment@3 { -+ target = <&i2c1>; -+ __overlay__ { -+ apds9960_irq: apds@39 { -+ #interrupt-cells=<2>; -+ interrupt-parent = <&gpio>; -+ interrupts = <4 1>; -+ }; -+ }; -+ }; -+ + __overrides__ { + gpiopin = <&apds9960_pins>,"brcm,pins:0", + <&apds9960_irq>,"interrupts:0"; -+ noints = <0>,"!1!3"; ++ noints = <0>,"!1!2"; + }; +}; + diff --git a/arch/arm/boot/dts/overlays/applepi-dac-overlay.dts b/arch/arm/boot/dts/overlays/applepi-dac-overlay.dts new file mode 100644 -index 000000000000..4769296ec9d6 +index 000000000000..cb7649d3a613 --- /dev/null +++ b/arch/arm/boot/dts/overlays/applepi-dac-overlay.dts @@ -0,0 +1,57 @@ @@ -15342,7 +23110,7 @@ index 000000000000..4769296ec9d6 + format = "i2s"; + + p_cpu_dai: cpu { -+ sound-dai = <&i2s>; ++ sound-dai = <&i2s_clk_producer>; + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <32>; + }; @@ -15366,7 +23134,7 @@ index 000000000000..4769296ec9d6 + }; + + fragment@2 { -+ target = <&i2s>; ++ target = <&i2s_clk_producer>; + __overlay__ { + #sound-dai-cells = <0>; + status = "okay"; @@ -15381,6 +23149,243 @@ index 000000000000..4769296ec9d6 + compile with: + dtc -@ -H epapr -O dtb -o ApplePi-DAC.dtbo -W no-unit_address_vs_reg ApplePi-DAC.dts +*/ +diff --git a/arch/arm/boot/dts/overlays/arducam-64mp-overlay.dts b/arch/arm/boot/dts/overlays/arducam-64mp-overlay.dts +new file mode 100644 +index 000000000000..02f01729a759 +--- /dev/null ++++ b/arch/arm/boot/dts/overlays/arducam-64mp-overlay.dts +@@ -0,0 +1,91 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++// Definitions for Arducam 64MP camera module on VC I2C bus ++/dts-v1/; ++/plugin/; ++ ++/{ ++ compatible = "brcm,bcm2835"; ++ ++ i2c_frag: fragment@0 { ++ target = <&i2c_csi_dsi>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "okay"; ++ ++ #include "arducam-64mp.dtsi" ++ }; ++ }; ++ ++ csi_frag: fragment@1 { ++ target = <&csi1>; ++ csi: __overlay__ { ++ status = "okay"; ++ brcm,media-controller; ++ ++ port{ ++ csi_ep: endpoint{ ++ remote-endpoint = <&cam_endpoint>; ++ clock-lanes = <0>; ++ data-lanes = <1 2>; ++ clock-noncontinuous; ++ }; ++ }; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&i2c0if>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++ ++ clk_frag: fragment@3 { ++ target = <&cam1_clk>; ++ __overlay__ { ++ clock-frequency = <24000000>; ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@4 { ++ target = <&i2c0mux>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@5 { ++ target = <&cam_node>; ++ __overlay__ { ++ lens-focus = <&vcm_node>; ++ }; ++ }; ++ ++ __overrides__ { ++ rotation = <&cam_node>,"rotation:0"; ++ orientation = <&cam_node>,"orientation:0"; ++ media-controller = <&csi>,"brcm,media-controller?"; ++ cam0 = <&i2c_frag>, "target:0=",<&i2c_csi_dsi0>, ++ <&csi_frag>, "target:0=",<&csi0>, ++ <&clk_frag>, "target:0=",<&cam0_clk>, ++ <&cam_node>, "clocks:0=",<&cam0_clk>, ++ <&cam_node>, "VANA-supply:0=",<&cam0_reg>, ++ <&vcm_node>, "VDD-supply:0=", <&cam0_reg>; ++ vcm = <&vcm_node>, "status", ++ <0>, "=5"; ++ }; ++}; ++ ++&cam_node { ++ status = "okay"; ++}; ++ ++&cam_endpoint { ++ remote-endpoint = <&csi_ep>; ++}; ++ ++&vcm_node { ++ status = "okay"; ++}; +diff --git a/arch/arm/boot/dts/overlays/arducam-64mp.dtsi b/arch/arm/boot/dts/overlays/arducam-64mp.dtsi +new file mode 100644 +index 000000000000..ed9f2e50c287 +--- /dev/null ++++ b/arch/arm/boot/dts/overlays/arducam-64mp.dtsi +@@ -0,0 +1,34 @@ ++// Fragment that configures a Arducam64MP ++ ++cam_node: arducam_64mp@1a { ++ compatible = "arducam,64mp"; ++ reg = <0x1a>; ++ status = "disabled"; ++ ++ clocks = <&cam1_clk>; ++ clock-names = "xclk"; ++ ++ VANA-supply = <&cam1_reg>; /* 2.8v */ ++ VDIG-supply = <&cam_dummy_reg>; /* 1.8v */ ++ VDDL-supply = <&cam_dummy_reg>; /* 1.2v */ ++ ++ rotation = <0>; ++ orientation = <2>; ++ ++ port { ++ cam_endpoint: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2>; ++ clock-noncontinuous; ++ link-frequencies = ++ /bits/ 64 <456000000>; ++ }; ++ }; ++}; ++ ++vcm_node: dw9817_arducam64mp@c { ++ compatible = "dongwoon,dw9817-vcm"; ++ reg = <0x0c>; ++ status = "disabled"; ++ VDD-supply = <&cam1_reg>; ++}; +diff --git a/arch/arm/boot/dts/overlays/arducam-pivariety-overlay.dts b/arch/arm/boot/dts/overlays/arducam-pivariety-overlay.dts +new file mode 100644 +index 000000000000..fab27a56db6e +--- /dev/null ++++ b/arch/arm/boot/dts/overlays/arducam-pivariety-overlay.dts +@@ -0,0 +1,94 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++// Definitions for Arducam Pivariety camera module on VC I2C bus ++/dts-v1/; ++/plugin/; ++ ++/{ ++ compatible = "brcm,bcm2835"; ++ ++ i2c_frag: fragment@0 { ++ target = <&i2c_csi_dsi>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "okay"; ++ ++ arducam_pivariety: arducam_pivariety@c { ++ compatible = "arducam,arducam-pivariety"; ++ reg = <0x0c>; ++ status = "okay"; ++ ++ clocks = <&cam1_clk>; ++ clock-names = "xclk"; ++ ++ VANA-supply = <&cam1_reg>; /* 2.8v */ ++ VDIG-supply = <&cam_dummy_reg>; /* 1.8v */ ++ VDDL-supply = <&cam_dummy_reg>; /* 1.2v */ ++ ++ rotation = <0>; ++ orientation = <2>; ++ ++ port { ++ arducam_pivariety_0: endpoint { ++ remote-endpoint = <&csi1_ep>; ++ clock-lanes = <0>; ++ data-lanes = <1 2>; ++ clock-noncontinuous; ++ link-frequencies = ++ /bits/ 64 <493500000>; ++ }; ++ }; ++ }; ++ }; ++ }; ++ ++ csi_frag: fragment@1 { ++ target = <&csi1>; ++ csi: __overlay__ { ++ status = "okay"; ++ brcm,media-controller; ++ ++ port{ ++ csi1_ep: endpoint{ ++ remote-endpoint = <&arducam_pivariety_0>; ++ clock-lanes = <0>; ++ data-lanes = <1 2>; ++ clock-noncontinuous; ++ }; ++ }; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&i2c0if>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++ ++ clk_frag: fragment@3 { ++ target = <&cam1_clk>; ++ __overlay__ { ++ clock-frequency = <24000000>; ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@4 { ++ target = <&i2c0mux>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++ ++ __overrides__ { ++ rotation = <&arducam_pivariety>,"rotation:0"; ++ orientation = <&arducam_pivariety>,"orientation:0"; ++ media-controller = <&csi>,"brcm,media-controller?"; ++ cam0 = <&i2c_frag>, "target:0=",<&i2c_csi_dsi0>, ++ <&csi_frag>, "target:0=",<&csi0>, ++ <&clk_frag>, "target:0=",<&cam0_clk>, ++ <&arducam_pivariety>, "clocks:0=",<&cam0_clk>, ++ <&arducam_pivariety>, "VANA-supply:0=",<&cam0_reg>; ++ }; ++}; diff --git a/arch/arm/boot/dts/overlays/at86rf233-overlay.dts b/arch/arm/boot/dts/overlays/at86rf233-overlay.dts new file mode 100644 index 000000000000..5a3f4571ee78 @@ -15446,7 +23451,7 @@ index 000000000000..5a3f4571ee78 +}; diff --git a/arch/arm/boot/dts/overlays/audioinjector-addons-overlay.dts b/arch/arm/boot/dts/overlays/audioinjector-addons-overlay.dts new file mode 100644 -index 000000000000..57a66eac8e9b +index 000000000000..af72ea0b706a --- /dev/null +++ b/arch/arm/boot/dts/overlays/audioinjector-addons-overlay.dts @@ -0,0 +1,60 @@ @@ -15458,7 +23463,7 @@ index 000000000000..57a66eac8e9b + compatible = "brcm,bcm2835"; + + fragment@0 { -+ target = <&i2s>; ++ target = <&i2s_clk_producer>; + __overlay__ { + status = "okay"; + }; @@ -15500,7 +23505,7 @@ index 000000000000..57a66eac8e9b + mult-gpios = <&gpio 27 0>, <&gpio 22 0>, <&gpio 23 0>, + <&gpio 24 0>; + reset-gpios = <&gpio 5 0>; -+ i2s-controller = <&i2s>; ++ i2s-controller = <&i2s_clk_producer>; + codec = <&cs42448>; + status = "okay"; + }; @@ -15510,9 +23515,65 @@ index 000000000000..57a66eac8e9b + non-stop-clocks = <&snd>, "non-stop-clocks?"; + }; +}; +diff --git a/arch/arm/boot/dts/overlays/audioinjector-bare-i2s-overlay.dts b/arch/arm/boot/dts/overlays/audioinjector-bare-i2s-overlay.dts +new file mode 100644 +index 000000000000..a536fbb1a985 +--- /dev/null ++++ b/arch/arm/boot/dts/overlays/audioinjector-bare-i2s-overlay.dts +@@ -0,0 +1,50 @@ ++// Definitions for audioinjector.net audio soundcard ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "brcm,bcm2835"; ++ ++ fragment@0 { ++ target = <&i2s_clk_producer>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@1 { ++ target-path = "/"; ++ __overlay__ { ++ codec_bare: codec_bare { ++ compatible = "linux,spdif-dit"; ++ #sound-dai-cells = <0>; ++ status = "okay"; ++ }; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&sound>; ++ __overlay__ { ++ compatible = "simple-audio-card"; ++ i2s-controller = <&i2s_clk_producer>; ++ status = "okay"; ++ ++ simple-audio-card,name = "audioinjector-bare"; ++ simple-audio-card,format = "i2s"; ++ ++ simple-audio-card,bitclock-master = <&dailink0_master>; ++ simple-audio-card,frame-master = <&dailink0_master>; ++ ++ dailink0_master: simple-audio-card,cpu { ++ sound-dai = <&i2s_clk_producer>; ++ dai-tdm-slot-num = <2>; ++ dai-tdm-slot-width = <32>; ++ }; ++ ++ snd_codec: simple-audio-card,codec { ++ sound-dai = <&codec_bare>; ++ }; ++ }; ++ }; ++}; diff --git a/arch/arm/boot/dts/overlays/audioinjector-isolated-soundcard-overlay.dts b/arch/arm/boot/dts/overlays/audioinjector-isolated-soundcard-overlay.dts new file mode 100644 -index 000000000000..63e05cf9665d +index 000000000000..89faed778fcb --- /dev/null +++ b/arch/arm/boot/dts/overlays/audioinjector-isolated-soundcard-overlay.dts @@ -0,0 +1,55 @@ @@ -15524,7 +23585,7 @@ index 000000000000..63e05cf9665d + compatible = "brcm,bcm2835"; + + fragment@0 { -+ target = <&i2s>; ++ target = <&i2s_clk_consumer>; + __overlay__ { + status = "okay"; + }; @@ -15565,7 +23626,7 @@ index 000000000000..63e05cf9665d + snd: __overlay__ { + compatible = "ai,audioinjector-isolated-soundcard"; + mute-gpios = <&gpio 17 0>; -+ i2s-controller = <&i2s>; ++ i2s-controller = <&i2s_clk_consumer>; + codec = <&cs4272>; + status = "okay"; + }; @@ -15573,7 +23634,7 @@ index 000000000000..63e05cf9665d +}; diff --git a/arch/arm/boot/dts/overlays/audioinjector-ultra-overlay.dts b/arch/arm/boot/dts/overlays/audioinjector-ultra-overlay.dts new file mode 100644 -index 000000000000..fb4a4678a17a +index 000000000000..ee79441187bd --- /dev/null +++ b/arch/arm/boot/dts/overlays/audioinjector-ultra-overlay.dts @@ -0,0 +1,71 @@ @@ -15585,7 +23646,7 @@ index 000000000000..fb4a4678a17a + compatible = "brcm,bcm2835"; + + fragment@0 { -+ target = <&i2s>; ++ target = <&i2s_clk_consumer>; + __overlay__ { + status = "okay"; + }; @@ -15612,7 +23673,7 @@ index 000000000000..fb4a4678a17a + target = <&sound>; + __overlay__ { + compatible = "simple-audio-card"; -+ i2s-controller = <&i2s>; ++ i2s-controller = <&i2s_clk_consumer>; + status = "okay"; + + simple-audio-card,name = "audioinjector-ultra"; @@ -15636,7 +23697,7 @@ index 000000000000..fb4a4678a17a + simple-audio-card,frame-master = <&sound_master>; + + simple-audio-card,cpu { -+ sound-dai = <&i2s>; ++ sound-dai = <&i2s_clk_consumer>; + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <32>; + }; @@ -15650,7 +23711,7 @@ index 000000000000..fb4a4678a17a +}; diff --git a/arch/arm/boot/dts/overlays/audioinjector-wm8731-audio-overlay.dts b/arch/arm/boot/dts/overlays/audioinjector-wm8731-audio-overlay.dts new file mode 100644 -index 000000000000..68f4427d86c3 +index 000000000000..417353b2798e --- /dev/null +++ b/arch/arm/boot/dts/overlays/audioinjector-wm8731-audio-overlay.dts @@ -0,0 +1,39 @@ @@ -15662,7 +23723,7 @@ index 000000000000..68f4427d86c3 + compatible = "brcm,bcm2835"; + + fragment@0 { -+ target = <&i2s>; ++ target = <&i2s_clk_consumer>; + __overlay__ { + status = "okay"; + }; @@ -15688,14 +23749,14 @@ index 000000000000..68f4427d86c3 + target = <&sound>; + __overlay__ { + compatible = "ai,audioinjector-pi-soundcard"; -+ i2s-controller = <&i2s>; ++ i2s-controller = <&i2s_clk_consumer>; + status = "okay"; + }; + }; +}; diff --git a/arch/arm/boot/dts/overlays/audiosense-pi-overlay.dts b/arch/arm/boot/dts/overlays/audiosense-pi-overlay.dts new file mode 100644 -index 000000000000..81af26374d92 +index 000000000000..a89d38b2fe19 --- /dev/null +++ b/arch/arm/boot/dts/overlays/audiosense-pi-overlay.dts @@ -0,0 +1,82 @@ @@ -15709,7 +23770,7 @@ index 000000000000..81af26374d92 + compatible = "brcm,bcm2835"; + + fragment@0 { -+ target = <&i2s>; ++ target = <&i2s_clk_consumer>; + __overlay__ { + status = "okay"; + }; @@ -15776,17 +23837,17 @@ index 000000000000..81af26374d92 + target = <&sound>; + __overlay__ { + compatible = "as,audiosense-pi"; -+ i2s-controller = <&i2s>; ++ i2s-controller = <&i2s_clk_consumer>; + status = "okay"; + }; + }; +}; diff --git a/arch/arm/boot/dts/overlays/audremap-overlay.dts b/arch/arm/boot/dts/overlays/audremap-overlay.dts new file mode 100644 -index 000000000000..7324890ead86 +index 000000000000..95027c5c8f9e --- /dev/null +++ b/arch/arm/boot/dts/overlays/audremap-overlay.dts -@@ -0,0 +1,42 @@ +@@ -0,0 +1,38 @@ +/dts-v1/; +/plugin/; + @@ -15796,42 +23857,38 @@ index 000000000000..7324890ead86 + fragment@0 { + target = <&audio_pins>; + frag0: __overlay__ { ++ brcm,pins = <12 13>; ++ brcm,function = <4>; /* alt0 alt0 */ + }; + }; + + fragment@1 { -+ target = <&audio_pins>; -+ __overlay__ { -+ brcm,pins = < 12 13 >; -+ brcm,function = < 4 >; /* alt0 alt0 */ -+ }; -+ }; -+ -+ fragment@2 { -+ target = <&audio_pins>; -+ __dormant__ { -+ brcm,pins = < 18 19 >; -+ brcm,function = < 2 >; /* alt5 alt5 */ -+ }; -+ }; -+ -+ fragment@3 { -+ target = <&audio>; ++ target = <&chosen>; + __overlay__ { -+ brcm,disable-headphones = <0>; ++ bootargs = "snd_bcm2835.enable_headphones=1"; + }; + }; + + __overrides__ { + swap_lr = <&frag0>, "swap_lr?"; + enable_jack = <&frag0>, "enable_jack?"; -+ pins_12_13 = <0>,"+1-2"; -+ pins_18_19 = <0>,"-1+2"; ++ pins_12_13 = <&frag0>,"brcm,pins:0=12", ++ <&frag0>,"brcm,pins:4=13", ++ <&frag0>,"brcm,function:0=4"; ++ pins_18_19 = <&frag0>,"brcm,pins:0=18", ++ <&frag0>,"brcm,pins:4=19", ++ <&frag0>,"brcm,function:0=2"; ++ pins_40_41 = <&frag0>,"brcm,pins:0=40", ++ <&frag0>,"brcm,pins:4=41", ++ <&frag0>,"brcm,function:0=4"; ++ pins_40_45 = <&frag0>,"brcm,pins:0=40", ++ <&frag0>,"brcm,pins:4=45", ++ <&frag0>,"brcm,function:0=4"; + }; +}; diff --git a/arch/arm/boot/dts/overlays/balena-fin-overlay.dts b/arch/arm/boot/dts/overlays/balena-fin-overlay.dts new file mode 100644 -index 000000000000..e7ead7cdf5f5 +index 000000000000..8fc22587e69c --- /dev/null +++ b/arch/arm/boot/dts/overlays/balena-fin-overlay.dts @@ -0,0 +1,125 @@ @@ -15857,7 +23914,7 @@ index 000000000000..e7ead7cdf5f5 + fragment@1 { + target = <&gpio>; + __overlay__ { -+ sdio_pins: sdio_pins { ++ sdio_pins: sdio_ovl_pins { + brcm,pins = <34 35 36 37 38 39>; + brcm,function = <7>; /* ALT3 = SD1 */ + brcm,pull = <0 2 2 2 2 2>; @@ -15960,6 +24017,1596 @@ index 000000000000..e7ead7cdf5f5 + }; + }; +}; +diff --git a/arch/arm/boot/dts/overlays/bcm2712d0-overlay.dts b/arch/arm/boot/dts/overlays/bcm2712d0-overlay.dts +new file mode 100644 +index 000000000000..8f9c6a887064 +--- /dev/null ++++ b/arch/arm/boot/dts/overlays/bcm2712d0-overlay.dts +@@ -0,0 +1,75 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/dts-v1/; ++/plugin/; ++ ++#include ++#include ++ ++/ { ++ compatible = "brcm,bcm2712"; ++ ++ fragment@0 { ++ target = <&gio>; ++ __overlay__ { ++ brcm,gpio-bank-widths = <32 4>; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&gio_aon>; ++ __overlay__ { ++ brcm,gpio-bank-widths = <15 6>; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&pinctrl>; ++ __overlay__ { ++ compatible = "brcm,bcm2712d0-pinctrl"; ++ reg = <0x7d504100 0x20>; ++ }; ++ }; ++ ++ fragment@3 { ++ target = <&pinctrl_aon>; ++ __overlay__ { ++ compatible = "brcm,bcm2712d0-aon-pinctrl"; ++ reg = <0x7d510700 0x1c>; ++ }; ++ }; ++ ++ fragment@4 { ++ target = <&vc4>; ++ __overlay__ { ++ compatible = "brcm,bcm2712d0-vc6"; ++ }; ++ }; ++ ++ fragment@5 { ++ target = <&uart10>; ++ __overlay__ { ++ interrupts = ; ++ }; ++ }; ++ ++ fragment@6 { ++ target = <&spi10>; ++ __overlay__ { ++ dmas = <&dma40 3>, <&dma40 4>; ++ }; ++ }; ++ ++ fragment@7 { ++ target = <&hdmi0>; ++ __overlay__ { ++ dmas = <&dma40 (12|(1<<30)|(1<<24)|(10<<16)|(15<<20))>; ++ }; ++ }; ++ ++ fragment@8 { ++ target = <&hdmi1>; ++ __overlay__ { ++ dmas = <&dma40 (13|(1<<30)|(1<<24)|(10<<16)|(15<<20))>; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlays/camera-mux-2port-overlay.dts b/arch/arm/boot/dts/overlays/camera-mux-2port-overlay.dts +new file mode 100644 +index 000000000000..13d86cc693b3 +--- /dev/null ++++ b/arch/arm/boot/dts/overlays/camera-mux-2port-overlay.dts +@@ -0,0 +1,545 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++// Overlay to configure a 2 port camera multiplexer ++// ++// Configuration is based on the Arducam Doubleplexer ++// which uses a PCA9543 I2C multiplexer to handle the ++// I2C, and GPIO 4 to control the MIPI mux, and GPIO 17 ++// to enable the CSI-2 mux output (gpio-hog). ++ ++/dts-v1/; ++/plugin/; ++ ++#include ++ ++/{ ++ compatible = "brcm,bcm2835"; ++ ++ /* Fragments that complete the individual sensor fragments */ ++ /* IMX290 */ ++ fragment@0 { ++ target = <&imx290_0_ep>; ++ __overlay__ { ++ data-lanes = <1 2>; ++ link-frequencies = ++ /bits/ 64 <445500000 297000000>; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&imx290_1_ep>; ++ __overlay__ { ++ data-lanes = <1 2>; ++ link-frequencies = ++ /bits/ 64 <445500000 297000000>; ++ }; ++ }; ++ ++ /* IMX477 */ ++ fragment@10 { ++ target = <&imx477_0>; ++ __overlay__ { ++ compatible = "sony,imx477"; ++ }; ++ }; ++ ++ fragment@11 { ++ target = <&imx477_1>; ++ __overlay__ { ++ compatible = "sony,imx477"; ++ }; ++ }; ++ ++ /* Additional fragments affecting the mux nodes */ ++ fragment@100 { ++ target = <&mux_in0>; ++ __dormant__ { ++ data-lanes = <1>; ++ }; ++ }; ++ fragment@101 { ++ target = <&mux_in0>; ++ __overlay__ { ++ data-lanes = <1 2>; ++ }; ++ }; ++ ++ fragment@102 { ++ target = <&mux_in1>; ++ __dormant__ { ++ data-lanes = <1>; ++ }; ++ }; ++ fragment@103 { ++ target = <&mux_in1>; ++ __overlay__ { ++ data-lanes = <1 2>; ++ }; ++ }; ++ ++ /* Mux define */ ++ i2c_frag: fragment@200 { ++ target = <&i2c_csi_dsi>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "okay"; ++ ++ pca@70 { ++ reg = <0x70>; ++ compatible = "nxp,pca9543"; ++ ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ i2c@0 { ++ reg = <0>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ #define cam_node arducam_64mp_0 ++ #define cam_endpoint arducam_64mp_0_ep ++ #define vcm_node arducam_64mp_0_vcm ++ #define cam1_clk clk_24mhz ++ #include "arducam-64mp.dtsi" ++ #undef cam_node ++ #undef cam_endpoint ++ #undef vcm_node ++ #undef cam1_clk ++ ++ #define cam_node imx219_0 ++ #define cam_endpoint imx219_0_ep ++ #define cam1_clk clk_24mhz ++ #include "imx219.dtsi" ++ #undef cam_node ++ #undef cam_endpoint ++ #undef cam1_clk ++ ++ #define cam_node imx477_0 ++ #define cam_endpoint imx477_0_ep ++ #define cam1_clk clk_24mhz ++ #include "imx477_378.dtsi" ++ #undef cam_node ++ #undef cam_endpoint ++ #undef cam1_clk ++ ++ #define cam_node imx519_0 ++ #define cam_endpoint imx519_0_ep ++ #define vcm_node imx519_0_vcm ++ #define cam1_clk clk_24mhz ++ #include "imx519.dtsi" ++ #undef cam_node ++ #undef cam_endpoint ++ #undef vcm_node ++ #undef cam1_clk ++ ++ #define cam_node imx708_0 ++ #define cam_endpoint imx708_0_ep ++ #define vcm_node imx708_0_vcm ++ #define cam1_clk clk_24mhz ++ #include "imx708.dtsi" ++ #undef cam_node ++ #undef cam_endpoint ++ #undef vcm_node ++ #undef cam1_clk ++ ++ #define cam_node ov5647_0 ++ #define cam_endpoint ov5647_0_ep ++ #define cam1_clk clk_25mhz ++ #include "ov5647.dtsi" ++ #undef cam_node ++ #undef cam_endpoint ++ #undef cam1_clk ++ ++ #define cam_node ov7251_0 ++ #define cam_endpoint ov7251_0_ep ++ #define cam1_clk clk_24mhz ++ #include "ov7251.dtsi" ++ #undef cam_node ++ #undef cam_endpoint ++ #undef cam1_clk ++ ++ #define cam_node ov9281_0 ++ #define cam_endpoint ov9281_0_ep ++ #define cam1_clk clk_24mhz ++ #include "ov9281.dtsi" ++ #undef cam_node ++ #undef cam_endpoint ++ #undef cam1_clk ++ ++ #define cam_node imx258_0 ++ #define cam_endpoint imx258_0_ep ++ #define cam1_clk clk_24mhz ++ #include "imx258.dtsi" ++ #undef cam_node ++ #undef cam_endpoint ++ #undef cam1_clk ++ ++ #define cam_node imx290_0 ++ #define cam_endpoint imx290_0_ep ++ #define cam1_clk clk_imx290 ++ #include "imx290_327.dtsi" ++ #undef cam_node ++ #undef cam_endpoint ++ #undef cam1_clk ++ ++ #define cam_node ov2311_0 ++ #define cam_endpoint ov2311_0_ep ++ #define cam1_clk clk_24mhz ++ #include "ov2311.dtsi" ++ #undef cam_node ++ #undef cam_endpoint ++ #undef cam1_clk ++ ++ #define cam_node ov64a40_0 ++ #define cam_endpoint ov64a40_0_ep ++ #define vcm_node ov64a40_0_vcm ++ #define cam1_clk clk_24mhz ++ #include "ov64a40.dtsi" ++ #undef cam_node ++ #undef cam_endpoint ++ #undef vcm_node ++ #undef cam1_clk ++ }; ++ ++ i2c@1 { ++ reg = <1>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ #define cam_node arducam_64mp_1 ++ #define cam_endpoint arducam_64mp_1_ep ++ #define vcm_node arducam_64mp_1_vcm ++ #define cam1_clk clk_24mhz ++ #include "arducam-64mp.dtsi" ++ #undef cam_node ++ #undef cam_endpoint ++ #undef vcm_node ++ #undef cam1_clk ++ ++ #define cam_node imx219_1 ++ #define cam_endpoint imx219_1_ep ++ #define cam1_clk clk_24mhz ++ #include "imx219.dtsi" ++ #undef cam_node ++ #undef cam_endpoint ++ #undef cam1_clk ++ ++ #define cam_node imx477_1 ++ #define cam_endpoint imx477_1_ep ++ #define cam1_clk clk_24mhz ++ #include "imx477_378.dtsi" ++ #undef cam_node ++ #undef cam_endpoint ++ #undef cam1_clk ++ ++ #define cam_node imx519_1 ++ #define cam_endpoint imx519_1_ep ++ #define vcm_node imx519_1_vcm ++ #define cam1_clk clk_24mhz ++ #include "imx519.dtsi" ++ #undef cam_node ++ #undef cam_endpoint ++ #undef vcm_node ++ #undef cam1_clk ++ ++ #define cam_node imx708_1 ++ #define cam_endpoint imx708_1_ep ++ #define vcm_node imx708_1_vcm ++ #define cam1_clk clk_24mhz ++ #include "imx708.dtsi" ++ #undef cam_node ++ #undef cam_endpoint ++ #undef vcm_node ++ #undef cam1_clk ++ ++ #define cam_node ov5647_1 ++ #define cam_endpoint ov5647_1_ep ++ #define cam1_clk clk_25mhz ++ #include "ov5647.dtsi" ++ #undef cam_node ++ #undef cam_endpoint ++ #undef cam1_clk ++ ++ #define cam_node ov7251_1 ++ #define cam_endpoint ov7251_1_ep ++ #define cam1_clk clk_24mhz ++ #include "ov7251.dtsi" ++ #undef cam_node ++ #undef cam_endpoint ++ #undef cam1_clk ++ ++ #define cam_node ov9281_1 ++ #define cam_endpoint ov9281_1_ep ++ #define cam1_clk clk_24mhz ++ #include "ov9281.dtsi" ++ #undef cam_node ++ #undef cam_endpoint ++ #undef cam1_clk ++ ++ #define cam_node imx258_1 ++ #define cam_endpoint imx258_1_ep ++ #define cam1_clk clk_24mhz ++ #include "imx258.dtsi" ++ #undef cam_node ++ #undef cam_endpoint ++ #undef cam1_clk ++ ++ #define cam_node imx290_1 ++ #define cam_endpoint imx290_1_ep ++ #define cam1_clk clk_imx290 ++ #include "imx290_327.dtsi" ++ #undef cam_node ++ #undef cam_endpoint ++ #undef cam1_clk ++ ++ #define cam_node ov2311_1 ++ #define cam_endpoint ov2311_1_ep ++ #define cam1_clk clk_24mhz ++ #include "ov2311.dtsi" ++ #undef cam_node ++ #undef cam_endpoint ++ #undef cam1_clk ++ ++ #define cam_node ov64a40_1 ++ #define cam_endpoint ov64a40_1_ep ++ #define vcm_node ov64a40_1_vcm ++ #define cam1_clk clk_24mhz ++ #include "ov64a40.dtsi" ++ #undef cam_node ++ #undef cam_endpoint ++ #undef vcm_node ++ #undef cam1_clk ++ }; ++ }; ++ }; ++ }; ++ ++ csi_frag: fragment@201 { ++ target = <&csi1>; ++ __overlay__ { ++ status = "okay"; ++ ++ brcm,media-controller; ++ ++ port { ++ csi1_ep: endpoint { ++ remote-endpoint = <&mux_out>; ++ clock-lanes = <0>; ++ data-lanes = <1 2>; ++ }; ++ }; ++ }; ++ }; ++ ++ fragment@202 { ++ target = <&i2c0if>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@203 { ++ target-path="/"; ++ __overlay__ { ++ mux: mux-controller { ++ compatible = "gpio-mux"; ++ #mux-control-cells = <0>; ++ ++ mux-gpios = <&gpio 4 GPIO_ACTIVE_HIGH>; ++ }; ++ ++ video-mux { ++ compatible = "video-mux"; ++ mux-controls = <&mux>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ port@0 { ++ reg = <0>; ++ ++ mux_in0: endpoint { ++ clock-lanes = <0>; ++ }; ++ }; ++ ++ port@1 { ++ reg = <1>; ++ ++ mux_in1: endpoint { ++ clock-lanes = <0>; ++ }; ++ }; ++ ++ port@2 { ++ reg = <2>; ++ ++ mux_out: endpoint { ++ remote-endpoint = <&csi1_ep>; ++ clock-lanes = <0>; ++ }; ++ }; ++ }; ++ ++ clk_24mhz: clk_24mhz { ++ compatible = "fixed-clock"; ++ #clock-cells = <0>; ++ ++ clock-frequency = <24000000>; ++ status = "okay"; ++ }; ++ ++ clk_25mhz: clk_25mhz { ++ compatible = "fixed-clock"; ++ #clock-cells = <0>; ++ ++ clock-frequency = <25000000>; ++ status = "okay"; ++ }; ++ ++ clk_imx290: clk_imx290 { ++ compatible = "fixed-clock"; ++ #clock-cells = <0>; ++ ++ clock-frequency = <37125000>; ++ status = "okay"; ++ }; ++ }; ++ }; ++ ++ fragment@204 { ++ target = <&i2c0mux>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@205 { ++ target = <&gpio>; ++ __overlay__ { ++ mipi_sw_oe_hog { ++ gpio-hog; ++ gpios = <17 GPIO_ACTIVE_LOW>; ++ output-high; ++ }; ++ }; ++ }; ++ ++ __overrides__ { ++ cam0-arducam-64mp = <&mux_in0>, "remote-endpoint:0=",<&arducam_64mp_0_ep>, ++ <&arducam_64mp_0_ep>, "remote-endpoint:0=",<&mux_in0>, ++ <&mux_in0>, "clock-noncontinuous?", ++ <&arducam_64mp_0>, "status=okay", ++ <&arducam_64mp_0_vcm>, "status=okay", ++ <&arducam_64mp_0>,"lens-focus:0=", <&arducam_64mp_0_vcm>; ++ cam0-imx219 = <&mux_in0>, "remote-endpoint:0=",<&imx219_0_ep>, ++ <&imx219_0_ep>, "remote-endpoint:0=",<&mux_in0>, ++ <&mux_in0>, "clock-noncontinuous?", ++ <&imx219_0>, "status=okay"; ++ cam0-imx477 = <&mux_in0>, "remote-endpoint:0=",<&imx477_0_ep>, ++ <&imx477_0_ep>, "remote-endpoint:0=",<&mux_in0>, ++ <&mux_in0>, "clock-noncontinuous?", ++ <&imx477_0>, "status=okay"; ++ cam0-imx519 = <&mux_in0>, "remote-endpoint:0=",<&imx519_0_ep>, ++ <&imx519_0_ep>, "remote-endpoint:0=",<&mux_in0>, ++ <&mux_in0>, "clock-noncontinuous?", ++ <&imx519_0>, "status=okay", ++ <&imx519_0_vcm>, "status=okay", ++ <&imx519_0>,"lens-focus:0=", <&imx519_0_vcm>; ++ cam0-imx708 = <&mux_in0>, "remote-endpoint:0=",<&imx708_0_ep>, ++ <&imx708_0_ep>, "remote-endpoint:0=",<&mux_in0>, ++ <&mux_in0>, "clock-noncontinuous?", ++ <&imx708_0>, "status=okay", ++ <&imx708_0_vcm>, "status=okay", ++ <&imx708_0>,"lens-focus:0=", <&imx708_0_vcm>; ++ cam0-ov5647 = <&mux_in0>, "remote-endpoint:0=",<&ov5647_0_ep>, ++ <&ov5647_0_ep>, "remote-endpoint:0=",<&mux_in0>, ++ <&ov5647_0>, "status=okay"; ++ cam0-ov7251 = <&mux_in0>, "remote-endpoint:0=",<&ov7251_0_ep>, ++ <&ov7251_0_ep>, "remote-endpoint:0=",<&mux_in0>, ++ <&ov7251_0>, "status=okay", ++ <0>,"+100-101"; ++ cam0-ov9281 = <&mux_in0>, "remote-endpoint:0=",<&ov9281_0_ep>, ++ <&ov9281_0_ep>, "remote-endpoint:0=",<&mux_in0>, ++ <&ov9281_0>, "status=okay"; ++ cam0-imx258 = <&mux_in0>, "remote-endpoint:0=",<&imx258_0_ep>, ++ <&imx258_0_ep>, "remote-endpoint:0=",<&mux_in0>, ++ <&imx258_0>, "status=okay"; ++ cam0-imx290 = <&mux_in0>, "remote-endpoint:0=",<&imx290_0_ep>, ++ <&imx290_0_ep>, "remote-endpoint:0=",<&mux_in0>, ++ <&imx290_0>, "status=okay"; ++ cam0-ov2311 = <&mux_in0>, "remote-endpoint:0=",<&ov2311_0_ep>, ++ <&ov2311_0_ep>, "remote-endpoint:0=",<&mux_in0>, ++ <&ov2311_0>, "status=okay"; ++ cam0-ov64a40 = <&mux_in0>, "remote-endpoint:0=",<&ov64a40_0_ep>, ++ <&ov64a40_0_ep>, "remote-endpoint:0=",<&mux_in0>, ++ <&mux_in0>, "clock-noncontinuous?", ++ <&ov64a40_0>, "status=okay", ++ <&ov64a40_0_vcm>, "status=okay", ++ <&ov64a40_0>,"lens-focus:0=", <&ov64a40_0_vcm>; ++ ++ cam1-arducam-64mp = <&mux_in1>, "remote-endpoint:0=",<&arducam_64mp_1_ep>, ++ <&arducam_64mp_1_ep>, "remote-endpoint:0=",<&mux_in1>, ++ <&mux_in1>, "clock-noncontinuous?", ++ <&arducam_64mp_1>, "status=okay", ++ <&arducam_64mp_1_vcm>, "status=okay", ++ <&arducam_64mp_1>,"lens-focus:0=", <&arducam_64mp_1_vcm>; ++ cam1-imx219 = <&mux_in1>, "remote-endpoint:0=",<&imx219_1_ep>, ++ <&imx219_1_ep>, "remote-endpoint:0=",<&mux_in1>, ++ <&mux_in1>, "clock-noncontinuous?", ++ <&imx219_1>, "status=okay"; ++ cam1-imx477 = <&mux_in1>, "remote-endpoint:0=",<&imx477_1_ep>, ++ <&imx477_1_ep>, "remote-endpoint:0=",<&mux_in1>, ++ <&mux_in1>, "clock-noncontinuous?", ++ <&imx477_1>, "status=okay"; ++ cam1-imx519 = <&mux_in1>, "remote-endpoint:0=",<&imx519_1_ep>, ++ <&imx519_1_ep>, "remote-endpoint:0=",<&mux_in1>, ++ <&mux_in1>, "clock-noncontinuous?", ++ <&imx519_1>, "status=okay", ++ <&imx519_1_vcm>, "status=okay", ++ <&imx519_1>,"lens-focus:0=", <&imx519_1_vcm>; ++ cam1-imx708 = <&mux_in1>, "remote-endpoint:0=",<&imx708_1_ep>, ++ <&imx708_1_ep>, "remote-endpoint:0=",<&mux_in1>, ++ <&mux_in1>, "clock-noncontinuous?", ++ <&imx708_1>, "status=okay", ++ <&imx708_1_vcm>, "status=okay", ++ <&imx708_1>,"lens-focus:0=", <&imx708_1_vcm>; ++ cam1-ov5647 = <&mux_in1>, "remote-endpoint:0=",<&ov5647_1_ep>, ++ <&ov5647_1_ep>, "remote-endpoint:0=",<&mux_in1>, ++ <&ov5647_1>, "status=okay"; ++ cam1-ov7251 = <&mux_in1>, "remote-endpoint:0=",<&ov7251_1_ep>, ++ <&ov7251_1_ep>, "remote-endpoint:0=",<&mux_in1>, ++ <&ov7251_1>, "status=okay", ++ <0>,"+102-103"; ++ cam1-ov9281 = <&mux_in1>, "remote-endpoint:0=",<&ov9281_1_ep>, ++ <&ov9281_1_ep>, "remote-endpoint:0=",<&mux_in1>, ++ <&ov9281_1>, "status=okay"; ++ cam1-imx258 = <&mux_in1>, "remote-endpoint:0=",<&imx258_1_ep>, ++ <&imx258_1_ep>, "remote-endpoint:0=",<&mux_in1>, ++ <&imx258_1>, "status=okay"; ++ cam1-imx290 = <&mux_in1>, "remote-endpoint:0=",<&imx290_1_ep>, ++ <&imx290_1_ep>, "remote-endpoint:0=",<&mux_in1>, ++ <&imx290_1>, "status=okay"; ++ cam1-ov2311 = <&mux_in1>, "remote-endpoint:0=",<&ov2311_1_ep>, ++ <&ov2311_1_ep>, "remote-endpoint:0=",<&mux_in1>, ++ <&ov2311_1>, "status=okay"; ++ cam1-ov64a40 = <&mux_in1>, "remote-endpoint:0=",<&ov64a40_1_ep>, ++ <&ov64a40_1_ep>, "remote-endpoint:0=",<&mux_in1>, ++ <&mux_in1>, "clock-noncontinuous?", ++ <&ov64a40_1>, "status=okay", ++ <&ov64a40_1_vcm>, "status=okay", ++ <&ov64a40_1>,"lens-focus:0=", <&ov64a40_1_vcm>; ++ ++ cam0-imx290-clk-freq = <&clk_imx290>,"clock-frequency:0", ++ <&imx290_0>,"clock-frequency:0"; ++ cam1-imx290-clk-freq = <&clk_imx290>,"clock-frequency:0", ++ <&imx290_1>,"clock-frequency:0"; ++ ++ cam0 = <&i2c_frag>, "target:0=",<&i2c_csi_dsi0>, ++ <&csi_frag>, "target:0=",<&csi0>; ++ ++ cam0-sync-source = <&imx477_0>, "trigger-mode:0=1"; ++ cam0-sync-sink = <&imx477_0>, "trigger-mode:0=2"; ++ cam1-sync-source = <&imx477_1>, "trigger-mode:0=1"; ++ cam1-sync-sink = <&imx477_1>, "trigger-mode:0=2"; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlays/camera-mux-4port-overlay.dts b/arch/arm/boot/dts/overlays/camera-mux-4port-overlay.dts +new file mode 100644 +index 000000000000..c8f8f594cd61 +--- /dev/null ++++ b/arch/arm/boot/dts/overlays/camera-mux-4port-overlay.dts +@@ -0,0 +1,952 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++ ++// Overlay to configure a 4 port camera multiplexer ++// ++// Configuration is based on the Arducam 4 channel multiplexer ++// which uses a PCA9543 I2C multiplexer to handle the ++// I2C, and GPIOs 4, 17, and 18 to control the MIPI muxes. ++ ++/dts-v1/; ++/plugin/; ++ ++#include ++ ++/{ ++ compatible = "brcm,bcm2835"; ++ ++ /* Fragments that complete the individual sensor fragments */ ++ /* IMX290 */ ++ fragment@0 { ++ target = <&imx290_0_ep>; ++ __overlay__ { ++ data-lanes = <1 2>; ++ link-frequencies = ++ /bits/ 64 <445500000 297000000>; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&imx290_1_ep>; ++ __overlay__ { ++ data-lanes = <1 2>; ++ link-frequencies = ++ /bits/ 64 <445500000 297000000>; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&imx290_2_ep>; ++ __overlay__ { ++ data-lanes = <1 2>; ++ link-frequencies = ++ /bits/ 64 <445500000 297000000>; ++ }; ++ }; ++ ++ fragment@3 { ++ target = <&imx290_3_ep>; ++ __overlay__ { ++ data-lanes = <1 2>; ++ link-frequencies = ++ /bits/ 64 <445500000 297000000>; ++ }; ++ }; ++ ++ /* IMX477 */ ++ fragment@10 { ++ target = <&imx477_0>; ++ __overlay__ { ++ compatible = "sony,imx477"; ++ }; ++ }; ++ ++ fragment@11 { ++ target = <&imx477_1>; ++ __overlay__ { ++ compatible = "sony,imx477"; ++ }; ++ }; ++ ++ fragment@12 { ++ target = <&imx477_2>; ++ __overlay__ { ++ compatible = "sony,imx477"; ++ }; ++ }; ++ ++ fragment@13 { ++ target = <&imx477_3>; ++ __overlay__ { ++ compatible = "sony,imx477"; ++ }; ++ }; ++ ++ /* Additional fragments affecting the mux nodes */ ++ fragment@100 { ++ target = <&mux_in0>; ++ __dormant__ { ++ data-lanes = <1>; ++ }; ++ }; ++ fragment@101 { ++ target = <&mux_in0>; ++ __overlay__ { ++ data-lanes = <1 2>; ++ }; ++ }; ++ ++ fragment@102 { ++ target = <&mux_in1>; ++ __dormant__ { ++ data-lanes = <1>; ++ }; ++ }; ++ fragment@103 { ++ target = <&mux_in1>; ++ __overlay__ { ++ data-lanes = <1 2>; ++ }; ++ }; ++ ++ fragment@104 { ++ target = <&mux_in2>; ++ __dormant__ { ++ data-lanes = <1>; ++ }; ++ }; ++ fragment@105 { ++ target = <&mux_in2>; ++ __overlay__ { ++ data-lanes = <1 2>; ++ }; ++ }; ++ ++ fragment@106 { ++ target = <&mux_in3>; ++ __dormant__ { ++ data-lanes = <1>; ++ }; ++ }; ++ fragment@107 { ++ target = <&mux_in3>; ++ __overlay__ { ++ data-lanes = <1 2>; ++ }; ++ }; ++ ++ /* Mux define */ ++ i2c_frag: fragment@200 { ++ target = <&i2c_csi_dsi>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "okay"; ++ ++ pca@70 { ++ reg = <0x70>; ++ compatible = "nxp,pca9544"; ++ ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ i2c@0 { ++ reg = <0>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ #define cam_node arducam_64mp_0 ++ #define cam_endpoint arducam_64mp_0_ep ++ #define vcm_node arducam_64mp_0_vcm ++ #define cam1_clk clk_24mhz ++ #include "arducam-64mp.dtsi" ++ #undef cam_node ++ #undef cam_endpoint ++ #undef vcm_node ++ #undef cam1_clk ++ ++ #define cam_node imx219_0 ++ #define cam_endpoint imx219_0_ep ++ #define cam1_clk clk_24mhz ++ #include "imx219.dtsi" ++ #undef cam_node ++ #undef cam_endpoint ++ #undef cam1_clk ++ ++ #define cam_node imx477_0 ++ #define cam_endpoint imx477_0_ep ++ #define cam1_clk clk_24mhz ++ #include "imx477_378.dtsi" ++ #undef cam_node ++ #undef cam_endpoint ++ #undef cam1_clk ++ ++ #define cam_node imx519_0 ++ #define cam_endpoint imx519_0_ep ++ #define vcm_node imx519_0_vcm ++ #define cam1_clk clk_24mhz ++ #include "imx519.dtsi" ++ #undef cam_node ++ #undef cam_endpoint ++ #undef vcm_node ++ #undef cam1_clk ++ ++ #define cam_node imx708_0 ++ #define cam_endpoint imx708_0_ep ++ #define vcm_node imx708_0_vcm ++ #define cam1_clk clk_24mhz ++ #include "imx708.dtsi" ++ #undef cam_node ++ #undef cam_endpoint ++ #undef vcm_node ++ #undef cam1_clk ++ ++ #define cam_node ov5647_0 ++ #define cam_endpoint ov5647_0_ep ++ #define cam1_clk clk_25mhz ++ #include "ov5647.dtsi" ++ #undef cam_node ++ #undef cam_endpoint ++ #undef cam1_clk ++ ++ #define cam_node ov7251_0 ++ #define cam_endpoint ov7251_0_ep ++ #define cam1_clk clk_24mhz ++ #include "ov7251.dtsi" ++ #undef cam_node ++ #undef cam_endpoint ++ #undef cam1_clk ++ ++ #define cam_node ov9281_0 ++ #define cam_endpoint ov9281_0_ep ++ #define cam1_clk clk_24mhz ++ #include "ov9281.dtsi" ++ #undef cam_node ++ #undef cam_endpoint ++ #undef cam1_clk ++ ++ #define cam_node imx258_0 ++ #define cam_endpoint imx258_0_ep ++ #define cam1_clk clk_24mhz ++ #include "imx258.dtsi" ++ #undef cam_node ++ #undef cam_endpoint ++ #undef cam1_clk ++ ++ #define cam_node imx290_0 ++ #define cam_endpoint imx290_0_ep ++ #define cam1_clk clk_imx290 ++ #include "imx290_327.dtsi" ++ #undef cam_node ++ #undef cam_endpoint ++ #undef cam1_clk ++ ++ #define cam_node ov2311_0 ++ #define cam_endpoint ov2311_0_ep ++ #define cam1_clk clk_24mhz ++ #include "ov2311.dtsi" ++ #undef cam_node ++ #undef cam_endpoint ++ #undef cam1_clk ++ ++ #define cam_node ov64a40_0 ++ #define cam_endpoint ov64a40_0_ep ++ #define vcm_node ov64a40_0_vcm ++ #define cam1_clk clk_24mhz ++ #include "ov64a40.dtsi" ++ #undef cam_node ++ #undef cam_endpoint ++ #undef vcm_node ++ #undef cam1_clk ++ }; ++ ++ i2c@1 { ++ reg = <1>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ #define cam_node arducam_64mp_1 ++ #define cam_endpoint arducam_64mp_1_ep ++ #define vcm_node arducam_64mp_1_vcm ++ #define cam1_clk clk_24mhz ++ #include "arducam-64mp.dtsi" ++ #undef cam_node ++ #undef cam_endpoint ++ #undef vcm_node ++ #undef cam1_clk ++ ++ #define cam_node imx219_1 ++ #define cam_endpoint imx219_1_ep ++ #define cam1_clk clk_24mhz ++ #include "imx219.dtsi" ++ #undef cam_node ++ #undef cam_endpoint ++ #undef cam1_clk ++ ++ #define cam_node imx477_1 ++ #define cam_endpoint imx477_1_ep ++ #define cam1_clk clk_24mhz ++ #include "imx477_378.dtsi" ++ #undef cam_node ++ #undef cam_endpoint ++ #undef cam1_clk ++ ++ #define cam_node imx519_1 ++ #define cam_endpoint imx519_1_ep ++ #define vcm_node imx519_1_vcm ++ #define cam1_clk clk_24mhz ++ #include "imx519.dtsi" ++ #undef cam_node ++ #undef cam_endpoint ++ #undef vcm_node ++ #undef cam1_clk ++ ++ #define cam_node imx708_1 ++ #define cam_endpoint imx708_1_ep ++ #define vcm_node imx708_1_vcm ++ #define cam1_clk clk_24mhz ++ #include "imx708.dtsi" ++ #undef cam_node ++ #undef cam_endpoint ++ #undef vcm_node ++ #undef cam1_clk ++ ++ #define cam_node ov5647_1 ++ #define cam_endpoint ov5647_1_ep ++ #define cam1_clk clk_25mhz ++ #include "ov5647.dtsi" ++ #undef cam_node ++ #undef cam_endpoint ++ #undef cam1_clk ++ ++ #define cam_node ov7251_1 ++ #define cam_endpoint ov7251_1_ep ++ #define cam1_clk clk_24mhz ++ #include "ov7251.dtsi" ++ #undef cam_node ++ #undef cam_endpoint ++ #undef cam1_clk ++ ++ #define cam_node ov9281_1 ++ #define cam_endpoint ov9281_1_ep ++ #define cam1_clk clk_24mhz ++ #include "ov9281.dtsi" ++ #undef cam_node ++ #undef cam_endpoint ++ #undef cam1_clk ++ ++ #define cam_node imx258_1 ++ #define cam_endpoint imx258_1_ep ++ #define cam1_clk clk_24mhz ++ #include "imx258.dtsi" ++ #undef cam_node ++ #undef cam_endpoint ++ #undef cam1_clk ++ ++ #define cam_node imx290_1 ++ #define cam_endpoint imx290_1_ep ++ #define cam1_clk clk_imx290 ++ #include "imx290_327.dtsi" ++ #undef cam_node ++ #undef cam_endpoint ++ #undef cam1_clk ++ ++ #define cam_node ov2311_1 ++ #define cam_endpoint ov2311_1_ep ++ #define cam1_clk clk_24mhz ++ #include "ov2311.dtsi" ++ #undef cam_node ++ #undef cam_endpoint ++ #undef cam1_clk ++ ++ #define cam_node ov64a40_1 ++ #define cam_endpoint ov64a40_1_ep ++ #define vcm_node ov64a40_1_vcm ++ #define cam1_clk clk_24mhz ++ #include "ov64a40.dtsi" ++ #undef cam_node ++ #undef cam_endpoint ++ #undef vcm_node ++ #undef cam1_clk ++ }; ++ ++ i2c@2 { ++ reg = <2>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ #define cam_node arducam_64mp_2 ++ #define cam_endpoint arducam_64mp_2_ep ++ #define vcm_node arducam_64mp_2_vcm ++ #define cam1_clk clk_24mhz ++ #include "arducam-64mp.dtsi" ++ #undef cam_node ++ #undef cam_endpoint ++ #undef vcm_node ++ #undef cam1_clk ++ ++ #define cam_node imx219_2 ++ #define cam_endpoint imx219_2_ep ++ #define cam1_clk clk_24mhz ++ #include "imx219.dtsi" ++ #undef cam_node ++ #undef cam_endpoint ++ #undef cam1_clk ++ ++ #define cam_node imx477_2 ++ #define cam_endpoint imx477_2_ep ++ #define cam1_clk clk_24mhz ++ #include "imx477_378.dtsi" ++ #undef cam_node ++ #undef cam_endpoint ++ #undef cam1_clk ++ ++ #define cam_node imx519_2 ++ #define cam_endpoint imx519_2_ep ++ #define vcm_node imx519_2_vcm ++ #define cam1_clk clk_24mhz ++ #include "imx519.dtsi" ++ #undef cam_node ++ #undef cam_endpoint ++ #undef vcm_node ++ #undef cam1_clk ++ ++ #define cam_node imx708_2 ++ #define cam_endpoint imx708_2_ep ++ #define vcm_node imx708_2_vcm ++ #define cam1_clk clk_24mhz ++ #include "imx708.dtsi" ++ #undef cam_node ++ #undef cam_endpoint ++ #undef vcm_node ++ #undef cam1_clk ++ ++ #define cam_node ov5647_2 ++ #define cam_endpoint ov5647_2_ep ++ #define cam1_clk clk_25mhz ++ #include "ov5647.dtsi" ++ #undef cam_node ++ #undef cam_endpoint ++ #undef cam1_clk ++ ++ #define cam_node ov7251_2 ++ #define cam_endpoint ov7251_2_ep ++ #define cam1_clk clk_24mhz ++ #include "ov7251.dtsi" ++ #undef cam_node ++ #undef cam_endpoint ++ #undef cam1_clk ++ ++ #define cam_node ov9281_2 ++ #define cam_endpoint ov9281_2_ep ++ #define cam1_clk clk_24mhz ++ #include "ov9281.dtsi" ++ #undef cam_node ++ #undef cam_endpoint ++ #undef cam1_clk ++ ++ #define cam_node imx258_2 ++ #define cam_endpoint imx258_2_ep ++ #define cam1_clk clk_24mhz ++ #include "imx258.dtsi" ++ #undef cam_node ++ #undef cam_endpoint ++ #undef cam1_clk ++ ++ #define cam_node imx290_2 ++ #define cam_endpoint imx290_2_ep ++ #define cam1_clk clk_imx290 ++ #include "imx290_327.dtsi" ++ #undef cam_node ++ #undef cam_endpoint ++ #undef cam1_clk ++ ++ #define cam_node ov2311_2 ++ #define cam_endpoint ov2311_2_ep ++ #define cam1_clk clk_24mhz ++ #include "ov2311.dtsi" ++ #undef cam_node ++ #undef cam_endpoint ++ #undef cam1_clk ++ ++ #define cam_node ov64a40_2 ++ #define cam_endpoint ov64a40_2_ep ++ #define vcm_node ov64a40_2_vcm ++ #define cam1_clk clk_24mhz ++ #include "ov64a40.dtsi" ++ #undef cam_node ++ #undef cam_endpoint ++ #undef vcm_node ++ #undef cam1_clk ++ }; ++ ++ i2c@3 { ++ reg = <3>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ #define cam_node arducam_64mp_3 ++ #define cam_endpoint arducam_64mp_3_ep ++ #define vcm_node arducam_64mp_3_vcm ++ #define cam1_clk clk_24mhz ++ #include "arducam-64mp.dtsi" ++ #undef cam_node ++ #undef cam_endpoint ++ #undef vcm_node ++ #undef cam1_clk ++ ++ #define cam_node imx219_3 ++ #define cam_endpoint imx219_3_ep ++ #define cam1_clk clk_24mhz ++ #include "imx219.dtsi" ++ #undef cam_node ++ #undef cam_endpoint ++ #undef cam1_clk ++ ++ #define cam_node imx477_3 ++ #define cam_endpoint imx477_3_ep ++ #define cam1_clk clk_24mhz ++ #include "imx477_378.dtsi" ++ #undef cam_node ++ #undef cam_endpoint ++ #undef cam1_clk ++ ++ #define cam_node imx519_3 ++ #define cam_endpoint imx519_3_ep ++ #define vcm_node imx519_3_vcm ++ #define cam1_clk clk_24mhz ++ #include "imx519.dtsi" ++ #undef cam_node ++ #undef cam_endpoint ++ #undef vcm_node ++ #undef cam1_clk ++ ++ #define cam_node imx708_3 ++ #define cam_endpoint imx708_3_ep ++ #define vcm_node imx708_3_vcm ++ #define cam1_clk clk_24mhz ++ #include "imx708.dtsi" ++ #undef cam_node ++ #undef cam_endpoint ++ #undef vcm_node ++ #undef cam1_clk ++ ++ #define cam_node ov5647_3 ++ #define cam_endpoint ov5647_3_ep ++ #define cam1_clk clk_25mhz ++ #include "ov5647.dtsi" ++ #undef cam_node ++ #undef cam_endpoint ++ #undef cam1_clk ++ ++ #define cam_node ov7251_3 ++ #define cam_endpoint ov7251_3_ep ++ #define cam1_clk clk_24mhz ++ #include "ov7251.dtsi" ++ #undef cam_node ++ #undef cam_endpoint ++ #undef cam1_clk ++ ++ #define cam_node ov9281_3 ++ #define cam_endpoint ov9281_3_ep ++ #define cam1_clk clk_24mhz ++ #include "ov9281.dtsi" ++ #undef cam_node ++ #undef cam_endpoint ++ #undef cam1_clk ++ ++ #define cam_node imx258_3 ++ #define cam_endpoint imx258_3_ep ++ #define cam1_clk clk_24mhz ++ #include "imx258.dtsi" ++ #undef cam_node ++ #undef cam_endpoint ++ #undef cam1_clk ++ ++ #define cam_node imx290_3 ++ #define cam_endpoint imx290_3_ep ++ #define cam1_clk clk_imx290 ++ #include "imx290_327.dtsi" ++ #undef cam_node ++ #undef cam_endpoint ++ #undef cam1_clk ++ ++ #define cam_node ov2311_3 ++ #define cam_endpoint ov2311_3_ep ++ #define cam1_clk clk_24mhz ++ #include "ov2311.dtsi" ++ #undef cam_node ++ #undef cam_endpoint ++ #undef cam1_clk ++ ++ #define cam_node ov64a40_3 ++ #define cam_endpoint ov64a40_3_ep ++ #define vcm_node ov64a40_3_vcm ++ #define cam1_clk clk_24mhz ++ #include "ov64a40.dtsi" ++ #undef cam_node ++ #undef cam_endpoint ++ #undef vcm_node ++ #undef cam1_clk ++ }; ++ }; ++ }; ++ }; ++ ++ csi_frag: fragment@201 { ++ target = <&csi1>; ++ __overlay__ { ++ status = "okay"; ++ ++ brcm,media-controller; ++ ++ port { ++ csi1_ep: endpoint { ++ remote-endpoint = <&mux_out>; ++ clock-lanes = <0>; ++ data-lanes = <1 2>; ++ }; ++ }; ++ }; ++ }; ++ ++ fragment@202 { ++ target = <&i2c0if>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@203 { ++ target-path="/"; ++ __overlay__ { ++ mux: mux-controller { ++ compatible = "gpio-mux"; ++ #mux-control-cells = <0>; ++ ++ /* SEL, En2, En1 */ ++ mux-gpios = <&gpio 4 GPIO_ACTIVE_HIGH>, ++ <&gpio 18 GPIO_ACTIVE_HIGH>, ++ <&gpio 17 GPIO_ACTIVE_HIGH>; ++ }; ++ ++ video-mux { ++ compatible = "video-mux"; ++ mux-controls = <&mux>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ /* GPIO mappings settings for selecting the different ++ * camera connectors are not direct, hence port@ values ++ * are not straight forward. ++ */ ++ port@2 { ++ /* Port A - GPIO 17 = 0, GPIO 18 = 1,GPIO 4 = 0 */ ++ reg = <2>; ++ ++ mux_in0: endpoint { ++ clock-lanes = <0>; ++ }; ++ }; ++ ++ port@3 { ++ /* Port B - GPIO 17 = 0, GPIO 18 = 1,GPIO 4 = 1 */ ++ reg = <3>; ++ ++ mux_in1: endpoint { ++ clock-lanes = <0>; ++ }; ++ }; ++ ++ port@4 { ++ /* Port C - GPIO 17 = 1, GPIO 18 = 0, GPIO 4 = 0 */ ++ reg = <4>; ++ ++ mux_in2: endpoint { ++ clock-lanes = <0>; ++ }; ++ }; ++ ++ port@5 { ++ /* Port D - GPIO 17 = 1, GPIO 18 = 0, GPIO 4 = 1 */ ++ reg = <5>; ++ ++ mux_in3: endpoint { ++ clock-lanes = <0>; ++ }; ++ }; ++ ++ port@6 { ++ /* Output port needs to be the highest port number */ ++ reg = <6>; ++ ++ mux_out: endpoint { ++ remote-endpoint = <&csi1_ep>; ++ clock-lanes = <0>; ++ }; ++ }; ++ }; ++ ++ clk_24mhz: clk_24mhz { ++ compatible = "fixed-clock"; ++ #clock-cells = <0>; ++ ++ clock-frequency = <24000000>; ++ status = "okay"; ++ }; ++ ++ clk_25mhz: clk_25mhz { ++ compatible = "fixed-clock"; ++ #clock-cells = <0>; ++ ++ clock-frequency = <25000000>; ++ status = "okay"; ++ }; ++ ++ clk_imx290: clk_imx290 { ++ compatible = "fixed-clock"; ++ #clock-cells = <0>; ++ ++ clock-frequency = <37125000>; ++ status = "okay"; ++ }; ++ }; ++ }; ++ ++ fragment@204 { ++ target = <&i2c0mux>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++ ++ __overrides__ { ++ cam0-arducam-64mp = <&mux_in0>, "remote-endpoint:0=",<&arducam_64mp_0_ep>, ++ <&arducam_64mp_0_ep>, "remote-endpoint:0=",<&mux_in0>, ++ <&mux_in0>, "clock-noncontinuous?", ++ <&arducam_64mp_0>, "status=okay", ++ <&arducam_64mp_0_vcm>, "status=okay", ++ <&arducam_64mp_0>,"lens-focus:0=", <&arducam_64mp_0_vcm>; ++ cam0-imx219 = <&mux_in0>, "remote-endpoint:0=",<&imx219_0_ep>, ++ <&imx219_0_ep>, "remote-endpoint:0=",<&mux_in0>, ++ <&mux_in0>, "clock-noncontinuous?", ++ <&imx219_0>, "status=okay"; ++ cam0-imx477 = <&mux_in0>, "remote-endpoint:0=",<&imx477_0_ep>, ++ <&imx477_0_ep>, "remote-endpoint:0=",<&mux_in0>, ++ <&mux_in0>, "clock-noncontinuous?", ++ <&imx477_0>, "status=okay"; ++ cam0-imx519 = <&mux_in0>, "remote-endpoint:0=",<&imx519_0_ep>, ++ <&imx519_0_ep>, "remote-endpoint:0=",<&mux_in0>, ++ <&mux_in0>, "clock-noncontinuous?", ++ <&imx519_0>, "status=okay", ++ <&imx519_0_vcm>, "status=okay", ++ <&imx519_0>,"lens-focus:0=", <&imx519_0_vcm>; ++ cam0-imx708 = <&mux_in0>, "remote-endpoint:0=",<&imx708_0_ep>, ++ <&imx708_0_ep>, "remote-endpoint:0=",<&mux_in0>, ++ <&mux_in0>, "clock-noncontinuous?", ++ <&imx708_0>, "status=okay", ++ <&imx708_0_vcm>, "status=okay", ++ <&imx708_0>,"lens-focus:0=", <&imx708_0_vcm>; ++ cam0-ov5647 = <&mux_in0>, "remote-endpoint:0=",<&ov5647_0_ep>, ++ <&ov5647_0_ep>, "remote-endpoint:0=",<&mux_in0>, ++ <&ov5647_0>, "status=okay"; ++ cam0-ov7251 = <&mux_in0>, "remote-endpoint:0=",<&ov7251_0_ep>, ++ <&ov7251_0_ep>, "remote-endpoint:0=",<&mux_in0>, ++ <&ov7251_0>, "status=okay", ++ <0>,"+100-101"; ++ cam0-ov9281 = <&mux_in0>, "remote-endpoint:0=",<&ov9281_0_ep>, ++ <&ov9281_0_ep>, "remote-endpoint:0=",<&mux_in0>, ++ <&ov9281_0>, "status=okay"; ++ cam0-imx258 = <&mux_in0>, "remote-endpoint:0=",<&imx258_0_ep>, ++ <&imx258_0_ep>, "remote-endpoint:0=",<&mux_in0>, ++ <&imx258_0>, "status=okay"; ++ cam0-imx290 = <&mux_in0>, "remote-endpoint:0=",<&imx290_0_ep>, ++ <&imx290_0_ep>, "remote-endpoint:0=",<&mux_in0>, ++ <&imx290_0>, "status=okay"; ++ cam0-ov2311 = <&mux_in0>, "remote-endpoint:0=",<&ov2311_0_ep>, ++ <&ov2311_0_ep>, "remote-endpoint:0=",<&mux_in0>, ++ <&ov2311_0>, "status=okay"; ++ cam0-ov64a40 = <&mux_in0>, "remote-endpoint:0=",<&ov64a40_0_ep>, ++ <&ov64a40_0_ep>, "remote-endpoint:0=",<&mux_in0>, ++ <&mux_in0>, "clock-noncontinuous?", ++ <&ov64a40_0>, "status=okay", ++ <&ov64a40_0_vcm>, "status=okay", ++ <&ov64a40_0>,"lens-focus:0=", <&ov64a40_0_vcm>; ++ ++ cam1-arducam-64mp = <&mux_in1>, "remote-endpoint:0=",<&arducam_64mp_1_ep>, ++ <&arducam_64mp_1_ep>, "remote-endpoint:0=",<&mux_in1>, ++ <&mux_in1>, "clock-noncontinuous?", ++ <&arducam_64mp_1>, "status=okay", ++ <&arducam_64mp_1_vcm>, "status=okay", ++ <&arducam_64mp_1>,"lens-focus:0=", <&arducam_64mp_1_vcm>; ++ cam1-imx219 = <&mux_in1>, "remote-endpoint:0=",<&imx219_1_ep>, ++ <&imx219_1_ep>, "remote-endpoint:0=",<&mux_in1>, ++ <&mux_in1>, "clock-noncontinuous?", ++ <&imx219_1>, "status=okay"; ++ cam1-imx477 = <&mux_in1>, "remote-endpoint:0=",<&imx477_1_ep>, ++ <&imx477_1_ep>, "remote-endpoint:0=",<&mux_in1>, ++ <&mux_in1>, "clock-noncontinuous?", ++ <&imx477_1>, "status=okay"; ++ cam1-imx519 = <&mux_in1>, "remote-endpoint:0=",<&imx519_1_ep>, ++ <&imx519_1_ep>, "remote-endpoint:0=",<&mux_in1>, ++ <&mux_in1>, "clock-noncontinuous?", ++ <&imx519_1>, "status=okay", ++ <&imx519_1_vcm>, "status=okay", ++ <&imx519_1>,"lens-focus:0=", <&imx519_1_vcm>; ++ cam1-imx708 = <&mux_in1>, "remote-endpoint:0=",<&imx708_1_ep>, ++ <&imx708_1_ep>, "remote-endpoint:0=",<&mux_in1>, ++ <&mux_in1>, "clock-noncontinuous?", ++ <&imx708_1>, "status=okay", ++ <&imx708_1_vcm>, "status=okay", ++ <&imx708_1>,"lens-focus:0=", <&imx708_1_vcm>; ++ cam1-ov5647 = <&mux_in1>, "remote-endpoint:0=",<&ov5647_1_ep>, ++ <&ov5647_1_ep>, "remote-endpoint:0=",<&mux_in1>, ++ <&ov5647_1>, "status=okay"; ++ cam1-ov7251 = <&mux_in1>, "remote-endpoint:0=",<&ov7251_1_ep>, ++ <&ov7251_1_ep>, "remote-endpoint:0=",<&mux_in1>, ++ <&ov7251_1>, "status=okay", ++ <0>,"+102-103"; ++ cam1-ov9281 = <&mux_in1>, "remote-endpoint:0=",<&ov9281_1_ep>, ++ <&ov9281_1_ep>, "remote-endpoint:0=",<&mux_in1>, ++ <&ov9281_1>, "status=okay"; ++ cam1-imx258 = <&mux_in1>, "remote-endpoint:0=",<&imx258_1_ep>, ++ <&imx258_1_ep>, "remote-endpoint:0=",<&mux_in1>, ++ <&imx258_1>, "status=okay"; ++ cam1-imx290 = <&mux_in1>, "remote-endpoint:0=",<&imx290_1_ep>, ++ <&imx290_1_ep>, "remote-endpoint:0=",<&mux_in1>, ++ <&imx290_1>, "status=okay"; ++ cam1-ov2311 = <&mux_in1>, "remote-endpoint:0=",<&ov2311_1_ep>, ++ <&ov2311_1_ep>, "remote-endpoint:0=",<&mux_in1>, ++ <&ov2311_1>, "status=okay"; ++ cam1-ov64a40 = <&mux_in1>, "remote-endpoint:0=",<&ov64a40_1_ep>, ++ <&ov64a40_1_ep>, "remote-endpoint:0=",<&mux_in1>, ++ <&mux_in1>, "clock-noncontinuous?", ++ <&ov64a40_1>, "status=okay", ++ <&ov64a40_1_vcm>, "status=okay", ++ <&ov64a40_1>,"lens-focus:0=", <&ov64a40_1_vcm>; ++ ++ cam2-arducam-64mp = <&mux_in2>, "remote-endpoint:0=",<&arducam_64mp_2_ep>, ++ <&arducam_64mp_2_ep>, "remote-endpoint:0=",<&mux_in2>, ++ <&mux_in2>, "clock-noncontinuous?", ++ <&arducam_64mp_2>, "status=okay", ++ <&arducam_64mp_2_vcm>, "status=okay", ++ <&arducam_64mp_2>,"lens-focus:0=", <&arducam_64mp_2_vcm>; ++ cam2-imx219 = <&mux_in2>, "remote-endpoint:0=",<&imx219_2_ep>, ++ <&imx219_2_ep>, "remote-endpoint:0=",<&mux_in2>, ++ <&mux_in2>, "clock-noncontinuous?", ++ <&imx219_2>, "status=okay"; ++ cam2-imx477 = <&mux_in2>, "remote-endpoint:0=",<&imx477_2_ep>, ++ <&imx477_2_ep>, "remote-endpoint:0=",<&mux_in2>, ++ <&mux_in2>, "clock-noncontinuous?", ++ <&imx477_2>, "status=okay"; ++ cam2-imx519 = <&mux_in2>, "remote-endpoint:0=",<&imx519_2_ep>, ++ <&imx519_2_ep>, "remote-endpoint:0=",<&mux_in2>, ++ <&mux_in2>, "clock-noncontinuous?", ++ <&imx519_2>, "status=okay", ++ <&imx519_2_vcm>, "status=okay", ++ <&imx519_2>,"lens-focus:0=", <&imx519_2_vcm>; ++ cam2-imx708 = <&mux_in2>, "remote-endpoint:0=",<&imx708_2_ep>, ++ <&imx708_2_ep>, "remote-endpoint:0=",<&mux_in2>, ++ <&mux_in2>, "clock-noncontinuous?", ++ <&imx708_2>, "status=okay", ++ <&imx708_2_vcm>, "status=okay", ++ <&imx708_2>,"lens-focus:0=", <&imx708_2_vcm>; ++ cam2-ov5647 = <&mux_in2>, "remote-endpoint:0=",<&ov5647_2_ep>, ++ <&ov5647_2_ep>, "remote-endpoint:0=",<&mux_in2>, ++ <&ov5647_2>, "status=okay"; ++ cam2-ov7251 = <&mux_in2>, "remote-endpoint:0=",<&ov7251_2_ep>, ++ <&ov7251_2_ep>, "remote-endpoint:0=",<&mux_in2>, ++ <&ov7251_2>, "status=okay", ++ <0>,"+104-105"; ++ cam2-ov9281 = <&mux_in2>, "remote-endpoint:0=",<&ov9281_2_ep>, ++ <&ov9281_2_ep>, "remote-endpoint:0=",<&mux_in2>, ++ <&ov9281_2>, "status=okay"; ++ cam2-imx258 = <&mux_in2>, "remote-endpoint:0=",<&imx258_2_ep>, ++ <&imx258_2>, "status=okay", ++ <&imx258_2>, "remote-endpoint:0=",<&mux_in2>; ++ cam2-imx290 = <&mux_in2>, "remote-endpoint:0=",<&imx290_2_ep>, ++ <&imx290_2_ep>, "remote-endpoint:0=",<&mux_in2>, ++ <&imx290_2>, "status=okay"; ++ cam2-ov2311 = <&mux_in2>, "remote-endpoint:0=",<&ov2311_2_ep>, ++ <&ov2311_2_ep>, "remote-endpoint:0=",<&mux_in2>, ++ <&ov2311_2>, "status=okay"; ++ cam2-ov64a40 = <&mux_in2>, "remote-endpoint:0=",<&ov64a40_2_ep>, ++ <&ov64a40_2_ep>, "remote-endpoint:0=",<&mux_in2>, ++ <&mux_in2>, "clock-noncontinuous?", ++ <&ov64a40_2>, "status=okay", ++ <&ov64a40_2_vcm>, "status=okay", ++ <&ov64a40_2>,"lens-focus:0=", <&ov64a40_2_vcm>; ++ ++ cam3-arducam-64mp = <&mux_in3>, "remote-endpoint:0=",<&arducam_64mp_3_ep>, ++ <&arducam_64mp_3_ep>, "remote-endpoint:0=",<&mux_in3>, ++ <&mux_in3>, "clock-noncontinuous?", ++ <&arducam_64mp_3>, "status=okay", ++ <&arducam_64mp_3_vcm>, "status=okay", ++ <&arducam_64mp_3>,"lens-focus:0=", <&arducam_64mp_3_vcm>; ++ cam3-imx219 = <&mux_in3>, "remote-endpoint:0=",<&imx219_3_ep>, ++ <&imx219_3_ep>, "remote-endpoint:0=",<&mux_in3>, ++ <&mux_in3>, "clock-noncontinuous?", ++ <&imx219_3>, "status=okay"; ++ cam3-imx477 = <&mux_in3>, "remote-endpoint:0=",<&imx477_3_ep>, ++ <&imx477_3_ep>, "remote-endpoint:0=",<&mux_in3>, ++ <&mux_in3>, "clock-noncontinuous?", ++ <&imx477_3>, "status=okay"; ++ cam3-imx519 = <&mux_in3>, "remote-endpoint:0=",<&imx519_3_ep>, ++ <&imx519_3_ep>, "remote-endpoint:0=",<&mux_in3>, ++ <&mux_in3>, "clock-noncontinuous?", ++ <&imx519_3>, "status=okay", ++ <&imx519_3_vcm>, "status=okay", ++ <&imx519_3>,"lens-focus:0=", <&imx519_3_vcm>; ++ cam3-imx708 = <&mux_in3>, "remote-endpoint:0=",<&imx708_3_ep>, ++ <&imx708_3_ep>, "remote-endpoint:0=",<&mux_in3>, ++ <&mux_in3>, "clock-noncontinuous?", ++ <&imx708_3>, "status=okay", ++ <&imx708_3_vcm>, "status=okay", ++ <&imx708_3>,"lens-focus:0=", <&imx708_3_vcm>; ++ cam3-ov5647 = <&mux_in3>, "remote-endpoint:0=",<&ov5647_3_ep>, ++ <&ov5647_3_ep>, "remote-endpoint:0=",<&mux_in3>, ++ <&ov5647_3>, "status=okay"; ++ cam3-ov7251 = <&mux_in3>, "remote-endpoint:0=",<&ov7251_3_ep>, ++ <&ov7251_3_ep>, "remote-endpoint:0=",<&mux_in3>, ++ <&ov7251_3>, "status=okay", ++ <0>,"+106-107"; ++ cam3-ov9281 = <&mux_in3>, "remote-endpoint:0=",<&ov9281_3_ep>, ++ <&ov9281_3_ep>, "remote-endpoint:0=",<&mux_in3>, ++ <&ov9281_3>, "status=okay"; ++ cam3-imx258 = <&mux_in3>, "remote-endpoint:0=",<&imx258_3_ep>, ++ <&imx258_3_ep>, "remote-endpoint:0=",<&mux_in3>, ++ <&imx258_3>, "status=okay"; ++ cam3-imx290 = <&mux_in3>, "remote-endpoint:0=",<&imx290_3_ep>, ++ <&imx290_3_ep>, "remote-endpoint:0=",<&mux_in3>, ++ <&imx290_3>, "status=okay"; ++ cam3-ov2311 = <&mux_in3>, "remote-endpoint:0=",<&ov2311_3_ep>, ++ <&ov2311_3_ep>, "remote-endpoint:0=",<&mux_in3>, ++ <&ov2311_3>, "status=okay"; ++ cam3-ov64a40 = <&mux_in3>, "remote-endpoint:0=",<&ov64a40_3_ep>, ++ <&ov64a40_3_ep>, "remote-endpoint:0=",<&mux_in3>, ++ <&mux_in3>, "clock-noncontinuous?", ++ <&ov64a40_3>, "status=okay", ++ <&ov64a40_3_vcm>, "status=okay", ++ <&ov64a40_3>,"lens-focus:0=", <&ov64a40_3_vcm>; ++ ++ cam0-imx290-clk-freq = <&clk_imx290>,"clock-frequency:0", ++ <&imx290_0>,"clock-frequency:0"; ++ cam1-imx290-clk-freq = <&clk_imx290>,"clock-frequency:0", ++ <&imx290_1>,"clock-frequency:0"; ++ cam2-imx290-clk-freq = <&clk_imx290>,"clock-frequency:0", ++ <&imx290_2>,"clock-frequency:0"; ++ cam3-imx290-clk-freq = <&clk_imx290>,"clock-frequency:0", ++ <&imx290_3>,"clock-frequency:0"; ++ ++ cam0 = <&i2c_frag>, "target:0=",<&i2c_csi_dsi0>, ++ <&csi_frag>, "target:0=",<&csi0>; ++ ++ cam0-sync-source = <&imx477_0>, "trigger-mode:0=1"; ++ cam0-sync-sink = <&imx477_0>, "trigger-mode:0=2"; ++ cam1-sync-source = <&imx477_1>, "trigger-mode:0=1"; ++ cam1-sync-sink = <&imx477_1>, "trigger-mode:0=2"; ++ cam2-sync-source = <&imx477_2>, "trigger-mode:0=1"; ++ cam2-sync-sink = <&imx477_2>, "trigger-mode:0=2"; ++ cam3-sync-source = <&imx477_3>, "trigger-mode:0=1"; ++ cam3-sync-sink = <&imx477_3>, "trigger-mode:0=2"; ++ }; ++}; diff --git a/arch/arm/boot/dts/overlays/cap1106-overlay.dts b/arch/arm/boot/dts/overlays/cap1106-overlay.dts new file mode 100644 index 000000000000..0a585e725f84 @@ -16020,7 +25667,7 @@ index 000000000000..0a585e725f84 +}; diff --git a/arch/arm/boot/dts/overlays/chipdip-dac-overlay.dts b/arch/arm/boot/dts/overlays/chipdip-dac-overlay.dts new file mode 100644 -index 000000000000..09c7417b4707 +index 000000000000..3ef7565a9312 --- /dev/null +++ b/arch/arm/boot/dts/overlays/chipdip-dac-overlay.dts @@ -0,0 +1,46 @@ @@ -16035,7 +25682,7 @@ index 000000000000..09c7417b4707 + compatible = "brcm,bcm2835"; + + fragment@0 { -+ target = <&i2s>; ++ target = <&i2s_clk_consumer>; + __overlay__ { + status = "okay"; + }; @@ -16058,7 +25705,7 @@ index 000000000000..09c7417b4707 + target = <&sound>; + __overlay__ { + compatible = "chipdip,chipdip-dac"; -+ i2s-controller = <&i2s>; ++ i2s-controller = <&i2s_clk_consumer>; + sr0-gpios = <&gpio 5 0>; + sr1-gpios = <&gpio 6 0>; + sr2-gpios = <&gpio 12 0>; @@ -16070,6 +25717,217 @@ index 000000000000..09c7417b4707 + }; + }; +}; +diff --git a/arch/arm/boot/dts/overlays/cirrus-wm5102-overlay.dts b/arch/arm/boot/dts/overlays/cirrus-wm5102-overlay.dts +new file mode 100644 +index 000000000000..a82b422ba16e +--- /dev/null ++++ b/arch/arm/boot/dts/overlays/cirrus-wm5102-overlay.dts +@@ -0,0 +1,172 @@ ++// Definitions for the Cirrus Logic Audio Card ++/dts-v1/; ++/plugin/; ++#include ++#include ++#include ++ ++/ { ++ compatible = "brcm,bcm2835"; ++ ++ fragment@0 { ++ target = <&i2s_clk_consumer>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&gpio>; ++ __overlay__ { ++ wlf_5102_pins: wlf_5102_pins { ++ brcm,pins = <17 22 27>; ++ brcm,function = < ++ BCM2835_FSEL_GPIO_OUT ++ BCM2835_FSEL_GPIO_OUT ++ BCM2835_FSEL_GPIO_IN ++ >; ++ }; ++ wlf_8804_pins: wlf_8804_pins { ++ brcm,pins = <8>; ++ brcm,function = ; ++ }; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&spi0_cs_pins>; ++ __overlay__ { ++ brcm,pins = <7>; ++ brcm,function = ; ++ }; ++ }; ++ ++ ++ fragment@3 { ++ target-path = "/"; ++ __overlay__ { ++ rpi_cirrus_reg_1v8: rpi_cirrus_reg_1v8 { ++ compatible = "regulator-fixed"; ++ regulator-name = "RPi-Cirrus 1v8"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-always-on; ++ }; ++ }; ++ }; ++ ++ fragment@4 { ++ target = <&spidev0>; ++ __overlay__ { ++ status = "disabled"; ++ }; ++ }; ++ ++ fragment@5 { ++ target = <&spidev1>; ++ __overlay__ { ++ status = "disabled"; ++ }; ++ }; ++ ++ fragment@6 { ++ target = <&spi0>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "okay"; ++ cs-gpios = <&gpio 7 GPIO_ACTIVE_LOW>; ++ ++ wm5102@0{ ++ compatible = "wlf,wm5102"; ++ reg = <0>; ++ ++ pinctrl-names = "default"; ++ pinctrl-0 = <&wlf_5102_pins>; ++ ++ spi-max-frequency = <500000>; ++ ++ interrupt-parent = <&gpio>; ++ interrupts = <27 8>; ++ interrupt-controller; ++ #interrupt-cells = <2>; ++ ++ gpio-controller; ++ #gpio-cells = <2>; ++ ++ LDOVDD-supply = <&rpi_cirrus_reg_1v8>; ++ AVDD-supply = <&rpi_cirrus_reg_1v8>; ++ DBVDD1-supply = <&rpi_cirrus_reg_1v8>; ++ DBVDD2-supply = <&vdd_3v3_reg>; ++ DBVDD3-supply = <&vdd_3v3_reg>; ++ CPVDD-supply = <&rpi_cirrus_reg_1v8>; ++ SPKVDDL-supply = <&vdd_5v0_reg>; ++ SPKVDDR-supply = <&vdd_5v0_reg>; ++ DCVDD-supply = <&arizona_ldo1>; ++ ++ reset-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; ++ wlf,ldoena = <&gpio 22 GPIO_ACTIVE_HIGH>; ++ wlf,gpio-defaults = < ++ ARIZONA_GP_DEFAULT ++ ARIZONA_GP_DEFAULT ++ ARIZONA_GP_DEFAULT ++ ARIZONA_GP_DEFAULT ++ ARIZONA_GP_DEFAULT ++ >; ++ wlf,micd-configs = <0 1 0>; ++ wlf,dmic-ref = < ++ ARIZONA_DMIC_MICVDD ++ ARIZONA_DMIC_MICBIAS2 ++ ARIZONA_DMIC_MICVDD ++ ARIZONA_DMIC_MICVDD ++ >; ++ wlf,inmode = < ++ ARIZONA_INMODE_DIFF ++ ARIZONA_INMODE_DMIC ++ ARIZONA_INMODE_SE ++ ARIZONA_INMODE_DIFF ++ >; ++ status = "okay"; ++ ++ arizona_ldo1: ldo1 { ++ regulator-name = "LDO1"; ++ // default constraints as in ++ // arizona-ldo1.c ++ regulator-min-microvolt = <1200000>; ++ regulator-max-microvolt = <1800000>; ++ }; ++ }; ++ }; ++ }; ++ ++ fragment@7 { ++ target = <&i2c1>; ++ __overlay__ { ++ status = "okay"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ wm8804@3b { ++ compatible = "wlf,wm8804"; ++ reg = <0x3b>; ++ status = "okay"; ++ ++ pinctrl-names = "default"; ++ pinctrl-0 = <&wlf_8804_pins>; ++ ++ PVDD-supply = <&vdd_3v3_reg>; ++ DVDD-supply = <&vdd_3v3_reg>; ++ wlf,reset-gpio = <&gpio 8 GPIO_ACTIVE_HIGH>; ++ }; ++ }; ++ }; ++ ++ fragment@8 { ++ target = <&sound>; ++ __overlay__ { ++ compatible = "wlf,rpi-cirrus"; ++ i2s-controller = <&i2s_clk_consumer>; ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlays/cm-swap-i2c0-overlay.dts b/arch/arm/boot/dts/overlays/cm-swap-i2c0-overlay.dts +new file mode 100644 +index 000000000000..6b7f599f7611 +--- /dev/null ++++ b/arch/arm/boot/dts/overlays/cm-swap-i2c0-overlay.dts +@@ -0,0 +1,27 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++// Definitions for IMX708 camera module on VC I2C bus ++/dts-v1/; ++/plugin/; ++ ++#include ++ ++/{ ++ compatible = "brcm,bcm2835"; ++ ++ fragment@0 { ++ target = <&i2c0mux>; ++ i2c0mux_frag: __overlay__ { ++ pinctrl-0 = <&i2c0_gpio28>; ++ pinctrl-1 = <&i2c0_gpio0>; ++ }; ++ }; ++ ++ __overrides__ { ++ i2c0-gpio0 = <&i2c0mux_frag>, "pinctrl-0:0=",<&i2c0_gpio0>; ++ i2c0-gpio28 = <&i2c0mux_frag>, "pinctrl-0:0=",<&i2c0_gpio28>; ++ i2c0-gpio44 = <&i2c0mux_frag>, "pinctrl-0:0=",<&i2c0_gpio44>; ++ i2c10-gpio0 = <&i2c0mux_frag>, "pinctrl-1:0=",<&i2c0_gpio0>; ++ i2c10-gpio28 = <&i2c0mux_frag>, "pinctrl-1:0=",<&i2c0_gpio28>; ++ i2c10-gpio44 = <&i2c0mux_frag>, "pinctrl-1:0=",<&i2c0_gpio44>; ++ }; ++}; diff --git a/arch/arm/boot/dts/overlays/cma-overlay.dts b/arch/arm/boot/dts/overlays/cma-overlay.dts new file mode 100644 index 000000000000..1d87c599f909 @@ -16112,9 +25970,139 @@ index 000000000000..1d87c599f909 + cma-default = <0>,"-0"; + }; +}; +diff --git a/arch/arm/boot/dts/overlays/crystalfontz-cfa050_pi_m-overlay.dts b/arch/arm/boot/dts/overlays/crystalfontz-cfa050_pi_m-overlay.dts +new file mode 100644 +index 000000000000..544036589b66 +--- /dev/null ++++ b/arch/arm/boot/dts/overlays/crystalfontz-cfa050_pi_m-overlay.dts +@@ -0,0 +1,124 @@ ++/* ++ * crystalfontz-cfa050_pi_m-overlay.dts ++ * Configures the Crystalfontz CFA050-PI-M series of modules ++ * using CFAF7201280A0-050TC/TN panels with RaspberryPi CM4 DSI1 ++ */ ++/dts-v1/; ++/plugin/; ++/{ ++// RaspberryPi CM4 ++ compatible = "brcm,bcm2835"; ++// PCF8574 I2C GPIO EXPANDER ++ fragment@0 { ++ target = <&i2c_csi_dsi>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "okay"; ++ pcf8574a: pcf8574a@38 { ++ reg = <0x38>; ++ compatible = "nxp,pcf8574"; ++ gpio-controller; ++ #gpio-cells = <2>; ++ ngpios = <8>; ++ gpio-line-names = "TFT_RESET", "TOUCH_RESET", "EXT_P2", "EXT_P3", ++ "EXT_P4", "EXT_P5", "EXT_P6", "EXT_P7"; ++ }; ++ }; ++ }; ++// LM3630a BACKLIGHT LED CONTROLLER ++ fragment@1 { ++ target = <&i2c_csi_dsi>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "okay"; ++ lm3630a: backlight@36 { ++ reg = <0x36>; ++ compatible = "ti,lm3630a"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ led@0 { ++ reg = <0>; ++ led-sources = <0 1>; ++ label = "lcd-backlight"; ++ default-brightness = <128>; ++ max-brightness = <255>; ++ }; ++ }; ++ }; ++ }; ++// CFAF7201280A0_050Tx TFT DSI PANEL ++ fragment@2 { ++ target = <&dsi1>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "okay"; ++ port { ++ dsi_out: endpoint { ++ remote-endpoint = <&panel_in>; ++ }; ++ }; ++ dsi_panel: dsi_panel@0 { ++ compatible = "crystalfontz,cfaf7201280a0_050tx"; ++ reg = <0>; ++ reset-gpios = <&pcf8574a 0 1>; ++ backlight = <&lm3630a>; ++ fps = <60>; ++ port { ++ panel_in: endpoint { ++ remote-endpoint = <&dsi_out>; ++ }; ++ }; ++ }; ++ }; ++ }; ++// rPI GPIO INPUT FOR TOUCH IC IRQ ++ fragment@3 { ++ target = <&gpio>; ++ __dormant__ { ++ gt928intpins: gt928intpins { ++ brcm,pins = <26>; ++ brcm,function = <0>; ++ brcm,pull = <1>; ++ }; ++ }; ++ }; ++// GT928 TOUCH CONTROLLER IC ++ fragment@4 { ++ target = <&i2c_csi_dsi>; ++ __dormant__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "okay"; ++ gt928@5d { ++ compatible = "goodix,gt928"; ++ reg = <0x5d>; ++ interrupt-parent = <&gpio>; ++ interrupts = <26 2>; ++ irq-gpios = <&gpio 26 0>; ++ reset-gpios = <&pcf8574a 1 1>; ++ touchscreen-inverted-x; ++ touchscreen-inverted-y; ++ }; ++ }; ++ }; ++// PCF85063A RTC on I2C ++ fragment@5 { ++ target = <&i2c_csi_dsi>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "okay"; ++ pcf85063a@51 { ++ compatible = "nxp,pcf85063a"; ++ reg = <0x51>; ++ }; ++ }; ++ }; ++// CAPACITIVE TOUCH OPTION FOR TFT PANEL ++ __overrides__ { ++ captouch = <0>,"+3+4"; ++ }; ++}; diff --git a/arch/arm/boot/dts/overlays/cutiepi-panel-overlay.dts b/arch/arm/boot/dts/overlays/cutiepi-panel-overlay.dts new file mode 100644 -index 000000000000..6f9694e81d6a +index 000000000000..d14c3698eb75 --- /dev/null +++ b/arch/arm/boot/dts/overlays/cutiepi-panel-overlay.dts @@ -0,0 +1,117 @@ @@ -16180,7 +26168,7 @@ index 000000000000..6f9694e81d6a + compatible = "pwm-backlight"; + brightness-levels = <0 6 8 12 16 24 32 40 48 64 96 128 160 192 224 255>; + default-brightness-level = <6>; -+ pwms = <&pwm 0 200000>; ++ pwms = <&pwm 0 200000 0>; + power-supply = <&vdd_3v3_reg>; + status = "okay"; + }; @@ -16235,12 +26223,89 @@ index 000000000000..6f9694e81d6a + }; + }; +}; +diff --git a/arch/arm/boot/dts/overlays/dacberry400-overlay.dts b/arch/arm/boot/dts/overlays/dacberry400-overlay.dts +new file mode 100644 +index 000000000000..c9ac11db20de +--- /dev/null ++++ b/arch/arm/boot/dts/overlays/dacberry400-overlay.dts +@@ -0,0 +1,71 @@ ++// Definitions for DACberry400 ++/dts-v1/; ++/plugin/; ++/ { ++ compatible = "brcm,bcm2835"; ++ ++ fragment@0 { ++ target = <&i2s_clk_producer>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@1 { ++ target-path = "/"; ++ __overlay__ { ++ codec_1v8_reg: codec-1v8-reg { ++ compatible = "regulator-fixed"; ++ regulator-name = "tlv320aic3104_1v8"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-always-on; ++ }; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&gpio>; ++ __overlay__ { ++ codec_rst: codec-rst { ++ brcm,pins = <26>; ++ brcm,function = <1>; ++ }; ++ }; ++ }; ++ ++ fragment@3 { ++ target = <&i2c1>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "okay"; ++ ++ tlv320aic3104@18 { ++ #sound-dai-cells = <0>; ++ reg = <0x18>; ++ ++ compatible = "ti,tlv320aic3x"; ++ AVDD-supply = <&vdd_3v3_reg>; ++ DRVDD-supply = <&vdd_3v3_reg>; ++ DVDD-supply = <&codec_1v8_reg>; ++ IOVDD-supply = <&codec_1v8_reg>; ++ ++ gpio-controller; ++ reset-gpios = <&gpio 26 1>; ++ status = "okay"; ++ }; ++ }; ++ }; ++ ++ fragment@4 { ++ target = <&sound>; ++ __overlay__ { ++ compatible = "osaelectronics,dacberry400"; ++ i2s-controller = <&i2s_clk_producer>; ++ status = "okay"; ++ }; ++ }; ++}; ++ ++ diff --git a/arch/arm/boot/dts/overlays/dht11-overlay.dts b/arch/arm/boot/dts/overlays/dht11-overlay.dts new file mode 100644 -index 000000000000..6feeeb402493 +index 000000000000..8b0fc6b7a3cb --- /dev/null +++ b/arch/arm/boot/dts/overlays/dht11-overlay.dts -@@ -0,0 +1,41 @@ +@@ -0,0 +1,48 @@ +/* + * Overlay for the DHT11/21/22 humidity/temperature sensor modules. + */ @@ -16253,13 +26318,19 @@ index 000000000000..6feeeb402493 + fragment@0 { + target-path = "/"; + __overlay__ { -+ -+ dht11: dht11@0 { ++ dht11: dht11@4 { + compatible = "dht11"; + pinctrl-names = "default"; + pinctrl-0 = <&dht11_pins>; + gpios = <&gpio 4 0>; + status = "okay"; ++ #io-channel-cells = <1>; ++ }; ++ ++ iio: iio-hwmon@4 { ++ compatible = "iio-hwmon"; ++ status = "okay"; ++ io-channels = <&dht11 0>, <&dht11 1>; + }; + }; + }; @@ -16267,7 +26338,7 @@ index 000000000000..6feeeb402493 + fragment@1 { + target = <&gpio>; + __overlay__ { -+ dht11_pins: dht11_pins@0 { ++ dht11_pins: dht11_pins@4 { + brcm,pins = <4>; + brcm,function = <0>; // in + brcm,pull = <0>; // off @@ -16279,12 +26350,58 @@ index 000000000000..6feeeb402493 + gpiopin = <&dht11_pins>,"brcm,pins:0", + <&dht11_pins>, "reg:0", + <&dht11>,"gpios:4", -+ <&dht11>,"reg:0"; ++ <&dht11>,"reg:0", ++ <&iio>,"reg:0"; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlays/dionaudio-kiwi-overlay.dts b/arch/arm/boot/dts/overlays/dionaudio-kiwi-overlay.dts +new file mode 100644 +index 000000000000..ab0144cd17dc +--- /dev/null ++++ b/arch/arm/boot/dts/overlays/dionaudio-kiwi-overlay.dts +@@ -0,0 +1,39 @@ ++// Definitions for Dion Audio KIWI streamer ++ ++/* ++ * PCM1794 DAC (in hardware mode). ++ */ ++ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "brcm,bcm2835"; ++ ++ fragment@0 { ++ target = <&i2s_clk_producer>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@1 { ++ target-path = "/"; ++ __overlay__ { ++ pcm1794a-codec { ++ #sound-dai-cells = <0>; ++ compatible = "ti,pcm1794a"; ++ status = "okay"; ++ }; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&sound>; ++ __overlay__ { ++ compatible = "dionaudio,dionaudio-kiwi"; ++ i2s-controller = <&i2s_clk_producer>; ++ status = "okay"; ++ }; + }; +}; diff --git a/arch/arm/boot/dts/overlays/dionaudio-loco-overlay.dts b/arch/arm/boot/dts/overlays/dionaudio-loco-overlay.dts new file mode 100644 -index 000000000000..d863e5c167cc +index 000000000000..6f4a9c1a8243 --- /dev/null +++ b/arch/arm/boot/dts/overlays/dionaudio-loco-overlay.dts @@ -0,0 +1,39 @@ @@ -16301,7 +26418,7 @@ index 000000000000..d863e5c167cc + compatible = "brcm,bcm2835"; + + fragment@0 { -+ target = <&i2s>; ++ target = <&i2s_clk_producer>; + __overlay__ { + status = "okay"; + }; @@ -16322,14 +26439,14 @@ index 000000000000..d863e5c167cc + target = <&sound>; + __overlay__ { + compatible = "dionaudio,loco-pcm5242-tpa3118"; -+ i2s-controller = <&i2s>; ++ i2s-controller = <&i2s_clk_producer>; + status = "okay"; + }; + }; +}; diff --git a/arch/arm/boot/dts/overlays/dionaudio-loco-v2-overlay.dts b/arch/arm/boot/dts/overlays/dionaudio-loco-v2-overlay.dts new file mode 100644 -index 000000000000..dfb8922a654b +index 000000000000..975a844eb272 --- /dev/null +++ b/arch/arm/boot/dts/overlays/dionaudio-loco-v2-overlay.dts @@ -0,0 +1,49 @@ @@ -16350,13 +26467,13 @@ index 000000000000..dfb8922a654b + target = <&sound>; + frag0: __overlay__ { + compatible = "dionaudio,dionaudio-loco-v2"; -+ i2s-controller = <&i2s>; ++ i2s-controller = <&i2s_clk_producer>; + status = "okay"; + }; + }; + + fragment@1 { -+ target = <&i2s>; ++ target = <&i2s_clk_producer>; + __overlay__ { + status = "okay"; + }; @@ -16384,19 +26501,14 @@ index 000000000000..dfb8922a654b +}; diff --git a/arch/arm/boot/dts/overlays/disable-bt-overlay.dts b/arch/arm/boot/dts/overlays/disable-bt-overlay.dts new file mode 100644 -index 000000000000..d5a66e5d76a9 +index 000000000000..f3a8af1375f0 --- /dev/null +++ b/arch/arm/boot/dts/overlays/disable-bt-overlay.dts -@@ -0,0 +1,64 @@ +@@ -0,0 +1,59 @@ +/dts-v1/; +/plugin/; + -+/* Disable Bluetooth and restore UART0/ttyAMA0 over GPIOs 14 & 15. -+ To disable the systemd service that initialises the modem so it doesn't use -+ the UART: -+ -+ sudo systemctl disable hciuart -+*/ ++/* Disable Bluetooth and restore UART0/ttyAMA0 over GPIOs 14 & 15. */ + +#include + @@ -16452,6 +26564,48 @@ index 000000000000..d5a66e5d76a9 + }; + }; +}; +diff --git a/arch/arm/boot/dts/overlays/disable-bt-pi5-overlay.dts b/arch/arm/boot/dts/overlays/disable-bt-pi5-overlay.dts +new file mode 100644 +index 000000000000..6e23b64d44e7 +--- /dev/null ++++ b/arch/arm/boot/dts/overlays/disable-bt-pi5-overlay.dts +@@ -0,0 +1,17 @@ ++/dts-v1/; ++/plugin/; ++ ++/* Disable Bluetooth */ ++ ++#include ++ ++/{ ++ compatible = "brcm,bcm2712"; ++ ++ fragment@0 { ++ target = <&bluetooth>; ++ __overlay__ { ++ status = "disabled"; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlays/disable-emmc2-overlay.dts b/arch/arm/boot/dts/overlays/disable-emmc2-overlay.dts +new file mode 100644 +index 000000000000..8cd1d7fa4a90 +--- /dev/null ++++ b/arch/arm/boot/dts/overlays/disable-emmc2-overlay.dts +@@ -0,0 +1,13 @@ ++/dts-v1/; ++/plugin/; ++ ++/{ ++ compatible = "brcm,bcm2711"; ++ ++ fragment@0 { ++ target = <&emmc2>; ++ __overlay__ { ++ status = "disabled"; ++ }; ++ }; ++}; diff --git a/arch/arm/boot/dts/overlays/disable-wifi-overlay.dts b/arch/arm/boot/dts/overlays/disable-wifi-overlay.dts new file mode 100644 index 000000000000..75e046463900 @@ -16478,6 +26632,25 @@ index 000000000000..75e046463900 + }; + }; +}; +diff --git a/arch/arm/boot/dts/overlays/disable-wifi-pi5-overlay.dts b/arch/arm/boot/dts/overlays/disable-wifi-pi5-overlay.dts +new file mode 100644 +index 000000000000..d5389c5dbb69 +--- /dev/null ++++ b/arch/arm/boot/dts/overlays/disable-wifi-pi5-overlay.dts +@@ -0,0 +1,13 @@ ++/dts-v1/; ++/plugin/; ++ ++/{ ++ compatible = "brcm,bcm2712"; ++ ++ fragment@0 { ++ target = <&sdio2>; ++ __overlay__ { ++ status = "disabled"; ++ }; ++ }; ++}; diff --git a/arch/arm/boot/dts/overlays/dpi18-overlay.dts b/arch/arm/boot/dts/overlays/dpi18-overlay.dts new file mode 100644 index 000000000000..4abe5be744db @@ -16602,7 +26775,7 @@ index 000000000000..44335cc81277 +}; diff --git a/arch/arm/boot/dts/overlays/draws-overlay.dts b/arch/arm/boot/dts/overlays/draws-overlay.dts new file mode 100644 -index 000000000000..d18187d7f343 +index 000000000000..b8801f583369 --- /dev/null +++ b/arch/arm/boot/dts/overlays/draws-overlay.dts @@ -0,0 +1,208 @@ @@ -16617,7 +26790,7 @@ index 000000000000..d18187d7f343 +/ { + compatible = "brcm,bcm2835"; + fragment@0 { -+ target = <&i2s>; ++ target = <&i2s_clk_producer>; + __overlay__ { + status = "okay"; + }; @@ -16739,7 +26912,7 @@ index 000000000000..d18187d7f343 + target = <&sound>; + snd: __overlay__ { + compatible = "simple-audio-card"; -+ i2s-controller = <&i2s>; ++ i2s-controller = <&i2s_clk_producer>; + status = "okay"; + + simple-audio-card,name = "draws"; @@ -16761,7 +26934,7 @@ index 000000000000..d18187d7f343 + "Line Out", "LOL"; + + dailink0_master: simple-audio-card,cpu { -+ sound-dai = <&i2s>; ++ sound-dai = <&i2s_clk_producer>; + }; + + simple-audio-card,codec { @@ -16868,10 +27041,10 @@ index 000000000000..0d83e344ad97 +}; diff --git a/arch/arm/boot/dts/overlays/edt-ft5406-overlay.dts b/arch/arm/boot/dts/overlays/edt-ft5406-overlay.dts new file mode 100644 -index 000000000000..1210e4b8e6dc +index 000000000000..6e40c0ebb3bf --- /dev/null +++ b/arch/arm/boot/dts/overlays/edt-ft5406-overlay.dts -@@ -0,0 +1,26 @@ +@@ -0,0 +1,46 @@ +/* + * Device Tree overlay for EDT 5406 touchscreen controller, as used on the + * Raspberry Pi 7" panel @@ -16897,13 +27070,33 @@ index 000000000000..1210e4b8e6dc + status = "okay"; + }; + }; ++ ++ __overrides__ { ++ i2c0 = <&ts_i2c_frag>,"target:0=",<&i2c0>; ++ i2c1 = <&ts_i2c_frag>, "target?=0", ++ <&ts_i2c_frag>, "target-path=i2c1", ++ <0>,"-0-1"; ++ i2c3 = <&ts_i2c_frag>, "target?=0", ++ <&ts_i2c_frag>, "target-path=i2c3", ++ <0>,"-0-1"; ++ i2c4 = <&ts_i2c_frag>, "target?=0", ++ <&ts_i2c_frag>, "target-path=i2c4", ++ <0>,"-0-1"; ++ i2c5 = <&ts_i2c_frag>, "target?=0", ++ <&ts_i2c_frag>, "target-path=i2c5", ++ <0>,"-0-1"; ++ i2c6 = <&ts_i2c_frag>, "target?=0", ++ <&ts_i2c_frag>, "target-path=i2c6", ++ <0>,"-0-1"; ++ addr = <&ft5406>,"reg:0"; ++ }; +}; diff --git a/arch/arm/boot/dts/overlays/edt-ft5406.dtsi b/arch/arm/boot/dts/overlays/edt-ft5406.dtsi new file mode 100644 -index 000000000000..2d0ff0e8b24e +index 000000000000..16aa5cf91df5 --- /dev/null +++ b/arch/arm/boot/dts/overlays/edt-ft5406.dtsi -@@ -0,0 +1,47 @@ +@@ -0,0 +1,49 @@ +/* + * Device Tree overlay for an EDT FT5406 touchscreen + * @@ -16928,11 +27121,13 @@ index 000000000000..2d0ff0e8b24e + }; + }; + -+ fragment@12 { ++ ts_i2c_frag: fragment@12 { + target = <&i2c_csi_dsi>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; ++ status = "okay"; ++ + ft5406: ts@38 { + compatible = "edt,edt-ft5506"; + reg = <0x38>; @@ -17736,7 +27931,7 @@ index 000000000000..db45f8c53bcc +}; diff --git a/arch/arm/boot/dts/overlays/fe-pi-audio-overlay.dts b/arch/arm/boot/dts/overlays/fe-pi-audio-overlay.dts new file mode 100644 -index 000000000000..743f14ae5768 +index 000000000000..10624fe4f5ac --- /dev/null +++ b/arch/arm/boot/dts/overlays/fe-pi-audio-overlay.dts @@ -0,0 +1,70 @@ @@ -17779,7 +27974,7 @@ index 000000000000..743f14ae5768 + #size-cells = <0>; + status = "okay"; + -+ sgtl5000@0a { ++ sgtl5000@a { + #sound-dai-cells = <0>; + compatible = "fsl,sgtl5000"; + reg = <0x0a>; @@ -17795,7 +27990,7 @@ index 000000000000..743f14ae5768 + }; + + fragment@3 { -+ target = <&i2s>; ++ target = <&i2s_clk_consumer>; + __overlay__ { + status = "okay"; + }; @@ -17805,7 +28000,7 @@ index 000000000000..743f14ae5768 + target = <&sound>; + __overlay__ { + compatible = "fe-pi,fe-pi-audio"; -+ i2s-controller = <&i2s>; ++ i2s-controller = <&i2s_clk_consumer>; + status = "okay"; + }; + }; @@ -17920,9 +28115,166 @@ index 000000000000..e9944f5cd258 + fsm_debug = <&fsm_demo>,"debug:0"; + }; +}; +diff --git a/arch/arm/boot/dts/overlays/gc9a01-overlay.dts b/arch/arm/boot/dts/overlays/gc9a01-overlay.dts +new file mode 100644 +index 000000000000..3d31030c5564 +--- /dev/null ++++ b/arch/arm/boot/dts/overlays/gc9a01-overlay.dts +@@ -0,0 +1,151 @@ ++/* ++ Device Tree overlay for Galaxycore GC9A01A single chip driver ++ for use on SPI TFT LCD, 240x240 65K RGB ++ Based on Galaxycore's GC9A01A datasheet Rev.1.0 (2019/07/02) ++ Copyright (C) 2022, Julianno F. C. Silva (@juliannojungle) ++ ++ This program is free software: you can redistribute it and/or modify ++ it under the terms of the GNU Affero General Public License as published ++ by the Free Software Foundation, either version 3 of the License, or ++ (at your option) any later version. ++ ++ This program is distributed in the hope that it will be useful, ++ but WITHOUT ANY WARRANTY; without even the implied warranty of ++ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ GNU Affero General Public License for more details. ++ ++ You should have received a copy of the GNU Affero General Public License ++ along with this program. If not, see . ++ ++ Init sequence partially based on Waveshare team's Arduino LCD_Driver V1.0 (2020/12/09). ++ ++ Permission is hereby granted, free of UBYTEge, to any person obtaining a copy ++ of this software and associated documnetation files (the "Software"), to deal ++ in the Software without restriction, including without limitation the rights ++ to use, copy, modify, merge, publish, distribute, sublicense, and/or sell ++ copies of the Software, and to permit persons to whom the Software is ++ furished to do so, subject to the following conditions: ++ ++ The above copyright notice and this permission notice shall be included in ++ all copies or substantial portions of the Software. ++ */ ++ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "brcm,bcm2835"; ++ ++ fragment@0 { ++ target = <&spidev0>; ++ __overlay__ { ++ status = "disabled"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&gpio>; ++ __overlay__ { ++ gc9a01_pins: gc9a01_pins { ++ brcm,pins = <25 27>; ++ brcm,function = <1 1>; /* out */ ++ brcm,pull = <0 0>; /* none */ ++ }; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&spi0>; ++ __overlay__ { ++ /* needed to avoid dtc warning */ ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "okay"; ++ ++ gc9a01: gc9a01@0 { ++ compatible = "ilitek,ili9340"; ++ reg = <0>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&gc9a01_pins>; ++ reset-gpios = <&gpio 27 1>; ++ dc-gpios = <&gpio 25 0>; ++ led-gpios = <&gpio 18 0>; ++ spi-max-frequency = <40000000>; ++ buswidth = <8>; ++ width = <240>; ++ height = <240>; ++ rotate = <0>; ++ fps = <50>; ++ bgr; ++ debug = <0>; ++ init = < ++ 0x01000011 /* Sleep mode OFF */ ++ 0x02000078 /* Delay 120ms */ ++ 0x010000EF /* Inter register enable 2 */ ++ 0x010000EB 0x14 ++ /* BEGIN set inter_command HIGH */ ++ 0x010000FE /* Inter register enable 1 */ ++ 0x010000EF /* Inter register enable 2 */ ++ /* END set inter_command HIGH */ ++ 0x010000EB 0x14 ++ 0x01000084 0x40 ++ 0x01000085 0xFF ++ 0x01000086 0xFF ++ 0x01000087 0xFF ++ 0x01000088 0x0A ++ 0x01000089 0x21 ++ 0x0100008A 0x00 ++ 0x0100008B 0x80 ++ 0x0100008C 0x01 ++ 0x0100008D 0x01 ++ 0x0100008E 0xFF ++ 0x0100008F 0xFF ++ 0x010000B6 0x00 0x00 /* Display function control */ ++ 0x01000036 0x08 /* Memory access control */ ++ 0x0100003A 0x05 /* Pixel format */ ++ 0x01000090 0x08 0x08 0x08 0x08 ++ 0x010000BD 0x06 ++ 0x010000BC 0x00 ++ 0x010000FF 0x60 0x01 0x04 ++ 0x010000C3 0x13 /* Voltage regulator 1a */ ++ 0x010000C4 0x13 /* Voltage regulator 1b */ ++ 0x010000C9 0x22 /* Voltage regulator 2a */ ++ 0x010000BE 0x11 ++ 0x010000E1 0x10 0x0E ++ 0x010000DF 0x21 0x0c 0x02 ++ 0x010000F0 0x45 0x09 0x08 0x08 0x26 0x2A /* Set gamma1 */ ++ 0x010000F1 0x43 0x70 0x72 0x36 0x37 0x6F /* Set gamma2 */ ++ 0x010000F2 0x45 0x09 0x08 0x08 0x26 0x2A /* Set gamma3 */ ++ 0x010000F3 0x43 0x70 0x72 0x36 0x37 0x6F /* Set gamma4 */ ++ 0x010000ED 0x1B 0x0B ++ 0x010000AE 0x77 ++ 0x010000CD 0x63 ++ 0x01000070 0x07 0x07 0x04 0x0E 0x0F 0x09 0x07 0x08 0x03 ++ 0x010000E8 0x34 /* Frame rate */ ++ 0x01000062 0x18 0x0D 0x71 0xED 0x70 0x70 0x18 0x0F 0x71 0xEF 0x70 0x70 ++ 0x01000063 0x18 0x11 0x71 0xF1 0x70 0x70 0x18 0x13 0x71 0xF3 0x70 0x70 ++ 0x01000064 0x28 0x29 0xF1 0x01 0xF1 0x00 0x07 ++ 0x01000066 0x3C 0x00 0xCD 0x67 0x45 0x45 0x10 0x00 0x00 0x00 ++ 0x01000067 0x00 0x3C 0x00 0x00 0x00 0x01 0x54 0x10 0x32 0x98 ++ 0x01000074 0x10 0x85 0x80 0x00 0x00 0x4E 0x00 ++ 0x01000098 0x3e 0x07 ++ 0x01000035 /* Tearing effect ON */ ++ 0x01000021 /* Display inversion ON */ ++ 0x01000011 /* Sleep mode OFF */ ++ 0x0200000C /* Delay 12ms */ ++ 0x01000029 /* Display ON */ ++ 0x02000014 /* Delay 20ms */ ++ >; ++ }; ++ }; ++ }; ++ ++ __overrides__ { ++ speed = <&gc9a01>,"spi-max-frequency:0"; ++ rotate = <&gc9a01>,"rotate:0"; ++ width = <&gc9a01>,"width:0"; ++ height = <&gc9a01>,"height:0"; ++ fps = <&gc9a01>,"fps:0"; ++ debug = <&gc9a01>,"debug:0"; ++ }; ++}; diff --git a/arch/arm/boot/dts/overlays/ghost-amp-overlay.dts b/arch/arm/boot/dts/overlays/ghost-amp-overlay.dts new file mode 100644 -index 000000000000..7509e00679c8 +index 000000000000..d2f1e9a888e0 --- /dev/null +++ b/arch/arm/boot/dts/overlays/ghost-amp-overlay.dts @@ -0,0 +1,145 @@ @@ -17942,7 +28294,7 @@ index 000000000000..7509e00679c8 + compatible = "brcm,bcm2835"; + + fragment@0 { -+ target = <&i2s>; ++ target = <&i2s_clk_producer>; + __overlay__ { + status = "okay"; + }; @@ -17971,7 +28323,7 @@ index 000000000000..7509e00679c8 + target = <&sound>; + iqaudio_dac: __overlay__ { + compatible = "iqaudio,iqaudio-dac"; -+ i2s-controller = <&i2s>; ++ i2s-controller = <&i2s_clk_producer>; + mute-gpios = <& 0 0>; + iqaudio-dac,auto-mute-amp; + status = "okay"; @@ -18125,7 +28477,7 @@ index 000000000000..8571527de49a +}; diff --git a/arch/arm/boot/dts/overlays/googlevoicehat-soundcard-overlay.dts b/arch/arm/boot/dts/overlays/googlevoicehat-soundcard-overlay.dts new file mode 100644 -index 000000000000..e443be1f9a0e +index 000000000000..1063f1898562 --- /dev/null +++ b/arch/arm/boot/dts/overlays/googlevoicehat-soundcard-overlay.dts @@ -0,0 +1,49 @@ @@ -18137,7 +28489,7 @@ index 000000000000..e443be1f9a0e + compatible = "brcm,bcm2835"; + + fragment@0 { -+ target = <&i2s>; ++ target = <&i2s_clk_producer>; + __overlay__ { + status = "okay"; + }; @@ -18173,17 +28525,65 @@ index 000000000000..e443be1f9a0e + target = <&sound>; + __overlay__ { + compatible = "googlevoicehat,googlevoicehat-soundcard"; -+ i2s-controller = <&i2s>; ++ i2s-controller = <&i2s_clk_producer>; + status = "okay"; + }; + }; +}; +diff --git a/arch/arm/boot/dts/overlays/gpio-charger-overlay.dts b/arch/arm/boot/dts/overlays/gpio-charger-overlay.dts +new file mode 100644 +index 000000000000..2868aa06dd6d +--- /dev/null ++++ b/arch/arm/boot/dts/overlays/gpio-charger-overlay.dts +@@ -0,0 +1,42 @@ ++// Definitions for gpio-charger module ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "brcm,bcm2835"; ++ ++ fragment@0 { ++ // Configure the gpio pin controller ++ target = <&gpio>; ++ __overlay__ { ++ pin_state: charger_pins@0 { ++ brcm,pins = <4>; // gpio number ++ brcm,function = <0>; // 0 = input, 1 = output ++ brcm,pull = <1>; // 0 = none, 1 = pull down, 2 = pull up ++ }; ++ }; ++ }; ++ fragment@1 { ++ target-path = "/"; ++ __overlay__ { ++ charger: charger@0 { ++ compatible = "gpio-charger"; ++ pinctrl-0 = <&pin_state>; ++ status = "okay"; ++ gpios = <&gpio 4 0>; ++ charger-type = "mains"; ++ }; ++ }; ++ }; ++ ++ __overrides__ { ++ gpio = <&charger>,"reg:0", ++ <&charger>,"gpios:4", ++ <&pin_state>,"reg:0", ++ <&pin_state>,"brcm,pins:0"; ++ type = <&charger>,"charger-type"; ++ gpio_pull = <&pin_state>,"brcm,pull:0"; ++ active_low = <&charger>,"gpios:8"; ++ }; ++ ++}; diff --git a/arch/arm/boot/dts/overlays/gpio-fan-overlay.dts b/arch/arm/boot/dts/overlays/gpio-fan-overlay.dts new file mode 100644 -index 000000000000..77a7bbb41e3b +index 000000000000..17b77bb27931 --- /dev/null +++ b/arch/arm/boot/dts/overlays/gpio-fan-overlay.dts -@@ -0,0 +1,79 @@ +@@ -0,0 +1,89 @@ +/* + * Overlay for the Raspberry Pi GPIO Fan @ BCM GPIO12. + * References: @@ -18241,26 +28641,69 @@ index 000000000000..77a7bbb41e3b + + fragment@1 { + target = <&cpu_thermal>; -+ polling-delay = <2000>; /* milliseconds */ + __overlay__ { -+ trips { -+ cpu_hot: trip-point@0 { -+ temperature = <55000>; /* (millicelsius) Fan started at 55°C */ -+ hysteresis = <10000>; /* (millicelsius) Fan stopped at 45°C */ -+ type = "active"; -+ }; -+ }; -+ cooling-maps { -+ map0 { -+ trip = <&cpu_hot>; -+ cooling-device = <&fan0 1 1>; -+ }; ++ polling-delay = <2000>; /* milliseconds */ ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&thermal_trips>; ++ __overlay__ { ++ cpu_hot: trip-point@0 { ++ temperature = <55000>; /* (millicelsius) Fan started at 55°C */ ++ hysteresis = <10000>; /* (millicelsius) Fan stopped at 45°C */ ++ type = "active"; + }; + }; + }; ++ ++ fragment@3 { ++ target = <&cooling_maps>; ++ __overlay__ { ++ map0 { ++ trip = <&cpu_hot>; ++ cooling-device = <&fan0 1 1>; ++ }; ++ }; ++ }; ++ + __overrides__ { + gpiopin = <&fan0>,"gpios:4", <&fan0>,"brcm,pins:0"; + temp = <&cpu_hot>,"temperature:0"; ++ hyst = <&cpu_hot>,"hysteresis:0"; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlays/gpio-hog-overlay.dts b/arch/arm/boot/dts/overlays/gpio-hog-overlay.dts +new file mode 100644 +index 000000000000..c9e39046fed9 +--- /dev/null ++++ b/arch/arm/boot/dts/overlays/gpio-hog-overlay.dts +@@ -0,0 +1,27 @@ ++// Configure a "hog" on the specified GPIO ++/dts-v1/; ++/plugin/; ++ ++#include ++ ++/ { ++ compatible = "brcm,bcm2835"; ++ ++ fragment@0 { ++ target = <&gpio>; ++ __overlay__ { ++ hog: hog@1a { ++ gpio-hog; ++ gpios = <26 GPIO_ACTIVE_HIGH>; ++ output-high; ++ }; ++ }; ++ }; ++ ++ __overrides__ { ++ gpio = <&hog>,"reg:0", ++ <&hog>,"gpios:0"; ++ active_low = <&hog>,"output-high!", ++ <&hog>,"output-low?"; + }; +}; diff --git a/arch/arm/boot/dts/overlays/gpio-ir-overlay.dts b/arch/arm/boot/dts/overlays/gpio-ir-overlay.dts @@ -18694,6 +29137,110 @@ index 000000000000..da148064aedd + }; + +}; +diff --git a/arch/arm/boot/dts/overlays/hat_map.dts b/arch/arm/boot/dts/overlays/hat_map.dts +new file mode 100644 +index 000000000000..cb96b680cb4f +--- /dev/null ++++ b/arch/arm/boot/dts/overlays/hat_map.dts +@@ -0,0 +1,98 @@ ++/dts-v1/; ++ ++/ { ++ hifiberry-amp100-1 { ++ uuid = [ 5eb863b8 12f9 41ad 978f 4cee1b3eca62 ]; ++ overlay = "hifiberry-amp100"; ++ }; ++ ++ hifiberry-amp100-2 { ++ uuid = [ b1a57dbe 8b52 447f 939e 1baf72157d79 ]; ++ overlay = "hifiberry-amp100"; ++ }; ++ ++ hifiberry-amp4pro { ++ uuid = [ 3619722a c92d 4092 95bd 493a2903e933 ]; ++ overlay = "hifiberry-amp4pro"; ++ }; ++ ++ hifiberry-amp4 { ++ uuid = [ fcb6ec42 a182 419d a314 7eeae416f608 ]; ++ overlay = "hifiberry-dacplus-std"; ++ }; ++ ++ hifiberry-dac2proadc { ++ uuid = [ 30660215 dbb2 4c57 953f 099370b63e2e ]; ++ overlay = "hifiberry-dacplusadcpro"; ++ }; ++ ++ hifiberry-dac2hd { ++ uuid = [ 482ad277 5586 480c 88e7 85ae89c4e501 ]; ++ overlay = "hifiberry-dacplushd"; ++ }; ++ ++ hifiberry-dac2pro { ++ uuid = [ ebf9cfc4 6d77 4880 89fd 353690467dfc ]; ++ overlay = "hifiberry-dacplus-pro"; ++ }; ++ ++ hifiberry-dac8x { ++ uuid = [ f65985f9 5354 4457 ae3b 3da39ba2cf6d ]; ++ overlay = "hifiberry-dac8x"; ++ }; ++ ++ hifiberry-dacplus-amp2-1 { ++ uuid = [ 81cac43d 27c6 4a1e a0b2 c70b4e608ab6 ]; ++ overlay = "hifiberry-dacplus-std"; ++ }; ++ ++ hifiberry-dacplus-amp2-2 { ++ uuid = [ ef586afc 2efa 47a0 be2e 95a7d952fe98 ]; ++ overlay = "hifiberry-dacplus-std"; ++ }; ++ ++ hifiberry-digiplus-pro { ++ uuid = [ 2154f80b 0f92 45e4 96db c1643ec2b46b ]; ++ overlay = "hifiberry-digi-pro"; ++ }; ++ ++ hifiberry-dacplusadcpro { ++ uuid = [ 36e3d3da 1ed9 468b aea3 cd165f6820f0 ]; ++ overlay = "hifiberry-dacplusadcpro"; ++ }; ++ ++ hifiberry-digi2pro { ++ uuid = [ 5af941bb 4dcf 4eac 82a8 e36e84fcabef ]; ++ overlay = "hifiberry-digi-pro"; ++ }; ++ ++ hifiberry-digi2standard { ++ uuid = [ 7c980a0e 9d15 40af 9f40 bddfbd3aee8c ]; ++ overlay = "hifiberry-digi"; ++ }; ++ ++ hifiberry-dsp2x4 { ++ uuid = [ 8f287583 429d 4206 a751 862264bbda63 ]; ++ overlay = "hifiberry-dacplus-dsp"; ++ }; ++ ++ iqaudio-pi-codecplus { ++ uuid = [ dc1c9594 c1ab 4c6c acda a88dc59a3c5b ]; ++ overlay = "iqaudio-codec"; ++ }; ++ ++ iqaudio-pi-codeczero { ++ uuid = [ e15c739c 877d 4e29 ab36 4dc73c21127c ]; ++ overlay = "iqaudio-codec"; ++ }; ++ ++ pisound { ++ uuid = [ a7ee5d28 da03 41f5 bbd7 20438a4bec5d ]; ++ overlay = "pisound"; ++ }; ++ ++ recalbox-rgbdual { ++ uuid = [ 1c955808 681f 4bbc a2ef b7ea47cd388e ]; ++ overlay = "recalboxrgbdual"; ++ }; ++}; diff --git a/arch/arm/boot/dts/overlays/hd44780-lcd-overlay.dts b/arch/arm/boot/dts/overlays/hd44780-lcd-overlay.dts new file mode 100644 index 000000000000..ee726669ff51 @@ -18801,7 +29348,7 @@ index 000000000000..50b9a2665c80 +}; diff --git a/arch/arm/boot/dts/overlays/hifiberry-amp-overlay.dts b/arch/arm/boot/dts/overlays/hifiberry-amp-overlay.dts new file mode 100644 -index 000000000000..142518ab348b +index 000000000000..667cd2601806 --- /dev/null +++ b/arch/arm/boot/dts/overlays/hifiberry-amp-overlay.dts @@ -0,0 +1,39 @@ @@ -18813,7 +29360,7 @@ index 000000000000..142518ab348b + compatible = "brcm,bcm2835"; + + fragment@0 { -+ target = <&i2s>; ++ target = <&i2s_clk_producer>; + __overlay__ { + status = "okay"; + }; @@ -18839,17 +29386,17 @@ index 000000000000..142518ab348b + target = <&sound>; + __overlay__ { + compatible = "hifiberry,hifiberry-amp"; -+ i2s-controller = <&i2s>; ++ i2s-controller = <&i2s_clk_producer>; + status = "okay"; + }; + }; +}; diff --git a/arch/arm/boot/dts/overlays/hifiberry-amp100-overlay.dts b/arch/arm/boot/dts/overlays/hifiberry-amp100-overlay.dts new file mode 100644 -index 000000000000..ebdef55d6110 +index 000000000000..b38e6631a572 --- /dev/null +++ b/arch/arm/boot/dts/overlays/hifiberry-amp100-overlay.dts -@@ -0,0 +1,64 @@ +@@ -0,0 +1,67 @@ +// Definitions for HiFiBerry AMP100 +/dts-v1/; +/plugin/; @@ -18867,8 +29414,8 @@ index 000000000000..ebdef55d6110 + }; + }; + -+ fragment@1 { -+ target = <&i2s>; ++ frag1: fragment@1 { ++ target = <&i2s_clk_consumer>; + __overlay__ { + status = "okay"; + }; @@ -18898,7 +29445,7 @@ index 000000000000..ebdef55d6110 + target = <&sound>; + hifiberry_dacplus: __overlay__ { + compatible = "hifiberry,hifiberry-dacplus"; -+ i2s-controller = <&i2s>; ++ i2s-controller = <&i2s_clk_consumer>; + status = "okay"; + mute-gpio = <&gpio 4 0>; + reset-gpio = <&gpio 17 0x11>; @@ -18908,15 +29455,150 @@ index 000000000000..ebdef55d6110 + __overrides__ { + 24db_digital_gain = + <&hifiberry_dacplus>,"hifiberry,24db_digital_gain?"; -+ slave = <&hifiberry_dacplus>,"hifiberry-dacplus,slave?"; ++ slave = <&hifiberry_dacplus>,"hifiberry-dacplus,slave?", ++ <&frag1>,"target:0=",<&i2s_clk_producer>, ++ <&hifiberry_dacplus>,"i2s-controller:0=",<&i2s_clk_producer>; ++ + leds_off = <&hifiberry_dacplus>,"hifiberry-dacplus,leds_off?"; + mute_ext_ctl = <&hifiberry_dacplus>,"hifiberry-dacplus,mute_ext_ctl:0"; + auto_mute = <&hifiberry_dacplus>,"hifiberry-dacplus,auto_mute?"; + }; +}; +diff --git a/arch/arm/boot/dts/overlays/hifiberry-amp3-overlay.dts b/arch/arm/boot/dts/overlays/hifiberry-amp3-overlay.dts +new file mode 100644 +index 000000000000..fc8f11b6294e +--- /dev/null ++++ b/arch/arm/boot/dts/overlays/hifiberry-amp3-overlay.dts +@@ -0,0 +1,57 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++// Definitions for HiFiBerry's Amp3 ++/dts-v1/; ++/plugin/; ++#include ++#include ++ ++ ++/ { ++ compatible = "brcm,bcm2835"; ++ ++ fragment@0 { ++ target = <&i2s_clk_producer>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&gpio>; ++ __overlay__ { ++ hifiberry_amp3_pins: hifiberry_amp3_pins { ++ brcm,pins = <23 17>; ++ brcm,function = <0 1>; ++ brcm,pull = <2 1>; ++ }; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&i2c1>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "okay"; ++ ++ hifiberry_amp2: ma120x0p@20 { ++ #sound-dai-cells = <0>; ++ compatible = "ma,ma120x0p"; ++ reg = <0x20>; ++ status = "okay"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&hifiberry_amp3_pins>; ++ error_gp-gpios = <&gpio 23 GPIO_ACTIVE_HIGH>; ++ }; ++ }; ++ }; ++ ++ fragment@3 { ++ target = <&sound>; ++ __overlay__ { ++ compatible = "hifiberry,hifiberry-amp3"; ++ i2s-controller = <&i2s_clk_producer>; ++ status = "okay"; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlays/hifiberry-amp4pro-overlay.dts b/arch/arm/boot/dts/overlays/hifiberry-amp4pro-overlay.dts +new file mode 100644 +index 000000000000..6b211c2932dd +--- /dev/null ++++ b/arch/arm/boot/dts/overlays/hifiberry-amp4pro-overlay.dts +@@ -0,0 +1,63 @@ ++// Definitions for HiFiBerry AMP4PRO ++/dts-v1/; ++/plugin/; ++#include ++ ++/ { ++ compatible = "brcm,bcm2835"; ++ ++ fragment@0 { ++ target-path = "/"; ++ __overlay__ { ++ dacpro_osc: dacpro_osc { ++ compatible = "hifiberry,dacpro-clk"; ++ #clock-cells = <0>; ++ }; ++ }; ++ }; ++ ++ frag1: fragment@1 { ++ target = <&i2s_clk_consumer>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&i2c1>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "okay"; ++ ++ tas5756@4d { ++ #sound-dai-cells = <0>; ++ compatible = "ti,tas5756"; ++ reg = <0x4d>; ++ clocks = <&dacpro_osc>; ++ status = "okay"; ++ }; ++ }; ++ }; ++ ++ fragment@3 { ++ target = <&sound>; ++ hifiberry_dacplus: __overlay__ { ++ compatible = "hifiberry,hifiberry-dacplus"; ++ i2s-controller = <&i2s_clk_consumer>; ++ status = "okay"; ++ mute-gpio = <&gpio 4 GPIO_ACTIVE_LOW>; ++ }; ++ }; ++ ++ __overrides__ { ++ 24db_digital_gain = ++ <&hifiberry_dacplus>,"hifiberry-amp4,24db_digital_gain?"; ++ leds_off = <&hifiberry_dacplus>,"hifiberry-amp4,leds_off?"; ++ mute_ext_ctl = <&hifiberry_dacplus>,"hifiberry-amp4,mute_ext_ctl:0"; ++ auto_mute = <&hifiberry_dacplus>,"hifiberry-amp4,auto_mute?"; ++ slave = <&hifiberry_dacplus>,"hifiberry-dacplus,slave?", ++ <&frag1>,"target:0=",<&i2s_clk_producer>, ++ <&hifiberry_dacplus>,"i2s-controller:0=",<&i2s_clk_producer>; ++ }; ++}; diff --git a/arch/arm/boot/dts/overlays/hifiberry-dac-overlay.dts b/arch/arm/boot/dts/overlays/hifiberry-dac-overlay.dts new file mode 100644 -index 000000000000..ea8a6c8f36c0 +index 000000000000..efb0e18dbdc4 --- /dev/null +++ b/arch/arm/boot/dts/overlays/hifiberry-dac-overlay.dts @@ -0,0 +1,34 @@ @@ -18928,7 +29610,7 @@ index 000000000000..ea8a6c8f36c0 + compatible = "brcm,bcm2835"; + + fragment@0 { -+ target = <&i2s>; ++ target = <&i2s_clk_producer>; + __overlay__ { + status = "okay"; + }; @@ -18949,17 +29631,73 @@ index 000000000000..ea8a6c8f36c0 + target = <&sound>; + __overlay__ { + compatible = "hifiberry,hifiberry-dac"; -+ i2s-controller = <&i2s>; ++ i2s-controller = <&i2s_clk_producer>; + status = "okay"; + }; + }; +}; +diff --git a/arch/arm/boot/dts/overlays/hifiberry-dac8x-overlay.dts b/arch/arm/boot/dts/overlays/hifiberry-dac8x-overlay.dts +new file mode 100644 +index 000000000000..efeff792f396 +--- /dev/null ++++ b/arch/arm/boot/dts/overlays/hifiberry-dac8x-overlay.dts +@@ -0,0 +1,50 @@ ++// Definitions for HiFiBerry DAC8x ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "brcm,bcm2712"; ++ ++ fragment@0 { ++ target = <&gpio>; ++ __overlay__ { ++ rp1_i2s0_dac8x: rp1_i2s0_dac8x { ++ function = "i2s0"; ++ pins = "gpio18", "gpio19", "gpio21", ++ "gpio23", "gpio25", "gpio27"; ++ bias-disable; ++ status = "okay"; ++ }; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&i2s_clk_producer>; ++ __overlay__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&rp1_i2s0_dac8x>; ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@2 { ++ target-path = "/"; ++ __overlay__ { ++ pcm5102a-codec { ++ #sound-dai-cells = <0>; ++ compatible = "ti,pcm5102a"; ++ status = "okay"; ++ }; ++ }; ++ }; ++ ++ fragment@3 { ++ target = <&sound>; ++ __overlay__ { ++ compatible = "hifiberry,hifiberry-dac8x"; ++ i2s-controller = <&i2s_clk_producer>; ++ status = "okay"; ++ }; ++ }; ++ ++}; diff --git a/arch/arm/boot/dts/overlays/hifiberry-dacplus-overlay.dts b/arch/arm/boot/dts/overlays/hifiberry-dacplus-overlay.dts new file mode 100644 -index 000000000000..ff19015ba656 +index 000000000000..0d0ab068112f --- /dev/null +++ b/arch/arm/boot/dts/overlays/hifiberry-dacplus-overlay.dts -@@ -0,0 +1,65 @@ +@@ -0,0 +1,68 @@ +// Definitions for HiFiBerry DAC+ +/dts-v1/; +/plugin/; @@ -18977,8 +29715,8 @@ index 000000000000..ff19015ba656 + }; + }; + -+ fragment@1 { -+ target = <&i2s>; ++ frag1: fragment@1 { ++ target = <&i2s_clk_consumer>; + __overlay__ { + status = "okay"; + }; @@ -19013,7 +29751,7 @@ index 000000000000..ff19015ba656 + target = <&sound>; + hifiberry_dacplus: __overlay__ { + compatible = "hifiberry,hifiberry-dacplus"; -+ i2s-controller = <&i2s>; ++ i2s-controller = <&i2s_clk_consumer>; + status = "okay"; + }; + }; @@ -19021,17 +29759,90 @@ index 000000000000..ff19015ba656 + __overrides__ { + 24db_digital_gain = + <&hifiberry_dacplus>,"hifiberry,24db_digital_gain?"; -+ slave = <&hifiberry_dacplus>,"hifiberry-dacplus,slave?"; ++ slave = <&hifiberry_dacplus>,"hifiberry-dacplus,slave?", ++ <&frag1>,"target:0=",<&i2s_clk_producer>, ++ <&hifiberry_dacplus>,"i2s-controller:0=",<&i2s_clk_producer>; ++ + leds_off = <&hifiberry_dacplus>,"hifiberry-dacplus,leds_off?"; + }; +}; -diff --git a/arch/arm/boot/dts/overlays/hifiberry-dacplusadc-overlay.dts b/arch/arm/boot/dts/overlays/hifiberry-dacplusadc-overlay.dts +diff --git a/arch/arm/boot/dts/overlays/hifiberry-dacplus-pro-overlay.dts b/arch/arm/boot/dts/overlays/hifiberry-dacplus-pro-overlay.dts new file mode 100644 -index 000000000000..540563dec10f +index 000000000000..28b1c2f2f1a8 --- /dev/null -+++ b/arch/arm/boot/dts/overlays/hifiberry-dacplusadc-overlay.dts -@@ -0,0 +1,72 @@ -+// Definitions for HiFiBerry DAC+ADC ++++ b/arch/arm/boot/dts/overlays/hifiberry-dacplus-pro-overlay.dts +@@ -0,0 +1,64 @@ ++// Definitions for HiFiBerry DAC+ PRO, with onboard clocks ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "brcm,bcm2835"; ++ ++ fragment@0 { ++ target-path = "/"; ++ __overlay__ { ++ dacpro_osc: dacpro_osc { ++ compatible = "hifiberry,dacpro-clk"; ++ #clock-cells = <0>; ++ }; ++ }; ++ }; ++ ++ frag1: fragment@1 { ++ target = <&i2s_clk_consumer>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&i2c1>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "okay"; ++ ++ pcm5122@4d { ++ #sound-dai-cells = <0>; ++ compatible = "ti,pcm5122"; ++ reg = <0x4d>; ++ clocks = <&dacpro_osc>; ++ AVDD-supply = <&vdd_3v3_reg>; ++ DVDD-supply = <&vdd_3v3_reg>; ++ CPVDD-supply = <&vdd_3v3_reg>; ++ status = "okay"; ++ }; ++ hpamp: hpamp@60 { ++ compatible = "ti,tpa6130a2"; ++ reg = <0x60>; ++ status = "disabled"; ++ }; ++ }; ++ }; ++ ++ fragment@3 { ++ target = <&sound>; ++ hifiberry_dacplus: __overlay__ { ++ compatible = "hifiberry,hifiberry-dacplus"; ++ i2s-controller = <&i2s_clk_consumer>; ++ status = "okay"; ++ }; ++ }; ++ ++ __overrides__ { ++ 24db_digital_gain = ++ <&hifiberry_dacplus>,"hifiberry,24db_digital_gain?"; ++ leds_off = <&hifiberry_dacplus>,"hifiberry-dacplus,leds_off?"; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlays/hifiberry-dacplus-std-overlay.dts b/arch/arm/boot/dts/overlays/hifiberry-dacplus-std-overlay.dts +new file mode 100644 +index 000000000000..8872e3aa348d +--- /dev/null ++++ b/arch/arm/boot/dts/overlays/hifiberry-dacplus-std-overlay.dts +@@ -0,0 +1,65 @@ ++// Definitions for HiFiBerry DAC+ Standard w/o onboard clocks +/dts-v1/; +/plugin/; + @@ -19049,7 +29860,78 @@ index 000000000000..540563dec10f + }; + + fragment@1 { -+ target = <&i2s>; ++ target = <&i2s_clk_producer>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&i2c1>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "okay"; ++ ++ pcm5122@4d { ++ #sound-dai-cells = <0>; ++ compatible = "ti,pcm5122"; ++ reg = <0x4d>; ++ clocks = <&dacpro_osc>; ++ AVDD-supply = <&vdd_3v3_reg>; ++ DVDD-supply = <&vdd_3v3_reg>; ++ CPVDD-supply = <&vdd_3v3_reg>; ++ status = "okay"; ++ }; ++ hpamp: hpamp@60 { ++ compatible = "ti,tpa6130a2"; ++ reg = <0x60>; ++ status = "disabled"; ++ }; ++ }; ++ }; ++ ++ fragment@3 { ++ target = <&sound>; ++ hifiberry_dacplus: __overlay__ { ++ compatible = "hifiberry,hifiberry-dacplus"; ++ i2s-controller = <&i2s_clk_producer>; ++ hifiberry-dacplus,slave; ++ status = "okay"; ++ }; ++ }; ++ ++ __overrides__ { ++ 24db_digital_gain = ++ <&hifiberry_dacplus>,"hifiberry,24db_digital_gain?"; ++ leds_off = <&hifiberry_dacplus>,"hifiberry-dacplus,leds_off?"; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlays/hifiberry-dacplusadc-overlay.dts b/arch/arm/boot/dts/overlays/hifiberry-dacplusadc-overlay.dts +new file mode 100644 +index 000000000000..ea4c3572826f +--- /dev/null ++++ b/arch/arm/boot/dts/overlays/hifiberry-dacplusadc-overlay.dts +@@ -0,0 +1,72 @@ ++// Definitions for HiFiBerry DAC+ADC, no onboard clocks ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "brcm,bcm2835"; ++ ++ fragment@0 { ++ target-path = "/"; ++ __overlay__ { ++ dacpro_osc: dacpro_osc { ++ compatible = "hifiberry,dacpro-clk"; ++ #clock-cells = <0>; ++ }; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&i2s_clk_producer>; + __overlay__ { + status = "okay"; + }; @@ -19091,7 +29973,8 @@ index 000000000000..540563dec10f + target = <&sound>; + hifiberry_dacplusadc: __overlay__ { + compatible = "hifiberry,hifiberry-dacplusadc"; -+ i2s-controller = <&i2s>; ++ i2s-controller = <&i2s_clk_producer>; ++ hifiberry-dacplusadc,slave; + status = "okay"; + }; + }; @@ -19099,16 +29982,15 @@ index 000000000000..540563dec10f + __overrides__ { + 24db_digital_gain = + <&hifiberry_dacplusadc>,"hifiberry,24db_digital_gain?"; -+ slave = <&hifiberry_dacplusadc>,"hifiberry-dacplusadc,slave?"; + leds_off = <&hifiberry_dacplusadc>,"hifiberry-dacplusadc,leds_off?"; + }; +}; diff --git a/arch/arm/boot/dts/overlays/hifiberry-dacplusadcpro-overlay.dts b/arch/arm/boot/dts/overlays/hifiberry-dacplusadcpro-overlay.dts new file mode 100644 -index 000000000000..561cd84bbb79 +index 000000000000..a4268bd72477 --- /dev/null +++ b/arch/arm/boot/dts/overlays/hifiberry-dacplusadcpro-overlay.dts -@@ -0,0 +1,70 @@ +@@ -0,0 +1,72 @@ +// Definitions for HiFiBerry DAC+ADC PRO +/dts-v1/; +/plugin/; @@ -19126,8 +30008,8 @@ index 000000000000..561cd84bbb79 + }; + }; + -+ fragment@1 { -+ target = <&i2s>; ++ frag1: fragment@1 { ++ target = <&i2s_clk_consumer>; + __overlay__ { + status = "okay"; + }; @@ -19167,7 +30049,7 @@ index 000000000000..561cd84bbb79 + hifiberry_dacplusadcpro: __overlay__ { + compatible = "hifiberry,hifiberry-dacplusadcpro"; + audio-codec = <&hb_dac &hb_adc>; -+ i2s-controller = <&i2s>; ++ i2s-controller = <&i2s_clk_consumer>; + status = "okay"; + }; + }; @@ -19175,13 +30057,15 @@ index 000000000000..561cd84bbb79 + __overrides__ { + 24db_digital_gain = + <&hifiberry_dacplusadcpro>,"hifiberry-dacplusadcpro,24db_digital_gain?"; -+ slave = <&hifiberry_dacplusadcpro>,"hifiberry-dacplusadcpro,slave?"; ++ slave = <&hifiberry_dacplusadcpro>,"hifiberry-dacplusadcpro,slave?", ++ <&frag1>,"target:0=",<&i2s_clk_producer>, ++ <&hifiberry_dacplusadcpro>,"i2s-controller:0=",<&i2s_clk_producer>; + leds_off = <&hifiberry_dacplusadcpro>,"hifiberry-dacplusadcpro,leds_off?"; + }; +}; diff --git a/arch/arm/boot/dts/overlays/hifiberry-dacplusdsp-overlay.dts b/arch/arm/boot/dts/overlays/hifiberry-dacplusdsp-overlay.dts new file mode 100644 -index 000000000000..63432e8b983f +index 000000000000..e916485f737e --- /dev/null +++ b/arch/arm/boot/dts/overlays/hifiberry-dacplusdsp-overlay.dts @@ -0,0 +1,34 @@ @@ -19193,7 +30077,7 @@ index 000000000000..63432e8b983f + compatible = "brcm,bcm2835"; + + fragment@0 { -+ target = <&i2s>; ++ target = <&i2s_clk_producer>; + __overlay__ { + status = "okay"; + }; @@ -19214,17 +30098,17 @@ index 000000000000..63432e8b983f + target = <&sound>; + __overlay__ { + compatible = "hifiberrydacplusdsp,hifiberrydacplusdsp-soundcard"; -+ i2s-controller = <&i2s>; ++ i2s-controller = <&i2s_clk_producer>; + status = "okay"; + }; + }; +}; diff --git a/arch/arm/boot/dts/overlays/hifiberry-dacplushd-overlay.dts b/arch/arm/boot/dts/overlays/hifiberry-dacplushd-overlay.dts new file mode 100644 -index 000000000000..c5583e010339 +index 000000000000..1856ac19793b --- /dev/null +++ b/arch/arm/boot/dts/overlays/hifiberry-dacplushd-overlay.dts -@@ -0,0 +1,106 @@ +@@ -0,0 +1,94 @@ +// Definitions for HiFiBerry DAC+ HD +/dts-v1/; +/plugin/; @@ -19235,23 +30119,13 @@ index 000000000000..c5583e010339 + compatible = "brcm,bcm2835"; + + fragment@0 { -+ target-path = "/"; -+ __overlay__ { -+ dachd_osc: pll_dachd_osc { -+ compatible = "hifiberry,dachd-clk"; -+ #clock-cells = <0>; -+ }; -+ }; -+ }; -+ -+ fragment@1 { -+ target = <&i2s>; ++ target = <&i2s_clk_consumer>; + __overlay__ { + status = "okay"; + }; + }; + -+ fragment@2 { ++ fragment@1 { + target = <&i2c1>; + __overlay__ { + #address-cells = <1>; @@ -19262,7 +30136,6 @@ index 000000000000..c5583e010339 + compatible = "ti,pcm1792a"; + #sound-dai-cells = <0>; + #clock-cells = <0>; -+ clocks = <&dachd_osc>; + reg = <0x4c>; + status = "okay"; + }; @@ -19270,7 +30143,6 @@ index 000000000000..c5583e010339 + compatible = "hifiberry,dachd-clk"; + #clock-cells = <0>; + reg = <0x62>; -+ clocks = <&dachd_osc>; + status = "okay"; + common_pll_regs = [ + 02 53 03 00 07 20 0F 00 @@ -19319,11 +30191,11 @@ index 000000000000..c5583e010339 + }; + }; + -+ fragment@3 { ++ fragment@2 { + target = <&sound>; + __overlay__ { + compatible = "hifiberry,hifiberry-dacplushd"; -+ i2s-controller = <&i2s>; ++ i2s-controller = <&i2s_clk_consumer>; + clocks = <&pll 0>; + reset-gpio = <&gpio 16 GPIO_ACTIVE_LOW>; + status = "okay"; @@ -19333,7 +30205,7 @@ index 000000000000..c5583e010339 +}; diff --git a/arch/arm/boot/dts/overlays/hifiberry-digi-overlay.dts b/arch/arm/boot/dts/overlays/hifiberry-digi-overlay.dts new file mode 100644 -index 000000000000..a2309a50e8d8 +index 000000000000..eb68f117a92a --- /dev/null +++ b/arch/arm/boot/dts/overlays/hifiberry-digi-overlay.dts @@ -0,0 +1,41 @@ @@ -19345,7 +30217,7 @@ index 000000000000..a2309a50e8d8 + compatible = "brcm,bcm2835"; + + fragment@0 { -+ target = <&i2s>; ++ target = <&i2s_clk_consumer>; + __overlay__ { + status = "okay"; + }; @@ -19373,14 +30245,14 @@ index 000000000000..a2309a50e8d8 + target = <&sound>; + __overlay__ { + compatible = "hifiberry,hifiberry-digi"; -+ i2s-controller = <&i2s>; ++ i2s-controller = <&i2s_clk_consumer>; + status = "okay"; + }; + }; +}; diff --git a/arch/arm/boot/dts/overlays/hifiberry-digi-pro-overlay.dts b/arch/arm/boot/dts/overlays/hifiberry-digi-pro-overlay.dts new file mode 100644 -index 000000000000..83de602e76ba +index 000000000000..18d16276e120 --- /dev/null +++ b/arch/arm/boot/dts/overlays/hifiberry-digi-pro-overlay.dts @@ -0,0 +1,43 @@ @@ -19392,7 +30264,7 @@ index 000000000000..83de602e76ba + compatible = "brcm,bcm2835"; + + fragment@0 { -+ target = <&i2s>; ++ target = <&i2s_clk_consumer>; + __overlay__ { + status = "okay"; + }; @@ -19420,7 +30292,7 @@ index 000000000000..83de602e76ba + target = <&sound>; + __overlay__ { + compatible = "hifiberry,hifiberry-digi"; -+ i2s-controller = <&i2s>; ++ i2s-controller = <&i2s_clk_consumer>; + status = "okay"; + clock44-gpio = <&gpio 5 0>; + clock48-gpio = <&gpio 6 0>; @@ -19498,7 +30370,7 @@ index 000000000000..46cb76c2d34f +}; diff --git a/arch/arm/boot/dts/overlays/hy28a-overlay.dts b/arch/arm/boot/dts/overlays/hy28a-overlay.dts new file mode 100644 -index 000000000000..5843a5e9c86a +index 000000000000..d0d52ebd9bd5 --- /dev/null +++ b/arch/arm/boot/dts/overlays/hy28a-overlay.dts @@ -0,0 +1,93 @@ @@ -19577,7 +30449,7 @@ index 000000000000..5843a5e9c86a + spi-max-frequency = <2000000>; + interrupts = <17 2>; /* high-to-low edge triggered */ + interrupt-parent = <&gpio>; -+ pendown-gpio = <&gpio 17 0>; ++ pendown-gpio = <&gpio 17 1>; + ti,x-plate-ohms = /bits/ 16 <100>; + ti,pressure-max = /bits/ 16 <255>; + }; @@ -19597,7 +30469,7 @@ index 000000000000..5843a5e9c86a +}; diff --git a/arch/arm/boot/dts/overlays/hy28b-2017-overlay.dts b/arch/arm/boot/dts/overlays/hy28b-2017-overlay.dts new file mode 100644 -index 000000000000..95bfb1eadc20 +index 000000000000..9df33c5d95bb --- /dev/null +++ b/arch/arm/boot/dts/overlays/hy28b-2017-overlay.dts @@ -0,0 +1,152 @@ @@ -19735,7 +30607,7 @@ index 000000000000..95bfb1eadc20 + spi-max-frequency = <2000000>; + interrupts = <17 2>; /* high-to-low edge triggered */ + interrupt-parent = <&gpio>; -+ pendown-gpio = <&gpio 17 0>; ++ pendown-gpio = <&gpio 17 1>; + ti,x-plate-ohms = /bits/ 16 <100>; + ti,pressure-max = /bits/ 16 <255>; + }; @@ -19755,7 +30627,7 @@ index 000000000000..95bfb1eadc20 +}; diff --git a/arch/arm/boot/dts/overlays/hy28b-overlay.dts b/arch/arm/boot/dts/overlays/hy28b-overlay.dts new file mode 100644 -index 000000000000..9edd0848d555 +index 000000000000..421bde94a4a0 --- /dev/null +++ b/arch/arm/boot/dts/overlays/hy28b-overlay.dts @@ -0,0 +1,148 @@ @@ -19889,7 +30761,7 @@ index 000000000000..9edd0848d555 + spi-max-frequency = <2000000>; + interrupts = <17 2>; /* high-to-low edge triggered */ + interrupt-parent = <&gpio>; -+ pendown-gpio = <&gpio 17 0>; ++ pendown-gpio = <&gpio 17 1>; + ti,x-plate-ohms = /bits/ 16 <100>; + ti,pressure-max = /bits/ 16 <255>; + }; @@ -19909,7 +30781,7 @@ index 000000000000..9edd0848d555 +}; diff --git a/arch/arm/boot/dts/overlays/i-sabre-q2m-overlay.dts b/arch/arm/boot/dts/overlays/i-sabre-q2m-overlay.dts new file mode 100644 -index 000000000000..0c4cff354674 +index 000000000000..6db52955a8f8 --- /dev/null +++ b/arch/arm/boot/dts/overlays/i-sabre-q2m-overlay.dts @@ -0,0 +1,39 @@ @@ -19924,13 +30796,13 @@ index 000000000000..0c4cff354674 + target = <&sound>; + frag0: __overlay__ { + compatible = "audiophonics,i-sabre-q2m"; -+ i2s-controller = <&i2s>; ++ i2s-controller = <&i2s_clk_producer>; + status = "okay"; + }; + }; + + fragment@1 { -+ target = <&i2s>; ++ target = <&i2s_clk_producer>; + __overlay__ { + status = "okay"; + }; @@ -19971,6 +30843,120 @@ index 000000000000..8204b6b3aef8 + }; + }; +}; +diff --git a/arch/arm/boot/dts/overlays/i2c-fan-overlay.dts b/arch/arm/boot/dts/overlays/i2c-fan-overlay.dts +new file mode 100644 +index 000000000000..f2f4a2aa797a +--- /dev/null ++++ b/arch/arm/boot/dts/overlays/i2c-fan-overlay.dts +@@ -0,0 +1,108 @@ ++// Definitions for I2C based sensors using the Industrial IO or HWMON interface. ++/dts-v1/; ++/plugin/; ++ ++#include ++ ++/ { ++ compatible = "brcm,bcm2835"; ++ ++ fragment@0 { ++ target = <&i2cbus>; ++ __dormant__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "okay"; ++ ++ emc2301: emc2301@2f { ++ compatible = "microchip,emc2301"; ++ reg = <0x2f>; ++ status = "okay"; ++ #cooling-cells = <0x02>; ++ }; ++ }; ++ }; ++ ++ frag100: fragment@100 { ++ target = <&i2c_arm>; ++ i2cbus: __overlay__ { ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@101 { ++ target = <&i2c0if>; ++ __dormant__ { ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@102 { ++ target = <&i2c0mux>; ++ __dormant__ { ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@103 { ++ target = <&cpu_thermal>; ++ __overlay__ { ++ polling-delay = <2000>; /* milliseconds */ ++ }; ++ }; ++ ++ fragment@104 { ++ target = <&thermal_trips>; ++ __overlay__ { ++ fanmid0: fanmid0 { ++ temperature = <50000>; ++ hysteresis = <2000>; ++ type = "active"; ++ }; ++ fanmax0: fanmax0 { ++ temperature = <75000>; ++ hysteresis = <2000>; ++ type = "active"; ++ }; ++ }; ++ }; ++ ++ fragment@105 { ++ target = <&cooling_maps>; ++ __overlay__ { ++ map0: map0 { ++ trip = <&fanmid0>; ++ cooling-device = <&emc2301 2 6>; ++ }; ++ map1: map1 { ++ trip = <&fanmax0>; ++ cooling-device = <&emc2301 7 THERMAL_NO_LIMIT>; ++ }; ++ }; ++ }; ++ ++ __overrides__ { ++ i2c0 = <&frag100>,"target:0=",<&i2c0>; ++ i2c_csi_dsi = <&frag100>,"target:0=",<&i2c_csi_dsi>, ++ <0>,"+101+102"; ++ i2c3 = <&frag100>, "target?=0", ++ <&frag100>, "target-path=i2c3"; ++ i2c4 = <&frag100>, "target?=0", ++ <&frag100>, "target-path=i2c4"; ++ i2c5 = <&frag100>, "target?=0", ++ <&frag100>, "target-path=i2c5"; ++ i2c6 = <&frag100>, "target?=0", ++ <&frag100>, "target-path=i2c6"; ++ addr = <&emc2301>,"reg:0"; ++ minpwm = <&emc2301>,"emc2305,pwm-min.0"; ++ maxpwm = <&emc2301>,"emc2305,pwm-max.0"; ++ midtemp = <&fanmid0>,"temperature:0"; ++ midtemp_hyst = <&fanmid0>,"hysteresis:0"; ++ maxtemp = <&fanmax0>,"temperature:0"; ++ maxtemp_hyst = <&fanmax0>,"hysteresis:0"; ++ ++ emc2301 = <0>,"+0", ++ <&map0>,"cooling-device:0=",<&emc2301>, ++ <&map1>,"cooling-device:0=",<&emc2301>; ++ }; ++}; diff --git a/arch/arm/boot/dts/overlays/i2c-gpio-overlay.dts b/arch/arm/boot/dts/overlays/i2c-gpio-overlay.dts new file mode 100644 index 000000000000..63231b5d7c0c @@ -20026,20 +31012,22 @@ index 000000000000..63231b5d7c0c +}; diff --git a/arch/arm/boot/dts/overlays/i2c-mux-overlay.dts b/arch/arm/boot/dts/overlays/i2c-mux-overlay.dts new file mode 100644 -index 000000000000..112aed91ecb2 +index 000000000000..0575b276cd26 --- /dev/null +++ b/arch/arm/boot/dts/overlays/i2c-mux-overlay.dts -@@ -0,0 +1,139 @@ +@@ -0,0 +1,183 @@ +// Umbrella I2C Mux overlay + +/dts-v1/; +/plugin/; + ++#include ++ +/{ + compatible = "brcm,bcm2835"; + + fragment@0 { -+ target = <&i2c_arm>; ++ target = <&i2cbus>; + __dormant__ { + #address-cells = <1>; + #size-cells = <0>; @@ -20066,7 +31054,7 @@ index 000000000000..112aed91ecb2 + }; + + fragment@1 { -+ target = <&i2c_arm>; ++ target = <&i2cbus>; + __dormant__ { + #address-cells = <1>; + #size-cells = <0>; @@ -20103,7 +31091,7 @@ index 000000000000..112aed91ecb2 + }; + + fragment@2 { -+ target = <&i2c_arm>; ++ target = <&i2cbus>; + __dormant__ { + #address-cells = <1>; + #size-cells = <0>; @@ -20159,6 +31147,27 @@ index 000000000000..112aed91ecb2 + }; + }; + ++ frag100: fragment@100 { ++ target = <&i2c_arm>; ++ i2cbus: __overlay__ { ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@101 { ++ target = <&i2c0if>; ++ __dormant__ { ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@102 { ++ target = <&i2c0mux>; ++ __dormant__ { ++ status = "okay"; ++ }; ++ }; ++ + __overrides__ { + pca9542 = <0>, "+0"; + pca9545 = <0>, "+1"; @@ -20167,14 +31176,35 @@ index 000000000000..112aed91ecb2 + addr = <&pca9542>,"reg:0", + <&pca9545>,"reg:0", + <&pca9548>,"reg:0"; ++ ++ base = <&pca9542>,"base-nr:0", ++ <&pca9545>,"base-nr:0", ++ <&pca9548>,"base-nr:0"; ++ ++ i2c0 = <&frag100>, "target:0=",<&i2c0>, ++ <0>,"+101+102"; ++ i2c_csi_dsi = <&frag100>, "target:0=",<&i2c_csi_dsi>, ++ <0>,"+101+102"; ++ i2c3 = <&frag100>, "target?=0", ++ <&frag100>, "target-path=i2c3"; ++ i2c4 = <&frag100>, "target?=0", ++ <&frag100>, "target-path=i2c4"; ++ i2c5 = <&frag100>, "target?=0", ++ <&frag100>, "target-path=i2c5"; ++ i2c6 = <&frag100>, "target?=0", ++ <&frag100>, "target-path=i2c6"; ++ disconnect_on_idle = ++ <&pca9542>,"idle-state:0=", , ++ <&pca9545>,"idle-state:0=", , ++ <&pca9548>,"idle-state:0=", ; + }; +}; diff --git a/arch/arm/boot/dts/overlays/i2c-pwm-pca9685a-overlay.dts b/arch/arm/boot/dts/overlays/i2c-pwm-pca9685a-overlay.dts new file mode 100644 -index 000000000000..9bb16465a50e +index 000000000000..b8dfbd56d121 --- /dev/null +++ b/arch/arm/boot/dts/overlays/i2c-pwm-pca9685a-overlay.dts -@@ -0,0 +1,26 @@ +@@ -0,0 +1,61 @@ +// Definitions for NXP PCA9685A I2C PWM controller on ARM I2C bus. +/dts-v1/; +/plugin/; @@ -20183,7 +31213,7 @@ index 000000000000..9bb16465a50e + compatible = "brcm,bcm2835"; + + fragment@0 { -+ target = <&i2c_arm>; ++ target = <&i2cbus>; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; @@ -20197,16 +31227,51 @@ index 000000000000..9bb16465a50e + }; + }; + }; ++ ++ ++ frag100: fragment@100 { ++ target = <&i2c_arm>; ++ i2cbus: __overlay__ { ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@101 { ++ target = <&i2c0if>; ++ __dormant__ { ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@102 { ++ target = <&i2c0mux>; ++ __dormant__ { ++ status = "okay"; ++ }; ++ }; ++ + __overrides__ { + addr = <&pca>,"reg:0"; ++ i2c0 = <&frag100>, "target:0=",<&i2c0>, ++ <0>,"+101+102"; ++ i2c_csi_dsi = <&frag100>, "target:0=",<&i2c_csi_dsi>, ++ <0>,"+101+102"; ++ i2c3 = <&frag100>, "target?=0", ++ <&frag100>, "target-path=i2c3"; ++ i2c4 = <&frag100>, "target?=0", ++ <&frag100>, "target-path=i2c4"; ++ i2c5 = <&frag100>, "target?=0", ++ <&frag100>, "target-path=i2c5"; ++ i2c6 = <&frag100>, "target?=0", ++ <&frag100>, "target-path=i2c6"; + }; +}; diff --git a/arch/arm/boot/dts/overlays/i2c-rtc-common.dtsi b/arch/arm/boot/dts/overlays/i2c-rtc-common.dtsi new file mode 100644 -index 000000000000..7f749fc2d802 +index 000000000000..d2b54fe23339 --- /dev/null +++ b/arch/arm/boot/dts/overlays/i2c-rtc-common.dtsi -@@ -0,0 +1,323 @@ +@@ -0,0 +1,367 @@ +// Definitions for several I2C based Real Time Clocks + +/ { @@ -20459,7 +31524,7 @@ index 000000000000..7f749fc2d802 + #size-cells = <0>; + + s35390a: s35390a@30 { -+ compatible = "ablic,s35390a"; ++ compatible = "sii,s35390a"; + reg = <0x30>; + }; + }; @@ -20479,6 +31544,44 @@ index 000000000000..7f749fc2d802 + }; + }; + ++ fragment@20 { ++ target = <&i2cbus>; ++ __dormant__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ rv8803: rv8803@32 { ++ compatible = "microcrystal,rv8803"; ++ reg = <0x32>; ++ }; ++ }; ++ }; ++ ++ fragment@21 { ++ target = <&i2cbus>; ++ __dormant__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ rv3032: rv3032@51 { ++ compatible = "microcrystal,rv3032"; ++ reg = <0x51>; ++ }; ++ }; ++ }; ++ ++ fragment@22 { ++ target = <&i2cbus>; ++ __dormant__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ pcf2131@53 { ++ compatible = "nxp,pcf2131"; ++ reg = <0x53>; ++ }; ++ }; ++ }; + + __overrides__ { + abx80x = <0>,"+0"; @@ -20501,6 +31604,9 @@ index 000000000000..7f749fc2d802 + pcf85063a = <0>,"+16"; + s35390a = <0>,"+18"; + bq32000 = <0>,"+19"; ++ rv8803 = <0>,"+20"; ++ rv3032 = <0>,"+21"; ++ pcf2131 = <0>,"+22"; + + addr = <&abx80x>, "reg:0", + <&ds1307>, "reg:0", @@ -20520,14 +31626,17 @@ index 000000000000..7f749fc2d802 + <&ds1340>,"trickle-resistor-ohms:0", + <&abx80x>,"abracon,tc-resistor:0", + <&rv3028>,"trickle-resistor-ohms:0", ++ <&rv3032>,"trickle-resistor-ohms:0", + <&rv1805>,"abracon,tc-resistor:0", + <&bq32000>,"abracon,tc-resistor:0"; ++ trickle-voltage-mv = <&rv3032>,"trickle-voltage-millivolts:0"; + backup-switchover-mode = <&rv3028>,"backup-switchover-mode:0"; + wakeup-source = <&ds1339>,"wakeup-source?", + <&ds3231>,"wakeup-source?", + <&mcp7940x>,"wakeup-source?", + <&mcp7941x>,"wakeup-source?", -+ <&m41t62>,"wakeup-source?"; ++ <&m41t62>,"wakeup-source?", ++ <&pcf8563>,"wakeup-source?"; + }; +}; diff --git a/arch/arm/boot/dts/overlays/i2c-rtc-gpio-overlay.dts b/arch/arm/boot/dts/overlays/i2c-rtc-gpio-overlay.dts @@ -20569,10 +31678,10 @@ index 000000000000..c83480c1c327 +}; diff --git a/arch/arm/boot/dts/overlays/i2c-rtc-overlay.dts b/arch/arm/boot/dts/overlays/i2c-rtc-overlay.dts new file mode 100644 -index 000000000000..1eae9e1a5c96 +index 000000000000..cd31eac7e333 --- /dev/null +++ b/arch/arm/boot/dts/overlays/i2c-rtc-overlay.dts -@@ -0,0 +1,34 @@ +@@ -0,0 +1,42 @@ +// Definitions for several I2C based Real Time Clocks +/dts-v1/; +/plugin/; @@ -20605,23 +31714,33 @@ index 000000000000..1eae9e1a5c96 + i2c0 = <&frag100>, "target:0=",<&i2c0>; + i2c_csi_dsi = <&frag100>, "target:0=",<&i2c_csi_dsi>, + <0>,"+101+102"; ++ i2c3 = <&frag100>, "target?=0", ++ <&frag100>, "target-path=i2c3"; ++ i2c4 = <&frag100>, "target?=0", ++ <&frag100>, "target-path=i2c4"; ++ i2c5 = <&frag100>, "target?=0", ++ <&frag100>, "target-path=i2c5"; ++ i2c6 = <&frag100>, "target?=0", ++ <&frag100>, "target-path=i2c6"; + }; +}; -diff --git a/arch/arm/boot/dts/overlays/i2c-sensor-overlay.dts b/arch/arm/boot/dts/overlays/i2c-sensor-overlay.dts +diff --git a/arch/arm/boot/dts/overlays/i2c-sensor-common.dtsi b/arch/arm/boot/dts/overlays/i2c-sensor-common.dtsi new file mode 100755 -index 000000000000..33965be4b1e8 +index 000000000000..2f7d1fe402eb --- /dev/null -+++ b/arch/arm/boot/dts/overlays/i2c-sensor-overlay.dts -@@ -0,0 +1,340 @@ ++++ b/arch/arm/boot/dts/overlays/i2c-sensor-common.dtsi +@@ -0,0 +1,578 @@ +// Definitions for I2C based sensors using the Industrial IO or HWMON interface. +/dts-v1/; +/plugin/; + ++#include ++ +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { -+ target = <&i2c_arm>; ++ target = <&i2cbus>; + __dormant__ { + #address-cells = <1>; + #size-cells = <0>; @@ -20636,7 +31755,7 @@ index 000000000000..33965be4b1e8 + }; + + fragment@1 { -+ target = <&i2c_arm>; ++ target = <&i2cbus>; + __dormant__ { + #address-cells = <1>; + #size-cells = <0>; @@ -20652,7 +31771,7 @@ index 000000000000..33965be4b1e8 + }; + + fragment@2 { -+ target = <&i2c_arm>; ++ target = <&i2cbus>; + __dormant__ { + #address-cells = <1>; + #size-cells = <0>; @@ -20667,7 +31786,7 @@ index 000000000000..33965be4b1e8 + }; + + fragment@3 { -+ target = <&i2c_arm>; ++ target = <&i2cbus>; + __dormant__ { + #address-cells = <1>; + #size-cells = <0>; @@ -20682,14 +31801,14 @@ index 000000000000..33965be4b1e8 + }; + + fragment@4 { -+ target = <&i2c_arm>; ++ target = <&i2cbus>; + __dormant__ { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + htu21: htu21@40 { -+ compatible = "htu21"; ++ compatible = "meas,htu21"; + reg = <0x40>; + status = "okay"; + }; @@ -20697,14 +31816,14 @@ index 000000000000..33965be4b1e8 + }; + + fragment@5 { -+ target = <&i2c_arm>; ++ target = <&i2cbus>; + __dormant__ { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + lm75: lm75@4f { -+ compatible = "lm75"; ++ compatible = "national,lm75"; + reg = <0x4f>; + status = "okay"; + }; @@ -20712,14 +31831,14 @@ index 000000000000..33965be4b1e8 + }; + + fragment@6 { -+ target = <&i2c_arm>; ++ target = <&i2cbus>; + __dormant__ { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + si7020: si7020@40 { -+ compatible = "si7020"; ++ compatible = "silabs,si7020"; + reg = <0x40>; + status = "okay"; + }; @@ -20727,7 +31846,7 @@ index 000000000000..33965be4b1e8 + }; + + fragment@7 { -+ target = <&i2c_arm>; ++ target = <&i2cbus>; + __dormant__ { + #address-cells = <1>; + #size-cells = <0>; @@ -20742,14 +31861,14 @@ index 000000000000..33965be4b1e8 + }; + + fragment@8 { -+ target = <&i2c_arm>; ++ target = <&i2cbus>; + __dormant__ { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + hdc100x: hdc100x@40 { -+ compatible = "hdc100x"; ++ compatible = "ti,hdc1000"; + reg = <0x40>; + status = "okay"; + }; @@ -20757,14 +31876,14 @@ index 000000000000..33965be4b1e8 + }; + + fragment@9 { -+ target = <&i2c_arm>; ++ target = <&i2cbus>; + __dormant__ { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + tsl4531: tsl4531@29 { -+ compatible = "tsl4531"; ++ compatible = "amstaos,tsl4531"; + reg = <0x29>; + status = "okay"; + }; @@ -20772,14 +31891,14 @@ index 000000000000..33965be4b1e8 + }; + + fragment@10 { -+ target = <&i2c_arm>; ++ target = <&i2cbus>; + __dormant__ { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + veml6070: veml6070@38 { -+ compatible = "veml6070"; ++ compatible = "vishay,veml6070"; + reg = <0x38>; + status = "okay"; + }; @@ -20787,14 +31906,14 @@ index 000000000000..33965be4b1e8 + }; + + fragment@11 { -+ target = <&i2c_arm>; ++ target = <&i2cbus>; + __dormant__ { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + sht3x: sht3x@44 { -+ compatible = "sht3x"; ++ compatible = "sensirion,sht3x"; + reg = <0x44>; + status = "okay"; + }; @@ -20802,14 +31921,14 @@ index 000000000000..33965be4b1e8 + }; + + fragment@12 { -+ target = <&i2c_arm>; ++ target = <&i2cbus>; + __dormant__ { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + ds1621: ds1621@48 { -+ compatible = "ds1621"; ++ compatible = "dallas,ds1621"; + reg = <0x48>; + status = "okay"; + }; @@ -20817,7 +31936,7 @@ index 000000000000..33965be4b1e8 + }; + + fragment@13 { -+ target = <&i2c_arm>; ++ target = <&i2cbus>; + __dormant__ { + #address-cells = <1>; + #size-cells = <0>; @@ -20832,7 +31951,7 @@ index 000000000000..33965be4b1e8 + }; + + fragment@14 { -+ target = <&i2c_arm>; ++ target = <&i2cbus>; + __dormant__ { + #address-cells = <1>; + #size-cells = <0>; @@ -20847,7 +31966,7 @@ index 000000000000..33965be4b1e8 + }; + + fragment@15 { -+ target = <&i2c_arm>; ++ target = <&i2cbus>; + __dormant__ { + #address-cells = <1>; + #size-cells = <0>; @@ -20862,7 +31981,7 @@ index 000000000000..33965be4b1e8 + }; + + fragment@16 { -+ target = <&i2c_arm>; ++ target = <&i2cbus>; + __dormant__ { + #address-cells = <1>; + #size-cells = <0>; @@ -20877,14 +31996,14 @@ index 000000000000..33965be4b1e8 + }; + + fragment@17 { -+ target = <&i2c_arm>; ++ target = <&i2cbus>; + __dormant__ { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + ccs811: ccs811@5b { -+ compatible = "ccs811"; ++ compatible = "ams,ccs811"; + reg = <0x5b>; + status = "okay"; + }; @@ -20892,14 +32011,14 @@ index 000000000000..33965be4b1e8 + }; + + fragment@18 { -+ target = <&i2c_arm>; ++ target = <&i2cbus>; + __dormant__ { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + bh1750: bh1750@23 { -+ compatible = "bh1750"; ++ compatible = "rohm,bh1750"; + reg = <0x23>; + status = "okay"; + }; @@ -20907,7 +32026,7 @@ index 000000000000..33965be4b1e8 + }; + + fragment@19 { -+ target = <&i2c_arm>; ++ target = <&i2cbus>; + __dormant__ { + #address-cells = <1>; + #size-cells = <0>; @@ -20924,16 +32043,224 @@ index 000000000000..33965be4b1e8 + }; + }; + ++ fragment@20 { ++ target = <&i2cbus>; ++ __dormant__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "okay"; ++ ++ aht10: aht10@38 { ++ compatible = "aosong,aht10"; ++ reg = <0x38>; ++ }; ++ }; ++ }; ++ ++ fragment@21 { ++ target = <&i2cbus>; ++ __dormant__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "okay"; ++ ++ mcp980x: mcp980x@18 { ++ compatible = "maxim,mcp980x"; ++ reg = <0x18>; ++ }; ++ }; ++ }; ++ ++ fragment@22 { ++ target = <&i2cbus>; ++ __dormant__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "okay"; ++ ++ jc42: jc42@18 { ++ compatible = "jedec,jc-42.4-temp"; ++ reg = <0x18>; ++ }; ++ }; ++ }; ++ ++ fragment@23 { ++ target = <&i2cbus>; ++ __dormant__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "okay"; ++ ++ ms5637: ms5637@76 { ++ compatible = "meas,ms5637"; ++ reg = <0x76>; ++ }; ++ }; ++ }; ++ ++ fragment@24 { ++ target = <&i2cbus>; ++ __dormant__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "okay"; ++ ++ ms5803: ms5803@76 { ++ compatible = "meas,ms5803"; ++ reg = <0x76>; ++ }; ++ }; ++ }; ++ ++ fragment@25 { ++ target = <&i2cbus>; ++ __dormant__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "okay"; ++ ++ ms5805: ms5805@76 { ++ compatible = "meas,ms5805"; ++ reg = <0x76>; ++ }; ++ }; ++ }; ++ ++ fragment@26 { ++ target = <&i2cbus>; ++ __dormant__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "okay"; ++ ++ ms5837: ms5837@76 { ++ compatible = "meas,ms5837"; ++ reg = <0x76>; ++ }; ++ }; ++ }; ++ ++ fragment@27 { ++ target = <&i2cbus>; ++ __dormant__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "okay"; ++ ++ ms8607: ms8607@76 { ++ compatible = "meas,ms8607-temppressure"; ++ reg = <0x76>; ++ }; ++ }; ++ }; ++ ++ fragment@28 { ++ target = <&i2cbus>; ++ __dormant__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "okay"; ++ clock-frequency = <400000>; ++ ++ mpu6050: mpu6050@68 { ++ compatible = "invensense,mpu6050"; ++ reg = <0x68>; ++ interrupt-parent = <&gpio>; ++ interrupts = <4 2>; ++ }; ++ }; ++ }; ++ ++ fragment@29 { ++ target = <&i2cbus>; ++ __dormant__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "okay"; ++ clock-frequency = <400000>; ++ ++ mpu9250: mpu9250@68 { ++ compatible = "invensense,mpu9250"; ++ reg = <0x68>; ++ interrupt-parent = <&gpio>; ++ interrupts = <4 2>; ++ }; ++ }; ++ }; ++ ++ fragment@30 { ++ target = <&bno055>; ++ __dormant__ { ++ reset-gpios = <&gpio 5 GPIO_ACTIVE_LOW>; ++ }; ++ }; ++ ++ fragment@31 { ++ target = <&i2cbus>; ++ __dormant__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "okay"; ++ ++ bno055: bno055@29 { ++ compatible = "bosch,bno055"; ++ reg = <0x29>; ++ }; ++ }; ++ }; ++ ++ fragment@32 { ++ target = <&i2cbus>; ++ __dormant__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "okay"; ++ ++ sht4x: sht4x@44 { ++ compatible = "sensirion,sht4x"; ++ reg = <0x44>; ++ status = "okay"; ++ }; ++ }; ++ }; ++ ++ fragment@33 { ++ target = <&i2cbus>; ++ __dormant__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "okay"; ++ ++ bmp380: bmp380@76 { ++ compatible = "bosch,bmp380"; ++ reg = <0x76>; ++ status = "okay"; ++ }; ++ }; ++ }; ++ ++ fragment@34 { ++ target = <&i2cbus>; ++ __dormant__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "okay"; ++ ++ adt7410: adt7410@48 { ++ compatible = "adi,adt7410", "adi,adt7420"; ++ reg = <0x48>; ++ status = "okay"; ++ }; ++ }; ++ }; ++ + __overrides__ { -+ addr = <&bme280>,"reg:0", <&bmp280>,"reg:0", <&tmp102>,"reg:0", -+ <&lm75>,"reg:0", <&hdc100x>,"reg:0", <&sht3x>,"reg:0", -+ <&ds1621>,"reg:0", <&bme680>,"reg:0", <&ccs811>,"reg:0", -+ <&bh1750>,"reg:0"; -+ int_pin = <&max30102>, "interrupts:0"; + bme280 = <0>,"+0"; + bmp085 = <0>,"+1"; + bmp180 = <0>,"+2"; + bmp280 = <0>,"+3"; ++ bmp380 = <0>,"+33"; + htu21 = <0>,"+4"; + lm75 = <0>,"+5"; + lm75addr = <&lm75>,"reg:0"; @@ -20951,6 +32278,82 @@ index 000000000000..33965be4b1e8 + ccs811 = <0>, "+17"; + bh1750 = <0>, "+18"; + max30102 = <0>,"+19"; ++ aht10 = <0>,"+20"; ++ mcp980x = <0>,"+21"; ++ jc42 = <0>,"+22"; ++ ms5637 = <0>,"+23"; ++ ms5803 = <0>,"+24"; ++ ms5805 = <0>,"+25"; ++ ms5837 = <0>,"+26"; ++ ms8607 = <0>,"+27"; ++ mpu6050 = <0>,"+28"; ++ mpu9250 = <0>,"+29"; ++ bno055 = <0>,"+31"; ++ sht4x = <0>,"+32"; ++ adt7410 = <0>,"+34"; ++ ++ addr = <&bme280>,"reg:0", <&bmp280>,"reg:0", <&tmp102>,"reg:0", ++ <&lm75>,"reg:0", <&hdc100x>,"reg:0", <&sht3x>,"reg:0", ++ <&ds1621>,"reg:0", <&bme680>,"reg:0", <&ccs811>,"reg:0", ++ <&bh1750>,"reg:0", <&mcp980x>,"reg:0", <&jc42>,"reg:0", ++ <&ms5637>,"reg:0", <&ms5803>,"reg:0", <&ms5805>,"reg:0", ++ <&ms5837>,"reg:0", <&ms8607>,"reg:0", ++ <&mpu6050>,"reg:0", <&mpu9250>,"reg:0", ++ <&bno055>,"reg:0", <&sht4x>,"reg:0", ++ <&bmp380>,"reg:0", <&adt7410>,"reg:0"; ++ int_pin = <&max30102>, "interrupts:0", ++ <&mpu6050>, "interrupts:0", ++ <&mpu9250>, "interrupts:0"; ++ no_timeout = <&jc42>, "smbus-timeout-disable?"; ++ reset_pin = <&bno055>,"reset-gpios:4", <0>,"+30"; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlays/i2c-sensor-overlay.dts b/arch/arm/boot/dts/overlays/i2c-sensor-overlay.dts +new file mode 100755 +index 000000000000..f8a39659d83e +--- /dev/null ++++ b/arch/arm/boot/dts/overlays/i2c-sensor-overlay.dts +@@ -0,0 +1,42 @@ ++// Definitions for I2C based sensors using the Industrial IO or HWMON interface. ++/dts-v1/; ++/plugin/; ++ ++#include "i2c-sensor-common.dtsi" ++ ++/ { ++ frag100: fragment@100 { ++ target = <&i2c_arm>; ++ i2cbus: __overlay__ { ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@101 { ++ target = <&i2c0if>; ++ __dormant__ { ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@102 { ++ target = <&i2c0mux>; ++ __dormant__ { ++ status = "okay"; ++ }; ++ }; ++ ++ __overrides__ { ++ i2c0 = <&frag100>, "target:0=",<&i2c0>; ++ i2c_csi_dsi = <&frag100>, "target:0=",<&i2c_csi_dsi>, ++ <0>,"+101+102"; ++ i2c3 = <&frag100>, "target?=0", ++ <&frag100>, "target-path=i2c3"; ++ i2c4 = <&frag100>, "target?=0", ++ <&frag100>, "target-path=i2c4"; ++ i2c5 = <&frag100>, "target?=0", ++ <&frag100>, "target-path=i2c5"; ++ i2c6 = <&frag100>, "target?=0", ++ <&frag100>, "target-path=i2c6"; + }; +}; diff --git a/arch/arm/boot/dts/overlays/i2c0-overlay.dts b/arch/arm/boot/dts/overlays/i2c0-overlay.dts @@ -21042,6 +32445,46 @@ index 000000000000..46bf1bf2dc5c + combine = <0>, "!5"; + }; +}; +diff --git a/arch/arm/boot/dts/overlays/i2c0-pi5-overlay.dts b/arch/arm/boot/dts/overlays/i2c0-pi5-overlay.dts +new file mode 100644 +index 000000000000..152794822552 +--- /dev/null ++++ b/arch/arm/boot/dts/overlays/i2c0-pi5-overlay.dts +@@ -0,0 +1,34 @@ ++/dts-v1/; ++/plugin/; ++ ++/{ ++ compatible = "brcm,bcm2712"; ++ ++ fragment@0 { ++ target = <&i2c0>; ++ frag0: __overlay__ { ++ status = "okay"; ++ clock-frequency = <100000>; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&frag0>; ++ __overlay__ { ++ pinctrl-0 = <&rp1_i2c0_0_1>; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&frag0>; ++ __dormant__ { ++ pinctrl-0 = <&rp1_i2c0_8_9>; ++ }; ++ }; ++ ++ __overrides__ { ++ pins_0_1 = <0>,"+1-2"; ++ pins_8_9 = <0>,"-1+2"; ++ baudrate = <&frag0>, "clock-frequency:0"; ++ }; ++}; diff --git a/arch/arm/boot/dts/overlays/i2c1-overlay.dts b/arch/arm/boot/dts/overlays/i2c1-overlay.dts new file mode 100644 index 000000000000..addaed73e665 @@ -21092,12 +32535,79 @@ index 000000000000..addaed73e665 + combine = <0>, "!3"; + }; +}; +diff --git a/arch/arm/boot/dts/overlays/i2c1-pi5-overlay.dts b/arch/arm/boot/dts/overlays/i2c1-pi5-overlay.dts +new file mode 100644 +index 000000000000..719966ceb59a +--- /dev/null ++++ b/arch/arm/boot/dts/overlays/i2c1-pi5-overlay.dts +@@ -0,0 +1,34 @@ ++/dts-v1/; ++/plugin/; ++ ++/{ ++ compatible = "brcm,bcm2712"; ++ ++ fragment@0 { ++ target = <&i2c1>; ++ frag0: __overlay__ { ++ status = "okay"; ++ clock-frequency = <100000>; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&frag0>; ++ __overlay__ { ++ pinctrl-0 = <&rp1_i2c1_2_3>; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&frag0>; ++ __dormant__ { ++ pinctrl-0 = <&rp1_i2c1_10_11>; ++ }; ++ }; ++ ++ __overrides__ { ++ pins_2_3 = <0>,"+1-2"; ++ pins_10_11 = <0>,"-1+2"; ++ baudrate = <&frag0>, "clock-frequency:0"; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlays/i2c2-pi5-overlay.dts b/arch/arm/boot/dts/overlays/i2c2-pi5-overlay.dts +new file mode 100644 +index 000000000000..324d344052b8 +--- /dev/null ++++ b/arch/arm/boot/dts/overlays/i2c2-pi5-overlay.dts +@@ -0,0 +1,21 @@ ++/dts-v1/; ++/plugin/; ++ ++/{ ++ compatible = "brcm,bcm2712"; ++ ++ fragment@0 { ++ target = <&i2c2>; ++ frag0: __overlay__ { ++ status = "okay"; ++ clock-frequency = <100000>; ++ pinctrl-0 = <&rp1_i2c2_4_5>; ++ }; ++ }; ++ ++ __overrides__ { ++ pins_4_5 = <&frag0>,"pinctrl-0:0=", <&rp1_i2c2_4_5>; ++ pins_12_13 = <&frag0>,"pinctrl-0:0=", <&rp1_i2c2_12_13>; ++ baudrate = <&frag0>, "clock-frequency:0"; ++ }; ++}; diff --git a/arch/arm/boot/dts/overlays/i2c3-overlay.dts b/arch/arm/boot/dts/overlays/i2c3-overlay.dts new file mode 100644 -index 000000000000..e24a1df21f99 +index 000000000000..663d4f060ee8 --- /dev/null +++ b/arch/arm/boot/dts/overlays/i2c3-overlay.dts -@@ -0,0 +1,36 @@ +@@ -0,0 +1,34 @@ +/dts-v1/; +/plugin/; + @@ -21108,8 +32618,6 @@ index 000000000000..e24a1df21f99 + target = <&i2c3>; + frag0: __overlay__ { + status = "okay"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c3_pins>; + clock-frequency = <100000>; + }; + }; @@ -21134,12 +32642,40 @@ index 000000000000..e24a1df21f99 + baudrate = <&frag0>, "clock-frequency:0"; + }; +}; +diff --git a/arch/arm/boot/dts/overlays/i2c3-pi5-overlay.dts b/arch/arm/boot/dts/overlays/i2c3-pi5-overlay.dts +new file mode 100644 +index 000000000000..cbd1f9ff650d +--- /dev/null ++++ b/arch/arm/boot/dts/overlays/i2c3-pi5-overlay.dts +@@ -0,0 +1,22 @@ ++/dts-v1/; ++/plugin/; ++ ++/{ ++ compatible = "brcm,bcm2712"; ++ ++ fragment@0 { ++ target = <&i2c3>; ++ frag0: __overlay__ { ++ status = "okay"; ++ clock-frequency = <100000>; ++ pinctrl-0 = <&rp1_i2c3_6_7>; ++ }; ++ }; ++ ++ __overrides__ { ++ pins_6_7 = <&frag0>,"pinctrl-0:0=", <&rp1_i2c3_6_7>; ++ pins_14_15 = <&frag0>,"pinctrl-0:0=", <&rp1_i2c3_14_15>; ++ pins_22_23 = <&frag0>,"pinctrl-0:0=", <&rp1_i2c3_22_23>; ++ baudrate = <&frag0>, "clock-frequency:0"; ++ }; ++}; diff --git a/arch/arm/boot/dts/overlays/i2c4-overlay.dts b/arch/arm/boot/dts/overlays/i2c4-overlay.dts new file mode 100644 -index 000000000000..14c7f4d1da4c +index 000000000000..495de00f7aa1 --- /dev/null +++ b/arch/arm/boot/dts/overlays/i2c4-overlay.dts -@@ -0,0 +1,36 @@ +@@ -0,0 +1,34 @@ +/dts-v1/; +/plugin/; + @@ -21150,8 +32686,6 @@ index 000000000000..14c7f4d1da4c + target = <&i2c4>; + frag0: __overlay__ { + status = "okay"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c4_pins>; + clock-frequency = <100000>; + }; + }; @@ -21178,10 +32712,10 @@ index 000000000000..14c7f4d1da4c +}; diff --git a/arch/arm/boot/dts/overlays/i2c5-overlay.dts b/arch/arm/boot/dts/overlays/i2c5-overlay.dts new file mode 100644 -index 000000000000..7953621112de +index 000000000000..d498ebc72de6 --- /dev/null +++ b/arch/arm/boot/dts/overlays/i2c5-overlay.dts -@@ -0,0 +1,36 @@ +@@ -0,0 +1,34 @@ +/dts-v1/; +/plugin/; + @@ -21192,8 +32726,6 @@ index 000000000000..7953621112de + target = <&i2c5>; + frag0: __overlay__ { + status = "okay"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c5_pins>; + clock-frequency = <100000>; + }; + }; @@ -21220,10 +32752,10 @@ index 000000000000..7953621112de +}; diff --git a/arch/arm/boot/dts/overlays/i2c6-overlay.dts b/arch/arm/boot/dts/overlays/i2c6-overlay.dts new file mode 100644 -index 000000000000..555305a7ee1f +index 000000000000..4d26178a73ca --- /dev/null +++ b/arch/arm/boot/dts/overlays/i2c6-overlay.dts -@@ -0,0 +1,36 @@ +@@ -0,0 +1,34 @@ +/dts-v1/; +/plugin/; + @@ -21234,8 +32766,6 @@ index 000000000000..555305a7ee1f + target = <&i2c6>; + frag0: __overlay__ { + status = "okay"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c6_pins>; + clock-frequency = <100000>; + }; + }; @@ -21260,6 +32790,46 @@ index 000000000000..555305a7ee1f + baudrate = <&frag0>, "clock-frequency:0"; + }; +}; +diff --git a/arch/arm/boot/dts/overlays/i2s-dac-overlay.dts b/arch/arm/boot/dts/overlays/i2s-dac-overlay.dts +new file mode 100644 +index 000000000000..1d8874a18860 +--- /dev/null ++++ b/arch/arm/boot/dts/overlays/i2s-dac-overlay.dts +@@ -0,0 +1,34 @@ ++// Definitions for RPi DAC ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "brcm,bcm2835"; ++ ++ fragment@0 { ++ target = <&i2s_clk_producer>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@1 { ++ target-path = "/"; ++ __overlay__ { ++ pcm1794a-codec { ++ #sound-dai-cells = <0>; ++ compatible = "ti,pcm1794a"; ++ status = "okay"; ++ }; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&sound>; ++ __overlay__ { ++ compatible = "rpi,rpi-dac"; ++ i2s-controller = <&i2s_clk_producer>; ++ status = "okay"; ++ }; ++ }; ++}; diff --git a/arch/arm/boot/dts/overlays/i2s-gpio28-31-overlay.dts b/arch/arm/boot/dts/overlays/i2s-gpio28-31-overlay.dts new file mode 100644 index 000000000000..cf43094c6ff4 @@ -21337,10 +32907,10 @@ index 000000000000..551aba591d26 +}; diff --git a/arch/arm/boot/dts/overlays/imx219-overlay.dts b/arch/arm/boot/dts/overlays/imx219-overlay.dts new file mode 100644 -index 000000000000..bc1217397dd5 +index 000000000000..4c4bcd309a3d --- /dev/null +++ b/arch/arm/boot/dts/overlays/imx219-overlay.dts -@@ -0,0 +1,96 @@ +@@ -0,0 +1,89 @@ +// SPDX-License-Identifier: GPL-2.0-only +// Definitions for IMX219 camera module on VC I2C bus +/dts-v1/; @@ -21380,31 +32950,13 @@ index 000000000000..bc1217397dd5 + #size-cells = <0>; + status = "okay"; + -+ imx219: imx219@10 { -+ compatible = "sony,imx219"; -+ reg = <0x10>; -+ status = "okay"; ++ #include "imx219.dtsi" + -+ clocks = <&cam1_clk>; -+ clock-names = "xclk"; -+ -+ VANA-supply = <&cam1_reg>; /* 2.8v */ -+ VDIG-supply = <&cam_dummy_reg>; /* 1.8v */ -+ VDDL-supply = <&cam_dummy_reg>; /* 1.2v */ -+ -+ rotation = <180>; -+ orientation = <2>; -+ -+ port { -+ imx219_0: endpoint { -+ remote-endpoint = <&csi_ep>; -+ clock-lanes = <0>; -+ data-lanes = <1 2>; -+ clock-noncontinuous; -+ link-frequencies = -+ /bits/ 64 <456000000>; -+ }; -+ }; ++ vcm: ad5398@c { ++ compatible = "adi,ad5398"; ++ reg = <0x0c>; ++ status = "disabled"; ++ VANA-supply = <&cam1_reg>; + }; + }; + }; @@ -21417,7 +32969,7 @@ index 000000000000..bc1217397dd5 + + port { + csi_ep: endpoint { -+ remote-endpoint = <&imx219_0>; ++ remote-endpoint = <&cam_endpoint>; + clock-lanes = <0>; + data-lanes = <1 2>; + clock-noncontinuous; @@ -21427,19 +32979,233 @@ index 000000000000..bc1217397dd5 + }; + + __overrides__ { -+ rotation = <&imx219>,"rotation:0"; -+ orientation = <&imx219>,"orientation:0"; ++ rotation = <&cam_node>,"rotation:0"; ++ orientation = <&cam_node>,"orientation:0"; + media-controller = <&csi>,"brcm,media-controller?"; -+ cam0 = <&i2c_frag>, "target:0=",<&i2c_vc>, ++ cam0 = <&i2c_frag>, "target:0=",<&i2c_csi_dsi0>, + <&csi_frag>, "target:0=",<&csi0>, + <&clk_frag>, "target:0=",<&cam0_clk>, -+ <&imx219>, "clocks:0=",<&cam0_clk>, -+ <&imx219>, "VANA-supply:0=",<&cam0_reg>; ++ <&cam_node>, "clocks:0=",<&cam0_clk>, ++ <&cam_node>, "VANA-supply:0=",<&cam0_reg>, ++ <&vcm>, "VANA-supply:0=", <&cam0_reg>; ++ vcm = <&vcm>, "status=okay", ++ <&cam_node>,"lens-focus:0=", <&vcm>; ++ }; ++}; ++ ++&cam_node { ++ status = "okay"; ++}; ++ ++&cam_endpoint { ++ remote-endpoint = <&csi_ep>; ++}; +diff --git a/arch/arm/boot/dts/overlays/imx219.dtsi b/arch/arm/boot/dts/overlays/imx219.dtsi +new file mode 100644 +index 000000000000..fa870f77ef07 +--- /dev/null ++++ b/arch/arm/boot/dts/overlays/imx219.dtsi +@@ -0,0 +1,27 @@ ++// Fragment that configures an imx219 ++ ++cam_node: imx219@10 { ++ compatible = "sony,imx219"; ++ reg = <0x10>; ++ status = "disabled"; ++ ++ clocks = <&cam1_clk>; ++ clock-names = "xclk"; ++ ++ VANA-supply = <&cam1_reg>; /* 2.8v */ ++ VDIG-supply = <&cam_dummy_reg>; /* 1.8v */ ++ VDDL-supply = <&cam_dummy_reg>; /* 1.2v */ ++ ++ rotation = <180>; ++ orientation = <2>; ++ ++ port { ++ cam_endpoint: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2>; ++ clock-noncontinuous; ++ link-frequencies = ++ /bits/ 64 <456000000>; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlays/imx258-overlay.dts b/arch/arm/boot/dts/overlays/imx258-overlay.dts +new file mode 100644 +index 000000000000..656a588f15cc +--- /dev/null ++++ b/arch/arm/boot/dts/overlays/imx258-overlay.dts +@@ -0,0 +1,131 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++// Definitions for IMX258 camera module on VC I2C bus ++/dts-v1/; ++/plugin/; ++ ++#include ++ ++/{ ++ compatible = "brcm,bcm2835"; ++ ++ fragment@0 { ++ target = <&i2c0if>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++ ++ clk_frag: fragment@1 { ++ target = <&cam1_clk>; ++ cam_clk: __overlay__ { ++ clock-frequency = <24000000>; ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&i2c0mux>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@11 { ++ target = <&cam_endpoint>; ++ __overlay__ { ++ data-lanes = <1 2>; ++ link-frequencies = /bits/ 64 <633600000 ++ 320000000>; ++ }; ++ }; ++ ++ fragment@12 { ++ target = <&cam_endpoint>; ++ __dormant__ { ++ data-lanes = <1 2 3 4>; ++ link-frequencies = ++ /bits/ 64 <633600000 320000000>; ++ }; ++ }; ++ ++ fragment@13 { ++ target = <&csi_ep>; ++ __overlay__ { ++ data-lanes = <1 2>; ++ }; ++ }; ++ ++ fragment@14 { ++ target = <&csi_ep>; ++ __dormant__ { ++ data-lanes = <1 2 3 4>; ++ }; ++ }; ++ ++ csi_frag: fragment@101 { ++ target = <&csi1>; ++ csi: __overlay__ { ++ status = "okay"; ++ brcm,media-controller; ++ ++ port { ++ csi_ep: endpoint { ++ remote-endpoint = <&cam_endpoint>; ++ clock-lanes = <0>; ++ clock-noncontinuous; ++ }; ++ }; ++ }; ++ }; ++ ++ reg_frag: fragment@5 { ++ target = <&cam1_reg>; ++ cam_reg: __overlay__ { ++ regulator-name = "imx258_vana"; ++ startup-delay-us = <300000>; ++ regulator-min-microvolt = <2700000>; ++ regulator-max-microvolt = <2700000>; ++ }; ++ }; ++ ++ i2c_frag: fragment@100 { ++ target = <&i2c_csi_dsi>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "okay"; ++ ++ #include "imx258.dtsi" ++ ++ vcm: ad5398@c { ++ compatible = "adi,ad5398"; ++ reg = <0x0c>; ++ status = "disabled"; ++ VANA-supply = <&cam1_reg>; ++ }; ++ }; ++ }; ++ ++ __overrides__ { ++ rotation = <&cam_node>,"rotation:0"; ++ orientation = <&cam_node>,"orientation:0"; ++ media-controller = <&csi>,"brcm,media-controller?"; ++ cam0 = <&i2c_frag>, "target:0=",<&i2c_csi_dsi0>, ++ <&csi_frag>, "target:0=",<&csi0>, ++ <&clk_frag>, "target:0=",<&cam0_clk>, ++ <®_frag>, "target:0=",<&cam0_reg>, ++ <&cam_node>, "clocks:0=",<&cam0_clk>, ++ <&cam_node>, "vana-supply:0=",<&cam0_reg>; ++ vcm = <&vcm>, "status=okay", ++ <&cam_node>,"lens-focus:0=", <&vcm>; ++ 4lane = <0>, "-11+12-13+14"; ++ }; ++}; ++ ++&cam_node { ++ status = "okay"; ++}; ++ ++&cam_endpoint { ++ remote-endpoint = <&csi_ep>; ++}; +diff --git a/arch/arm/boot/dts/overlays/imx258.dtsi b/arch/arm/boot/dts/overlays/imx258.dtsi +new file mode 100644 +index 000000000000..cca81e1aa8b3 +--- /dev/null ++++ b/arch/arm/boot/dts/overlays/imx258.dtsi +@@ -0,0 +1,27 @@ ++// Fragment that configures a Sony IMX258 ++ ++cam_node: imx258@10 { ++ compatible = "sony,imx258"; ++ reg = <0x10>; ++ status = "disabled"; ++ ++ clocks = <&cam1_clk>; ++ clock-names = "xclk"; ++ ++ vana-supply = <&cam1_reg>; /* 2.8v */ ++ vdig-supply = <&cam_dummy_reg>; /* 1.05v */ ++ vif-supply = <&cam_dummy_reg>; /* 1.8v */ ++ ++ rotation = <180>; ++ orientation = <2>; ++ ++ port { ++ cam_endpoint: endpoint { ++ clock-lanes = <0>; ++ clock-noncontinuous; ++ link-frequencies = ++ /bits/ 64 <633600000 ++ 320000000>; ++ }; + }; +}; diff --git a/arch/arm/boot/dts/overlays/imx290-overlay.dts b/arch/arm/boot/dts/overlays/imx290-overlay.dts new file mode 100644 -index 000000000000..e536aa7f9e33 +index 000000000000..3de3c3910d90 --- /dev/null +++ b/arch/arm/boot/dts/overlays/imx290-overlay.dts @@ -0,0 +1,32 @@ @@ -21458,16 +33224,16 @@ index 000000000000..e536aa7f9e33 + // included imx290_327 overlay file. + + fragment@101 { -+ target = <&imx290>; ++ target = <&cam_node>; + __overlay__ { -+ compatible = "sony,imx290"; ++ compatible = "sony,imx290lqr"; + }; + }; + + fragment@102 { -+ target = <&imx290>; ++ target = <&cam_node>; + __dormant__ { -+ compatible = "sony,imx290-mono"; ++ compatible = "sony,imx290llr"; + }; + }; + @@ -21477,10 +33243,10 @@ index 000000000000..e536aa7f9e33 +}; diff --git a/arch/arm/boot/dts/overlays/imx290_327-overlay.dtsi b/arch/arm/boot/dts/overlays/imx290_327-overlay.dtsi new file mode 100644 -index 000000000000..111d69597554 +index 000000000000..8fe48352e695 --- /dev/null +++ b/arch/arm/boot/dts/overlays/imx290_327-overlay.dtsi -@@ -0,0 +1,125 @@ +@@ -0,0 +1,112 @@ +// SPDX-License-Identifier: GPL-2.0-only +// Partial definitions for IMX290 or IMX327 camera module on VC I2C bus +// The compatible string should be set in an overlay that then includes this one @@ -21499,28 +33265,7 @@ index 000000000000..111d69597554 + #size-cells = <0>; + status = "okay"; + -+ imx290: imx290@1a { -+ reg = <0x1a>; -+ status = "okay"; -+ -+ clocks = <&cam1_clk>; -+ clock-names = "xclk"; -+ clock-frequency = <37125000>; -+ -+ rotation = <0>; -+ orientation = <2>; -+ -+ vdda-supply = <&cam1_reg>; /* 2.8v */ -+ vdddo-supply = <&cam_dummy_reg>; /* 1.8v */ -+ vddd-supply = <&cam_dummy_reg>; /* 1.5v */ -+ -+ port { -+ imx290_0: endpoint { -+ remote-endpoint = <&csi1_ep>; -+ clock-lanes = <0>; -+ }; -+ }; -+ }; ++ #include "imx290_327.dtsi" + }; + }; + @@ -21531,8 +33276,8 @@ index 000000000000..111d69597554 + brcm,media-controller; + + port { -+ csi1_ep: endpoint { -+ remote-endpoint = <&imx290_0>; ++ csi_ep: endpoint { ++ remote-endpoint = <&cam_endpoint>; + }; + }; + }; @@ -21561,7 +33306,7 @@ index 000000000000..111d69597554 + }; + + fragment@6 { -+ target = <&imx290_0>; ++ target = <&cam_endpoint>; + __overlay__ { + data-lanes = <1 2>; + link-frequencies = @@ -21570,7 +33315,7 @@ index 000000000000..111d69597554 + }; + + fragment@7 { -+ target = <&imx290_0>; ++ target = <&cam_endpoint>; + __dormant__ { + data-lanes = <1 2 3 4>; + link-frequencies = @@ -21579,14 +33324,14 @@ index 000000000000..111d69597554 + }; + + fragment@8 { -+ target = <&csi1_ep>; ++ target = <&csi_ep>; + __overlay__ { + data-lanes = <1 2>; + }; + }; + + fragment@9 { -+ target = <&csi1_ep>; ++ target = <&csi_ep>; + __dormant__ { + data-lanes = <1 2 3 4>; + }; @@ -21595,77 +33340,87 @@ index 000000000000..111d69597554 + __overrides__ { + 4lane = <0>, "-6+7-8+9"; + clock-frequency = <&cam_clk>,"clock-frequency:0", -+ <&imx290>,"clock-frequency:0"; -+ rotation = <&imx290>,"rotation:0"; -+ orientation = <&imx290>,"orientation:0"; ++ <&cam_node>,"clock-frequency:0"; ++ rotation = <&cam_node>,"rotation:0"; ++ orientation = <&cam_node>,"orientation:0"; + media-controller = <&csi>,"brcm,media-controller?"; -+ cam0 = <&i2c_frag>, "target:0=",<&i2c_vc>, ++ cam0 = <&i2c_frag>, "target:0=",<&i2c_csi_dsi0>, + <&csi_frag>, "target:0=",<&csi0>, + <&clk_frag>, "target:0=",<&cam0_clk>, -+ <&imx290>, "clocks:0=",<&cam0_clk>, -+ <&imx290>, "vdda-supply:0=",<&cam0_reg>; ++ <&cam_node>, "clocks:0=",<&cam0_clk>, ++ <&cam_node>, "vdda-supply:0=",<&cam0_reg>; + }; +}; -diff --git a/arch/arm/boot/dts/overlays/imx378-overlay.dts b/arch/arm/boot/dts/overlays/imx378-overlay.dts ++ ++&cam_node { ++ status = "okay"; ++}; ++ ++&cam_endpoint { ++ remote-endpoint = <&csi_ep>; ++}; +diff --git a/arch/arm/boot/dts/overlays/imx290_327.dtsi b/arch/arm/boot/dts/overlays/imx290_327.dtsi new file mode 100644 -index 000000000000..74c7288d12f5 +index 000000000000..14d1f0b95bb3 --- /dev/null -+++ b/arch/arm/boot/dts/overlays/imx378-overlay.dts -@@ -0,0 +1,10 @@ ++++ b/arch/arm/boot/dts/overlays/imx290_327.dtsi +@@ -0,0 +1,24 @@ ++// Fragment to configure and IMX290 / IMX327 / IMX462 image sensor ++ ++cam_node: imx290@1a { ++ compatible = "sony,imx290lqr"; ++ reg = <0x1a>; ++ status = "disabled"; ++ ++ clocks = <&cam1_clk>; ++ clock-names = "xclk"; ++ clock-frequency = <37125000>; ++ ++ rotation = <0>; ++ orientation = <2>; ++ ++ vdda-supply = <&cam1_reg>; /* 2.8v */ ++ vdddo-supply = <&cam_dummy_reg>; /* 1.8v */ ++ vddd-supply = <&cam_dummy_reg>; /* 1.5v */ ++ ++ port { ++ cam_endpoint: endpoint { ++ clock-lanes = <0>; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlays/imx296-overlay.dts b/arch/arm/boot/dts/overlays/imx296-overlay.dts +new file mode 100644 +index 000000000000..0eb4d9c2dc3b +--- /dev/null ++++ b/arch/arm/boot/dts/overlays/imx296-overlay.dts +@@ -0,0 +1,114 @@ +// SPDX-License-Identifier: GPL-2.0-only -+// Definitions for IMX378 camera module on VC I2C bus ++// Definitions for IMX296 camera module on VC I2C bus +/dts-v1/; +/plugin/; + -+#include "imx477_378-overlay.dtsi" -+ -+&imx477 { -+ compatible = "sony,imx378"; -+}; -diff --git a/arch/arm/boot/dts/overlays/imx477-overlay.dts b/arch/arm/boot/dts/overlays/imx477-overlay.dts -new file mode 100644 -index 000000000000..ca315d120e6b ---- /dev/null -+++ b/arch/arm/boot/dts/overlays/imx477-overlay.dts -@@ -0,0 +1,10 @@ -+// SPDX-License-Identifier: GPL-2.0-only -+// Definitions for IMX477 camera module on VC I2C bus -+/dts-v1/; -+/plugin/; -+ -+#include "imx477_378-overlay.dtsi" -+ -+&imx477 { -+ compatible = "sony,imx477"; -+}; -diff --git a/arch/arm/boot/dts/overlays/imx477_378-overlay.dtsi b/arch/arm/boot/dts/overlays/imx477_378-overlay.dtsi -new file mode 100644 -index 000000000000..bfea40ce98d6 ---- /dev/null -+++ b/arch/arm/boot/dts/overlays/imx477_378-overlay.dtsi -@@ -0,0 +1,99 @@ -+// SPDX-License-Identifier: GPL-2.0-only -+// Definitions for IMX477 camera module on VC I2C bus ++#include + +/{ + compatible = "brcm,bcm2835"; + -+ fragment@2 { ++ fragment@0 { + target = <&i2c0if>; + __overlay__ { + status = "okay"; + }; + }; + -+ clk_frag: fragment@3 { ++ clk_frag: fragment@1 { + target = <&cam1_clk>; -+ cam_clk: __overlay__ { -+ clock-frequency = <24000000>; ++ clk_over: __overlay__ { + status = "okay"; ++ clock-frequency = <54000000>; + }; + }; + -+ fragment@4 { ++ fragment@2 { + target = <&i2c0mux>; + __overlay__ { + status = "okay"; @@ -21675,7 +33430,14 @@ index 000000000000..bfea40ce98d6 + reg_frag: fragment@5 { + target = <&cam1_reg>; + cam_reg: __overlay__ { -+ startup-delay-us = <300000>; ++ startup-delay-us = <500000>; ++ }; ++ }; ++ ++ reg_alwayson_frag: fragment@99 { ++ target = <&cam1_reg>; ++ __dormant__ { ++ regulator-always-on; + }; + }; + @@ -21686,28 +33448,29 @@ index 000000000000..bfea40ce98d6 + #size-cells = <0>; + status = "okay"; + -+ imx477: imx477@1a { ++ imx296: imx296@1a { ++ compatible = "sony,imx296"; + reg = <0x1a>; + status = "okay"; + + clocks = <&cam1_clk>; -+ clock-names = "xclk"; ++ clock-names = "inck"; + -+ VANA-supply = <&cam1_reg>; /* 2.8v */ -+ VDIG-supply = <&cam_dummy_reg>; /* 1.05v */ -+ VDDL-supply = <&cam_dummy_reg>; /* 1.8v */ ++ avdd-supply = <&cam1_reg>; /* 3.3v */ ++ dvdd-supply = <&cam_dummy_reg>; /* 1.8v */ ++ ovdd-supply = <&cam_dummy_reg>; /* 1.2v */ + + rotation = <180>; + orientation = <2>; + + port { -+ imx477_0: endpoint { ++ imx296_0: endpoint { + remote-endpoint = <&csi_ep>; + clock-lanes = <0>; -+ data-lanes = <1 2>; ++ data-lanes = <1>; + clock-noncontinuous; + link-frequencies = -+ /bits/ 64 <450000000>; ++ /bits/ 64 <594000000>; + }; + }; + }; @@ -21722,7 +33485,228 @@ index 000000000000..bfea40ce98d6 + + port { + csi_ep: endpoint { -+ remote-endpoint = <&imx477_0>; ++ remote-endpoint = <&imx296_0>; ++ clock-lanes = <0>; ++ data-lanes = <1>; ++ clock-noncontinuous; ++ }; ++ }; ++ }; ++ }; ++ ++ __overrides__ { ++ rotation = <&imx296>,"rotation:0"; ++ orientation = <&imx296>,"orientation:0"; ++ media-controller = <&csi>,"brcm,media-controller?"; ++ cam0 = <&i2c_frag>, "target:0=",<&i2c_csi_dsi0>, ++ <&csi_frag>, "target:0=",<&csi0>, ++ <&clk_frag>, "target:0=",<&cam0_clk>, ++ <®_frag>, "target:0=",<&cam0_reg>, ++ <®_alwayson_frag>, "target:0=",<&cam0_reg>, ++ <&imx296>, "clocks:0=",<&cam0_clk>, ++ <&imx296>, "avdd-supply:0=",<&cam0_reg>; ++ clock-frequency = <&clk_over>, "clock-frequency:0"; ++ always-on = <0>, "+99"; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlays/imx327-overlay.dts b/arch/arm/boot/dts/overlays/imx327-overlay.dts +new file mode 100644 +index 000000000000..0776954bdba2 +--- /dev/null ++++ b/arch/arm/boot/dts/overlays/imx327-overlay.dts +@@ -0,0 +1,33 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++// Definitions for IMX327 camera module on VC I2C bus ++/dts-v1/; ++/plugin/; ++ ++#include ++#include "imx290_327-overlay.dtsi" ++ ++/{ ++ compatible = "brcm,bcm2835"; ++ ++ // Fragment numbers deliberately high to avoid conflicts with the ++ // included imx290_327 overlay file. ++ ++ fragment@101 { ++ target = <&cam_node>; ++ __overlay__ { ++ compatible = "sony,imx327lqr"; ++ }; ++ }; ++ ++ fragment@102 { ++ target = <&cam_node>; ++ __dormant__ { ++ // No mono IMX327 is currently defined. Use IMX290. ++ compatible = "sony,imx290llr"; ++ }; ++ }; ++ ++ __overrides__ { ++ mono = <0>, "-101+102"; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlays/imx378-overlay.dts b/arch/arm/boot/dts/overlays/imx378-overlay.dts +new file mode 100644 +index 000000000000..4a5072489a34 +--- /dev/null ++++ b/arch/arm/boot/dts/overlays/imx378-overlay.dts +@@ -0,0 +1,17 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++// Definitions for IMX378 camera module on VC I2C bus ++/dts-v1/; ++/plugin/; ++ ++#include "imx477_378-overlay.dtsi" ++ ++&cam_node { ++ compatible = "sony,imx378"; ++}; ++ ++/{ ++ __overrides__ { ++ sync-sink = <&cam_node>,"trigger-mode:0=2"; ++ sync-source = <&cam_node>,"trigger-mode:0=1"; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlays/imx462-overlay.dts b/arch/arm/boot/dts/overlays/imx462-overlay.dts +new file mode 100644 +index 000000000000..c4d7aabe2efe +--- /dev/null ++++ b/arch/arm/boot/dts/overlays/imx462-overlay.dts +@@ -0,0 +1,39 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++// Definitions for IMX462 camera module on VC I2C bus ++ ++// IMX462 is the successor to IMX290. The drivers currently don't support ++// any additional feature of IMX462, so use the IMX290 compatible strings ++// for now. ++ ++/dts-v1/; ++/plugin/; ++ ++#include ++#include "imx290_327-overlay.dtsi" ++ ++/{ ++ compatible = "brcm,bcm2835"; ++ ++ // Fragment numbers deliberately high to avoid conflicts with the ++ // included imx290_327 overlay file. ++ ++ //IMX462 is not defined in the bindings, so use IMX290 for now. ++ ++ fragment@101 { ++ target = <&cam_node>; ++ __overlay__ { ++ compatible = "sony,imx290lqr"; ++ }; ++ }; ++ ++ fragment@102 { ++ target = <&cam_node>; ++ __dormant__ { ++ compatible = "sony,imx290llr"; ++ }; ++ }; ++ ++ __overrides__ { ++ mono = <0>, "-101+102"; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlays/imx477-overlay.dts b/arch/arm/boot/dts/overlays/imx477-overlay.dts +new file mode 100644 +index 000000000000..8645162682f4 +--- /dev/null ++++ b/arch/arm/boot/dts/overlays/imx477-overlay.dts +@@ -0,0 +1,17 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++// Definitions for IMX477 camera module on VC I2C bus ++/dts-v1/; ++/plugin/; ++ ++#include "imx477_378-overlay.dtsi" ++ ++&cam_node { ++ compatible = "sony,imx477"; ++}; ++ ++/{ ++ __overrides__ { ++ sync-sink = <&cam_node>,"trigger-mode:0=2"; ++ sync-source = <&cam_node>,"trigger-mode:0=1"; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlays/imx477_378-overlay.dtsi b/arch/arm/boot/dts/overlays/imx477_378-overlay.dtsi +new file mode 100644 +index 000000000000..1ce42c2c8946 +--- /dev/null ++++ b/arch/arm/boot/dts/overlays/imx477_378-overlay.dtsi +@@ -0,0 +1,92 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++// Definitions for IMX477 camera module on VC I2C bus ++ ++/{ ++ compatible = "brcm,bcm2835"; ++ ++ fragment@0 { ++ target = <&i2c0if>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++ ++ clk_frag: fragment@1 { ++ target = <&cam1_clk>; ++ cam_clk: __overlay__ { ++ clock-frequency = <24000000>; ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&i2c0mux>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++ ++ reg_frag: fragment@3 { ++ target = <&cam1_reg>; ++ cam_reg: __overlay__ { ++ startup-delay-us = <300000>; ++ }; ++ }; ++ ++ reg_alwayson_frag: fragment@99 { ++ target = <&cam1_reg>; ++ __dormant__ { ++ regulator-always-on; ++ }; ++ }; ++ ++ i2c_frag: fragment@100 { ++ target = <&i2c_csi_dsi>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "okay"; ++ ++ #include "imx477_378.dtsi" ++ }; ++ }; ++ ++ csi_frag: fragment@101 { ++ target = <&csi1>; ++ csi: __overlay__ { ++ status = "okay"; ++ brcm,media-controller; ++ ++ port { ++ csi_ep: endpoint { ++ remote-endpoint = <&cam_endpoint>; + clock-lanes = <0>; + data-lanes = <1 2>; + clock-noncontinuous; @@ -21732,23 +33716,63 @@ index 000000000000..bfea40ce98d6 + }; + + __overrides__ { -+ rotation = <&imx477>,"rotation:0"; -+ orientation = <&imx477>,"orientation:0"; ++ rotation = <&cam_node>,"rotation:0"; ++ orientation = <&cam_node>,"orientation:0"; + media-controller = <&csi>,"brcm,media-controller?"; -+ cam0 = <&i2c_frag>, "target:0=",<&i2c_vc>, ++ cam0 = <&i2c_frag>, "target:0=",<&i2c_csi_dsi0>, + <&csi_frag>, "target:0=",<&csi0>, + <&clk_frag>, "target:0=",<&cam0_clk>, + <®_frag>, "target:0=",<&cam0_reg>, -+ <&imx477>, "clocks:0=",<&cam0_clk>, -+ <&imx477>, "vdda-supply:0=",<&cam0_reg>; ++ <®_alwayson_frag>, "target:0=",<&cam0_reg>, ++ <&cam_node>, "clocks:0=",<&cam0_clk>, ++ <&cam_node>, "VANA-supply:0=",<&cam0_reg>; ++ always-on = <0>, "+99"; ++ }; ++}; ++ ++&cam_node { ++ status = "okay"; ++}; ++ ++&cam_endpoint { ++ remote-endpoint = <&csi_ep>; ++}; +diff --git a/arch/arm/boot/dts/overlays/imx477_378.dtsi b/arch/arm/boot/dts/overlays/imx477_378.dtsi +new file mode 100644 +index 000000000000..a0c154c2a11f +--- /dev/null ++++ b/arch/arm/boot/dts/overlays/imx477_378.dtsi +@@ -0,0 +1,24 @@ ++cam_node: imx477@1a { ++ reg = <0x1a>; ++ status = "disabled"; ++ ++ clocks = <&cam1_clk>; ++ clock-names = "xclk"; ++ ++ VANA-supply = <&cam1_reg>; /* 2.8v */ ++ VDIG-supply = <&cam_dummy_reg>; /* 1.05v */ ++ VDDL-supply = <&cam_dummy_reg>; /* 1.8v */ ++ ++ rotation = <180>; ++ orientation = <2>; ++ ++ port { ++ cam_endpoint: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2>; ++ clock-noncontinuous; ++ link-frequencies = ++ /bits/ 64 <450000000>; ++ }; + }; +}; diff --git a/arch/arm/boot/dts/overlays/imx519-overlay.dts b/arch/arm/boot/dts/overlays/imx519-overlay.dts new file mode 100644 -index 000000000000..ada1224dd19b +index 000000000000..f572634836b8 --- /dev/null +++ b/arch/arm/boot/dts/overlays/imx519-overlay.dts -@@ -0,0 +1,96 @@ +@@ -0,0 +1,93 @@ +// SPDX-License-Identifier: GPL-2.0-only +// Definitions for imx519 camera module on VC I2C bus +/dts-v1/; @@ -21766,32 +33790,7 @@ index 000000000000..ada1224dd19b + #size-cells = <0>; + status = "okay"; + -+ imx519: imx519@1a { -+ compatible = "sony,imx519"; -+ reg = <0x1a>; -+ status = "okay"; -+ -+ clocks = <&cam1_clk>; -+ clock-names = "xclk"; -+ -+ VANA-supply = <&cam1_reg>; /* 2.8v */ -+ VDIG-supply = <&cam_dummy_reg>; /* 1.8v */ -+ VDDL-supply = <&cam_dummy_reg>; /* 1.2v */ -+ -+ rotation = <0>; -+ orientation = <2>; -+ -+ port { -+ imx519_0: endpoint { -+ remote-endpoint = <&csi1_ep>; -+ clock-lanes = <0>; -+ data-lanes = <1 2>; -+ clock-noncontinuous; -+ link-frequencies = -+ /bits/ 64 <493500000>; -+ }; -+ }; -+ }; ++ #include "imx519.dtsi" + }; + }; + @@ -21802,8 +33801,8 @@ index 000000000000..ada1224dd19b + brcm,media-controller; + + port{ -+ csi1_ep: endpoint{ -+ remote-endpoint = <&imx519_0>; ++ csi_ep: endpoint{ ++ remote-endpoint = <&cam_endpoint>; + clock-lanes = <0>; + data-lanes = <1 2>; + clock-noncontinuous; @@ -21834,20 +33833,368 @@ index 000000000000..ada1224dd19b + }; + }; + ++ fragment@5 { ++ target = <&cam_node>; ++ __overlay__ { ++ lens-focus = <&vcm_node>; ++ }; ++ }; ++ + __overrides__ { -+ rotation = <&imx519>,"rotation:0"; -+ orientation = <&imx519>,"orientation:0"; ++ rotation = <&cam_node>,"rotation:0"; ++ orientation = <&cam_node>,"orientation:0"; + media-controller = <&csi>,"brcm,media-controller?"; -+ cam0 = <&i2c_frag>, "target:0=",<&i2c_vc>, ++ cam0 = <&i2c_frag>, "target:0=",<&i2c_csi_dsi0>, + <&csi_frag>, "target:0=",<&csi0>, + <&clk_frag>, "target:0=",<&cam0_clk>, -+ <&imx519>, "clocks:0=",<&cam0_clk>, -+ <&imx519>, "VANA-supply:0=",<&cam0_reg>; ++ <&cam_node>, "clocks:0=",<&cam0_clk>, ++ <&cam_node>, "VANA-supply:0=",<&cam0_reg>, ++ <&vcm_node>, "vdd-supply:0=",<&cam0_reg>; ++ vcm = <&vcm_node>, "status", ++ <0>, "=5"; + }; +}; ++ ++&cam_node { ++ status = "okay"; ++}; ++ ++&cam_endpoint { ++ remote-endpoint = <&csi_ep>; ++}; ++ ++&vcm_node { ++ status = "okay"; ++}; +diff --git a/arch/arm/boot/dts/overlays/imx519.dtsi b/arch/arm/boot/dts/overlays/imx519.dtsi +new file mode 100644 +index 000000000000..18cba1781ec4 +--- /dev/null ++++ b/arch/arm/boot/dts/overlays/imx519.dtsi +@@ -0,0 +1,34 @@ ++// Fragment that configures a Sony IMX519 ++ ++cam_node: imx519@1a { ++ compatible = "sony,imx519"; ++ reg = <0x1a>; ++ status = "disabled"; ++ ++ clocks = <&cam1_clk>; ++ clock-names = "xclk"; ++ ++ VANA-supply = <&cam1_reg>; /* 2.8v */ ++ VDIG-supply = <&cam_dummy_reg>; /* 1.8v */ ++ VDDL-supply = <&cam_dummy_reg>; /* 1.2v */ ++ ++ rotation = <0>; ++ orientation = <2>; ++ ++ port { ++ cam_endpoint: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2>; ++ clock-noncontinuous; ++ link-frequencies = ++ /bits/ 64 <408000000>; ++ }; ++ }; ++}; ++ ++vcm_node: ak7375@c { ++ compatible = "asahi-kasei,ak7375"; ++ reg = <0x0c>; ++ status = "disabled"; ++ vdd-supply = <&cam1_reg>; ++}; +diff --git a/arch/arm/boot/dts/overlays/imx708-overlay.dts b/arch/arm/boot/dts/overlays/imx708-overlay.dts +new file mode 100644 +index 000000000000..a7042284a1ea +--- /dev/null ++++ b/arch/arm/boot/dts/overlays/imx708-overlay.dts +@@ -0,0 +1,105 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++// Definitions for IMX708 camera module on VC I2C bus ++/dts-v1/; ++/plugin/; ++ ++#include ++ ++/{ ++ compatible = "brcm,bcm2835"; ++ ++ fragment@0 { ++ target = <&i2c0if>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++ ++ clk_frag: fragment@1 { ++ target = <&cam1_clk>; ++ __overlay__ { ++ status = "okay"; ++ clock-frequency = <24000000>; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&i2c0mux>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++ ++ reg_frag: fragment@3 { ++ target = <&cam1_reg>; ++ cam_reg: __overlay__ { ++ startup-delay-us = <70000>; ++ off-on-delay-us = <30000>; ++ regulator-min-microvolt = <2700000>; ++ regulator-max-microvolt = <2700000>; ++ }; ++ }; ++ ++ fragment@4 { ++ target = <&cam_node>; ++ __overlay__ { ++ lens-focus = <&vcm_node>; ++ }; ++ }; ++ ++ i2c_frag: fragment@100 { ++ target = <&i2c_csi_dsi>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "okay"; ++ ++ #include "imx708.dtsi" ++ }; ++ }; ++ ++ csi_frag: fragment@101 { ++ target = <&csi1>; ++ csi: __overlay__ { ++ status = "okay"; ++ brcm,media-controller; ++ ++ port { ++ csi_ep: endpoint { ++ remote-endpoint = <&cam_endpoint>; ++ clock-lanes = <0>; ++ data-lanes = <1 2>; ++ clock-noncontinuous; ++ }; ++ }; ++ }; ++ }; ++ ++ __overrides__ { ++ rotation = <&cam_node>,"rotation:0"; ++ orientation = <&cam_node>,"orientation:0"; ++ media-controller = <&csi>,"brcm,media-controller?"; ++ cam0 = <&i2c_frag>, "target:0=",<&i2c_csi_dsi0>, ++ <&csi_frag>, "target:0=",<&csi0>, ++ <&clk_frag>, "target:0=",<&cam0_clk>, ++ <®_frag>, "target:0=",<&cam0_reg>, ++ <&cam_node>, "clocks:0=",<&cam0_clk>, ++ <&cam_node>, "vana1-supply:0=",<&cam0_reg>, ++ <&vcm_node>, "VDD-supply:0=",<&cam0_reg>; ++ vcm = <&vcm_node>, "status", ++ <0>, "=4"; ++ link-frequency = <&cam_endpoint>,"link-frequencies#0"; ++ }; ++}; ++ ++&cam_node { ++ status = "okay"; ++}; ++ ++&cam_endpoint { ++ remote-endpoint = <&csi_ep>; ++}; ++ ++&vcm_node { ++ status = "okay"; ++}; +diff --git a/arch/arm/boot/dts/overlays/imx708.dtsi b/arch/arm/boot/dts/overlays/imx708.dtsi +new file mode 100644 +index 000000000000..1558458d58ec +--- /dev/null ++++ b/arch/arm/boot/dts/overlays/imx708.dtsi +@@ -0,0 +1,35 @@ ++// Fragment that configures a Sony IMX708 ++ ++cam_node: imx708@1a { ++ compatible = "sony,imx708"; ++ reg = <0x1a>; ++ status = "disabled"; ++ ++ clocks = <&cam1_clk>; ++ clock-names = "inclk"; ++ ++ vana1-supply = <&cam1_reg>; /* 2.8v */ ++ vana2-supply = <&cam_dummy_reg>;/* 1.8v */ ++ vdig-supply = <&cam_dummy_reg>; /* 1.1v */ ++ vddl-supply = <&cam_dummy_reg>; /* 1.8v */ ++ ++ rotation = <180>; ++ orientation = <2>; ++ ++ port { ++ cam_endpoint: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2>; ++ clock-noncontinuous; ++ link-frequencies = ++ /bits/ 64 <450000000>; ++ }; ++ }; ++}; ++ ++vcm_node: dw9817@c { ++ compatible = "dongwoon,dw9817-vcm"; ++ reg = <0x0c>; ++ status = "disabled"; ++ VDD-supply = <&cam1_reg>; ++}; +diff --git a/arch/arm/boot/dts/overlays/interludeaudio-analog-overlay.dts b/arch/arm/boot/dts/overlays/interludeaudio-analog-overlay.dts +new file mode 100644 +index 000000000000..e2590135f919 +--- /dev/null ++++ b/arch/arm/boot/dts/overlays/interludeaudio-analog-overlay.dts +@@ -0,0 +1,73 @@ ++// Definitions for Interlude audio analog hat ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "brcm,bcm2835"; ++ ++ fragment@0 { ++ target = <&sound>; ++ __overlay__ { ++ compatible = "simple-audio-card"; ++ i2s-controller = <&i2s_clk_consumer>; ++ status = "okay"; ++ ++ simple-audio-card,name = "snd_IA_Analog_Hat"; ++ ++ simple-audio-card,widgets = ++ "Line", "Line In", ++ "Line", "Line Out"; ++ ++ simple-audio-card,routing = ++ "Line Out","AOUTA+", ++ "Line Out","AOUTA-", ++ "Line Out","AOUTB+", ++ "Line Out","AOUTB-", ++ "AINA","Line In", ++ "AINB","Line In"; ++ ++ simple-audio-card,format = "i2s"; ++ ++ simple-audio-card,bitclock-master = <&sound_master>; ++ simple-audio-card,frame-master = <&sound_master>; ++ ++ simple-audio-card,cpu { ++ sound-dai = <&i2s>; ++ dai-tdm-slot-num = <2>; ++ dai-tdm-slot-width = <32>; ++ }; ++ ++ sound_master: simple-audio-card,codec { ++ sound-dai = <&cs4271>; ++ system-clock-frequency = <24576000>; ++ }; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&i2s_clk_consumer>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&i2c1>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "okay"; ++ ++ cs4271: cs4271@10 { ++ #sound-dai-cells = <0>; ++ compatible = "cirrus,cs4271"; ++ reg = <0x10>; ++ status = "okay"; ++ reset-gpio = <&gpio 24 0>; /* Pin 26, active high */ ++ }; ++ }; ++ }; ++ __overrides__ { ++ gpiopin = <&cs4271>,"reset-gpio:4"; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlays/interludeaudio-digital-overlay.dts b/arch/arm/boot/dts/overlays/interludeaudio-digital-overlay.dts +new file mode 100644 +index 000000000000..24be00860310 +--- /dev/null ++++ b/arch/arm/boot/dts/overlays/interludeaudio-digital-overlay.dts +@@ -0,0 +1,49 @@ ++// Definitions for Interlude Audio Digital Hat ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "brcm,bcm2835"; ++ ++ fragment@0 { ++ target = <&i2s_clk_consumer>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&i2c1>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "okay"; ++ ++ wm8804@3b { ++ #sound-dai-cells = <0>; ++ compatible = "wlf,wm8804"; ++ reg = <0x3b>; ++ PVDD-supply = <&vdd_3v3_reg>; ++ DVDD-supply = <&vdd_3v3_reg>; ++ status = "okay"; ++ }; ++ }; ++ }; ++ ++ ++ fragment@2 { ++ target = <&sound>; ++ __overlay__ { ++ compatible = "interludeaudio,interludeaudio-digital"; ++ i2s-controller = <&i2s_clk_consumer>; ++ status = "okay"; ++ clock44-gpio = <&gpio 22 0>; ++ clock48-gpio = <&gpio 27 0>; ++ led1-gpio = <&gpio 13 0>; ++ led2-gpio = <&gpio 12 0>; ++ led3-gpio = <&gpio 6 0>; ++ reset-gpio = <&gpio 23 0>; ++ }; ++ }; ++ ++}; diff --git a/arch/arm/boot/dts/overlays/iqaudio-codec-overlay.dts b/arch/arm/boot/dts/overlays/iqaudio-codec-overlay.dts new file mode 100644 -index 000000000000..9110f5d34298 +index 000000000000..bffff5a4d64c --- /dev/null +++ b/arch/arm/boot/dts/overlays/iqaudio-codec-overlay.dts @@ -0,0 +1,42 @@ @@ -21859,7 +34206,7 @@ index 000000000000..9110f5d34298 + compatible = "brcm,bcm2835"; + + fragment@0 { -+ target = <&i2s>; ++ target = <&i2s_clk_consumer>; + __overlay__ { + status = "okay"; + }; @@ -21885,7 +34232,7 @@ index 000000000000..9110f5d34298 + target = <&sound>; + iqaudio_dac: __overlay__ { + compatible = "iqaudio,iqaudio-codec"; -+ i2s-controller = <&i2s>; ++ i2s-controller = <&i2s_clk_consumer>; + status = "okay"; + }; + }; @@ -21895,7 +34242,7 @@ index 000000000000..9110f5d34298 +}; diff --git a/arch/arm/boot/dts/overlays/iqaudio-dac-overlay.dts b/arch/arm/boot/dts/overlays/iqaudio-dac-overlay.dts new file mode 100644 -index 000000000000..24073cadd0ef +index 000000000000..05d348f5e58a --- /dev/null +++ b/arch/arm/boot/dts/overlays/iqaudio-dac-overlay.dts @@ -0,0 +1,46 @@ @@ -21907,7 +34254,7 @@ index 000000000000..24073cadd0ef + compatible = "brcm,bcm2835"; + + fragment@0 { -+ target = <&i2s>; ++ target = <&i2s_clk_producer>; + __overlay__ { + status = "okay"; + }; @@ -21936,7 +34283,7 @@ index 000000000000..24073cadd0ef + target = <&sound>; + frag2: __overlay__ { + compatible = "iqaudio,iqaudio-dac"; -+ i2s-controller = <&i2s>; ++ i2s-controller = <&i2s_clk_producer>; + status = "okay"; + }; + }; @@ -21947,7 +34294,7 @@ index 000000000000..24073cadd0ef +}; diff --git a/arch/arm/boot/dts/overlays/iqaudio-dacplus-overlay.dts b/arch/arm/boot/dts/overlays/iqaudio-dacplus-overlay.dts new file mode 100644 -index 000000000000..7c70b25e58d7 +index 000000000000..3993580f7ac1 --- /dev/null +++ b/arch/arm/boot/dts/overlays/iqaudio-dacplus-overlay.dts @@ -0,0 +1,49 @@ @@ -21959,7 +34306,7 @@ index 000000000000..7c70b25e58d7 + compatible = "brcm,bcm2835"; + + fragment@0 { -+ target = <&i2s>; ++ target = <&i2s_clk_producer>; + __overlay__ { + status = "okay"; + }; @@ -21988,7 +34335,7 @@ index 000000000000..7c70b25e58d7 + target = <&sound>; + iqaudio_dac: __overlay__ { + compatible = "iqaudio,iqaudio-dac"; -+ i2s-controller = <&i2s>; ++ i2s-controller = <&i2s_clk_producer>; + mute-gpios = <&gpio 22 0>; + status = "okay"; + }; @@ -22002,7 +34349,7 @@ index 000000000000..7c70b25e58d7 +}; diff --git a/arch/arm/boot/dts/overlays/iqaudio-digi-wm8804-audio-overlay.dts b/arch/arm/boot/dts/overlays/iqaudio-digi-wm8804-audio-overlay.dts new file mode 100644 -index 000000000000..ee54095c869b +index 000000000000..f24faf11ecfa --- /dev/null +++ b/arch/arm/boot/dts/overlays/iqaudio-digi-wm8804-audio-overlay.dts @@ -0,0 +1,47 @@ @@ -22014,7 +34361,7 @@ index 000000000000..ee54095c869b + compatible = "brcm,bcm2835"; + + fragment@0 { -+ target = <&i2s>; ++ target = <&i2s_clk_consumer>; + __overlay__ { + status = "okay"; + }; @@ -22042,7 +34389,7 @@ index 000000000000..ee54095c869b + target = <&sound>; + wm8804_digi: __overlay__ { + compatible = "iqaudio,wm8804-digi"; -+ i2s-controller = <&i2s>; ++ i2s-controller = <&i2s_clk_consumer>; + status = "okay"; + }; + }; @@ -22053,9 +34400,74 @@ index 000000000000..ee54095c869b + dai_stream_name = <&wm8804_digi>,"wm8804-digi,dai-stream-name"; + }; +}; +diff --git a/arch/arm/boot/dts/overlays/iqs550-overlay.dts b/arch/arm/boot/dts/overlays/iqs550-overlay.dts +new file mode 100644 +index 000000000000..c3956937055f +--- /dev/null ++++ b/arch/arm/boot/dts/overlays/iqs550-overlay.dts +@@ -0,0 +1,59 @@ ++// SPDX-License-Identifier: GPL-2.0-or-later ++// Definitions for Azoteq IQS550 trackpad/touchscreen controller ++/dts-v1/; ++/plugin/; ++#include ++#include ++ ++/ { ++ compatible = "brcm,bcm2835"; ++ ++ fragment@0 { ++ target = <&i2c1>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "okay"; ++ ++ iqs550: iqs550@74 { ++ compatible = "azoteq,iqs550"; ++ reg = <0x74>; ++ interrupt-parent = <&gpio>; ++ interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&iqs550_pins>; ++ touchscreen-size-x = <800>; ++ touchscreen-size-y = <480>; ++ }; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&iqs550>; ++ iqs550_reset: __dormant__ { ++ reset-gpios = <&gpio 255 (GPIO_ACTIVE_LOW | ++ GPIO_PUSH_PULL)>; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&gpio>; ++ __overlay__ { ++ iqs550_pins: iqs550_pins { ++ brcm,pins = <4>; ++ brcm,pull = <1>; ++ }; ++ }; ++ }; ++ ++ __overrides__ { ++ interrupt = <&iqs550>,"interrupts:0", ++ <&iqs550_pins>,"brcm,pins:0"; ++ reset = <0>,"+1", <&iqs550_reset>,"reset-gpios:4"; ++ sizex = <&iqs550>,"touchscreen-size-x:0"; ++ sizey = <&iqs550>,"touchscreen-size-y:0"; ++ invx = <&iqs550>,"touchscreen-inverted-x?"; ++ invy = <&iqs550>,"touchscreen-inverted-y?"; ++ swapxy = <&iqs550>,"touchscreen-swapped-x-y?"; ++ }; ++}; diff --git a/arch/arm/boot/dts/overlays/irs1125-overlay.dts b/arch/arm/boot/dts/overlays/irs1125-overlay.dts new file mode 100644 -index 000000000000..8f8432c07a89 +index 000000000000..0fe854557cd7 --- /dev/null +++ b/arch/arm/boot/dts/overlays/irs1125-overlay.dts @@ -0,0 +1,90 @@ @@ -22143,7 +34555,7 @@ index 000000000000..8f8432c07a89 + + __overrides__ { + media-controller = <&csi>,"brcm,media-controller?"; -+ cam0 = <&i2c_frag>, "target:0=",<&i2c_vc>, ++ cam0 = <&i2c_frag>, "target:0=",<&i2c_csi_dsi0>, + <&csi_frag>, "target:0=",<&csi0>, + <&clk_frag>, "target:0=",<&cam0_clk>, + <&irs1125>, "clocks:0=",<&cam0_clk>; @@ -22151,15 +34563,16 @@ index 000000000000..8f8432c07a89 +}; diff --git a/arch/arm/boot/dts/overlays/jedec-spi-nor-overlay.dts b/arch/arm/boot/dts/overlays/jedec-spi-nor-overlay.dts new file mode 100644 -index 000000000000..585c7dbcdf7f +index 000000000000..fb6d4bc91bf3 --- /dev/null +++ b/arch/arm/boot/dts/overlays/jedec-spi-nor-overlay.dts -@@ -0,0 +1,309 @@ +@@ -0,0 +1,136 @@ +// Overlay for JEDEC SPI-NOR Flash Devices (aka m25p80) + +// dtparams: +// flash-spi- - Enables flash device on SPI, CS#. +// flash-fastr-spi- - Enables flash device with fast read capability on SPI, CS#. ++// speed - Set the SPI clock speed in Hz +// +// If devices are present on SPI1 or SPI2, those interfaces must be enabled with one of the spi1-1/2/3cs and/or spi2-1/2/3cs overlays. +// @@ -22236,16 +34649,23 @@ index 000000000000..585c7dbcdf7f + }; + }; + -+ // enable flash on spi0.0 ++ // Enable fast read for device ++ // Use default active low interrupt signalling. + fragment@8 { ++ target = <&spi_nor>; ++ __dormant__ { ++ m25p,fast-read; ++ }; ++ }; ++ ++ payload: fragment@100 { + target = <&spi0>; -+ __dormant__ { ++ __overlay__ { + status = "okay"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ spi_nor_00: spi_nor@0 { -+ #address-cells = <1>; -+ #size-cells = <1>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ spi_nor: spi_nor@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <500000>; @@ -22253,220 +34673,39 @@ index 000000000000..585c7dbcdf7f + }; + }; + -+ // enable flash on spi0.1 -+ fragment@9 { -+ target = <&spi0>; -+ __dormant__ { -+ status = "okay"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ spi_nor_01: spi_nor@1 { -+ #address-cells = <1>; -+ #size-cells = <1>; -+ compatible = "jedec,spi-nor"; -+ reg = <1>; -+ spi-max-frequency = <500000>; -+ }; -+ }; -+ }; -+ -+ // enable flash on spi1.0 -+ fragment@10 { -+ target = <&spi1>; -+ __dormant__ { -+ status = "okay"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ spi_nor_10: spi_nor@0 { -+ #address-cells = <1>; -+ #size-cells = <1>; -+ compatible = "jedec,spi-nor"; -+ reg = <0>; -+ spi-max-frequency = <500000>; -+ }; -+ }; -+ }; -+ -+ // enable flash on spi1.1 -+ fragment@11 { -+ target = <&spi1>; -+ __dormant__ { -+ status = "okay"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ spi_nor_11: spi_nor@1 { -+ #address-cells = <1>; -+ #size-cells = <1>; -+ compatible = "jedec,spi-nor"; -+ reg = <1>; -+ spi-max-frequency = <500000>; -+ }; -+ }; -+ }; -+ -+ // enable flash on spi1.2 -+ fragment@12 { -+ target = <&spi1>; -+ __dormant__ { -+ status = "okay"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ spi_nor_12: spi_nor@2 { -+ #address-cells = <1>; -+ #size-cells = <1>; -+ compatible = "jedec,spi-nor"; -+ reg = <2>; -+ spi-max-frequency = <500000>; -+ }; -+ }; -+ }; -+ -+ // enable flash on spi2.0 -+ fragment@13 { -+ target = <&spi2>; -+ __dormant__ { -+ status = "okay"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ spi_nor_20: spi_nor@0 { -+ #address-cells = <1>; -+ #size-cells = <1>; -+ compatible = "jedec,spi-nor"; -+ reg = <0>; -+ spi-max-frequency = <500000>; -+ }; -+ }; -+ }; -+ -+ // enable flash on spi2.1 -+ fragment@14 { -+ target = <&spi2>; -+ __dormant__ { -+ status = "okay"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ spi_nor_21: spi_nor@1 { -+ #address-cells = <1>; -+ #size-cells = <1>; -+ compatible = "jedec,spi-nor"; -+ reg = <1>; -+ spi-max-frequency = <500000>; -+ }; -+ }; -+ }; -+ -+ // enable flash on spi2.2 -+ fragment@15 { -+ target = <&spi2>; -+ __dormant__ { -+ status = "okay"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ spi_nor_22: spi_nor@2 { -+ #address-cells = <1>; -+ #size-cells = <1>; -+ compatible = "jedec,spi-nor"; -+ reg = <2>; -+ spi-max-frequency = <500000>; -+ }; -+ }; -+ }; -+ -+ // Enable fast read for device on spi0.0. -+ // Use default active low interrupt signalling. -+ fragment@16 { -+ target = <&spi_nor_00>; -+ __dormant__ { -+ m25p,fast-read; -+ }; -+ }; -+ -+ // Enable fast read for device on spi0.1. -+ // Use default active low interrupt signalling. -+ fragment@17 { -+ target = <&spi_nor_01>; -+ __dormant__ { -+ m25p,fast-read; -+ }; -+ }; -+ -+ // Enable fast read for device on spi1.0. -+ // Use default active low interrupt signalling. -+ fragment@18 { -+ target = <&spi_nor_10>; -+ __dormant__ { -+ m25p,fast-read; -+ }; -+ }; -+ -+ // Enable fast read for device on spi1.1. -+ // Use default active low interrupt signalling. -+ fragment@19 { -+ target = <&spi_nor_11>; -+ __dormant__ { -+ m25p,fast-read; -+ }; -+ }; -+ -+ // Enable fast read for device on spi1.2. -+ // Use default active low interrupt signalling. -+ fragment@20 { -+ target = <&spi_nor_12>; -+ __dormant__ { -+ m25p,fast-read; -+ }; -+ }; -+ -+ // Enable fast read for device on spi2.0. -+ // Use default active low interrupt signalling. -+ fragment@21 { -+ target = <&spi_nor_20>; -+ __dormant__ { -+ m25p,fast-read; -+ }; -+ }; -+ -+ // Enable fast read for device on spi2.1. -+ // Use default active low interrupt signalling. -+ fragment@22 { -+ target = <&spi_nor_21>; -+ __dormant__ { -+ m25p,fast-read; -+ }; -+ }; -+ -+ // Enable fast read for device on spi2.2. -+ // Use default active low interrupt signalling. -+ fragment@23 { -+ target = <&spi_nor_22>; -+ __dormant__ { -+ m25p,fast-read; -+ }; -+ }; -+ + __overrides__ { -+ flash-spi0-0 = <0>,"+0+8"; -+ flash-spi0-1 = <0>,"+1+9"; -+ flash-spi1-0 = <0>,"+2+10"; -+ flash-spi1-1 = <0>,"+3+11"; -+ flash-spi1-2 = <0>,"+4+12"; -+ flash-spi2-0 = <0>,"+5+13"; -+ flash-spi2-1 = <0>,"+6+14"; -+ flash-spi2-2 = <0>,"+7+15"; -+ flash-fastr-spi0-0 = <0>,"+0+8+16"; -+ flash-fastr-spi0-1 = <0>,"+1+9+17"; -+ flash-fastr-spi1-0 = <0>,"+2+10+18"; -+ flash-fastr-spi1-1 = <0>,"+3+11+19"; -+ flash-fastr-spi1-2 = <0>,"+4+12+20"; -+ flash-fastr-spi2-0 = <0>,"+5+13+21"; -+ flash-fastr-spi2-1 = <0>,"+6+14+22"; -+ flash-fastr-spi2-2 = <0>,"+7+15+23"; ++ spi0-0 = <0>,"+0", <&payload>,"target:0=",<&spi0>, <&spi_nor>,"reg:0=0"; ++ spi0-1 = <0>,"+1", <&payload>,"target:0=",<&spi0>, <&spi_nor>,"reg:0=1"; ++ spi1-0 = <0>,"+2", <&payload>,"target:0=",<&spi1>, <&spi_nor>,"reg:0=0"; ++ spi1-1 = <0>,"+3", <&payload>,"target:0=",<&spi1>, <&spi_nor>,"reg:0=1"; ++ spi1-2 = <0>,"+4", <&payload>,"target:0=",<&spi1>, <&spi_nor>,"reg:0=2"; ++ spi2-0 = <0>,"+5", <&payload>,"target:0=",<&spi2>, <&spi_nor>,"reg:0=0"; ++ spi2-1 = <0>,"+6", <&payload>,"target:0=",<&spi2>, <&spi_nor>,"reg:0=1"; ++ spi2-2 = <0>,"+7", <&payload>,"target:0=",<&spi2>, <&spi_nor>,"reg:0=2"; ++ flash-spi0-0 = <0>,"+0", <&payload>,"target:0=",<&spi0>, <&spi_nor>,"reg:0=0"; ++ flash-spi0-1 = <0>,"+1", <&payload>,"target:0=",<&spi0>, <&spi_nor>,"reg:0=1"; ++ flash-spi1-0 = <0>,"+2", <&payload>,"target:0=",<&spi1>, <&spi_nor>,"reg:0=0"; ++ flash-spi1-1 = <0>,"+3", <&payload>,"target:0=",<&spi1>, <&spi_nor>,"reg:0=1"; ++ flash-spi1-2 = <0>,"+4", <&payload>,"target:0=",<&spi1>, <&spi_nor>,"reg:0=2"; ++ flash-spi2-0 = <0>,"+5", <&payload>,"target:0=",<&spi2>, <&spi_nor>,"reg:0=0"; ++ flash-spi2-1 = <0>,"+6", <&payload>,"target:0=",<&spi2>, <&spi_nor>,"reg:0=1"; ++ flash-spi2-2 = <0>,"+7", <&payload>,"target:0=",<&spi2>, <&spi_nor>,"reg:0=2"; ++ flash-fastr-spi0-0 = <0>,"+0+8", <&payload>,"target:0=",<&spi0>, <&spi_nor>,"reg:0=0"; ++ flash-fastr-spi0-1 = <0>,"+1+8", <&payload>,"target:0=",<&spi0>, <&spi_nor>,"reg:0=1"; ++ flash-fastr-spi1-0 = <0>,"+2+8", <&payload>,"target:0=",<&spi1>, <&spi_nor>,"reg:0=0"; ++ flash-fastr-spi1-1 = <0>,"+3+8", <&payload>,"target:0=",<&spi1>, <&spi_nor>,"reg:0=1"; ++ flash-fastr-spi1-2 = <0>,"+4+8", <&payload>,"target:0=",<&spi1>, <&spi_nor>,"reg:0=2"; ++ flash-fastr-spi2-0 = <0>,"+5+8", <&payload>,"target:0=",<&spi2>, <&spi_nor>,"reg:0=0"; ++ flash-fastr-spi2-1 = <0>,"+6+8", <&payload>,"target:0=",<&spi2>, <&spi_nor>,"reg:0=1"; ++ flash-fastr-spi2-2 = <0>,"+7+8", <&payload>,"target:0=",<&spi2>, <&spi_nor>,"reg:0=2"; ++ fastr = <0>,"+8"; ++ speed = <&spi_nor>, "spi-max-frequency:0"; + }; +}; + diff --git a/arch/arm/boot/dts/overlays/justboom-both-overlay.dts b/arch/arm/boot/dts/overlays/justboom-both-overlay.dts new file mode 100644 -index 000000000000..9c42670631c0 +index 000000000000..9185d668d1d5 --- /dev/null +++ b/arch/arm/boot/dts/overlays/justboom-both-overlay.dts @@ -0,0 +1,65 @@ @@ -22479,7 +34718,7 @@ index 000000000000..9c42670631c0 + compatible = "brcm,bcm2835"; + + fragment@0 { -+ target = <&i2s>; ++ target = <&i2s_clk_consumer>; + __overlay__ { + status = "okay"; + }; @@ -22526,7 +34765,7 @@ index 000000000000..9c42670631c0 + target = <&sound>; + frag3: __overlay__ { + compatible = "justboom,justboom-both"; -+ i2s-controller = <&i2s>; ++ i2s-controller = <&i2s_clk_consumer>; + status = "okay"; + }; + }; @@ -22537,7 +34776,7 @@ index 000000000000..9c42670631c0 +}; diff --git a/arch/arm/boot/dts/overlays/justboom-dac-overlay.dts b/arch/arm/boot/dts/overlays/justboom-dac-overlay.dts new file mode 100644 -index 000000000000..d00515dca419 +index 000000000000..901a6aaba4bc --- /dev/null +++ b/arch/arm/boot/dts/overlays/justboom-dac-overlay.dts @@ -0,0 +1,46 @@ @@ -22549,7 +34788,7 @@ index 000000000000..d00515dca419 + compatible = "brcm,bcm2835"; + + fragment@0 { -+ target = <&i2s>; ++ target = <&i2s_clk_producer>; + __overlay__ { + status = "okay"; + }; @@ -22578,7 +34817,7 @@ index 000000000000..d00515dca419 + target = <&sound>; + frag2: __overlay__ { + compatible = "justboom,justboom-dac"; -+ i2s-controller = <&i2s>; ++ i2s-controller = <&i2s_clk_producer>; + status = "okay"; + }; + }; @@ -22589,7 +34828,7 @@ index 000000000000..d00515dca419 +}; diff --git a/arch/arm/boot/dts/overlays/justboom-digi-overlay.dts b/arch/arm/boot/dts/overlays/justboom-digi-overlay.dts new file mode 100644 -index 000000000000..e73336029c54 +index 000000000000..c4c968200a4c --- /dev/null +++ b/arch/arm/boot/dts/overlays/justboom-digi-overlay.dts @@ -0,0 +1,41 @@ @@ -22601,7 +34840,7 @@ index 000000000000..e73336029c54 + compatible = "brcm,bcm2835"; + + fragment@0 { -+ target = <&i2s>; ++ target = <&i2s_clk_consumer>; + __overlay__ { + status = "okay"; + }; @@ -22629,7 +34868,7 @@ index 000000000000..e73336029c54 + target = <&sound>; + __overlay__ { + compatible = "justboom,justboom-digi"; -+ i2s-controller = <&i2s>; ++ i2s-controller = <&i2s_clk_consumer>; + status = "okay"; + }; + }; @@ -22728,7 +34967,7 @@ index 000000000000..6d971f3649ca +}; diff --git a/arch/arm/boot/dts/overlays/max98357a-overlay.dts b/arch/arm/boot/dts/overlays/max98357a-overlay.dts new file mode 100644 -index 000000000000..9e2afb05b7cb +index 000000000000..263d071fe977 --- /dev/null +++ b/arch/arm/boot/dts/overlays/max98357a-overlay.dts @@ -0,0 +1,84 @@ @@ -22746,7 +34985,7 @@ index 000000000000..9e2afb05b7cb + + /* Enable I2S */ + fragment@0 { -+ target = <&i2s>; ++ target = <&i2s_clk_producer>; + __overlay__ { + status = "okay"; + }; @@ -22786,7 +35025,7 @@ index 000000000000..9e2afb05b7cb + simple-audio-card,name = "MAX98357A"; + status = "okay"; + simple-audio-card,cpu { -+ sound-dai = <&i2s>; ++ sound-dai = <&i2s_clk_producer>; + }; + simple-audio-card,codec { + sound-dai = <&max98357a_dac>; @@ -22803,7 +35042,7 @@ index 000000000000..9e2afb05b7cb + simple-audio-card,name = "MAX98357A"; + status = "okay"; + simple-audio-card,cpu { -+ sound-dai = <&i2s>; ++ sound-dai = <&i2s_clk_producer>; + }; + simple-audio-card,codec { + sound-dai = <&max98357a_nsd>; @@ -23010,7 +35249,7 @@ index 000000000000..9964e246c14f +}; diff --git a/arch/arm/boot/dts/overlays/mbed-dac-overlay.dts b/arch/arm/boot/dts/overlays/mbed-dac-overlay.dts new file mode 100644 -index 000000000000..840dd9b31db4 +index 000000000000..e3f56608c643 --- /dev/null +++ b/arch/arm/boot/dts/overlays/mbed-dac-overlay.dts @@ -0,0 +1,64 @@ @@ -23022,7 +35261,7 @@ index 000000000000..840dd9b31db4 + compatible = "brcm,bcm2835"; + + fragment@0 { -+ target = <&i2s>; ++ target = <&i2s_clk_producer>; + __overlay__ { + status = "okay"; + }; @@ -23048,7 +35287,7 @@ index 000000000000..840dd9b31db4 + target = <&sound>; + __overlay__ { + compatible = "simple-audio-card"; -+ i2s-controller = <&i2s>; ++ i2s-controller = <&i2s_clk_producer>; + status = "okay"; + + simple-audio-card,name = "mbed-DAC"; @@ -23068,7 +35307,7 @@ index 000000000000..840dd9b31db4 + simple-audio-card,format = "i2s"; + + simple-audio-card,cpu { -+ sound-dai = <&i2s>; ++ sound-dai = <&i2s_clk_producer>; + }; + + sound_master: simple-audio-card,codec { @@ -23080,10 +35319,10 @@ index 000000000000..840dd9b31db4 +}; diff --git a/arch/arm/boot/dts/overlays/mcp23017-overlay.dts b/arch/arm/boot/dts/overlays/mcp23017-overlay.dts new file mode 100644 -index 000000000000..c546d8ba7e6d +index 000000000000..d77690b17711 --- /dev/null +++ b/arch/arm/boot/dts/overlays/mcp23017-overlay.dts -@@ -0,0 +1,69 @@ +@@ -0,0 +1,103 @@ +// Definitions for MCP23017 Gpio Extender from Microchip Semiconductor + +/dts-v1/; @@ -23093,7 +35332,7 @@ index 000000000000..c546d8ba7e6d + compatible = "brcm,bcm2835"; + + fragment@0 { -+ target = <&i2c1>; ++ target = <&i2cbus>; + __overlay__ { + status = "okay"; + }; @@ -23110,30 +35349,13 @@ index 000000000000..c546d8ba7e6d + }; + + fragment@2 { -+ target = <&i2c1>; -+ __overlay__ { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ mcp23017: mcp@20 { -+ compatible = "microchip,mcp23017"; -+ reg = <0x20>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ -+ status = "okay"; -+ }; -+ }; -+ }; -+ -+ fragment@3 { + target = <&mcp23017>; + __dormant__ { + compatible = "microchip,mcp23008"; + }; + }; + -+ fragment@4 { ++ fragment@3 { + target = <&mcp23017>; + mcp23017_irq: __overlay__ { + #interrupt-cells=<2>; @@ -23144,12 +35366,63 @@ index 000000000000..c546d8ba7e6d + }; + }; + ++ fragment@4 { ++ target = <&i2cbus>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ mcp23017: mcp@20 { ++ compatible = "microchip,mcp23017"; ++ pinctrl-name = "default"; ++ pinctrl-0 = <&mcp23017_pins>; ++ reg = <0x20>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ ++ status = "okay"; ++ }; ++ }; ++ }; ++ ++ frag100: fragment@100 { ++ target = <&i2c1>; ++ i2cbus: __overlay__ { ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@101 { ++ target = <&i2c0if>; ++ __dormant__ { ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@102 { ++ target = <&i2c0mux>; ++ __dormant__ { ++ status = "okay"; ++ }; ++ }; ++ + __overrides__ { + gpiopin = <&mcp23017_pins>,"brcm,pins:0", + <&mcp23017_irq>,"interrupts:0"; + addr = <&mcp23017>,"reg:0", <&mcp23017_pins>,"reg:0"; -+ mcp23008 = <0>,"=3"; -+ noints = <0>,"!1!4"; ++ mcp23008 = <0>,"=2"; ++ noints = <0>,"!1!3"; ++ i2c0 = <&frag100>, "target:0=",<&i2c0>; ++ i2c_csi_dsi = <&frag100>, "target:0=",<&i2c_csi_dsi>, ++ <0>,"+101+102"; ++ i2c3 = <&frag100>, "target?=0", ++ <&frag100>, "target-path=i2c3"; ++ i2c4 = <&frag100>, "target?=0", ++ <&frag100>, "target-path=i2c4"; ++ i2c5 = <&frag100>, "target?=0", ++ <&frag100>, "target-path=i2c5"; ++ i2c6 = <&frag100>, "target?=0", ++ <&frag100>, "target-path=i2c6"; + }; +}; + @@ -25037,10 +37310,10 @@ index 000000000000..714eca5a4b5e + diff --git a/arch/arm/boot/dts/overlays/media-center-overlay.dts b/arch/arm/boot/dts/overlays/media-center-overlay.dts new file mode 100644 -index 000000000000..1b56963f4f16 +index 000000000000..4bc2eaa1f215 --- /dev/null +++ b/arch/arm/boot/dts/overlays/media-center-overlay.dts -@@ -0,0 +1,134 @@ +@@ -0,0 +1,86 @@ +/* + * Device Tree overlay for Media Center HAT by Pi Supply + * @@ -25053,21 +37326,20 @@ index 000000000000..1b56963f4f16 + compatible = "brcm,bcm2835"; + + fragment@0 { -+ target = <&spi0>; ++ target = <&spidev0>; + __overlay__ { -+ status = "okay"; -+ -+ spidev@0{ -+ status = "disabled"; -+ }; -+ -+ spidev@1{ -+ status = "disabled"; -+ }; ++ status = "disabled"; + }; + }; + + fragment@1 { ++ target = <&spidev1>; ++ __overlay__ { ++ status = "disabled"; ++ }; ++ }; ++ ++ fragment@2 { + target = <&gpio>; + __overlay__ { + rpi_display_pins: rpi_display_pins { @@ -25078,12 +37350,13 @@ index 000000000000..1b56963f4f16 + }; + }; + -+ fragment@2 { ++ fragment@3 { + target = <&spi0>; + __overlay__ { + /* needed to avoid dtc warning */ + #address-cells = <1>; + #size-cells = <0>; ++ status = "okay"; + + rpidisplay: rpi-display@0{ + compatible = "ilitek,ili9341"; @@ -25116,71 +37389,23 @@ index 000000000000..1b56963f4f16 + }; + }; + -+ fragment@3 { -+ target-path = "/"; -+ __overlay__ { -+ lirc_rpi: lirc_rpi { -+ compatible = "rpi,lirc-rpi"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&lirc_pins>; -+ status = "okay"; -+ -+ // Override autodetection of IR receiver circuit -+ // (0 = active high, 1 = active low, -1 = no override ) -+ rpi,sense = <0xffffffff>; -+ -+ // Software carrier -+ // (0 = off, 1 = on) -+ rpi,softcarrier = <1>; -+ -+ // Invert output -+ // (0 = off, 1 = on) -+ rpi,invert = <0>; -+ -+ // Enable debugging messages -+ // (0 = off, 1 = on) -+ rpi,debug = <0>; -+ }; -+ }; -+ }; -+ -+ fragment@4 { -+ target = <&gpio>; -+ __overlay__ { -+ lirc_pins: lirc_pins { -+ brcm,pins = <6 5>; -+ brcm,function = <1 0>; // out in -+ brcm,pull = <0 1>; // off down -+ }; -+ }; -+ }; -+ + __overrides__ { + speed = <&rpidisplay>,"spi-max-frequency:0"; + rotate = <&rpidisplay>,"rotate:0"; + fps = <&rpidisplay>,"fps:0"; -+ debug = <&rpidisplay>,"debug:0", -+ <&lirc_rpi>,"rpi,debug:0"; ++ debug = <&rpidisplay>,"debug:0"; + xohms = <&rpidisplay_ts>,"ti,x-plate-ohms;0"; + swapxy = <&rpidisplay_ts>,"ti,swap-xy?"; + backlight = <&rpidisplay>,"led-gpios:4", + <&rpi_display_pins>,"brcm,pins:0"; -+ -+ gpio_out_pin = <&lirc_pins>,"brcm,pins:0"; -+ gpio_in_pin = <&lirc_pins>,"brcm,pins:4"; -+ gpio_in_pull = <&lirc_pins>,"brcm,pull:4"; -+ -+ sense = <&lirc_rpi>,"rpi,sense:0"; -+ softcarrier = <&lirc_rpi>,"rpi,softcarrier:0"; -+ invert = <&lirc_rpi>,"rpi,invert:0"; + }; +}; diff --git a/arch/arm/boot/dts/overlays/merus-amp-overlay.dts b/arch/arm/boot/dts/overlays/merus-amp-overlay.dts new file mode 100644 -index 000000000000..4501fbdc253d +index 000000000000..96159a48d33f --- /dev/null +++ b/arch/arm/boot/dts/overlays/merus-amp-overlay.dts -@@ -0,0 +1,60 @@ +@@ -0,0 +1,59 @@ +// SPDX-License-Identifier: GPL-2.0-only +// Definitions for Infineon Merus-Amp +/dts-v1/; @@ -25188,12 +37413,11 @@ index 000000000000..4501fbdc253d +#include +#include + -+ +/ { + compatible = "brcm,bcm2835"; + + fragment@0 { -+ target = <&i2s>; ++ target = <&i2s_clk_producer>; + __overlay__ { + status = "okay"; + }; @@ -25203,9 +37427,9 @@ index 000000000000..4501fbdc253d + target = <&gpio>; + __overlay__ { + merus_amp_pins: merus_amp_pins { -+ brcm,pins = <23>; -+ brcm,function = <0>; /* in */ -+ brcm,pull = <2>; /* up */ ++ brcm,pins = <23 8>; ++ brcm,function = <0 0>; ++ brcm,pull = <2 0>; + }; + }; + }; @@ -25236,7 +37460,7 @@ index 000000000000..4501fbdc253d + target = <&sound>; + __overlay__ { + compatible = "merus,merus-amp"; -+ i2s-controller = <&i2s>; ++ i2s-controller = <&i2s_clk_producer>; + status = "okay"; + }; + }; @@ -25283,6 +37507,47 @@ index 000000000000..f7e44d29e101 + }; + }; +}; +diff --git a/arch/arm/boot/dts/overlays/midi-uart0-pi5-overlay.dts b/arch/arm/boot/dts/overlays/midi-uart0-pi5-overlay.dts +new file mode 100644 +index 000000000000..6cd1f3ed2d8d +--- /dev/null ++++ b/arch/arm/boot/dts/overlays/midi-uart0-pi5-overlay.dts +@@ -0,0 +1,35 @@ ++/dts-v1/; ++/plugin/; ++ ++#include ++ ++/* ++ * Fake a higher clock rate to get a larger divisor, and thereby a lower ++ * baudrate. The real clock is 100MHz, which we scale so that requesting ++ * 38.4kHz results in an actual 31.25kHz. ++ * ++ * 100000000*38400/31250 = 122880000 ++ */ ++ ++/{ ++ compatible = "brcm,bcm2712"; ++ ++ fragment@0 { ++ target-path = "/"; ++ __overlay__ { ++ midi_clk: midi_clk0 { ++ compatible = "fixed-clock"; ++ #clock-cells = <0>; ++ clock-output-names = "uart0_pclk"; ++ clock-frequency = <122880000>; ++ }; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&uart0>; ++ __overlay__ { ++ clocks = <&midi_clk &rp1_clocks RP1_PLL_SYS_PRI_PH>; ++ }; ++ }; ++}; diff --git a/arch/arm/boot/dts/overlays/midi-uart1-overlay.dts b/arch/arm/boot/dts/overlays/midi-uart1-overlay.dts new file mode 100644 index 000000000000..e0bc410acbff @@ -25332,9 +37597,50 @@ index 000000000000..e0bc410acbff + }; + }; +}; +diff --git a/arch/arm/boot/dts/overlays/midi-uart1-pi5-overlay.dts b/arch/arm/boot/dts/overlays/midi-uart1-pi5-overlay.dts +new file mode 100644 +index 000000000000..18f526865eed +--- /dev/null ++++ b/arch/arm/boot/dts/overlays/midi-uart1-pi5-overlay.dts +@@ -0,0 +1,35 @@ ++/dts-v1/; ++/plugin/; ++ ++#include ++ ++/* ++ * Fake a higher clock rate to get a larger divisor, and thereby a lower ++ * baudrate. The real clock is 100MHz, which we scale so that requesting ++ * 38.4kHz results in an actual 31.25kHz. ++ * ++ * 100000000*38400/31250 = 122880000 ++ */ ++ ++/{ ++ compatible = "brcm,bcm2712"; ++ ++ fragment@0 { ++ target-path = "/"; ++ __overlay__ { ++ midi_clk: midi_clk1 { ++ compatible = "fixed-clock"; ++ #clock-cells = <0>; ++ clock-output-names = "uart1_pclk"; ++ clock-frequency = <122880000>; ++ }; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&uart1>; ++ __overlay__ { ++ clocks = <&midi_clk &rp1_clocks RP1_PLL_SYS_PRI_PH>; ++ }; ++ }; ++}; diff --git a/arch/arm/boot/dts/overlays/midi-uart2-overlay.dts b/arch/arm/boot/dts/overlays/midi-uart2-overlay.dts new file mode 100644 -index 000000000000..66f3092e9a74 +index 000000000000..5c6985f41ea2 --- /dev/null +++ b/arch/arm/boot/dts/overlays/midi-uart2-overlay.dts @@ -0,0 +1,37 @@ @@ -25352,7 +37658,7 @@ index 000000000000..66f3092e9a74 + */ + +/{ -+ compatible = "brcm,bcm2835"; ++ compatible = "brcm,bcm2711"; + + fragment@0 { + target-path = "/"; @@ -25375,9 +37681,50 @@ index 000000000000..66f3092e9a74 + }; +}; + +diff --git a/arch/arm/boot/dts/overlays/midi-uart2-pi5-overlay.dts b/arch/arm/boot/dts/overlays/midi-uart2-pi5-overlay.dts +new file mode 100644 +index 000000000000..5e1e0c6fd7a9 +--- /dev/null ++++ b/arch/arm/boot/dts/overlays/midi-uart2-pi5-overlay.dts +@@ -0,0 +1,35 @@ ++/dts-v1/; ++/plugin/; ++ ++#include ++ ++/* ++ * Fake a higher clock rate to get a larger divisor, and thereby a lower ++ * baudrate. The real clock is 100MHz, which we scale so that requesting ++ * 38.4kHz results in an actual 31.25kHz. ++ * ++ * 100000000*38400/31250 = 122880000 ++ */ ++ ++/{ ++ compatible = "brcm,bcm2712"; ++ ++ fragment@0 { ++ target-path = "/"; ++ __overlay__ { ++ midi_clk: midi_clk2 { ++ compatible = "fixed-clock"; ++ #clock-cells = <0>; ++ clock-output-names = "uart2_pclk"; ++ clock-frequency = <122880000>; ++ }; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&uart2>; ++ __overlay__ { ++ clocks = <&midi_clk &rp1_clocks RP1_PLL_SYS_PRI_PH>; ++ }; ++ }; ++}; diff --git a/arch/arm/boot/dts/overlays/midi-uart3-overlay.dts b/arch/arm/boot/dts/overlays/midi-uart3-overlay.dts new file mode 100644 -index 000000000000..55c6cb94f963 +index 000000000000..052027db0564 --- /dev/null +++ b/arch/arm/boot/dts/overlays/midi-uart3-overlay.dts @@ -0,0 +1,38 @@ @@ -25395,7 +37742,7 @@ index 000000000000..55c6cb94f963 + */ + +/{ -+ compatible = "brcm,bcm2835"; ++ compatible = "brcm,bcm2711"; + + fragment@0 { + target-path = "/"; @@ -25419,9 +37766,50 @@ index 000000000000..55c6cb94f963 +}; + + +diff --git a/arch/arm/boot/dts/overlays/midi-uart3-pi5-overlay.dts b/arch/arm/boot/dts/overlays/midi-uart3-pi5-overlay.dts +new file mode 100644 +index 000000000000..705a2793d00c +--- /dev/null ++++ b/arch/arm/boot/dts/overlays/midi-uart3-pi5-overlay.dts +@@ -0,0 +1,35 @@ ++/dts-v1/; ++/plugin/; ++ ++#include ++ ++/* ++ * Fake a higher clock rate to get a larger divisor, and thereby a lower ++ * baudrate. The real clock is 100MHz, which we scale so that requesting ++ * 38.4kHz results in an actual 31.25kHz. ++ * ++ * 100000000*38400/31250 = 122880000 ++ */ ++ ++/{ ++ compatible = "brcm,bcm2712"; ++ ++ fragment@0 { ++ target-path = "/"; ++ __overlay__ { ++ midi_clk: midi_clk3 { ++ compatible = "fixed-clock"; ++ #clock-cells = <0>; ++ clock-output-names = "uart3_pclk"; ++ clock-frequency = <122880000>; ++ }; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&uart3>; ++ __overlay__ { ++ clocks = <&midi_clk &rp1_clocks RP1_PLL_SYS_PRI_PH>; ++ }; ++ }; ++}; diff --git a/arch/arm/boot/dts/overlays/midi-uart4-overlay.dts b/arch/arm/boot/dts/overlays/midi-uart4-overlay.dts new file mode 100644 -index 000000000000..5819df1a6b2e +index 000000000000..5f09a7ccd675 --- /dev/null +++ b/arch/arm/boot/dts/overlays/midi-uart4-overlay.dts @@ -0,0 +1,38 @@ @@ -25439,7 +37827,7 @@ index 000000000000..5819df1a6b2e + */ + +/{ -+ compatible = "brcm,bcm2835"; ++ compatible = "brcm,bcm2711"; + + fragment@0 { + target-path = "/"; @@ -25463,9 +37851,50 @@ index 000000000000..5819df1a6b2e +}; + + +diff --git a/arch/arm/boot/dts/overlays/midi-uart4-pi5-overlay.dts b/arch/arm/boot/dts/overlays/midi-uart4-pi5-overlay.dts +new file mode 100644 +index 000000000000..0d2f823ed7dd +--- /dev/null ++++ b/arch/arm/boot/dts/overlays/midi-uart4-pi5-overlay.dts +@@ -0,0 +1,35 @@ ++/dts-v1/; ++/plugin/; ++ ++#include ++ ++/* ++ * Fake a higher clock rate to get a larger divisor, and thereby a lower ++ * baudrate. The real clock is 100MHz, which we scale so that requesting ++ * 38.4kHz results in an actual 31.25kHz. ++ * ++ * 100000000*38400/31250 = 122880000 ++ */ ++ ++/{ ++ compatible = "brcm,bcm2712"; ++ ++ fragment@0 { ++ target-path = "/"; ++ __overlay__ { ++ midi_clk: midi_clk4 { ++ compatible = "fixed-clock"; ++ #clock-cells = <0>; ++ clock-output-names = "uart4_pclk"; ++ clock-frequency = <122880000>; ++ }; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&uart4>; ++ __overlay__ { ++ clocks = <&midi_clk &rp1_clocks RP1_PLL_SYS_PRI_PH>; ++ }; ++ }; ++}; diff --git a/arch/arm/boot/dts/overlays/midi-uart5-overlay.dts b/arch/arm/boot/dts/overlays/midi-uart5-overlay.dts new file mode 100644 -index 000000000000..a1d37f7103ff +index 000000000000..74551ec2a672 --- /dev/null +++ b/arch/arm/boot/dts/overlays/midi-uart5-overlay.dts @@ -0,0 +1,38 @@ @@ -25483,7 +37912,7 @@ index 000000000000..a1d37f7103ff + */ + +/{ -+ compatible = "brcm,bcm2835"; ++ compatible = "brcm,bcm2711"; + + fragment@0 { + target-path = "/"; @@ -25509,7 +37938,7 @@ index 000000000000..a1d37f7103ff + diff --git a/arch/arm/boot/dts/overlays/minipitft13-overlay.dts b/arch/arm/boot/dts/overlays/minipitft13-overlay.dts new file mode 100644 -index 000000000000..b1a0a2a41f72 +index 000000000000..5e0941e8ba54 --- /dev/null +++ b/arch/arm/boot/dts/overlays/minipitft13-overlay.dts @@ -0,0 +1,70 @@ @@ -25525,21 +37954,20 @@ index 000000000000..b1a0a2a41f72 + compatible = "brcm,bcm2835"; + + fragment@0 { -+ target = <&spi0>; ++ target = <&spidev0>; + __overlay__ { -+ status = "okay"; -+ -+ spidev@0{ -+ status = "disabled"; -+ }; -+ -+ spidev@1{ -+ status = "disabled"; -+ }; ++ status = "disabled"; + }; + }; + + fragment@1 { ++ target = <&spidev1>; ++ __overlay__ { ++ status = "disabled"; ++ }; ++ }; ++ ++ fragment@2 { + target = <&gpio>; + __overlay__ { + pitft_pins: pitft_pins { @@ -25550,12 +37978,13 @@ index 000000000000..b1a0a2a41f72 + }; + }; + -+ fragment@2 { ++ fragment@3 { + target = <&spi0>; + __overlay__ { + /* needed to avoid dtc warning */ + #address-cells = <1>; + #size-cells = <0>; ++ status = "okay"; + + pitft: pitft@0 { + compatible = "fbtft,minipitft13"; @@ -25585,10 +38014,10 @@ index 000000000000..b1a0a2a41f72 +}; diff --git a/arch/arm/boot/dts/overlays/miniuart-bt-overlay.dts b/arch/arm/boot/dts/overlays/miniuart-bt-overlay.dts new file mode 100644 -index 000000000000..da49f14a0940 +index 000000000000..757e5cd3c4e8 --- /dev/null +++ b/arch/arm/boot/dts/overlays/miniuart-bt-overlay.dts -@@ -0,0 +1,93 @@ +@@ -0,0 +1,83 @@ +/dts-v1/; +/plugin/; + @@ -25631,7 +38060,7 @@ index 000000000000..da49f14a0940 + target = <&uart1>; + __overlay__ { + pinctrl-names = "default"; -+ pinctrl-0 = <&uart1_pins &bt_pins &fake_bt_cts>; ++ pinctrl-0 = <&uart1_pins>; + status = "okay"; + }; + }; @@ -25646,35 +38075,25 @@ index 000000000000..da49f14a0940 + }; + + fragment@4 { -+ target = <&uart1_pins>; ++ target = <&uart1>; + __overlay__ { -+ brcm,pins = <32 33>; -+ brcm,function = <2>; /* alt5=UART1 */ -+ brcm,pull = <0 2>; ++ pinctrl-0 = <&uart1_bt_pins>; + }; + }; + + fragment@5 { -+ target = <&gpio>; -+ __overlay__ { -+ fake_bt_cts: fake_bt_cts { -+ brcm,pins = <31>; -+ brcm,function = <1>; /* output */ -+ }; -+ }; -+ }; -+ -+ fragment@6 { + target-path = "/aliases"; + __overlay__ { + serial0 = "/soc/serial@7e201000"; + serial1 = "/soc/serial@7e215040"; ++ bluetooth = "/soc/serial@7e215040/bluetooth"; + }; + }; + -+ fragment@7 { ++ fragment@6 { + target = <&minibt>; + minibt_frag: __overlay__ { ++ status = "okay"; + }; + }; + @@ -25682,6 +38101,187 @@ index 000000000000..da49f14a0940 + krnbt = <&minibt_frag>,"status"; + }; +}; +diff --git a/arch/arm/boot/dts/overlays/mipi-dbi-spi-overlay.dts b/arch/arm/boot/dts/overlays/mipi-dbi-spi-overlay.dts +new file mode 100644 +index 000000000000..63fb3a5f2388 +--- /dev/null ++++ b/arch/arm/boot/dts/overlays/mipi-dbi-spi-overlay.dts +@@ -0,0 +1,175 @@ ++/* ++ * mipi-dbi-spi-overlay.dts ++ */ ++ ++#include ++ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "brcm,bcm2835"; ++ ++ spidev_fragment: fragment@0 { ++ target-path = "spi0/spidev@0"; ++ __overlay__ { ++ status = "disabled"; ++ }; ++ }; ++ ++ panel_fragment: fragment@1 { ++ target = <&spi0>; ++ __overlay__ { ++ /* needed to avoid dtc warning */ ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ status = "okay"; ++ ++ panel: panel@0 { ++ compatible = "panel", "panel-mipi-dbi-spi"; ++ reg = <0>; ++ spi-max-frequency = <32000000>; ++ ++ width-mm = <0>; ++ height-mm = <0>; ++ ++ timing: panel-timing { ++ hactive = <320>; ++ vactive = <240>; ++ hback-porch = <0>; ++ vback-porch = <0>; ++ ++ clock-frequency = <0>; ++ hfront-porch = <0>; ++ hsync-len = <0>; ++ vfront-porch = <0>; ++ vsync-len = <0>; ++ }; ++ }; ++ }; ++ }; ++ ++ fragment@10 { ++ target = <&panel>; ++ __dormant__ { ++ backlight = <&backlight_gpio>; ++ }; ++ }; ++ ++ fragment@11 { ++ target-path = "/"; ++ __dormant__ { ++ backlight_gpio: backlight_gpio { ++ compatible = "gpio-backlight"; ++ gpios = <&gpio 255 GPIO_ACTIVE_HIGH>; ++ }; ++ }; ++ }; ++ ++ fragment@20 { ++ target = <&panel>; ++ __dormant__ { ++ backlight = <&backlight_pwm>; ++ }; ++ }; ++ ++ fragment@21 { ++ target-path = "/"; ++ __dormant__ { ++ backlight_pwm: backlight_pwm { ++ compatible = "pwm-backlight"; ++ brightness-levels = <0 6 8 12 16 24 32 40 48 64 96 128 160 192 224 255>; ++ default-brightness-level = <15>; ++ pwms = <&pwm 0 200000 0>; ++ }; ++ }; ++ }; ++ ++ fragment@22 { ++ target = <&pwm>; ++ __dormant__ { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pwm_pins>; ++ assigned-clock-rates = <1000000>; ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@23 { ++ target = <&gpio>; ++ __dormant__ { ++ pwm_pins: pwm_pins { ++ brcm,pins = <18>; ++ brcm,function = <2>; /* Alt5 */ ++ }; ++ }; ++ }; ++ ++ fragment@24 { ++ target = <&chosen>; ++ __dormant__ { ++ bootargs = "snd_bcm2835.enable_headphones=0"; ++ }; ++ }; ++ ++ __overrides__ { ++ compatible = <&panel>, "compatible"; ++ ++ spi0-0 = <&panel_fragment>, "target:0=",<&spi0>, ++ <&spidev_fragment>, "target-path=spi0/spidev@0", ++ <&panel>, "reg:0=0"; ++ spi0-1 = <&panel_fragment>, "target:0=",<&spi0>, ++ <&spidev_fragment>, "target-path=spi0/spidev@1", ++ <&panel>, "reg:0=1"; ++ spi1-0 = <&panel_fragment>, "target:0=",<&spi1>, ++ <&spidev_fragment>, "target-path=spi1/spidev@0", ++ <&panel>, "reg:0=0"; ++ spi1-1 = <&panel_fragment>, "target:0=",<&spi1>, ++ <&spidev_fragment>, "target-path=spi1/spidev@1", ++ <&panel>, "reg:0=1"; ++ spi1-2 = <&panel_fragment>, "target:0=",<&spi1>, ++ <&spidev_fragment>, "target-path=spi1/spidev@2", ++ <&panel>, "reg:0=2"; ++ spi2-0 = <&panel_fragment>, "target:0=",<&spi2>, ++ <&spidev_fragment>, "target-path=spi2/spidev@0", ++ <&panel>, "reg:0=0"; ++ spi2-1 = <&panel_fragment>, "target:0=",<&spi2>, ++ <&spidev_fragment>, "target-path=spi2/spidev@1", ++ <&panel>, "reg:0=1"; ++ spi2-2 = <&panel_fragment>, "target:0=",<&spi2>, ++ <&spidev_fragment>, "target-path=spi2/spidev@2", ++ <&panel>, "reg:0=2"; ++ ++ speed = <&panel>, "spi-max-frequency:0"; ++ cpha = <&panel>, "spi-cpha?"; ++ cpol = <&panel>, "spi-cpol?"; ++ ++ write-only = <&panel>, "write-only?"; ++ ++ width = <&timing>, "hactive:0"; ++ height = <&timing>, "vactive:0"; ++ x-offset = <&timing>, "hback-porch:0"; ++ y-offset = <&timing>, "vback-porch:0"; ++ clock-frequency = <&timing>, "clock-frequency:0"; ++ ++ width-mm = <&panel>, "width-mm:0"; ++ height-mm = <&panel>, "height-mm:0"; ++ ++ /* optional gpios */ ++ reset-gpio = <&panel>, "reset-gpios:0=", <&gpio>, ++ <&panel>, "reset-gpios:4", ++ <&panel>, "reset-gpios:8=0"; /* GPIO_ACTIVE_HIGH */ ++ dc-gpio = <&panel>, "dc-gpios:0=", <&gpio>, ++ <&panel>, "dc-gpios:4", ++ <&panel>, "dc-gpios:8=0"; /* GPIO_ACTIVE_HIGH */ ++ ++ backlight-gpio = <0>, "+10+11", ++ <&backlight_gpio>, "gpios:4"; ++ backlight-pwm = <0>, "+20+21+22+23+24"; ++ backlight-pwm-chan = <&backlight_pwm>, "pwms:4"; ++ backlight-pwm-gpio = <&pwm_pins>, "brcm,pins:0"; ++ backlight-pwm-func = <&pwm_pins>, "brcm,function:0"; ++ backlight-def-brightness = <&backlight_pwm>, "default-brightness-level:0"; ++ }; ++}; diff --git a/arch/arm/boot/dts/overlays/mlx90640-overlay.dts b/arch/arm/boot/dts/overlays/mlx90640-overlay.dts new file mode 100644 index 000000000000..a2655ed82585 @@ -25762,44 +38362,9 @@ index 000000000000..c1a2f691aa1e + overclock_50 = <&frag0>,"brcm,overclock-50:0"; + }; +}; -diff --git a/arch/arm/boot/dts/overlays/mpu6050-overlay.dts b/arch/arm/boot/dts/overlays/mpu6050-overlay.dts -new file mode 100644 -index 000000000000..1b4c06535687 ---- /dev/null -+++ b/arch/arm/boot/dts/overlays/mpu6050-overlay.dts -@@ -0,0 +1,29 @@ -+// Definitions for MPU6050 -+/dts-v1/; -+/plugin/; -+ -+/ { -+ compatible = "brcm,bcm2835"; -+ -+ fragment@0 { -+ target = <&i2c1>; -+ __overlay__ { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "okay"; -+ clock-frequency = <400000>; -+ -+ mpu6050: mpu6050@68 { -+ compatible = "invensense,mpu6050"; -+ reg = <0x68>; -+ interrupt-parent = <&gpio>; -+ interrupts = <4 1>; -+ }; -+ }; -+ }; -+ -+ __overrides__ { -+ interrupt = <&mpu6050>,"interrupts:0"; -+ addr = <&mpu6050>,"reg:0"; -+ }; -+}; diff --git a/arch/arm/boot/dts/overlays/mz61581-overlay.dts b/arch/arm/boot/dts/overlays/mz61581-overlay.dts new file mode 100644 -index 000000000000..6e00e8b2ddf2 +index 000000000000..101ad21d8093 --- /dev/null +++ b/arch/arm/boot/dts/overlays/mz61581-overlay.dts @@ -0,0 +1,117 @@ @@ -25904,7 +38469,7 @@ index 000000000000..6e00e8b2ddf2 + spi-max-frequency = <2000000>; + interrupts = <4 2>; /* high-to-low edge triggered */ + interrupt-parent = <&gpio>; -+ pendown-gpio = <&gpio 4 0>; ++ pendown-gpio = <&gpio 4 1>; + + ti,x-plate-ohms = /bits/ 16 <60>; + ti,pressure-max = /bits/ 16 <255>; @@ -25920,12 +38485,127 @@ index 000000000000..6e00e8b2ddf2 + xohms = <&mz61581_ts>,"ti,x-plate-ohms;0"; + }; +}; +diff --git a/arch/arm/boot/dts/overlays/ov2311-overlay.dts b/arch/arm/boot/dts/overlays/ov2311-overlay.dts +new file mode 100644 +index 000000000000..f51c772428ca +--- /dev/null ++++ b/arch/arm/boot/dts/overlays/ov2311-overlay.dts +@@ -0,0 +1,77 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++// Definitions for OV2311 camera module on VC I2C bus ++/dts-v1/; ++/plugin/; ++ ++#include ++ ++/{ ++ compatible = "brcm,bcm2835"; ++ ++ i2c_frag: fragment@0 { ++ target = <&i2c_csi_dsi>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "okay"; ++ ++ #include "ov2311.dtsi" ++ }; ++ }; ++ ++ csi_frag: fragment@1 { ++ target = <&csi1>; ++ csi: __overlay__ { ++ status = "okay"; ++ brcm,media-controller; ++ ++ port { ++ csi_ep: endpoint { ++ remote-endpoint = <&cam_endpoint>; ++ data-lanes = <1 2>; ++ }; ++ }; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&i2c0if>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@3 { ++ target = <&i2c0mux>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++ ++ clk_frag: fragment@4{ ++ target = <&cam1_clk>; ++ __overlay__ { ++ status = "okay"; ++ clock-frequency = <24000000>; ++ }; ++ }; ++ ++ __overrides__ { ++ rotation = <&cam_node>,"rotation:0"; ++ orientation = <&cam_node>,"orientation:0"; ++ media-controller = <&csi>,"brcm,media-controller?"; ++ cam0 = <&i2c_frag>, "target:0=",<&i2c_csi_dsi0>, ++ <&csi_frag>, "target:0=",<&csi0>, ++ <&clk_frag>, "target:0=",<&cam0_clk>, ++ <&cam_node>, "clocks:0=",<&cam0_clk>, ++ <&cam_node>, "avdd-supply:0=",<&cam0_reg>; ++ }; ++}; ++ ++&cam_node { ++ status = "okay"; ++}; ++ ++&cam_endpoint { ++ remote-endpoint = <&csi_ep>; ++}; +diff --git a/arch/arm/boot/dts/overlays/ov2311.dtsi b/arch/arm/boot/dts/overlays/ov2311.dtsi +new file mode 100644 +index 000000000000..a1714d6941c3 +--- /dev/null ++++ b/arch/arm/boot/dts/overlays/ov2311.dtsi +@@ -0,0 +1,26 @@ ++// Fragment that configures an ov2311 ++ ++cam_node: ov2311@60 { ++ compatible = "ovti,ov2311"; ++ reg = <0x60>; ++ status = "disabled"; ++ ++ clocks = <&cam1_clk>; ++ clock-names = "xvclk"; ++ ++ avdd-supply = <&cam1_reg>; ++ dovdd-supply = <&cam_dummy_reg>; ++ dvdd-supply = <&cam_dummy_reg>; ++ ++ rotation = <0>; ++ orientation = <2>; ++ ++ port { ++ cam_endpoint: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2>; ++ link-frequencies = ++ /bits/ 64 <400000000>; ++ }; ++ }; ++}; diff --git a/arch/arm/boot/dts/overlays/ov5647-overlay.dts b/arch/arm/boot/dts/overlays/ov5647-overlay.dts new file mode 100644 -index 000000000000..a1221024d334 +index 000000000000..37fe46412439 --- /dev/null +++ b/arch/arm/boot/dts/overlays/ov5647-overlay.dts -@@ -0,0 +1,99 @@ +@@ -0,0 +1,93 @@ +// SPDX-License-Identifier: GPL-2.0-only +// Definitions for OV5647 camera module on VC I2C bus +/dts-v1/; @@ -25941,30 +38621,13 @@ index 000000000000..a1221024d334 + #size-cells = <0>; + status = "okay"; + -+ ov5647: ov5647@36 { -+ compatible = "ovti,ov5647"; -+ reg = <0x36>; -+ status = "okay"; ++ #include "ov5647.dtsi" + -+ clocks = <&cam1_clk>; -+ -+ avdd-supply = <&cam1_reg>; -+ dovdd-supply = <&cam_dummy_reg>; -+ dvdd-supply = <&cam_dummy_reg>; -+ -+ rotation = <0>; -+ orientation = <2>; -+ -+ port { -+ ov5647_0: endpoint { -+ remote-endpoint = <&csi1_ep>; -+ clock-lanes = <0>; -+ data-lanes = <1 2>; -+ clock-noncontinuous; -+ link-frequencies = -+ /bits/ 64 <297000000>; -+ }; -+ }; ++ vcm_node: ad5398@c { ++ compatible = "adi,ad5398"; ++ reg = <0x0c>; ++ status = "disabled"; ++ VANA-supply = <&cam1_reg>; + }; + }; + }; @@ -25976,8 +38639,8 @@ index 000000000000..a1221024d334 + brcm,media-controller; + + port { -+ csi1_ep: endpoint { -+ remote-endpoint = <&ov5647_0>; ++ csi_ep: endpoint { ++ remote-endpoint = <&cam_endpoint>; + data-lanes = <1 2>; + }; + }; @@ -26014,23 +38677,202 @@ index 000000000000..a1221024d334 + }; + + __overrides__ { -+ rotation = <&ov5647>,"rotation:0"; -+ orientation = <&ov5647>,"orientation:0"; ++ rotation = <&cam_node>,"rotation:0"; ++ orientation = <&cam_node>,"orientation:0"; + media-controller = <&csi>,"brcm,media-controller?"; -+ cam0 = <&i2c_frag>, "target:0=",<&i2c_vc>, ++ cam0 = <&i2c_frag>, "target:0=",<&i2c_csi_dsi0>, + <&csi_frag>, "target:0=",<&csi0>, + <®_frag>, "target:0=",<&cam0_reg>, + <&clk_frag>, "target:0=",<&cam0_clk>, -+ <&ov5647>, "clocks:0=",<&cam0_clk>, -+ <&ov5647>, "avdd-supply:0=",<&cam0_reg>; ++ <&cam_node>, "clocks:0=",<&cam0_clk>, ++ <&cam_node>, "avdd-supply:0=",<&cam0_reg>, ++ <&vcm_node>, "VANA-supply:0=",<&cam0_reg>; ++ vcm = <&vcm_node>, "status=okay", ++ <&cam_node>,"lens-focus:0=", <&vcm_node>; + }; +}; ++ ++&cam_node { ++ status = "okay"; ++}; ++ ++&cam_endpoint { ++ remote-endpoint = <&csi_ep>; ++}; +diff --git a/arch/arm/boot/dts/overlays/ov5647.dtsi b/arch/arm/boot/dts/overlays/ov5647.dtsi +new file mode 100644 +index 000000000000..6455a191a394 +--- /dev/null ++++ b/arch/arm/boot/dts/overlays/ov5647.dtsi +@@ -0,0 +1,25 @@ ++cam_node: ov5647@36 { ++ compatible = "ovti,ov5647"; ++ reg = <0x36>; ++ status = "disabled"; ++ ++ clocks = <&cam1_clk>; ++ ++ avdd-supply = <&cam1_reg>; ++ dovdd-supply = <&cam_dummy_reg>; ++ dvdd-supply = <&cam_dummy_reg>; ++ ++ rotation = <0>; ++ orientation = <2>; ++ ++ port { ++ cam_endpoint: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2>; ++ clock-noncontinuous; ++ link-frequencies = ++ /bits/ 64 <297000000>; ++ }; ++ }; ++}; ++ +diff --git a/arch/arm/boot/dts/overlays/ov64a40-overlay.dts b/arch/arm/boot/dts/overlays/ov64a40-overlay.dts +new file mode 100644 +index 000000000000..b6f8586d6b24 +--- /dev/null ++++ b/arch/arm/boot/dts/overlays/ov64a40-overlay.dts +@@ -0,0 +1,91 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++// Definitions for OV64A40 camera module on VC I2C bus ++/dts-v1/; ++/plugin/; ++ ++/{ ++ compatible = "brcm,bcm2835"; ++ ++ i2c_frag: fragment@0 { ++ target = <&i2c_csi_dsi>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "okay"; ++ ++ #include "ov64a40.dtsi" ++ }; ++ }; ++ ++ csi_frag: fragment@1 { ++ target = <&csi1>; ++ csi: __overlay__ { ++ status = "okay"; ++ brcm,media-controller; ++ ++ port{ ++ csi_ep: endpoint{ ++ remote-endpoint = <&cam_endpoint>; ++ clock-lanes = <0>; ++ data-lanes = <1 2>; ++ }; ++ }; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&i2c0if>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++ ++ clk_frag: fragment@3 { ++ target = <&cam1_clk>; ++ __overlay__ { ++ clock-frequency = <24000000>; ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@4 { ++ target = <&i2c0mux>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@5 { ++ target = <&cam_node>; ++ __overlay__ { ++ lens-focus = <&vcm_node>; ++ }; ++ }; ++ ++ __overrides__ { ++ rotation = <&cam_node>,"rotation:0"; ++ orientation = <&cam_node>,"orientation:0"; ++ media-controller = <&csi>,"brcm,media-controller?"; ++ cam0 = <&i2c_frag>, "target:0=",<&i2c_csi_dsi0>, ++ <&csi_frag>, "target:0=",<&csi0>, ++ <&clk_frag>, "target:0=",<&cam0_clk>, ++ <&cam_node>, "clocks:0=",<&cam0_clk>, ++ <&cam_node>, "avdd-supply:0=",<&cam0_reg>, ++ <&vcm_node>, "vdd-supply:0=",<&cam0_reg>; ++ vcm = <&vcm_node>, "status", ++ <0>, "=5"; ++ link-frequency = <&cam_endpoint>,"link-frequencies#0"; ++ }; ++}; ++ ++&cam_node { ++ status = "okay"; ++}; ++ ++&cam_endpoint { ++ remote-endpoint = <&csi_ep>; ++}; ++ ++&vcm_node { ++ status = "okay"; ++}; +diff --git a/arch/arm/boot/dts/overlays/ov64a40.dtsi b/arch/arm/boot/dts/overlays/ov64a40.dtsi +new file mode 100644 +index 000000000000..471b383fa151 +--- /dev/null ++++ b/arch/arm/boot/dts/overlays/ov64a40.dtsi +@@ -0,0 +1,34 @@ ++// Fragment that configures an OV64A40 ++ ++cam_node: ov64a40@36 { ++ compatible = "ovti,ov64a40"; ++ reg = <0x36>; ++ status = "disabled"; ++ ++ clocks = <&cam1_clk>; ++ clock-names = "xclk"; ++ ++ avdd-supply = <&cam1_reg>; /* 2.8v */ ++ dovdd-supply = <&cam_dummy_reg>;/* 1.8v */ ++ dvdd-supply = <&cam_dummy_reg>; /* 1.1v */ ++ ++ rotation = <180>; ++ orientation = <2>; ++ ++ port { ++ cam_endpoint: endpoint { ++ bus-type = <4>; ++ clock-lanes = <0>; ++ data-lanes = <1 2>; ++ link-frequencies = ++ /bits/ 64 <456000000>; ++ }; ++ }; ++}; ++ ++vcm_node: bu64754@76 { ++ compatible = "rohm,bu64754"; ++ reg = <0x76>; ++ status = "disabled"; ++ vdd-supply = <&cam1_reg>; ++}; diff --git a/arch/arm/boot/dts/overlays/ov7251-overlay.dts b/arch/arm/boot/dts/overlays/ov7251-overlay.dts new file mode 100644 -index 000000000000..0e44be8a4468 +index 000000000000..9975febc8995 --- /dev/null +++ b/arch/arm/boot/dts/overlays/ov7251-overlay.dts -@@ -0,0 +1,94 @@ +@@ -0,0 +1,77 @@ +// SPDX-License-Identifier: GPL-2.0-only +// Definitions for OV7251 camera module on VC I2C bus +/dts-v1/; @@ -26048,33 +38890,7 @@ index 000000000000..0e44be8a4468 + #size-cells = <0>; + status = "okay"; + -+ ov7251: ov7251@60 { -+ compatible = "ovti,ov7251"; -+ reg = <0x60>; -+ status = "okay"; -+ -+ clocks = <&cam1_clk>; -+ clock-names = "xclk"; -+ clock-frequency = <24000000>; -+ -+ vdddo-supply = <&cam_dummy_reg>; -+ vdda-supply = <&cam1_reg>; -+ vddd-supply = <&cam_dummy_reg>; -+ -+ rotation = <0>; -+ orientation = <2>; -+ -+ port { -+ ov7251_0: endpoint { -+ remote-endpoint = <&csi1_ep>; -+ clock-lanes = <0>; -+ data-lanes = <1>; -+ clock-noncontinuous; -+ link-frequencies = -+ /bits/ 64 <456000000>; -+ }; -+ }; -+ }; ++ #include "ov7251.dtsi" + }; + }; + @@ -26082,10 +38898,11 @@ index 000000000000..0e44be8a4468 + target = <&csi1>; + csi: __overlay__ { + status = "okay"; ++ brcm,media-controller; + + port { -+ csi1_ep: endpoint { -+ remote-endpoint = <&ov7251_0>; ++ csi_ep: endpoint { ++ remote-endpoint = <&cam_endpoint>; + data-lanes = <1>; + }; + }; @@ -26115,22 +38932,64 @@ index 000000000000..0e44be8a4468 + }; + + __overrides__ { -+ rotation = <&ov7251>,"rotation:0"; -+ orientation = <&ov7251>,"orientation:0"; ++ rotation = <&cam_node>,"rotation:0"; ++ orientation = <&cam_node>,"orientation:0"; + media-controller = <&csi>,"brcm,media-controller?"; -+ cam0 = <&i2c_frag>, "target:0=",<&i2c_vc>, ++ cam0 = <&i2c_frag>, "target:0=",<&i2c_csi_dsi0>, + <&csi_frag>, "target:0=",<&csi0>, + <&clk_frag>, "target:0=",<&cam0_clk>, -+ <&ov7251>, "clocks:0=",<&cam0_clk>, -+ <&ov7251>, "vdda-supply:0=",<&cam0_reg>; ++ <&cam_node>, "clocks:0=",<&cam0_clk>, ++ <&cam_node>, "vdda-supply:0=",<&cam0_reg>; ++ }; ++}; ++ ++&cam_node { ++ status = "okay"; ++}; ++ ++&cam_endpoint { ++ remote-endpoint = <&csi_ep>; ++}; +diff --git a/arch/arm/boot/dts/overlays/ov7251.dtsi b/arch/arm/boot/dts/overlays/ov7251.dtsi +new file mode 100644 +index 000000000000..561fed1db837 +--- /dev/null ++++ b/arch/arm/boot/dts/overlays/ov7251.dtsi +@@ -0,0 +1,28 @@ ++// Fragment that configures an ov7251 ++ ++cam_node: ov7251@60 { ++ compatible = "ovti,ov7251"; ++ reg = <0x60>; ++ status = "disabled"; ++ ++ clocks = <&cam1_clk>; ++ clock-names = "xclk"; ++ clock-frequency = <24000000>; ++ ++ vdddo-supply = <&cam_dummy_reg>; ++ vdda-supply = <&cam1_reg>; ++ vddd-supply = <&cam_dummy_reg>; ++ ++ rotation = <0>; ++ orientation = <2>; ++ ++ port { ++ cam_endpoint: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1>; ++ clock-noncontinuous; ++ link-frequencies = ++ /bits/ 64 <240000000>; ++ }; + }; +}; diff --git a/arch/arm/boot/dts/overlays/ov9281-overlay.dts b/arch/arm/boot/dts/overlays/ov9281-overlay.dts new file mode 100644 -index 000000000000..8c08a3a1077c +index 000000000000..ec95b7a8b2f1 --- /dev/null +++ b/arch/arm/boot/dts/overlays/ov9281-overlay.dts -@@ -0,0 +1,95 @@ +@@ -0,0 +1,78 @@ +// SPDX-License-Identifier: GPL-2.0-only +// Definitions for OV9281 camera module on VC I2C bus +/dts-v1/; @@ -26148,32 +39007,7 @@ index 000000000000..8c08a3a1077c + #size-cells = <0>; + status = "okay"; + -+ ov9281: ov9281@60 { -+ compatible = "ovti,ov9281"; -+ reg = <0x60>; -+ status = "okay"; -+ -+ clocks = <&cam1_clk>; -+ clock-names = "xvclk"; -+ -+ avdd-supply = <&cam1_reg>; -+ dovdd-supply = <&cam_dummy_reg>; -+ dvdd-supply = <&cam_dummy_reg>; -+ -+ rotation = <0>; -+ orientation = <2>; -+ -+ port { -+ ov9281_0: endpoint { -+ remote-endpoint = <&csi1_ep>; -+ clock-lanes = <0>; -+ data-lanes = <1 2>; -+ clock-noncontinuous; -+ link-frequencies = -+ /bits/ 64 <400000000>; -+ }; -+ }; -+ }; ++ #include "ov9281.dtsi" + }; + }; + @@ -26184,8 +39018,8 @@ index 000000000000..8c08a3a1077c + brcm,media-controller; + + port { -+ csi1_ep: endpoint { -+ remote-endpoint = <&ov9281_0>; ++ csi_ep: endpoint { ++ remote-endpoint = <&cam_endpoint>; + data-lanes = <1 2>; + clock-noncontinuous; + }; @@ -26216,47 +39050,164 @@ index 000000000000..8c08a3a1077c + }; + + __overrides__ { -+ rotation = <&ov9281>,"rotation:0"; -+ orientation = <&ov9281>,"orientation:0"; ++ rotation = <&cam_node>,"rotation:0"; ++ orientation = <&cam_node>,"orientation:0"; + media-controller = <&csi>,"brcm,media-controller?"; -+ cam0 = <&i2c_frag>, "target:0=",<&i2c_vc>, ++ cam0 = <&i2c_frag>, "target:0=",<&i2c_csi_dsi0>, + <&csi_frag>, "target:0=",<&csi0>, + <&clk_frag>, "target:0=",<&cam0_clk>, -+ <&ov9281>, "clocks:0=",<&cam0_clk>, -+ <&ov9281>, "avdd-supply:0=",<&cam0_reg>; ++ <&cam_node>, "clocks:0=",<&cam0_clk>, ++ <&cam_node>, "avdd-supply:0=",<&cam0_reg>; ++ }; ++}; ++ ++&cam_node { ++ status = "okay"; ++}; ++ ++&cam_endpoint { ++ remote-endpoint = <&csi_ep>; ++}; +diff --git a/arch/arm/boot/dts/overlays/ov9281.dtsi b/arch/arm/boot/dts/overlays/ov9281.dtsi +new file mode 100644 +index 000000000000..7df43bc6ef39 +--- /dev/null ++++ b/arch/arm/boot/dts/overlays/ov9281.dtsi +@@ -0,0 +1,27 @@ ++// Fragment that configures an ov9281 ++ ++cam_node: ov9281@60 { ++ compatible = "ovti,ov9281"; ++ reg = <0x60>; ++ status = "disabled"; ++ ++ clocks = <&cam1_clk>; ++ clock-names = "xvclk"; ++ ++ avdd-supply = <&cam1_reg>; ++ dovdd-supply = <&cam_dummy_reg>; ++ dvdd-supply = <&cam_dummy_reg>; ++ ++ rotation = <0>; ++ orientation = <2>; ++ ++ port { ++ cam_endpoint: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2>; ++ clock-noncontinuous; ++ link-frequencies = ++ /bits/ 64 <400000000>; ++ }; + }; +}; diff --git a/arch/arm/boot/dts/overlays/overlay_map.dts b/arch/arm/boot/dts/overlays/overlay_map.dts new file mode 100644 -index 000000000000..0e01f46d8db0 +index 000000000000..c2643b485bbc --- /dev/null +++ b/arch/arm/boot/dts/overlays/overlay_map.dts -@@ -0,0 +1,166 @@ +@@ -0,0 +1,493 @@ +/dts-v1/; + +/ { ++ audremap { ++ bcm2835; ++ bcm2711; ++ }; ++ ++ balena-fin { ++ bcm2835; ++ bcm2711; ++ }; ++ + bmp085_i2c-sensor { + deprecated = "use i2c-sensor,bmp085"; + }; + ++ cm-swap-i2c0 { ++ bcm2835; ++ bcm2711; ++ }; ++ + cutiepi-panel { + bcm2711; + }; + ++ disable-bt { ++ bcm2835; ++ bcm2711; ++ bcm2712 = "disable-bt-pi5"; ++ }; ++ ++ disable-bt-pi5 { ++ bcm2712; ++ }; ++ ++ disable-emmc2 { ++ bcm2711; ++ }; ++ ++ disable-wifi { ++ bcm2835; ++ bcm2711; ++ bcm2712 = "disable-wifi-pi5"; ++ }; ++ ++ disable-wifi-pi5 { ++ bcm2712; ++ }; ++ ++ hifiberry-dac8x { ++ bcm2712; ++ }; ++ + highperi { + bcm2711; + }; + ++ i2c0 { ++ bcm2835; ++ bcm2711; ++ bcm2712 = "i2c0-pi5"; ++ }; ++ + i2c0-bcm2708 { + deprecated = "use i2c0"; + }; + ++ i2c0-pi5 { ++ bcm2712; ++ }; ++ ++ i2c1 { ++ bcm2835; ++ bcm2711; ++ bcm2712 = "i2c1-pi5"; ++ }; ++ + i2c1-bcm2708 { + deprecated = "use i2c1"; + }; + ++ i2c1-pi5 { ++ bcm2712; ++ }; ++ ++ i2c2 { ++ bcm2712 = "i2c2-pi5"; ++ }; ++ ++ i2c2-pi5 { ++ bcm2712; ++ }; ++ + i2c3 { + bcm2711; ++ bcm2712 = "i2c3-pi5"; ++ }; ++ ++ i2c3-pi5 { ++ bcm2712; + }; + + i2c4 { @@ -26271,12 +39222,87 @@ index 000000000000..0e01f46d8db0 + bcm2711; + }; + ++ i2s-gpio28-31 { ++ bcm2835; ++ bcm2711; ++ }; ++ + lirc-rpi { + deprecated = "use gpio-ir"; + }; + ++ midi-uart0 { ++ bcm2835; ++ bcm2711; ++ bcm2712 = "midi-uart0-pi5"; ++ }; ++ ++ midi-uart0-pi5 { ++ bcm2712; ++ }; ++ ++ midi-uart1 { ++ bcm2835; ++ bcm2711; ++ bcm2712 = "midi-uart1-pi5"; ++ }; ++ ++ midi-uart1-pi5 { ++ bcm2712; ++ }; ++ ++ midi-uart2 { ++ bcm2711; ++ bcm2712 = "midi-uart2-pi5"; ++ }; ++ ++ midi-uart2-pi5 { ++ bcm2712; ++ }; ++ ++ midi-uart3 { ++ bcm2711; ++ bcm2712 = "midi-uart3-pi5"; ++ }; ++ ++ midi-uart3-pi5 { ++ bcm2712; ++ }; ++ ++ midi-uart4 { ++ bcm2711; ++ bcm2712 = "midi-uart4-pi5"; ++ }; ++ ++ midi-uart4-pi5 { ++ bcm2712; ++ }; ++ ++ midi-uart5 { ++ bcm2711; ++ }; ++ ++ miniuart-bt { ++ bcm2835; ++ bcm2711; ++ }; ++ ++ mmc { ++ bcm2835; ++ bcm2711; ++ }; ++ ++ mpu6050 { ++ deprecated = "use i2c-sensor,mpu6050"; ++ }; ++ + pcie-32bit-dma { + bcm2711; ++ bcm2712 = "pcie-32bit-dma-pi5"; ++ }; ++ ++ pcie-32bit-dma-pi5 { ++ bcm2712; + }; + + pi3-act-led { @@ -26295,7 +39321,56 @@ index 000000000000..0e01f46d8db0 + renamed = "miniuart-bt"; + }; + ++ pisound { ++ bcm2835; ++ bcm2711; ++ bcm2712 = "pisound-pi5"; ++ }; ++ ++ pisound-pi5 { ++ bcm2712; ++ }; ++ ++ pwm1 { ++ bcm2711; ++ }; ++ ++ ramoops { ++ bcm2835; ++ bcm2711 = "ramoops-pi4"; ++ }; ++ ++ ramoops-pi4 { ++ bcm2711; ++ }; ++ ++ rpi-cirrus-wm5102 { ++ renamed = "cirrus-wm5102"; ++ }; ++ ++ rpi-dac { ++ renamed = "i2s-dac"; ++ }; ++ ++ rpi-display { ++ renamed = "watterott-display"; ++ }; ++ ++ rpi-proto { ++ renamed = "proto-codec"; ++ }; ++ + rpivid-v4l2 { ++ deprecated = "no longer necessary"; ++ }; ++ ++ sdhost { ++ bcm2835; ++ bcm2711; ++ }; ++ ++ sdio { ++ bcm2835; + bcm2711; + }; + @@ -26303,10 +39378,29 @@ index 000000000000..0e01f46d8db0 + deprecated = "use sdio,bus_width=1,gpios_22_25"; + }; + ++ sdio-pi5 { ++ bcm2712; ++ }; ++ + sdtweak { + deprecated = "use 'dtparam=sd_poll_once' etc."; + }; + ++ smi { ++ bcm2835; ++ bcm2711; ++ }; ++ ++ smi-dev { ++ bcm2835; ++ bcm2711; ++ }; ++ ++ smi-nand { ++ bcm2835; ++ bcm2711; ++ }; ++ + spi0-cs { + renamed = "spi0-2cs"; + }; @@ -26315,12 +39409,42 @@ index 000000000000..0e01f46d8db0 + deprecated = "no longer necessary"; + }; + ++ spi2-1cs { ++ bcm2835; ++ bcm2711; ++ bcm2712 = "spi2-1cs-pi5"; ++ }; ++ ++ spi2-1cs-pi5 { ++ bcm2712; ++ }; ++ ++ spi2-2cs { ++ bcm2835; ++ bcm2711; ++ bcm2712 = "spi2-2cs-pi5"; ++ }; ++ ++ spi2-2cs-pi5 { ++ bcm2712; ++ }; ++ + spi3-1cs { + bcm2711; ++ bcm2712 = "spi3-1cs-pi5"; ++ }; ++ ++ spi3-1cs-pi5 { ++ bcm2712; + }; + + spi3-2cs { + bcm2711; ++ bcm2712 = "spi3-2cs-pi5"; ++ }; ++ ++ spi3-2cs-pi5 { ++ bcm2712; + }; + + spi4-1cs { @@ -26333,10 +39457,20 @@ index 000000000000..0e01f46d8db0 + + spi5-1cs { + bcm2711; ++ bcm2712 = "spi5-1cs-pi5"; ++ }; ++ ++ spi5-1cs-pi5 { ++ bcm2712; + }; + + spi5-2cs { + bcm2711; ++ bcm2712 = "spi5-2cs-pi5"; ++ }; ++ ++ spi5-2cs-pi5 { ++ bcm2712; + }; + + spi6-1cs { @@ -26347,16 +39481,51 @@ index 000000000000..0e01f46d8db0 + bcm2711; + }; + ++ uart0 { ++ bcm2835; ++ bcm2711; ++ bcm2712 = "uart0-pi5"; ++ }; ++ ++ uart0-pi5 { ++ bcm2712; ++ }; ++ ++ uart1 { ++ bcm2835; ++ bcm2711; ++ bcm2712 = "uart1-pi5"; ++ }; ++ ++ uart1-pi5 { ++ bcm2712; ++ }; ++ + uart2 { + bcm2711; ++ bcm2712 = "uart2-pi5"; ++ }; ++ ++ uart2-pi5 { ++ bcm2712; + }; + + uart3 { + bcm2711; ++ bcm2712 = "uart3-pi5"; ++ }; ++ ++ uart3-pi5 { ++ bcm2712; + }; + + uart4 { + bcm2711; ++ bcm2712 = "uart4-pi5"; ++ }; ++ ++ uart4-pi5 { ++ bcm2712; + }; + + uart5 { @@ -26379,10 +39548,12 @@ index 000000000000..0e01f46d8db0 + vc4-fkms-v3d { + bcm2835; + bcm2711 = "vc4-fkms-v3d-pi4"; ++ bcm2712 = "vc4-fkms-v3d-pi4"; + }; + + vc4-fkms-v3d-pi4 { + bcm2711; ++ bcm2712; + }; + + vc4-kms-dpi-at056tn53v1 { @@ -26392,18 +39563,49 @@ index 000000000000..0e01f46d8db0 + vc4-kms-v3d { + bcm2835; + bcm2711 = "vc4-kms-v3d-pi4"; ++ bcm2712 = "vc4-kms-v3d-pi5"; + }; + + vc4-kms-v3d-pi4 { + bcm2711; ++ bcm2712 = "vc4-kms-v3d-pi5"; + }; ++ ++ vc4-kms-v3d-pi5 { ++ bcm2712; ++ }; ++ ++ vl805 { ++ bcm2711; ++ }; ++ ++ w1-gpio { ++ bcm2835; ++ bcm2711; ++ bcm2712 = "w1-gpio-pi5"; ++ }; ++ ++ w1-gpio-pi5 { ++ bcm2712; ++ }; ++ ++ w1-gpio-pullup { ++ bcm2835; ++ bcm2711; ++ bcm2712 = "w1-gpio-pullup-pi5"; ++ }; ++ ++ w1-gpio-pullup-pi5 { ++ bcm2712; ++ }; ++ +}; diff --git a/arch/arm/boot/dts/overlays/papirus-overlay.dts b/arch/arm/boot/dts/overlays/papirus-overlay.dts new file mode 100644 -index 000000000000..7b6bcfd49c86 +index 000000000000..67052b53a59c --- /dev/null +++ b/arch/arm/boot/dts/overlays/papirus-overlay.dts -@@ -0,0 +1,89 @@ +@@ -0,0 +1,84 @@ +/* PaPiRus ePaper Screen by Pi Supply */ + +/dts-v1/; @@ -26420,7 +39622,7 @@ index 000000000000..7b6bcfd49c86 + status = "okay"; + + display_temp: lm75@48 { -+ compatible = "lm75b"; ++ compatible = "national,lm75b"; + reg = <0x48>; + status = "okay"; + #thermal-sensor-cells = <0>; @@ -26429,26 +39631,20 @@ index 000000000000..7b6bcfd49c86 + }; + + fragment@1 { -+ target-path = "/"; ++ target-path = "/thermal-zones"; + __overlay__ { -+ thermal-zones { -+ display { -+ polling-delay-passive = <0>; -+ polling-delay = <0>; -+ thermal-sensors = <&display_temp>; -+ }; ++ display { ++ polling-delay-passive = <0>; ++ polling-delay = <0>; ++ thermal-sensors = <&display_temp>; + }; + }; + }; + + fragment@2 { -+ target = <&spi0>; ++ target = <&spidev0>; + __overlay__ { -+ status = "okay"; -+ -+ spidev@0{ -+ status = "disabled"; -+ }; ++ status = "disabled"; + }; + }; + @@ -26468,6 +39664,7 @@ index 000000000000..7b6bcfd49c86 + /* needed to avoid dtc warning */ + #address-cells = <1>; + #size-cells = <0>; ++ status = "okay"; + + repaper: repaper@0{ + compatible = "not_set"; @@ -26495,7 +39692,7 @@ index 000000000000..7b6bcfd49c86 +}; diff --git a/arch/arm/boot/dts/overlays/pca953x-overlay.dts b/arch/arm/boot/dts/overlays/pca953x-overlay.dts new file mode 100644 -index 000000000000..8b6ee44665ce +index 000000000000..ab414e92e366 --- /dev/null +++ b/arch/arm/boot/dts/overlays/pca953x-overlay.dts @@ -0,0 +1,240 @@ @@ -26611,19 +39808,19 @@ index 000000000000..8b6ee44665ce + fragment@15 { + target = <&pca>; + __dormant__ { -+ compatible = "nxp,pca16416"; ++ compatible = "nxp,pcal6416"; + }; + }; + fragment@16 { + target = <&pca>; + __dormant__ { -+ compatible = "nxp,pca16524"; ++ compatible = "nxp,pcal6524"; + }; + }; + fragment@17 { + target = <&pca>; + __dormant__ { -+ compatible = "nxp,pca19555a"; ++ compatible = "nxp,pcal9555a"; + }; + }; + fragment@18 { @@ -26721,9 +39918,9 @@ index 000000000000..8b6ee44665ce + pca9574 = <0>, "+12"; + pca9575 = <0>, "+13"; + pca9698 = <0>, "+14"; -+ pca16416 = <0>, "+15"; -+ pca16524 = <0>, "+16"; -+ pca19555a = <0>, "+17"; ++ pcal6416 = <0>, "+15"; ++ pcal6524 = <0>, "+16"; ++ pcal9555a = <0>, "+17"; + max7310 = <0>, "+18"; + max7312 = <0>, "+19"; + max7313 = <0>, "+20"; @@ -26739,6 +39936,44 @@ index 000000000000..8b6ee44665ce + xra1202 = <0>, "+30"; + }; +}; +diff --git a/arch/arm/boot/dts/overlays/pcf857x-overlay.dts b/arch/arm/boot/dts/overlays/pcf857x-overlay.dts +new file mode 100644 +index 000000000000..68943e1c3320 +--- /dev/null ++++ b/arch/arm/boot/dts/overlays/pcf857x-overlay.dts +@@ -0,0 +1,32 @@ ++// Definitions for PCF857X GPIO Extender from NXP ++ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "brcm,bcm2835"; ++ ++ fragment@0 { ++ target = <&i2c_arm>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ pcf857x: pcf857x@0 { ++ compatible = ""; ++ reg = <0x00>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ status = "okay"; ++ }; ++ }; ++ }; ++ ++ __overrides__ { ++ pcf8574 = <&pcf857x>,"compatible=nxp,pcf8574", <&pcf857x>,"reg:0=0x20"; ++ pcf8574a = <&pcf857x>,"compatible=nxp,pcf8574a", <&pcf857x>,"reg:0=0x38"; ++ pcf8575 = <&pcf857x>,"compatible=nxp,pcf8575", <&pcf857x>,"reg:0=0x20"; ++ pca8574 = <&pcf857x>,"compatible=nxp,pca8574", <&pcf857x>,"reg:0=0x20"; ++ addr = <&pcf857x>,"reg:0"; ++ }; ++}; diff --git a/arch/arm/boot/dts/overlays/pcie-32bit-dma-overlay.dts b/arch/arm/boot/dts/overlays/pcie-32bit-dma-overlay.dts new file mode 100644 index 000000000000..955703563df7 @@ -26783,9 +40018,41 @@ index 000000000000..955703563df7 + }; + +}; +diff --git a/arch/arm/boot/dts/overlays/pcie-32bit-dma-pi5-overlay.dts b/arch/arm/boot/dts/overlays/pcie-32bit-dma-pi5-overlay.dts +new file mode 100644 +index 000000000000..f9908494f101 +--- /dev/null ++++ b/arch/arm/boot/dts/overlays/pcie-32bit-dma-pi5-overlay.dts +@@ -0,0 +1,26 @@ ++/* ++ * pcie-32bit-dma-pi5-overlay.dts ++ */ ++ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "brcm,bcm2712"; ++ ++ fragment@0 { ++ target = <&pcie1>; ++ __overlay__ { ++ /* ++ * The size of the range is rounded up to a power of 2, ++ * so the range ends up being 0-4GB, and the MSI vector ++ * gets pushed beyond 4GB. ++ */ ++ #address-cells = <3>; ++ #size-cells = <2>; ++ dma-ranges = <0x02000000 0x0 0x00000000 0x0 0x00000000 ++ 0x0 0x80000000>; ++ }; ++ }; ++ ++}; diff --git a/arch/arm/boot/dts/overlays/pibell-overlay.dts b/arch/arm/boot/dts/overlays/pibell-overlay.dts new file mode 100644 -index 000000000000..9333a9b09772 +index 000000000000..99d4b6d97969 --- /dev/null +++ b/arch/arm/boot/dts/overlays/pibell-overlay.dts @@ -0,0 +1,81 @@ @@ -26815,7 +40082,7 @@ index 000000000000..9333a9b09772 + }; + + fragment@1 { -+ target = <&i2s>; ++ target = <&i2s_clk_producer>; + __overlay__ { + #sound-dai-cells = <0>; + status = "okay"; @@ -26834,7 +40101,7 @@ index 000000000000..9333a9b09772 + format = "i2s"; + + r_cpu_dai: cpu { -+ sound-dai = <&i2s>; ++ sound-dai = <&i2s_clk_producer>; + +/* example TDM slot configuration + dai-tdm-slot-num = <2>; @@ -26851,7 +40118,7 @@ index 000000000000..9333a9b09772 + format = "i2s"; + + p_cpu_dai: cpu { -+ sound-dai = <&i2s>; ++ sound-dai = <&i2s_clk_producer>; + +/* example TDM slot configuration + dai-tdm-slot-num = <2>; @@ -27022,7 +40289,7 @@ index 000000000000..532a858683d6 +}; diff --git a/arch/arm/boot/dts/overlays/pifi-40-overlay.dts b/arch/arm/boot/dts/overlays/pifi-40-overlay.dts new file mode 100644 -index 000000000000..51a20e54977f +index 000000000000..d9ef4ea4097e --- /dev/null +++ b/arch/arm/boot/dts/overlays/pifi-40-overlay.dts @@ -0,0 +1,50 @@ @@ -27034,7 +40301,7 @@ index 000000000000..51a20e54977f + compatible = "brcm,bcm2835"; + + fragment@0 { -+ target = <&i2s>; ++ target = <&i2s_clk_producer>; + __overlay__ { + status = "okay"; + }; @@ -27070,7 +40337,7 @@ index 000000000000..51a20e54977f + pifi_40: __overlay__ { + compatible = "pifi,pifi-40"; + audio-codec = <&tas5711l &tas5711r>; -+ i2s-controller = <&i2s>; ++ i2s-controller = <&i2s_clk_producer>; + pdn-gpios = <&gpio 23 1>; + status = "okay"; + }; @@ -27078,7 +40345,7 @@ index 000000000000..51a20e54977f +}; diff --git a/arch/arm/boot/dts/overlays/pifi-dac-hd-overlay.dts b/arch/arm/boot/dts/overlays/pifi-dac-hd-overlay.dts new file mode 100644 -index 000000000000..67f50db7861a +index 000000000000..236098365dc2 --- /dev/null +++ b/arch/arm/boot/dts/overlays/pifi-dac-hd-overlay.dts @@ -0,0 +1,49 @@ @@ -27090,7 +40357,7 @@ index 000000000000..67f50db7861a + compatible = "brcm,bcm2835"; + + fragment@0 { -+ target = <&i2s>; ++ target = <&i2s_clk_producer>; + __overlay__ { + status = "okay"; + }; @@ -27122,7 +40389,7 @@ index 000000000000..67f50db7861a + simple-audio-card,dai-link@1 { + format = "i2s"; + cpu { -+ sound-dai = <&i2s>; ++ sound-dai = <&i2s_clk_producer>; + }; + codec { + sound-dai = <&pcm5142>; @@ -27133,7 +40400,7 @@ index 000000000000..67f50db7861a +}; diff --git a/arch/arm/boot/dts/overlays/pifi-dac-zero-overlay.dts b/arch/arm/boot/dts/overlays/pifi-dac-zero-overlay.dts new file mode 100644 -index 000000000000..645ea74cb435 +index 000000000000..dd272388779e --- /dev/null +++ b/arch/arm/boot/dts/overlays/pifi-dac-zero-overlay.dts @@ -0,0 +1,49 @@ @@ -27155,7 +40422,7 @@ index 000000000000..645ea74cb435 + format = "i2s"; + + cpu { -+ sound-dai = <&i2s>; ++ sound-dai = <&i2s_clk_producer>; + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <32>; + }; @@ -27179,7 +40446,7 @@ index 000000000000..645ea74cb435 + }; + + fragment@2 { -+ target = <&i2s>; ++ target = <&i2s_clk_producer>; + __overlay__ { + #sound-dai-cells = <0>; + status = "okay"; @@ -27188,7 +40455,7 @@ index 000000000000..645ea74cb435 +}; diff --git a/arch/arm/boot/dts/overlays/pifi-mini-210-overlay.dts b/arch/arm/boot/dts/overlays/pifi-mini-210-overlay.dts new file mode 100644 -index 000000000000..963597d611b5 +index 000000000000..a7b857144a48 --- /dev/null +++ b/arch/arm/boot/dts/overlays/pifi-mini-210-overlay.dts @@ -0,0 +1,42 @@ @@ -27200,7 +40467,7 @@ index 000000000000..963597d611b5 + compatible = "brcm,bcm2835"; + + fragment@0 { -+ target = <&i2s>; ++ target = <&i2s_clk_producer>; + __overlay__ { + status = "okay"; + }; @@ -27228,7 +40495,7 @@ index 000000000000..963597d611b5 + target = <&sound>; + __overlay__ { + compatible = "pifi,pifi-mini-210"; -+ i2s-controller = <&i2s>; ++ i2s-controller = <&i2s_clk_producer>; + + status = "okay"; + }; @@ -27339,10 +40606,10 @@ index 000000000000..075bceef158c +}; diff --git a/arch/arm/boot/dts/overlays/piscreen-overlay.dts b/arch/arm/boot/dts/overlays/piscreen-overlay.dts new file mode 100644 -index 000000000000..1ac75a248fab +index 000000000000..29bcd41f39cf --- /dev/null +++ b/arch/arm/boot/dts/overlays/piscreen-overlay.dts -@@ -0,0 +1,102 @@ +@@ -0,0 +1,107 @@ +/* + * Device Tree overlay for PiScreen 3.5" display shield by Ozzmaker + * @@ -27351,6 +40618,8 @@ index 000000000000..1ac75a248fab +/dts-v1/; +/plugin/; + ++#include ++ +/ { + compatible = "brcm,bcm2835"; + @@ -27404,9 +40673,9 @@ index 000000000000..1ac75a248fab + fps = <30>; + buswidth = <8>; + regwidth = <16>; -+ reset-gpios = <&gpio 25 1>; -+ dc-gpios = <&gpio 24 0>; -+ led-gpios = <&gpio 22 0>; ++ reset-gpios = <&gpio 25 GPIO_ACTIVE_LOW>; ++ dc-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>; ++ led-gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; + debug = <0>; + + init = <0x10000b0 0x00 @@ -27430,7 +40699,7 @@ index 000000000000..1ac75a248fab + spi-max-frequency = <2000000>; + interrupts = <17 2>; /* high-to-low edge triggered */ + interrupt-parent = <&gpio>; -+ pendown-gpio = <&gpio 17 0>; ++ pendown-gpio = <&gpio 17 GPIO_ACTIVE_LOW>; + ti,swap-xy; + ti,x-plate-ohms = /bits/ 16 <100>; + ti,pressure-max = /bits/ 16 <255>; @@ -27439,15 +40708,18 @@ index 000000000000..1ac75a248fab + }; + __overrides__ { + speed = <&piscreen>,"spi-max-frequency:0"; -+ rotate = <&piscreen>,"rotate:0"; ++ rotate = <&piscreen>,"rotate:0", ++ <&piscreen>,"rotation:0"; + fps = <&piscreen>,"fps:0"; + debug = <&piscreen>,"debug:0"; + xohms = <&piscreen_ts>,"ti,x-plate-ohms;0"; ++ drm = <&piscreen>,"compatible=waveshare,rpi-lcd-35", ++ <&piscreen>,"reset-gpios:8=",; + }; +}; diff --git a/arch/arm/boot/dts/overlays/piscreen2r-overlay.dts b/arch/arm/boot/dts/overlays/piscreen2r-overlay.dts new file mode 100644 -index 000000000000..9d2b51101969 +index 000000000000..4468f4a54bf7 --- /dev/null +++ b/arch/arm/boot/dts/overlays/piscreen2r-overlay.dts @@ -0,0 +1,106 @@ @@ -27541,7 +40813,7 @@ index 000000000000..9d2b51101969 + spi-max-frequency = <2000000>; + interrupts = <17 2>; /* high-to-low edge triggered */ + interrupt-parent = <&gpio>; -+ pendown-gpio = <&gpio 17 0>; ++ pendown-gpio = <&gpio 17 1>; + ti,swap-xy; + ti,x-plate-ohms = /bits/ 16 <100>; + ti,pressure-max = /bits/ 16 <255>; @@ -27559,13 +40831,13 @@ index 000000000000..9d2b51101969 + diff --git a/arch/arm/boot/dts/overlays/pisound-overlay.dts b/arch/arm/boot/dts/overlays/pisound-overlay.dts new file mode 100644 -index 000000000000..49efb2b768fb +index 000000000000..226bcbdf8a09 --- /dev/null +++ b/arch/arm/boot/dts/overlays/pisound-overlay.dts -@@ -0,0 +1,120 @@ +@@ -0,0 +1,118 @@ +/* + * Pisound Linux kernel module. -+ * Copyright (C) 2016-2017 Vilniaus Blokas UAB, https://blokas.io/pisound ++ * Copyright (C) 2016-2024 Vilniaus Blokas UAB, https://blokas.io/pisound + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License @@ -27620,9 +40892,8 @@ index 000000000000..49efb2b768fb + pisound_spi: pisound_spi@0{ + compatible = "blokaslabs,pisound-spi"; + reg = <0>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&spi0_pins>; + spi-max-frequency = <1000000>; ++ spi-speed-hz = <150000>; + }; + }; + }; @@ -27642,9 +40913,11 @@ index 000000000000..49efb2b768fb + target = <&sound>; + __overlay__ { + compatible = "blokaslabs,pisound"; -+ i2s-controller = <&i2s>; ++ i2s-controller = <&i2s_clk_consumer>; ++ spi-controller = <&pisound_spi>; + status = "okay"; + ++ pinctrl-names = "default"; + pinctrl-0 = <&pisound_button_pins>; + + osr-gpios = @@ -27665,9 +40938,6 @@ index 000000000000..49efb2b768fb + fragment@6 { + target = <&gpio>; + __overlay__ { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pisound_button_pins>; -+ + pisound_button_pins: pisound_button_pins { + brcm,pins = <17>; + brcm,function = <0>; // Input @@ -27677,18 +40947,55 @@ index 000000000000..49efb2b768fb + }; + + fragment@7 { -+ target = <&i2s>; ++ target = <&i2s_clk_consumer>; + __overlay__ { + status = "okay"; + }; + }; +}; +diff --git a/arch/arm/boot/dts/overlays/pisound-pi5-overlay.dts b/arch/arm/boot/dts/overlays/pisound-pi5-overlay.dts +new file mode 100644 +index 000000000000..a54974c446a0 +--- /dev/null ++++ b/arch/arm/boot/dts/overlays/pisound-pi5-overlay.dts +@@ -0,0 +1,31 @@ ++/* ++ * Pisound Linux kernel module. ++ * Copyright (C) 2016-2024 Vilniaus Blokas UAB, https://blokas.io/pisound ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * as published by the Free Software Foundation; version 2 of the ++ * License. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. ++ */ ++ ++/dts-v1/; ++/plugin/; ++ ++#include "pisound-overlay.dts" ++ ++&pisound_spi { ++ spi-speed-hz = <100000>; ++}; ++ ++/ { ++ compatible = "brcm,bcm2712"; ++}; diff --git a/arch/arm/boot/dts/overlays/pitft22-overlay.dts b/arch/arm/boot/dts/overlays/pitft22-overlay.dts new file mode 100644 -index 000000000000..589ad13795b1 +index 000000000000..5759d48aed57 --- /dev/null +++ b/arch/arm/boot/dts/overlays/pitft22-overlay.dts -@@ -0,0 +1,69 @@ +@@ -0,0 +1,71 @@ +/* + * Device Tree overlay for pitft by Adafruit + * @@ -27698,72 +41005,74 @@ index 000000000000..589ad13795b1 +/plugin/; + +/ { -+ compatible = "brcm,bcm2835"; ++ compatible = "brcm,bcm2835"; + -+ fragment@0 { -+ target = <&spi0>; -+ __overlay__ { -+ status = "okay"; -+ -+ spidev@0{ -+ status = "disabled"; -+ }; -+ -+ spidev@1{ -+ status = "disabled"; -+ }; -+ }; ++ fragment@0 { ++ target = <&spidev0>; ++ __overlay__ { ++ status = "disabled"; ++ }; + }; + -+ fragment@1 { -+ target = <&gpio>; -+ __overlay__ { -+ pitft_pins: pitft_pins { -+ brcm,pins = <25>; -+ brcm,function = <1>; /* out */ -+ brcm,pull = <0>; /* none */ -+ }; -+ }; -+ }; ++ fragment@1 { ++ target = <&spidev1>; ++ __overlay__ { ++ status = "disabled"; ++ }; ++ }; + -+ fragment@2 { -+ target = <&spi0>; -+ __overlay__ { -+ /* needed to avoid dtc warning */ -+ #address-cells = <1>; -+ #size-cells = <0>; ++ fragment@2 { ++ target = <&gpio>; ++ __overlay__ { ++ pitft_pins: pitft_pins { ++ brcm,pins = <25>; ++ brcm,function = <1>; /* out */ ++ brcm,pull = <0>; /* none */ ++ }; ++ }; ++ }; + -+ pitft: pitft@0{ -+ compatible = "ilitek,ili9340"; -+ reg = <0>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pitft_pins>; ++ fragment@3 { ++ target = <&spi0>; ++ __overlay__ { ++ /* needed to avoid dtc warning */ ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "okay"; + -+ spi-max-frequency = <32000000>; -+ rotate = <90>; -+ fps = <25>; -+ bgr; -+ buswidth = <8>; -+ dc-gpios = <&gpio 25 0>; -+ debug = <0>; -+ }; ++ pitft: pitft@0{ ++ compatible = "ilitek,ili9340"; ++ reg = <0>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pitft_pins>; + -+ }; -+ }; ++ spi-max-frequency = <32000000>; ++ rotate = <90>; ++ fps = <25>; ++ bgr; ++ buswidth = <8>; ++ dc-gpios = <&gpio 25 0>; ++ debug = <0>; ++ }; + -+ __overrides__ { -+ speed = <&pitft>,"spi-max-frequency:0"; -+ rotate = <&pitft>,"rotate:0"; -+ fps = <&pitft>,"fps:0"; -+ debug = <&pitft>,"debug:0"; -+ }; ++ }; ++ }; ++ ++ __overrides__ { ++ speed = <&pitft>,"spi-max-frequency:0"; ++ rotate = <&pitft>,"rotate:0", /* fbtft */ ++ <&pitft>,"rotation:0"; /* drm */ ++ fps = <&pitft>,"fps:0"; ++ debug = <&pitft>,"debug:0"; ++ drm = <&pitft>,"compatible=adafruit,yx240qv29"; ++ }; +}; diff --git a/arch/arm/boot/dts/overlays/pitft28-capacitive-overlay.dts b/arch/arm/boot/dts/overlays/pitft28-capacitive-overlay.dts new file mode 100644 -index 000000000000..33901ee1db7a +index 000000000000..de98ee7b4496 --- /dev/null +++ b/arch/arm/boot/dts/overlays/pitft28-capacitive-overlay.dts -@@ -0,0 +1,91 @@ +@@ -0,0 +1,93 @@ +/* + * Device Tree overlay for Adafruit PiTFT 2.8" capacitive touch screen + * @@ -27773,14 +41082,14 @@ index 000000000000..33901ee1db7a +/plugin/; + +/ { -+ compatible = "brcm,bcm2835"; ++ compatible = "brcm,bcm2835"; + -+ fragment@0 { -+ target = <&spi0>; -+ __overlay__ { -+ status = "okay"; -+ }; -+ }; ++ fragment@0 { ++ target = <&spi0>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; + + fragment@1 { + target = <&spidev0>; @@ -27789,78 +41098,80 @@ index 000000000000..33901ee1db7a + }; + }; + -+ fragment@2 { -+ target = <&gpio>; -+ __overlay__ { -+ pitft_pins: pitft_pins { -+ brcm,pins = <24 25>; -+ brcm,function = <0 1>; /* in out */ -+ brcm,pull = <2 0>; /* pullup none */ -+ }; -+ }; -+ }; ++ fragment@2 { ++ target = <&gpio>; ++ __overlay__ { ++ pitft_pins: pitft_pins { ++ brcm,pins = <24 25>; ++ brcm,function = <0 1>; /* in out */ ++ brcm,pull = <2 0>; /* pullup none */ ++ }; ++ }; ++ }; + -+ fragment@3 { -+ target = <&spi0>; -+ __overlay__ { -+ /* needed to avoid dtc warning */ -+ #address-cells = <1>; -+ #size-cells = <0>; ++ fragment@3 { ++ target = <&spi0>; ++ __overlay__ { ++ /* needed to avoid dtc warning */ ++ #address-cells = <1>; ++ #size-cells = <0>; + -+ pitft: pitft@0{ -+ compatible = "ilitek,ili9340"; -+ reg = <0>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pitft_pins>; ++ pitft: pitft@0{ ++ compatible = "ilitek,ili9340"; ++ reg = <0>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pitft_pins>; + -+ spi-max-frequency = <32000000>; -+ rotate = <90>; -+ fps = <25>; -+ bgr; -+ buswidth = <8>; -+ dc-gpios = <&gpio 25 0>; -+ debug = <0>; -+ }; -+ }; -+ }; ++ spi-max-frequency = <32000000>; ++ rotate = <90>; ++ fps = <25>; ++ bgr; ++ buswidth = <8>; ++ dc-gpios = <&gpio 25 0>; ++ debug = <0>; ++ }; ++ }; ++ }; + -+ fragment@4 { -+ target = <&i2c1>; -+ __overlay__ { -+ /* needed to avoid dtc warning */ -+ #address-cells = <1>; -+ #size-cells = <0>; ++ fragment@4 { ++ target = <&i2c1>; ++ __overlay__ { ++ /* needed to avoid dtc warning */ ++ #address-cells = <1>; ++ #size-cells = <0>; + -+ ft6236: ft6236@38 { -+ compatible = "focaltech,ft6236"; -+ reg = <0x38>; ++ ft6236: ft6236@38 { ++ compatible = "focaltech,ft6236"; ++ reg = <0x38>; + -+ interrupt-parent = <&gpio>; -+ interrupts = <24 2>; -+ touchscreen-size-x = <240>; -+ touchscreen-size-y = <320>; -+ }; -+ }; -+ }; ++ interrupt-parent = <&gpio>; ++ interrupts = <24 2>; ++ touchscreen-size-x = <240>; ++ touchscreen-size-y = <320>; ++ }; ++ }; ++ }; + -+ __overrides__ { -+ speed = <&pitft>,"spi-max-frequency:0"; -+ rotate = <&pitft>,"rotate:0"; -+ fps = <&pitft>,"fps:0"; -+ debug = <&pitft>,"debug:0"; -+ touch-sizex = <&ft6236>,"touchscreen-size-x?"; -+ touch-sizey = <&ft6236>,"touchscreen-size-y?"; -+ touch-invx = <&ft6236>,"touchscreen-inverted-x?"; -+ touch-invy = <&ft6236>,"touchscreen-inverted-y?"; -+ touch-swapxy = <&ft6236>,"touchscreen-swapped-x-y?"; -+ }; ++ __overrides__ { ++ speed = <&pitft>,"spi-max-frequency:0"; ++ rotate = <&pitft>,"rotate:0", /* fbtft */ ++ <&pitft>,"rotation:0"; /* drm */ ++ fps = <&pitft>,"fps:0"; ++ debug = <&pitft>,"debug:0"; ++ drm = <&pitft>,"compatible=adafruit,yx240qv29"; ++ touch-sizex = <&ft6236>,"touchscreen-size-x:0"; ++ touch-sizey = <&ft6236>,"touchscreen-size-y:0"; ++ touch-invx = <&ft6236>,"touchscreen-inverted-x?"; ++ touch-invy = <&ft6236>,"touchscreen-inverted-y?"; ++ touch-swapxy = <&ft6236>,"touchscreen-swapped-x-y?"; ++ }; +}; diff --git a/arch/arm/boot/dts/overlays/pitft28-resistive-overlay.dts b/arch/arm/boot/dts/overlays/pitft28-resistive-overlay.dts new file mode 100644 -index 000000000000..4a4a3f44c29d +index 000000000000..bc2597179b9c --- /dev/null +++ b/arch/arm/boot/dts/overlays/pitft28-resistive-overlay.dts -@@ -0,0 +1,119 @@ +@@ -0,0 +1,126 @@ +/* + * Device Tree overlay for Adafruit PiTFT 2.8" resistive touch screen + * @@ -27927,16 +41238,18 @@ index 000000000000..4a4a3f44c29d + }; + + pitft_ts@1 { ++ /* needed to avoid dtc warning */ ++ #address-cells = <1>; ++ #interrupt-cells = <1>; + compatible = "st,stmpe610"; + reg = <1>; + + spi-max-frequency = <500000>; -+ irq-gpio = <&gpio 24 0x2>; /* IRQF_TRIGGER_FALLING */ + interrupts = <24 2>; /* high-to-low edge triggered */ + interrupt-parent = <&gpio>; + interrupt-controller; + -+ stmpe_touchscreen { ++ stmpe_touchscreen: stmpe_touchscreen { + compatible = "st,stmpe-ts"; + st,sample-time = <4>; + st,mod-12b = <1>; @@ -27975,17 +41288,22 @@ index 000000000000..4a4a3f44c29d + + __overrides__ { + speed = <&pitft>,"spi-max-frequency:0"; -+ rotate = <&pitft>,"rotate:0"; ++ rotate = <&pitft>,"rotate:0", /* fbtft */ ++ <&pitft>,"rotation:0"; /* drm */ + fps = <&pitft>,"fps:0"; + debug = <&pitft>,"debug:0"; ++ drm = <&pitft>,"compatible=adafruit,yx240qv29"; ++ touch-invx = <&stmpe_touchscreen>,"touchscreen-inverted-x?"; ++ touch-invy = <&stmpe_touchscreen>,"touchscreen-inverted-y?"; ++ touch-swapxy = <&stmpe_touchscreen>,"touchscreen-swapped-x-y?"; + }; +}; diff --git a/arch/arm/boot/dts/overlays/pitft35-resistive-overlay.dts b/arch/arm/boot/dts/overlays/pitft35-resistive-overlay.dts new file mode 100644 -index 000000000000..37629f18a740 +index 000000000000..c3e81ef6003a --- /dev/null +++ b/arch/arm/boot/dts/overlays/pitft35-resistive-overlay.dts -@@ -0,0 +1,119 @@ +@@ -0,0 +1,127 @@ +/* + * Device Tree overlay for Adafruit PiTFT 3.5" resistive touch screen + * @@ -28037,7 +41355,7 @@ index 000000000000..37629f18a740 + #size-cells = <0>; + + pitft: pitft@0{ -+ compatible = "himax,hx8357d", "adafruit,yx350hv15"; ++ compatible = "himax,hx8357d"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pitft_pins>; @@ -28052,16 +41370,18 @@ index 000000000000..37629f18a740 + }; + + pitft_ts@1 { ++ /* needed to avoid dtc warning */ ++ #address-cells = <1>; ++ #interrupt-cells = <1>; + compatible = "st,stmpe610"; + reg = <1>; + + spi-max-frequency = <500000>; -+ irq-gpio = <&gpio 24 0x2>; /* IRQF_TRIGGER_FALLING */ + interrupts = <24 2>; /* high-to-low edge triggered */ + interrupt-parent = <&gpio>; + interrupt-controller; + -+ stmpe_touchscreen { ++ stmpe_touchscreen: stmpe_touchscreen { + compatible = "st,stmpe-ts"; + st,sample-time = <4>; + st,mod-12b = <1>; @@ -28090,7 +41410,7 @@ index 000000000000..37629f18a740 + fragment@5 { + target-path = "/soc"; + __overlay__ { -+ backlight { ++ backlight: backlight { + compatible = "gpio-backlight"; + gpios = <&stmpe_gpio 2 0>; + default-on; @@ -28100,17 +41420,23 @@ index 000000000000..37629f18a740 + + __overrides__ { + speed = <&pitft>,"spi-max-frequency:0"; -+ rotate = <&pitft>,"rotate:0"; ++ rotate = <&pitft>,"rotate:0", /* fbtft */ ++ <&pitft>,"rotation:0"; /* drm */ + fps = <&pitft>,"fps:0"; + debug = <&pitft>,"debug:0"; ++ drm = <&pitft>,"compatible=adafruit,yx350hv15", ++ <&pitft>,"backlight:0=",<&backlight>; ++ touch-invx = <&stmpe_touchscreen>,"touchscreen-inverted-x?"; ++ touch-invy = <&stmpe_touchscreen>,"touchscreen-inverted-y?"; ++ touch-swapxy = <&stmpe_touchscreen>,"touchscreen-swapped-x-y?"; + }; +}; diff --git a/arch/arm/boot/dts/overlays/pps-gpio-overlay.dts b/arch/arm/boot/dts/overlays/pps-gpio-overlay.dts new file mode 100644 -index 000000000000..524a1c1d3670 +index 000000000000..a4f6b868aad8 --- /dev/null +++ b/arch/arm/boot/dts/overlays/pps-gpio-overlay.dts -@@ -0,0 +1,38 @@ +@@ -0,0 +1,39 @@ +/dts-v1/; +/plugin/; + @@ -28147,14 +41473,60 @@ index 000000000000..524a1c1d3670 + <&pps_pins>,"reg:0"; + assert_falling_edge = <&pps>,"assert-falling-edge?"; + capture_clear = <&pps>,"capture-clear?"; ++ pull = <&pps_pins>,"brcm,pull:0"; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlays/proto-codec-overlay.dts b/arch/arm/boot/dts/overlays/proto-codec-overlay.dts +new file mode 100644 +index 000000000000..92f6ed158923 +--- /dev/null ++++ b/arch/arm/boot/dts/overlays/proto-codec-overlay.dts +@@ -0,0 +1,39 @@ ++// Definitions for Rpi-Proto ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "brcm,bcm2835"; ++ ++ fragment@0 { ++ target = <&i2s_clk_consumer>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&i2c1>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "okay"; ++ ++ wm8731@1a { ++ #sound-dai-cells = <0>; ++ compatible = "wlf,wm8731"; ++ reg = <0x1a>; ++ status = "okay"; ++ }; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&sound>; ++ __overlay__ { ++ compatible = "rpi,rpi-proto"; ++ i2s-controller = <&i2s_clk_consumer>; ++ status = "okay"; ++ }; + }; +}; diff --git a/arch/arm/boot/dts/overlays/pwm-2chan-overlay.dts b/arch/arm/boot/dts/overlays/pwm-2chan-overlay.dts new file mode 100644 -index 000000000000..4ddbbfa04065 +index 000000000000..823c8b4126d1 --- /dev/null +++ b/arch/arm/boot/dts/overlays/pwm-2chan-overlay.dts -@@ -0,0 +1,49 @@ +@@ -0,0 +1,48 @@ +/dts-v1/; +/plugin/; + @@ -28191,7 +41563,6 @@ index 000000000000..4ddbbfa04065 + frag1: __overlay__ { + pinctrl-names = "default"; + pinctrl-0 = <&pwm_pins>; -+ assigned-clock-rates = <100000000>; + status = "okay"; + }; + }; @@ -28206,7 +41577,7 @@ index 000000000000..4ddbbfa04065 +}; diff --git a/arch/arm/boot/dts/overlays/pwm-ir-tx-overlay.dts b/arch/arm/boot/dts/overlays/pwm-ir-tx-overlay.dts new file mode 100644 -index 000000000000..119caf746b3b +index 000000000000..33597eb79729 --- /dev/null +++ b/arch/arm/boot/dts/overlays/pwm-ir-tx-overlay.dts @@ -0,0 +1,40 @@ @@ -28240,7 +41611,7 @@ index 000000000000..119caf746b3b + __overlay__ { + pwm-ir-transmitter { + compatible = "pwm-ir-tx"; -+ pwms = <&pwm 0 100>; ++ pwms = <&pwm 0 100 0>; + }; + }; + }; @@ -28252,10 +41623,10 @@ index 000000000000..119caf746b3b +}; diff --git a/arch/arm/boot/dts/overlays/pwm-overlay.dts b/arch/arm/boot/dts/overlays/pwm-overlay.dts new file mode 100644 -index 000000000000..92876ab3bc8c +index 000000000000..32853492aaea --- /dev/null +++ b/arch/arm/boot/dts/overlays/pwm-overlay.dts -@@ -0,0 +1,45 @@ +@@ -0,0 +1,44 @@ +/dts-v1/; +/plugin/; + @@ -28290,7 +41661,6 @@ index 000000000000..92876ab3bc8c + frag1: __overlay__ { + pinctrl-names = "default"; + pinctrl-0 = <&pwm_pins>; -+ assigned-clock-rates = <100000000>; + status = "okay"; + }; + }; @@ -28301,6 +41671,71 @@ index 000000000000..92876ab3bc8c + clock = <&frag1>,"assigned-clock-rates:0"; + }; +}; +diff --git a/arch/arm/boot/dts/overlays/pwm1-overlay.dts b/arch/arm/boot/dts/overlays/pwm1-overlay.dts +new file mode 100644 +index 000000000000..3324d4160653 +--- /dev/null ++++ b/arch/arm/boot/dts/overlays/pwm1-overlay.dts +@@ -0,0 +1,59 @@ ++/dts-v1/; ++/plugin/; ++ ++#include ++ ++/ { ++ compatible = "brcm,bcm2711"; ++ ++ fragment@0 { ++ target = <&pins>; ++ __overlay__ { ++ brcm,pins = <40 41>; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&pins>; ++ __dormant__ { ++ brcm,pins = <40>; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&pins>; ++ __dormant__ { ++ brcm,pins = <41>; ++ }; ++ }; ++ ++ fragment@3 { ++ target = <&gpio>; ++ __overlay__ { ++ pins: pwm1_overlay_pins { ++ brcm,pins = <40 41>; ++ brcm,function = ; ++ brcm,pull = ; ++ }; ++ }; ++ }; ++ ++ fragment@4 { ++ target = <&pwm1>; ++ pwm: __overlay__ { ++ status = "okay"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pins>; ++ }; ++ }; ++ ++ __overrides__ { ++ clock = <&pwm>, "assigned-clock-rates:0"; ++ pins_40_41 = <0>,"+0-1-2"; ++ pins_40 = <0>,"-0+1-2"; ++ pins_41 = <0>,"-0-1+2"; ++ pull_up = <&pins>, "brcm,pull:0=", ; ++ pull_down = <&pins>, "brcm,pull:0=", ; ++ pull_off = <&pins>, "brcm,pull:0=", ; ++ }; ++}; diff --git a/arch/arm/boot/dts/overlays/qca7000-overlay.dts b/arch/arm/boot/dts/overlays/qca7000-overlay.dts new file mode 100644 index 000000000000..f695f36024fa @@ -28364,7 +41799,7 @@ index 000000000000..f695f36024fa +}; diff --git a/arch/arm/boot/dts/overlays/qca7000-uart0-overlay.dts b/arch/arm/boot/dts/overlays/qca7000-uart0-overlay.dts new file mode 100644 -index 000000000000..5dee70853289 +index 000000000000..f103916c9e1c --- /dev/null +++ b/arch/arm/boot/dts/overlays/qca7000-uart0-overlay.dts @@ -0,0 +1,46 @@ @@ -28394,7 +41829,7 @@ index 000000000000..5dee70853289 + fragment@1 { + target = <&gpio>; + __overlay__ { -+ uart0_pins: uart0_pins { ++ uart0_pins: uart0_ovl_pins { + brcm,pins = <14 15>; + brcm,function = <4>; /* alt0 */ + brcm,pull = <0 2>; @@ -28414,6 +41849,68 @@ index 000000000000..5dee70853289 + baudrate = <ð2>, "current-speed:0"; + }; +}; +diff --git a/arch/arm/boot/dts/overlays/ramoops-overlay.dts b/arch/arm/boot/dts/overlays/ramoops-overlay.dts +new file mode 100644 +index 000000000000..e5038658138d +--- /dev/null ++++ b/arch/arm/boot/dts/overlays/ramoops-overlay.dts +@@ -0,0 +1,25 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "brcm,bcm2835"; ++ ++ fragment@0 { ++ target = <&rmem>; ++ __overlay__ { ++ ramoops: ramoops@b000000 { ++ compatible = "ramoops"; ++ reg = <0x0b000000 0x10000>; /* 64kB */ ++ record-size = <0x4000>; /* 16kB */ ++ console-size = <0>; /* disabled by default */ ++ }; ++ }; ++ }; ++ ++ __overrides__ { ++ base-addr = <&ramoops>,"reg:0"; ++ total-size = <&ramoops>,"reg:4"; ++ record-size = <&ramoops>,"record-size:0"; ++ console-size = <&ramoops>,"console-size:0"; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlays/ramoops-pi4-overlay.dts b/arch/arm/boot/dts/overlays/ramoops-pi4-overlay.dts +new file mode 100644 +index 000000000000..1737e37f5724 +--- /dev/null ++++ b/arch/arm/boot/dts/overlays/ramoops-pi4-overlay.dts +@@ -0,0 +1,25 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "brcm,bcm2711"; ++ ++ fragment@0 { ++ target = <&rmem>; ++ __overlay__ { ++ ramoops: ramoops@b000000 { ++ compatible = "ramoops"; ++ reg = <0x0 0x0b000000 0x10000>; /* 64kB */ ++ record-size = <0x4000>; /* 16kB */ ++ console-size = <0>; /* disabled by default */ ++ }; ++ }; ++ }; ++ ++ __overrides__ { ++ base-addr = <&ramoops>,"reg#0"; ++ total-size = <&ramoops>,"reg:8"; ++ record-size = <&ramoops>,"record-size:0"; ++ console-size = <&ramoops>,"console-size:0"; ++ }; ++}; diff --git a/arch/arm/boot/dts/overlays/rotary-encoder-overlay.dts b/arch/arm/boot/dts/overlays/rotary-encoder-overlay.dts new file mode 100644 index 000000000000..ea1d952734e9 @@ -28506,319 +42003,88 @@ index 000000000000..cac5e44c6ec5 + }; + }; +}; -diff --git a/arch/arm/boot/dts/overlays/rpi-cirrus-wm5102-overlay.dts b/arch/arm/boot/dts/overlays/rpi-cirrus-wm5102-overlay.dts +diff --git a/arch/arm/boot/dts/overlays/rpi-codeczero-overlay.dts b/arch/arm/boot/dts/overlays/rpi-codeczero-overlay.dts new file mode 100644 -index 000000000000..ed0c2745399f +index 000000000000..c3b0564b2fb2 --- /dev/null -+++ b/arch/arm/boot/dts/overlays/rpi-cirrus-wm5102-overlay.dts -@@ -0,0 +1,172 @@ -+// Definitions for the Cirrus Logic Audio Card -+/dts-v1/; -+/plugin/; -+#include -+#include -+#include ++++ b/arch/arm/boot/dts/overlays/rpi-codeczero-overlay.dts +@@ -0,0 +1,9 @@ ++// Overlay for the Raspberry Pi Codec Zero soundcard + -+/ { -+ compatible = "brcm,bcm2835"; ++#include "iqaudio-codec-overlay.dts" + -+ fragment@0 { -+ target = <&i2s>; -+ __overlay__ { -+ status = "okay"; -+ }; -+ }; -+ -+ fragment@1 { -+ target = <&gpio>; -+ __overlay__ { -+ wlf_5102_pins: wlf_5102_pins { -+ brcm,pins = <17 22 27>; -+ brcm,function = < -+ BCM2835_FSEL_GPIO_OUT -+ BCM2835_FSEL_GPIO_OUT -+ BCM2835_FSEL_GPIO_IN -+ >; -+ }; -+ wlf_8804_pins: wlf_8804_pins { -+ brcm,pins = <8>; -+ brcm,function = ; -+ }; -+ }; -+ }; -+ -+ fragment@2 { -+ target = <&spi0_cs_pins>; -+ __overlay__ { -+ brcm,pins = <7>; -+ brcm,function = ; -+ }; -+ }; -+ -+ -+ fragment@3 { -+ target-path = "/"; -+ __overlay__ { -+ rpi_cirrus_reg_1v8: rpi_cirrus_reg_1v8 { -+ compatible = "regulator-fixed"; -+ regulator-name = "RPi-Cirrus 1v8"; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-always-on; -+ }; -+ }; -+ }; -+ -+ fragment@4 { -+ target = <&spidev0>; -+ __overlay__ { -+ status = "disabled"; -+ }; -+ }; -+ -+ fragment@5 { -+ target = <&spidev1>; -+ __overlay__ { -+ status = "disabled"; -+ }; -+ }; -+ -+ fragment@6 { -+ target = <&spi0>; -+ __overlay__ { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "okay"; -+ cs-gpios = <&gpio 7 GPIO_ACTIVE_LOW>; -+ -+ wm5102@0{ -+ compatible = "wlf,wm5102"; -+ reg = <0>; -+ -+ pinctrl-names = "default"; -+ pinctrl-0 = <&wlf_5102_pins>; -+ -+ spi-max-frequency = <500000>; -+ -+ interrupt-parent = <&gpio>; -+ interrupts = <27 8>; -+ interrupt-controller; -+ #interrupt-cells = <2>; -+ -+ gpio-controller; -+ #gpio-cells = <2>; -+ -+ LDOVDD-supply = <&rpi_cirrus_reg_1v8>; -+ AVDD-supply = <&rpi_cirrus_reg_1v8>; -+ DBVDD1-supply = <&rpi_cirrus_reg_1v8>; -+ DBVDD2-supply = <&vdd_3v3_reg>; -+ DBVDD3-supply = <&vdd_3v3_reg>; -+ CPVDD-supply = <&rpi_cirrus_reg_1v8>; -+ SPKVDDL-supply = <&vdd_5v0_reg>; -+ SPKVDDR-supply = <&vdd_5v0_reg>; -+ DCVDD-supply = <&arizona_ldo1>; -+ -+ reset-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; -+ wlf,ldoena = <&gpio 22 GPIO_ACTIVE_HIGH>; -+ wlf,gpio-defaults = < -+ ARIZONA_GP_DEFAULT -+ ARIZONA_GP_DEFAULT -+ ARIZONA_GP_DEFAULT -+ ARIZONA_GP_DEFAULT -+ ARIZONA_GP_DEFAULT -+ >; -+ wlf,micd-configs = <0 1 0>; -+ wlf,dmic-ref = < -+ ARIZONA_DMIC_MICVDD -+ ARIZONA_DMIC_MICBIAS2 -+ ARIZONA_DMIC_MICVDD -+ ARIZONA_DMIC_MICVDD -+ >; -+ wlf,inmode = < -+ ARIZONA_INMODE_DIFF -+ ARIZONA_INMODE_DMIC -+ ARIZONA_INMODE_SE -+ ARIZONA_INMODE_DIFF -+ >; -+ status = "okay"; -+ -+ arizona_ldo1: ldo1 { -+ regulator-name = "LDO1"; -+ // default constraints as in -+ // arizona-ldo1.c -+ regulator-min-microvolt = <1200000>; -+ regulator-max-microvolt = <1800000>; -+ }; -+ }; -+ }; -+ }; -+ -+ fragment@7 { -+ target = <&i2c1>; -+ __overlay__ { -+ status = "okay"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ wm8804@3b { -+ compatible = "wlf,wm8804"; -+ reg = <0x3b>; -+ status = "okay"; -+ -+ pinctrl-names = "default"; -+ pinctrl-0 = <&wlf_8804_pins>; -+ -+ PVDD-supply = <&vdd_3v3_reg>; -+ DVDD-supply = <&vdd_3v3_reg>; -+ wlf,reset-gpio = <&gpio 8 GPIO_ACTIVE_HIGH>; -+ }; -+ }; -+ }; -+ -+ fragment@8 { -+ target = <&sound>; -+ __overlay__ { -+ compatible = "wlf,rpi-cirrus"; -+ i2s-controller = <&i2s>; -+ status = "okay"; -+ }; -+ }; ++&iqaudio_dac { ++ card_name = "RPi Codec Zero"; ++ dai_name = "Raspberry Pi Codec Zero"; ++ dai_stream_name = "Raspberry Pi Codec Zero HiFi"; +}; -diff --git a/arch/arm/boot/dts/overlays/rpi-dac-overlay.dts b/arch/arm/boot/dts/overlays/rpi-dac-overlay.dts +diff --git a/arch/arm/boot/dts/overlays/rpi-dacplus-overlay.dts b/arch/arm/boot/dts/overlays/rpi-dacplus-overlay.dts new file mode 100644 -index 000000000000..07a915342702 +index 000000000000..47557aa17f19 --- /dev/null -+++ b/arch/arm/boot/dts/overlays/rpi-dac-overlay.dts -@@ -0,0 +1,34 @@ -+// Definitions for RPi DAC -+/dts-v1/; -+/plugin/; ++++ b/arch/arm/boot/dts/overlays/rpi-dacplus-overlay.dts +@@ -0,0 +1,17 @@ ++// Overlay for the Raspberry Pi DAC Plus soundcard + -+/ { -+ compatible = "brcm,bcm2835"; ++#include "iqaudio-dacplus-overlay.dts" + -+ fragment@0 { -+ target = <&i2s>; -+ __overlay__ { -+ status = "okay"; -+ }; -+ }; -+ -+ fragment@1 { -+ target-path = "/"; -+ __overlay__ { -+ pcm1794a-codec { -+ #sound-dai-cells = <0>; -+ compatible = "ti,pcm1794a"; -+ status = "okay"; -+ }; -+ }; -+ }; -+ -+ fragment@2 { -+ target = <&sound>; -+ __overlay__ { -+ compatible = "rpi,rpi-dac"; -+ i2s-controller = <&i2s>; -+ status = "okay"; -+ }; -+ }; ++&iqaudio_dac { ++ card_name = "RPi DAC+"; ++ dai_name = "Raspberry Pi DAC+"; ++ dai_stream_name = "Raspberry Pi DAC+ HiFi"; ++ /delete-property/ mute-gpios; +}; -diff --git a/arch/arm/boot/dts/overlays/rpi-display-overlay.dts b/arch/arm/boot/dts/overlays/rpi-display-overlay.dts -new file mode 100644 -index 000000000000..2cf937b56456 ---- /dev/null -+++ b/arch/arm/boot/dts/overlays/rpi-display-overlay.dts -@@ -0,0 +1,91 @@ -+/* -+ * Device Tree overlay for rpi-display by Watterott -+ * -+ */ -+ -+/dts-v1/; -+/plugin/; + +/ { -+ compatible = "brcm,bcm2835"; -+ -+ fragment@0 { -+ target = <&spi0>; -+ __overlay__ { -+ status = "okay"; -+ }; -+ }; -+ -+ fragment@1 { -+ target = <&spidev0>; -+ __overlay__ { -+ status = "disabled"; -+ }; -+ }; -+ -+ fragment@2 { -+ target = <&spidev1>; -+ __overlay__ { -+ status = "disabled"; -+ }; -+ }; -+ -+ fragment@3 { -+ target = <&gpio>; -+ __overlay__ { -+ rpi_display_pins: rpi_display_pins { -+ brcm,pins = <18 23 24 25>; -+ brcm,function = <1 1 1 0>; /* out out out in */ -+ brcm,pull = <0 0 0 2>; /* - - - up */ -+ }; -+ }; -+ }; -+ -+ fragment@4 { -+ target = <&spi0>; -+ __overlay__ { -+ /* needed to avoid dtc warning */ -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ rpidisplay: rpi-display@0{ -+ compatible = "ilitek,ili9341"; -+ reg = <0>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&rpi_display_pins>; -+ -+ spi-max-frequency = <32000000>; -+ rotate = <270>; -+ bgr; -+ fps = <30>; -+ buswidth = <8>; -+ reset-gpios = <&gpio 23 1>; -+ dc-gpios = <&gpio 24 0>; -+ led-gpios = <&gpio 18 1>; -+ debug = <0>; -+ }; -+ -+ rpidisplay_ts: rpi-display-ts@1 { -+ compatible = "ti,ads7846"; -+ reg = <1>; -+ -+ spi-max-frequency = <2000000>; -+ interrupts = <25 2>; /* high-to-low edge triggered */ -+ interrupt-parent = <&gpio>; -+ pendown-gpio = <&gpio 25 1>; -+ ti,x-plate-ohms = /bits/ 16 <60>; -+ ti,pressure-max = /bits/ 16 <255>; -+ }; -+ }; -+ }; + __overrides__ { -+ speed = <&rpidisplay>,"spi-max-frequency:0"; -+ rotate = <&rpidisplay>,"rotate:0"; -+ fps = <&rpidisplay>,"fps:0"; -+ debug = <&rpidisplay>,"debug:0"; -+ xohms = <&rpidisplay_ts>,"ti,x-plate-ohms;0"; -+ swapxy = <&rpidisplay_ts>,"ti,swap-xy?"; -+ backlight = <&rpidisplay>,"led-gpios:4", -+ <&rpi_display_pins>,"brcm,pins:0"; ++ /delete-property/ auto_mute_amp; ++ /delete-property/ unmute_amp; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlays/rpi-dacpro-overlay.dts b/arch/arm/boot/dts/overlays/rpi-dacpro-overlay.dts +new file mode 100644 +index 000000000000..412260c64edf +--- /dev/null ++++ b/arch/arm/boot/dts/overlays/rpi-dacpro-overlay.dts +@@ -0,0 +1,17 @@ ++// Overlay for the Raspberry Pi DAC Pro soundcard ++ ++#include "iqaudio-dacplus-overlay.dts" ++ ++&iqaudio_dac { ++ card_name = "RPi DAC Pro"; ++ dai_name = "Raspberry Pi DAC Pro"; ++ dai_stream_name = "Raspberry Pi DAC Pro HiFi"; ++ /delete-property/ mute-gpios; ++}; ++ ++/ { ++ __overrides__ { ++ /delete-property/ auto_mute_amp; ++ /delete-property/ unmute_amp; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlays/rpi-digiampplus-overlay.dts b/arch/arm/boot/dts/overlays/rpi-digiampplus-overlay.dts +new file mode 100644 +index 000000000000..5e73d6c1bf42 +--- /dev/null ++++ b/arch/arm/boot/dts/overlays/rpi-digiampplus-overlay.dts +@@ -0,0 +1,17 @@ ++// Overlay for the Raspberry Pi DAC Plus soundcard ++ ++#include "iqaudio-dacplus-overlay.dts" ++ ++&iqaudio_dac { ++ card_name = "RPi DigiAMP+"; ++ dai_name = "Raspberry Pi DigiAMP+"; ++ dai_stream_name = "Raspberry Pi DigiAMP+ HiFi"; ++ iqaudio-dac,auto-mute-amp; ++}; ++ ++/ { ++ __overrides__ { ++ unmute_amp = <&iqaudio_dac>,"iqaudio-dac,unmute-amp?", ++ <&iqaudio_dac>,"iqaudio-dac,auto-mute-amp!"; + }; +}; diff --git a/arch/arm/boot/dts/overlays/rpi-ft5406-overlay.dts b/arch/arm/boot/dts/overlays/rpi-ft5406-overlay.dts @@ -28854,10 +42120,10 @@ index 000000000000..8483c4f4b2eb +}; diff --git a/arch/arm/boot/dts/overlays/rpi-poe-overlay.dts b/arch/arm/boot/dts/overlays/rpi-poe-overlay.dts new file mode 100644 -index 000000000000..af812132a8f7 +index 000000000000..cfd9fe37e108 --- /dev/null +++ b/arch/arm/boot/dts/overlays/rpi-poe-overlay.dts -@@ -0,0 +1,95 @@ +@@ -0,0 +1,154 @@ +/* + * Overlay for the Raspberry Pi POE HAT. + */ @@ -28870,14 +42136,11 @@ index 000000000000..af812132a8f7 + fragment@0 { + target-path = "/"; + __overlay__ { -+ fan0: rpi-poe-fan@0 { -+ compatible = "raspberrypi,rpi-poe-fan"; -+ firmware = <&firmware>; -+ cooling-min-state = <0>; -+ cooling-max-state = <4>; -+ #cooling-cells = <2>; ++ fan: pwm-fan { ++ compatible = "pwm-fan"; + cooling-levels = <0 1 10 100 255>; -+ status = "okay"; ++ #cooling-cells = <2>; ++ pwms = <&fwpwm 0 80000 0>; + }; + }; + }; @@ -28885,52 +42148,61 @@ index 000000000000..af812132a8f7 + fragment@1 { + target = <&cpu_thermal>; + __overlay__ { -+ trips { -+ trip0: trip0 { -+ temperature = <40000>; -+ hysteresis = <2000>; -+ type = "active"; -+ }; -+ trip1: trip1 { -+ temperature = <45000>; -+ hysteresis = <2000>; -+ type = "active"; -+ }; -+ trip2: trip2 { -+ temperature = <50000>; -+ hysteresis = <2000>; -+ type = "active"; -+ }; -+ trip3: trip3 { -+ temperature = <55000>; -+ hysteresis = <5000>; -+ type = "active"; -+ }; -+ }; -+ cooling-maps { -+ map0 { -+ trip = <&trip0>; -+ cooling-device = <&fan0 0 1>; -+ }; -+ map1 { -+ trip = <&trip1>; -+ cooling-device = <&fan0 1 2>; -+ }; -+ map2 { -+ trip = <&trip2>; -+ cooling-device = <&fan0 2 3>; -+ }; -+ map3 { -+ trip = <&trip3>; -+ cooling-device = <&fan0 3 4>; -+ }; -+ }; ++ polling-delay = <2000>; /* milliseconds */ + }; + }; + + fragment@2 { -+ target-path = "/__overrides__"; ++ target = <&thermal_trips>; + __overlay__ { ++ trip0: trip0 { ++ temperature = <40000>; ++ hysteresis = <2000>; ++ type = "active"; ++ }; ++ trip1: trip1 { ++ temperature = <45000>; ++ hysteresis = <2000>; ++ type = "active"; ++ }; ++ trip2: trip2 { ++ temperature = <50000>; ++ hysteresis = <2000>; ++ type = "active"; ++ }; ++ trip3: trip3 { ++ temperature = <55000>; ++ hysteresis = <5000>; ++ type = "active"; ++ }; ++ }; ++ }; ++ ++ fragment@3 { ++ target = <&cooling_maps>; ++ __overlay__ { ++ map0 { ++ trip = <&trip0>; ++ cooling-device = <&fan 0 1>; ++ }; ++ map1 { ++ trip = <&trip1>; ++ cooling-device = <&fan 1 2>; ++ }; ++ map2 { ++ trip = <&trip2>; ++ cooling-device = <&fan 2 3>; ++ }; ++ map3 { ++ trip = <&trip3>; ++ cooling-device = <&fan 3 4>; ++ }; ++ }; ++ }; ++ ++ fragment@4 { ++ target-path = "/__overrides__"; ++ params: __overlay__ { + poe_fan_temp0 = <&trip0>,"temperature:0"; + poe_fan_temp0_hyst = <&trip0>,"hysteresis:0"; + poe_fan_temp1 = <&trip1>,"temperature:0"; @@ -28939,6 +42211,54 @@ index 000000000000..af812132a8f7 + poe_fan_temp2_hyst = <&trip2>,"hysteresis:0"; + poe_fan_temp3 = <&trip3>,"temperature:0"; + poe_fan_temp3_hyst = <&trip3>,"hysteresis:0"; ++ poe_fan_i2c = <&fwpwm>,"status=disabled", ++ <&poe_mfd>,"status=okay", ++ <&fan>,"pwms:0=",<&poe_mfd_pwm>; ++ }; ++ }; ++ ++ fragment@5 { ++ target = <&firmware>; ++ __overlay__ { ++ fwpwm: pwm { ++ compatible = "raspberrypi,firmware-poe-pwm"; ++ #pwm-cells = <2>; ++ }; ++ }; ++ }; ++ ++ fragment@6 { ++ target = <&i2c0>; ++ i2c_bus: __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ poe_mfd: poe@51 { ++ compatible = "raspberrypi,poe-core"; ++ reg = <0x51>; ++ status = "disabled"; ++ ++ poe_mfd_pwm: poe_pwm@f0 { ++ compatible = "raspberrypi,poe-pwm"; ++ reg = <0xf0>; ++ status = "okay"; ++ #pwm-cells = <2>; ++ }; ++ }; ++ }; ++ }; ++ ++ fragment@7 { ++ target = <&i2c0if>; ++ __dormant__ { ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@8 { ++ target = <&i2c0mux>; ++ __dormant__ { ++ status = "okay"; + }; + }; + @@ -28951,14 +42271,19 @@ index 000000000000..af812132a8f7 + poe_fan_temp2_hyst = <&trip2>,"hysteresis:0"; + poe_fan_temp3 = <&trip3>,"temperature:0"; + poe_fan_temp3_hyst = <&trip3>,"hysteresis:0"; ++ i2c = <0>, "+5+6", ++ <&fwpwm>,"status=disabled", ++ <&i2c_bus>,"status=okay", ++ <&poe_mfd>,"status=okay", ++ <&fan>,"pwms:0=",<&poe_mfd_pwm>; + }; +}; diff --git a/arch/arm/boot/dts/overlays/rpi-poe-plus-overlay.dts b/arch/arm/boot/dts/overlays/rpi-poe-plus-overlay.dts new file mode 100644 -index 000000000000..5b12d02c3707 +index 000000000000..54deda2f18c3 --- /dev/null +++ b/arch/arm/boot/dts/overlays/rpi-poe-plus-overlay.dts -@@ -0,0 +1,23 @@ +@@ -0,0 +1,49 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +// Overlay for the Raspberry Pi PoE+ HAT. + @@ -28967,66 +42292,47 @@ index 000000000000..5b12d02c3707 +/ { + compatible = "brcm,bcm2835"; + -+ fragment@3 { ++ fragment@10 { + target-path = "/"; + __overlay__ { -+ rpi_poe_power_supply: rpi-poe-power-supply@0 { ++ rpi_poe_power_supply: rpi-poe-power-supply { + compatible = "raspberrypi,rpi-poe-power-supply"; + firmware = <&firmware>; + status = "okay"; + }; + }; + }; -+}; -+ -+&fan0 { -+ cooling-levels = <0 32 64 128 255>; -+}; -diff --git a/arch/arm/boot/dts/overlays/rpi-proto-overlay.dts b/arch/arm/boot/dts/overlays/rpi-proto-overlay.dts -new file mode 100644 -index 000000000000..9cda044a0f62 ---- /dev/null -+++ b/arch/arm/boot/dts/overlays/rpi-proto-overlay.dts -@@ -0,0 +1,39 @@ -+// Definitions for Rpi-Proto -+/dts-v1/; -+/plugin/; -+ -+/ { -+ compatible = "brcm,bcm2835"; -+ -+ fragment@0 { -+ target = <&i2s>; ++ fragment@11 { ++ target = <&poe_mfd>; + __overlay__ { -+ status = "okay"; -+ }; -+ }; -+ -+ fragment@1 { -+ target = <&i2c1>; -+ __overlay__ { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "okay"; -+ -+ wm8731@1a { -+ #sound-dai-cells = <0>; -+ compatible = "wlf,wm8731"; -+ reg = <0x1a>; ++ rpi-poe-power-supply@f2 { ++ compatible = "raspberrypi,rpi-poe-power-supply"; ++ reg = <0xf2>; + status = "okay"; + }; + }; + }; + -+ fragment@2 { -+ target = <&sound>; -+ __overlay__ { -+ compatible = "rpi,rpi-proto"; -+ i2s-controller = <&i2s>; -+ status = "okay"; -+ }; ++ __overrides__ { ++ i2c = <0>, "+5+6", ++ <&fwpwm>,"status=disabled", ++ <&rpi_poe_power_supply>,"status=disabled", ++ <&i2c_bus>,"status=okay", ++ <&poe_mfd>,"status=okay", ++ <&fan>,"pwms:0=",<&poe_mfd_pwm>; + }; +}; ++ ++&fan { ++ cooling-levels = <0 32 64 128 255>; ++}; ++ ++¶ms { ++ poe_fan_i2c = <&fwpwm>,"status=disabled", ++ <&rpi_poe_power_supply>,"status=disabled", ++ <&poe_mfd>,"status=okay", ++ <&fan>,"pwms:0=",<&poe_mfd_pwm>; ++}; diff --git a/arch/arm/boot/dts/overlays/rpi-sense-overlay.dts b/arch/arm/boot/dts/overlays/rpi-sense-overlay.dts new file mode 100644 index 000000000000..89d8d2ea6b2e @@ -29080,6 +42386,59 @@ index 000000000000..89d8d2ea6b2e + }; + }; +}; +diff --git a/arch/arm/boot/dts/overlays/rpi-sense-v2-overlay.dts b/arch/arm/boot/dts/overlays/rpi-sense-v2-overlay.dts +new file mode 100644 +index 000000000000..1b86c032259b +--- /dev/null ++++ b/arch/arm/boot/dts/overlays/rpi-sense-v2-overlay.dts +@@ -0,0 +1,47 @@ ++// rpi-sense HAT ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "brcm,bcm2835"; ++ ++ fragment@0 { ++ target = <&i2c1>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "okay"; ++ ++ rpi-sense@46 { ++ compatible = "rpi,rpi-sense"; ++ reg = <0x46>; ++ keys-int-gpios = <&gpio 23 1>; ++ status = "okay"; ++ }; ++ ++ lsm9ds1-magn@1c { ++ compatible = "st,lsm9ds1-magn"; ++ reg = <0x1c>; ++ status = "okay"; ++ }; ++ ++ lps25h-press@5c { ++ compatible = "st,lps25h-press"; ++ reg = <0x5c>; ++ status = "okay"; ++ }; ++ ++ hts221-humid@5f { ++ compatible = "st,hts221-humid", "st,hts221"; ++ reg = <0x5f>; ++ status = "okay"; ++ }; ++ ++ lsm9ds1-accel@6a { ++ compatible = "st,lsm9ds1-accel"; ++ reg = <0x6a>; ++ status = "okay"; ++ }; ++ }; ++ }; ++}; diff --git a/arch/arm/boot/dts/overlays/rpi-tv-overlay.dts b/arch/arm/boot/dts/overlays/rpi-tv-overlay.dts new file mode 100644 index 000000000000..3c97a545d820 @@ -29120,65 +42479,9 @@ index 000000000000..3c97a545d820 + }; + +}; -diff --git a/arch/arm/boot/dts/overlays/rpivid-v4l2-overlay.dts b/arch/arm/boot/dts/overlays/rpivid-v4l2-overlay.dts -new file mode 100644 -index 000000000000..bdd1c0e5a915 ---- /dev/null -+++ b/arch/arm/boot/dts/overlays/rpivid-v4l2-overlay.dts -@@ -0,0 +1,50 @@ -+// SPDX-License-Identifier: GPL-2.0-only -+// Definitions for Raspberry Pi video decode engine -+/dts-v1/; -+/plugin/; -+ -+#include -+ -+/{ -+ compatible = "brcm,bcm2711"; -+ -+ fragment@0 { -+ target = <&scb>; -+ __overlay__ { -+ /* needed to avoid dtc warning */ -+ #address-cells = <2>; -+ #size-cells = <2>; -+ -+ codec@7eb10000 { -+ compatible = "raspberrypi,rpivid-vid-decoder"; -+ reg = <0x0 0x7eb10000 0x0 0x1000>, /* INTC */ -+ <0x0 0x7eb00000 0x0 0x10000>; /* HEVC */ -+ reg-names = "intc", -+ "hevc"; -+ -+ interrupts = ; -+ -+ clocks = <&firmware_clocks 11>; -+ clock-names = "hevc"; -+ }; -+ }; -+ }; -+ -+ fragment@1 { -+ target = <&scb>; -+ __overlay__ { -+ hevc-decoder@7eb00000 { -+ status = "disabled"; -+ }; -+ rpivid-local-intc@7eb10000 { -+ status = "disabled"; -+ }; -+ h264-decoder@7eb20000 { -+ status = "disabled"; -+ }; -+ vp9-decoder@7eb30000 { -+ status = "disabled"; -+ }; -+ }; -+ }; -+}; diff --git a/arch/arm/boot/dts/overlays/rra-digidac1-wm8741-audio-overlay.dts b/arch/arm/boot/dts/overlays/rra-digidac1-wm8741-audio-overlay.dts new file mode 100644 -index 000000000000..87e9a326eff1 +index 000000000000..97db53a91fda --- /dev/null +++ b/arch/arm/boot/dts/overlays/rra-digidac1-wm8741-audio-overlay.dts @@ -0,0 +1,49 @@ @@ -29190,7 +42493,7 @@ index 000000000000..87e9a326eff1 + compatible = "brcm,bcm2835"; + + fragment@0 { -+ target = <&i2s>; ++ target = <&i2s_clk_consumer>; + __overlay__ { + status = "okay"; + }; @@ -29226,7 +42529,7 @@ index 000000000000..87e9a326eff1 + target = <&sound>; + __overlay__ { + compatible = "rra,digidac1-soundcard"; -+ i2s-controller = <&i2s>; ++ i2s-controller = <&i2s_clk_consumer>; + status = "okay"; + }; + }; @@ -29642,6 +42945,36 @@ index 000000000000..873e49056379 + gpios_34_39 = <0>,"=5"; + }; +}; +diff --git a/arch/arm/boot/dts/overlays/sdio-pi5-overlay.dts b/arch/arm/boot/dts/overlays/sdio-pi5-overlay.dts +new file mode 100644 +index 000000000000..4e42cb5c856e +--- /dev/null ++++ b/arch/arm/boot/dts/overlays/sdio-pi5-overlay.dts +@@ -0,0 +1,24 @@ ++/dts-v1/; ++/plugin/; ++ ++/* SDIO/SD/MMC on RP1 bank 0 */ ++ ++/{ ++ compatible = "brcm,bcm2712"; ++ ++ fragment@0 { ++ target = <&rp1_mmc0>; ++ frag0: __overlay__ { ++ status = "okay"; ++ pinctrl-0 = <&rp1_sdio0_22_27>; ++ pinctrl-names = "default"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&rp1_sdio_clk0>; ++ frag1: __overlay__ { ++ status = "okay"; ++ }; ++ }; ++}; diff --git a/arch/arm/boot/dts/overlays/seeed-can-fd-hat-v1-overlay.dts b/arch/arm/boot/dts/overlays/seeed-can-fd-hat-v1-overlay.dts new file mode 100644 index 000000000000..210d027a073e @@ -30280,7 +43613,7 @@ index 000000000000..9ebcaf1b5ea0 +}; diff --git a/arch/arm/boot/dts/overlays/spi-rtc-overlay.dts b/arch/arm/boot/dts/overlays/spi-rtc-overlay.dts new file mode 100644 -index 000000000000..51b7fec281c0 +index 000000000000..df3286929c2e --- /dev/null +++ b/arch/arm/boot/dts/overlays/spi-rtc-overlay.dts @@ -0,0 +1,75 @@ @@ -30294,14 +43627,14 @@ index 000000000000..51b7fec281c0 + fragment@0 { + target = <&rtc>; + __dormant__ { -+ compatible = "maxim,ds3232"; ++ compatible = "dallas,ds3232"; + }; + }; + + fragment@1 { + target = <&rtc>; + __dormant__ { -+ compatible = "maxim,ds3234"; ++ compatible = "dallas,ds3234"; + }; + }; + @@ -30783,6 +44116,45 @@ index 000000000000..2a29750462af + cs0_spidev = <&spidev2_0>,"status"; + }; +}; +diff --git a/arch/arm/boot/dts/overlays/spi2-1cs-pi5-overlay.dts b/arch/arm/boot/dts/overlays/spi2-1cs-pi5-overlay.dts +new file mode 100644 +index 000000000000..44382cc5a7c0 +--- /dev/null ++++ b/arch/arm/boot/dts/overlays/spi2-1cs-pi5-overlay.dts +@@ -0,0 +1,33 @@ ++/dts-v1/; ++/plugin/; ++ ++ ++/ { ++ compatible = "brcm,bcm2712"; ++ ++ fragment@0 { ++ target = <&spi2>; ++ frag1: __overlay__ { ++ /* needed to avoid dtc warning */ ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ cs-gpios = <&gpio 0 1>; ++ status = "okay"; ++ ++ spidev2_0: spidev@0 { ++ compatible = "spidev"; ++ reg = <0>; /* CE0 */ ++ #address-cells = <1>; ++ #size-cells = <0>; ++ spi-max-frequency = <125000000>; ++ status = "okay"; ++ }; ++ }; ++ }; ++ ++ __overrides__ { ++ cs0_pin = <&frag1>,"cs-gpios:4"; ++ cs0_spidev = <&spidev2_0>,"status"; ++ }; ++}; diff --git a/arch/arm/boot/dts/overlays/spi2-2cs-overlay.dts b/arch/arm/boot/dts/overlays/spi2-2cs-overlay.dts new file mode 100644 index 000000000000..642678fc9ddd @@ -30858,6 +44230,56 @@ index 000000000000..642678fc9ddd + cs1_spidev = <&spidev2_1>,"status"; + }; +}; +diff --git a/arch/arm/boot/dts/overlays/spi2-2cs-pi5-overlay.dts b/arch/arm/boot/dts/overlays/spi2-2cs-pi5-overlay.dts +new file mode 100644 +index 000000000000..b37a2c21c7b4 +--- /dev/null ++++ b/arch/arm/boot/dts/overlays/spi2-2cs-pi5-overlay.dts +@@ -0,0 +1,44 @@ ++/dts-v1/; ++/plugin/; ++ ++ ++/ { ++ compatible = "brcm,bcm2712"; ++ ++ fragment@0 { ++ target = <&spi2>; ++ frag1: __overlay__ { ++ /* needed to avoid dtc warning */ ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ cs-gpios = <&gpio 0 1>, <&gpio 24 1>; ++ status = "okay"; ++ ++ spidev2_0: spidev@0 { ++ compatible = "spidev"; ++ reg = <0>; /* CE0 */ ++ #address-cells = <1>; ++ #size-cells = <0>; ++ spi-max-frequency = <125000000>; ++ status = "okay"; ++ }; ++ ++ spidev2_1: spidev@1 { ++ compatible = "spidev"; ++ reg = <1>; /* CE1 */ ++ #address-cells = <1>; ++ #size-cells = <0>; ++ spi-max-frequency = <125000000>; ++ status = "okay"; ++ }; ++ }; ++ }; ++ ++ __overrides__ { ++ cs0_pin = <&frag1>,"cs-gpios:4"; ++ cs1_pin = <&frag1>,"cs-gpios:16"; ++ cs0_spidev = <&spidev2_0>,"status"; ++ cs1_spidev = <&spidev2_1>,"status"; ++ }; ++}; diff --git a/arch/arm/boot/dts/overlays/spi2-3cs-overlay.dts b/arch/arm/boot/dts/overlays/spi2-3cs-overlay.dts new file mode 100644 index 000000000000..28d40c6c3c37 @@ -30947,10 +44369,10 @@ index 000000000000..28d40c6c3c37 +}; diff --git a/arch/arm/boot/dts/overlays/spi3-1cs-overlay.dts b/arch/arm/boot/dts/overlays/spi3-1cs-overlay.dts new file mode 100644 -index 000000000000..335af8637051 +index 000000000000..7abea6d86fd0 --- /dev/null +++ b/arch/arm/boot/dts/overlays/spi3-1cs-overlay.dts -@@ -0,0 +1,44 @@ +@@ -0,0 +1,42 @@ +/dts-v1/; +/plugin/; + @@ -30973,8 +44395,6 @@ index 000000000000..335af8637051 + #address-cells = <1>; + #size-cells = <0>; + -+ pinctrl-names = "default"; -+ pinctrl-0 = <&spi3_pins &spi3_cs_pins>; + cs-gpios = <&gpio 0 1>; + status = "okay"; + @@ -30995,12 +44415,51 @@ index 000000000000..335af8637051 + cs0_spidev = <&spidev3_0>,"status"; + }; +}; +diff --git a/arch/arm/boot/dts/overlays/spi3-1cs-pi5-overlay.dts b/arch/arm/boot/dts/overlays/spi3-1cs-pi5-overlay.dts +new file mode 100644 +index 000000000000..a94e3a9f35ce +--- /dev/null ++++ b/arch/arm/boot/dts/overlays/spi3-1cs-pi5-overlay.dts +@@ -0,0 +1,33 @@ ++/dts-v1/; ++/plugin/; ++ ++ ++/ { ++ compatible = "brcm,bcm2712"; ++ ++ fragment@0 { ++ target = <&spi3>; ++ frag1: __overlay__ { ++ /* needed to avoid dtc warning */ ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ cs-gpios = <&gpio 4 1>; ++ status = "okay"; ++ ++ spidev3_0: spidev@0 { ++ compatible = "spidev"; ++ reg = <0>; /* CE0 */ ++ #address-cells = <1>; ++ #size-cells = <0>; ++ spi-max-frequency = <125000000>; ++ status = "okay"; ++ }; ++ }; ++ }; ++ ++ __overrides__ { ++ cs0_pin = <&frag1>,"cs-gpios:4"; ++ cs0_spidev = <&spidev3_0>,"status"; ++ }; ++}; diff --git a/arch/arm/boot/dts/overlays/spi3-2cs-overlay.dts b/arch/arm/boot/dts/overlays/spi3-2cs-overlay.dts new file mode 100644 -index 000000000000..ce65da27f767 +index 000000000000..2f474ac769f5 --- /dev/null +++ b/arch/arm/boot/dts/overlays/spi3-2cs-overlay.dts -@@ -0,0 +1,56 @@ +@@ -0,0 +1,54 @@ +/dts-v1/; +/plugin/; + @@ -31023,8 +44482,6 @@ index 000000000000..ce65da27f767 + #address-cells = <1>; + #size-cells = <0>; + -+ pinctrl-names = "default"; -+ pinctrl-0 = <&spi3_pins &spi3_cs_pins>; + cs-gpios = <&gpio 0 1>, <&gpio 24 1>; + status = "okay"; + @@ -31057,12 +44514,62 @@ index 000000000000..ce65da27f767 + cs1_spidev = <&spidev3_1>,"status"; + }; +}; +diff --git a/arch/arm/boot/dts/overlays/spi3-2cs-pi5-overlay.dts b/arch/arm/boot/dts/overlays/spi3-2cs-pi5-overlay.dts +new file mode 100644 +index 000000000000..259548b37d5c +--- /dev/null ++++ b/arch/arm/boot/dts/overlays/spi3-2cs-pi5-overlay.dts +@@ -0,0 +1,44 @@ ++/dts-v1/; ++/plugin/; ++ ++ ++/ { ++ compatible = "brcm,bcm2712"; ++ ++ fragment@0 { ++ target = <&spi3>; ++ frag1: __overlay__ { ++ /* needed to avoid dtc warning */ ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ cs-gpios = <&gpio 4 1>, <&gpio 25 1>; ++ status = "okay"; ++ ++ spidev3_0: spidev@0 { ++ compatible = "spidev"; ++ reg = <0>; /* CE0 */ ++ #address-cells = <1>; ++ #size-cells = <0>; ++ spi-max-frequency = <125000000>; ++ status = "okay"; ++ }; ++ ++ spidev3_1: spidev@1 { ++ compatible = "spidev"; ++ reg = <1>; /* CE1 */ ++ #address-cells = <1>; ++ #size-cells = <0>; ++ spi-max-frequency = <125000000>; ++ status = "okay"; ++ }; ++ }; ++ }; ++ ++ __overrides__ { ++ cs0_pin = <&frag1>,"cs-gpios:4"; ++ cs1_pin = <&frag1>,"cs-gpios:16"; ++ cs0_spidev = <&spidev3_0>,"status"; ++ cs1_spidev = <&spidev3_1>,"status"; ++ }; ++}; diff --git a/arch/arm/boot/dts/overlays/spi4-1cs-overlay.dts b/arch/arm/boot/dts/overlays/spi4-1cs-overlay.dts new file mode 100644 -index 000000000000..85d70b40352b +index 000000000000..66d89521124a --- /dev/null +++ b/arch/arm/boot/dts/overlays/spi4-1cs-overlay.dts -@@ -0,0 +1,44 @@ +@@ -0,0 +1,42 @@ +/dts-v1/; +/plugin/; + @@ -31085,8 +44592,6 @@ index 000000000000..85d70b40352b + #address-cells = <1>; + #size-cells = <0>; + -+ pinctrl-names = "default"; -+ pinctrl-0 = <&spi4_pins &spi4_cs_pins>; + cs-gpios = <&gpio 4 1>; + status = "okay"; + @@ -31109,10 +44614,10 @@ index 000000000000..85d70b40352b +}; diff --git a/arch/arm/boot/dts/overlays/spi4-2cs-overlay.dts b/arch/arm/boot/dts/overlays/spi4-2cs-overlay.dts new file mode 100644 -index 000000000000..8bc2215a6a7e +index 000000000000..83d8cb8b918c --- /dev/null +++ b/arch/arm/boot/dts/overlays/spi4-2cs-overlay.dts -@@ -0,0 +1,56 @@ +@@ -0,0 +1,54 @@ +/dts-v1/; +/plugin/; + @@ -31135,8 +44640,6 @@ index 000000000000..8bc2215a6a7e + #address-cells = <1>; + #size-cells = <0>; + -+ pinctrl-names = "default"; -+ pinctrl-0 = <&spi4_pins &spi4_cs_pins>; + cs-gpios = <&gpio 4 1>, <&gpio 25 1>; + status = "okay"; + @@ -31171,10 +44674,10 @@ index 000000000000..8bc2215a6a7e +}; diff --git a/arch/arm/boot/dts/overlays/spi5-1cs-overlay.dts b/arch/arm/boot/dts/overlays/spi5-1cs-overlay.dts new file mode 100644 -index 000000000000..c0f8cb8510ee +index 000000000000..168b4825de34 --- /dev/null +++ b/arch/arm/boot/dts/overlays/spi5-1cs-overlay.dts -@@ -0,0 +1,44 @@ +@@ -0,0 +1,42 @@ +/dts-v1/; +/plugin/; + @@ -31197,8 +44700,6 @@ index 000000000000..c0f8cb8510ee + #address-cells = <1>; + #size-cells = <0>; + -+ pinctrl-names = "default"; -+ pinctrl-0 = <&spi5_pins &spi5_cs_pins>; + cs-gpios = <&gpio 12 1>; + status = "okay"; + @@ -31219,12 +44720,51 @@ index 000000000000..c0f8cb8510ee + cs0_spidev = <&spidev5_0>,"status"; + }; +}; +diff --git a/arch/arm/boot/dts/overlays/spi5-1cs-pi5-overlay.dts b/arch/arm/boot/dts/overlays/spi5-1cs-pi5-overlay.dts +new file mode 100644 +index 000000000000..bde1837f26c0 +--- /dev/null ++++ b/arch/arm/boot/dts/overlays/spi5-1cs-pi5-overlay.dts +@@ -0,0 +1,33 @@ ++/dts-v1/; ++/plugin/; ++ ++ ++/ { ++ compatible = "brcm,bcm2712"; ++ ++ fragment@0 { ++ target = <&spi5>; ++ frag1: __overlay__ { ++ /* needed to avoid dtc warning */ ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ cs-gpios = <&gpio 12 1>; ++ status = "okay"; ++ ++ spidev5_0: spidev@0 { ++ compatible = "spidev"; ++ reg = <0>; /* CE0 */ ++ #address-cells = <1>; ++ #size-cells = <0>; ++ spi-max-frequency = <125000000>; ++ status = "okay"; ++ }; ++ }; ++ }; ++ ++ __overrides__ { ++ cs0_pin = <&frag1>,"cs-gpios:4"; ++ cs0_spidev = <&spidev5_0>,"status"; ++ }; ++}; diff --git a/arch/arm/boot/dts/overlays/spi5-2cs-overlay.dts b/arch/arm/boot/dts/overlays/spi5-2cs-overlay.dts new file mode 100644 -index 000000000000..7758b9c00b4e +index 000000000000..c2a239a34b35 --- /dev/null +++ b/arch/arm/boot/dts/overlays/spi5-2cs-overlay.dts -@@ -0,0 +1,56 @@ +@@ -0,0 +1,54 @@ +/dts-v1/; +/plugin/; + @@ -31247,8 +44787,6 @@ index 000000000000..7758b9c00b4e + #address-cells = <1>; + #size-cells = <0>; + -+ pinctrl-names = "default"; -+ pinctrl-0 = <&spi5_pins &spi5_cs_pins>; + cs-gpios = <&gpio 12 1>, <&gpio 26 1>; + status = "okay"; + @@ -31281,12 +44819,62 @@ index 000000000000..7758b9c00b4e + cs1_spidev = <&spidev5_1>,"status"; + }; +}; +diff --git a/arch/arm/boot/dts/overlays/spi5-2cs-pi5-overlay.dts b/arch/arm/boot/dts/overlays/spi5-2cs-pi5-overlay.dts +new file mode 100644 +index 000000000000..2c9eee2a9db8 +--- /dev/null ++++ b/arch/arm/boot/dts/overlays/spi5-2cs-pi5-overlay.dts +@@ -0,0 +1,44 @@ ++/dts-v1/; ++/plugin/; ++ ++ ++/ { ++ compatible = "brcm,bcm2712"; ++ ++ fragment@0 { ++ target = <&spi5>; ++ frag1: __overlay__ { ++ /* needed to avoid dtc warning */ ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ cs-gpios = <&gpio 12 1>, <&gpio 26 1>; ++ status = "okay"; ++ ++ spidev5_0: spidev@0 { ++ compatible = "spidev"; ++ reg = <0>; /* CE0 */ ++ #address-cells = <1>; ++ #size-cells = <0>; ++ spi-max-frequency = <125000000>; ++ status = "okay"; ++ }; ++ ++ spidev5_1: spidev@1 { ++ compatible = "spidev"; ++ reg = <1>; /* CE1 */ ++ #address-cells = <1>; ++ #size-cells = <0>; ++ spi-max-frequency = <125000000>; ++ status = "okay"; ++ }; ++ }; ++ }; ++ ++ __overrides__ { ++ cs0_pin = <&frag1>,"cs-gpios:4"; ++ cs1_pin = <&frag1>,"cs-gpios:16"; ++ cs0_spidev = <&spidev5_0>,"status"; ++ cs1_spidev = <&spidev5_1>,"status"; ++ }; ++}; diff --git a/arch/arm/boot/dts/overlays/spi6-1cs-overlay.dts b/arch/arm/boot/dts/overlays/spi6-1cs-overlay.dts new file mode 100644 -index 000000000000..8c8a953eca01 +index 000000000000..a784f8a17d23 --- /dev/null +++ b/arch/arm/boot/dts/overlays/spi6-1cs-overlay.dts -@@ -0,0 +1,44 @@ +@@ -0,0 +1,42 @@ +/dts-v1/; +/plugin/; + @@ -31309,8 +44897,6 @@ index 000000000000..8c8a953eca01 + #address-cells = <1>; + #size-cells = <0>; + -+ pinctrl-names = "default"; -+ pinctrl-0 = <&spi6_pins &spi6_cs_pins>; + cs-gpios = <&gpio 18 1>; + status = "okay"; + @@ -31333,10 +44919,10 @@ index 000000000000..8c8a953eca01 +}; diff --git a/arch/arm/boot/dts/overlays/spi6-2cs-overlay.dts b/arch/arm/boot/dts/overlays/spi6-2cs-overlay.dts new file mode 100644 -index 000000000000..2ff897f21aed +index 000000000000..8ef513814d2b --- /dev/null +++ b/arch/arm/boot/dts/overlays/spi6-2cs-overlay.dts -@@ -0,0 +1,56 @@ +@@ -0,0 +1,54 @@ +/dts-v1/; +/plugin/; + @@ -31359,8 +44945,6 @@ index 000000000000..2ff897f21aed + #address-cells = <1>; + #size-cells = <0>; + -+ pinctrl-names = "default"; -+ pinctrl-0 = <&spi6_pins &spi6_cs_pins>; + cs-gpios = <&gpio 18 1>, <&gpio 27 1>; + status = "okay"; + @@ -31437,10 +45021,10 @@ index 000000000000..84cf10e489d3 +}; diff --git a/arch/arm/boot/dts/overlays/ssd1306-spi-overlay.dts b/arch/arm/boot/dts/overlays/ssd1306-spi-overlay.dts new file mode 100644 -index 000000000000..ffc90c7cecf6 +index 000000000000..679749fc3065 --- /dev/null +++ b/arch/arm/boot/dts/overlays/ssd1306-spi-overlay.dts -@@ -0,0 +1,84 @@ +@@ -0,0 +1,85 @@ +/* + * Device Tree overlay for SSD1306 based SPI OLED display + * @@ -31523,6 +45107,7 @@ index 000000000000..ffc90c7cecf6 + reset_pin = <&ssd1306>,"reset-gpios:4", + <&ssd1306_pins>,"brcm,pins:0"; + height = <&ssd1306>,"solomon,height:0"; ++ inverted = <&ssd1306>,"solomon,com-invdir?"; + }; +}; diff --git a/arch/arm/boot/dts/overlays/ssd1331-spi-overlay.dts b/arch/arm/boot/dts/overlays/ssd1331-spi-overlay.dts @@ -31705,7 +45290,7 @@ index 000000000000..ffc872c60648 +}; diff --git a/arch/arm/boot/dts/overlays/superaudioboard-overlay.dts b/arch/arm/boot/dts/overlays/superaudioboard-overlay.dts new file mode 100755 -index 000000000000..bad61535981e +index 000000000000..1006d5fe9e06 --- /dev/null +++ b/arch/arm/boot/dts/overlays/superaudioboard-overlay.dts @@ -0,0 +1,73 @@ @@ -31720,7 +45305,7 @@ index 000000000000..bad61535981e + target = <&sound>; + __overlay__ { + compatible = "simple-audio-card"; -+ i2s-controller = <&i2s>; ++ i2s-controller = <&i2s_clk_consumer>; + status = "okay"; + + simple-audio-card,name = "SuperAudioBoard"; @@ -31743,7 +45328,7 @@ index 000000000000..bad61535981e + simple-audio-card,frame-master = <&sound_master>; + + simple-audio-card,cpu { -+ sound-dai = <&i2s>; ++ sound-dai = <&i2s_clk_consumer>; + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <32>; + }; @@ -31756,7 +45341,7 @@ index 000000000000..bad61535981e + }; + + fragment@1 { -+ target = <&i2s>; ++ target = <&i2s_clk_consumer>; + __overlay__ { + status = "okay"; + }; @@ -33496,7 +47081,7 @@ index 000000000000..1d1069345da2 + diff --git a/arch/arm/boot/dts/overlays/tc358743-audio-overlay.dts b/arch/arm/boot/dts/overlays/tc358743-audio-overlay.dts new file mode 100644 -index 000000000000..047695bb0c71 +index 000000000000..6bb3dceb0df3 --- /dev/null +++ b/arch/arm/boot/dts/overlays/tc358743-audio-overlay.dts @@ -0,0 +1,52 @@ @@ -33510,7 +47095,7 @@ index 000000000000..047695bb0c71 + compatible = "brcm,bcm2835"; + + fragment@0 { -+ target = <&i2s>; ++ target = <&i2s_clk_consumer>; + __overlay__ { + status = "okay"; + }; @@ -33533,16 +47118,16 @@ index 000000000000..047695bb0c71 + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "tc358743"; -+ simple-audio-card,bitclock-master = <&dailink0_slave>; -+ simple-audio-card,frame-master = <&dailink0_slave>; ++ simple-audio-card,bitclock-master = <&dailink0_master>; ++ simple-audio-card,frame-master = <&dailink0_master>; + status = "okay"; + + simple-audio-card,cpu { -+ sound-dai = <&i2s>; ++ sound-dai = <&i2s_clk_consumer>; + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <32>; + }; -+ dailink0_slave: simple-audio-card,codec { ++ dailink0_master: simple-audio-card,codec { + sound-dai = <&tc358743_codec>; + }; + }; @@ -33554,7 +47139,7 @@ index 000000000000..047695bb0c71 +}; diff --git a/arch/arm/boot/dts/overlays/tc358743-overlay.dts b/arch/arm/boot/dts/overlays/tc358743-overlay.dts new file mode 100644 -index 000000000000..c3eebfd1f6ee +index 000000000000..2eb74d33b40d --- /dev/null +++ b/arch/arm/boot/dts/overlays/tc358743-overlay.dts @@ -0,0 +1,109 @@ @@ -33661,7 +47246,7 @@ index 000000000000..c3eebfd1f6ee + 4lane = <0>, "-2+3-7+8"; + link-frequency = <&tc358743_0>,"link-frequencies#0"; + media-controller = <&csi>,"brcm,media-controller?"; -+ cam0 = <&i2c_frag>, "target:0=",<&i2c_vc>, ++ cam0 = <&i2c_frag>, "target:0=",<&i2c_csi_dsi0>, + <&csi_frag>, "target:0=",<&csi0>, + <&clk_frag>, "target:0=",<&cam0_clk>, + <&tc358743>, "clocks:0=",<&cam0_clk>; @@ -33669,7 +47254,7 @@ index 000000000000..c3eebfd1f6ee +}; diff --git a/arch/arm/boot/dts/overlays/tinylcd35-overlay.dts b/arch/arm/boot/dts/overlays/tinylcd35-overlay.dts new file mode 100644 -index 000000000000..a102b09e3ab5 +index 000000000000..edc5889b6f5f --- /dev/null +++ b/arch/arm/boot/dts/overlays/tinylcd35-overlay.dts @@ -0,0 +1,222 @@ @@ -33796,7 +47381,7 @@ index 000000000000..a102b09e3ab5 + spi-max-frequency = <2000000>; + interrupts = <5 2>; /* high-to-low edge triggered */ + interrupt-parent = <&gpio>; -+ pendown-gpio = <&gpio 5 0>; ++ pendown-gpio = <&gpio 5 1>; + ti,x-plate-ohms = /bits/ 16 <100>; + ti,pressure-max = /bits/ 16 <255>; + }; @@ -33945,9 +47530,65 @@ index 000000000000..e69188503ca3 + }; + }; +}; +diff --git a/arch/arm/boot/dts/overlays/tpm-slb9673-overlay.dts b/arch/arm/boot/dts/overlays/tpm-slb9673-overlay.dts +new file mode 100644 +index 000000000000..cba8c25c30e5 +--- /dev/null ++++ b/arch/arm/boot/dts/overlays/tpm-slb9673-overlay.dts +@@ -0,0 +1,50 @@ ++/* ++ * Device Tree overlay for the Infineon SLB9673 Trusted Platform Module add-on ++ * boards, which can be used as a secure key storage and hwrng. ++ */ ++ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "brcm,bcm2835"; ++ ++ /* Due to issue https://github.com/raspberrypi/linux/issues/4884 the ++ hardware I2C needs to be disabled and software I2C enabled */ ++ fragment@0 { ++ target = <&i2c_arm>; ++ __overlay__ { ++ status = "disabled"; ++ }; ++ }; ++ ++ fragment@1 { ++ target-path = "/"; ++ __overlay__ { ++ i2c1: i2c-gpio@1 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ compatible = "i2c-gpio"; ++ gpios = <&gpio 2 6>, /* SDA GPIO_OPEN_DRAIN */ ++ <&gpio 3 6>; /* CLK GPIO_OPEN_DRAIN */ ++ clock-frequency = <400000>; ++ status = "okay"; ++ }; ++ }; ++ }; ++ ++ /* Add the TPM */ ++ fragment@2 { ++ target = <&i2c1>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ slb9673: slb9673@2e { ++ compatible = "infineon,slb9673", "tcg,tpm-tis-i2c"; ++ reg = <0x2e>; ++ status = "okay"; ++ }; ++ }; ++ }; ++}; diff --git a/arch/arm/boot/dts/overlays/uart0-overlay.dts b/arch/arm/boot/dts/overlays/uart0-overlay.dts new file mode 100755 -index 000000000000..73d563bbaabf +index 000000000000..6bf2e0fd5c61 --- /dev/null +++ b/arch/arm/boot/dts/overlays/uart0-overlay.dts @@ -0,0 +1,32 @@ @@ -33969,7 +47610,7 @@ index 000000000000..73d563bbaabf + fragment@1 { + target = <&gpio>; + __overlay__ { -+ uart0_pins: uart0_pins { ++ uart0_pins: uart0_ovl_pins { + brcm,pins = <14 15>; + brcm,function = <4>; /* alt0 */ + brcm,pull = <0 2>; @@ -33983,9 +47624,33 @@ index 000000000000..73d563bbaabf + pin_func = <&uart0_pins>,"brcm,function:0"; + }; +}; +diff --git a/arch/arm/boot/dts/overlays/uart0-pi5-overlay.dts b/arch/arm/boot/dts/overlays/uart0-pi5-overlay.dts +new file mode 100755 +index 000000000000..3cc9843b812d +--- /dev/null ++++ b/arch/arm/boot/dts/overlays/uart0-pi5-overlay.dts +@@ -0,0 +1,18 @@ ++/dts-v1/; ++/plugin/; ++ ++/{ ++ compatible = "brcm,bcm2712"; ++ ++ fragment@0 { ++ target = <&uart0>; ++ frag0: __overlay__ { ++ status = "okay"; ++ pinctrl-0 = <&uart0_pins>; ++ }; ++ }; ++ ++ __overrides__ { ++ ctsrts = <&frag0>,"pinctrl-0:4=",<&uart0_ctsrts_pins>; ++ }; ++}; diff --git a/arch/arm/boot/dts/overlays/uart1-overlay.dts b/arch/arm/boot/dts/overlays/uart1-overlay.dts new file mode 100644 -index 000000000000..986d725a2652 +index 000000000000..64163bf932b7 --- /dev/null +++ b/arch/arm/boot/dts/overlays/uart1-overlay.dts @@ -0,0 +1,38 @@ @@ -34007,7 +47672,7 @@ index 000000000000..986d725a2652 + fragment@1 { + target = <&gpio>; + __overlay__ { -+ uart1_pins: uart1_pins { ++ uart1_pins: uart1_ovl_pins { + brcm,pins = <14 15>; + brcm,function = <2>; /* alt5 */ + brcm,pull = <0 2>; @@ -34027,12 +47692,36 @@ index 000000000000..986d725a2652 + rxd1_pin = <&uart1_pins>,"brcm,pins:4"; + }; +}; +diff --git a/arch/arm/boot/dts/overlays/uart1-pi5-overlay.dts b/arch/arm/boot/dts/overlays/uart1-pi5-overlay.dts +new file mode 100755 +index 000000000000..739f5a941ffa +--- /dev/null ++++ b/arch/arm/boot/dts/overlays/uart1-pi5-overlay.dts +@@ -0,0 +1,18 @@ ++/dts-v1/; ++/plugin/; ++ ++/{ ++ compatible = "brcm,bcm2712"; ++ ++ fragment@0 { ++ target = <&uart1>; ++ frag0: __overlay__ { ++ status = "okay"; ++ pinctrl-0 = <&uart1_pins>; ++ }; ++ }; ++ ++ __overrides__ { ++ ctsrts = <&frag0>,"pinctrl-0:4=",<&uart1_ctsrts_pins>; ++ }; ++}; diff --git a/arch/arm/boot/dts/overlays/uart2-overlay.dts b/arch/arm/boot/dts/overlays/uart2-overlay.dts new file mode 100644 -index 000000000000..9face240aca1 +index 000000000000..d98cb5795f6a --- /dev/null +++ b/arch/arm/boot/dts/overlays/uart2-overlay.dts -@@ -0,0 +1,27 @@ +@@ -0,0 +1,25 @@ +/dts-v1/; +/plugin/; + @@ -34042,8 +47731,6 @@ index 000000000000..9face240aca1 + fragment@0 { + target = <&uart2>; + __overlay__ { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&uart2_pins>; + status = "okay"; + }; + }; @@ -34060,12 +47747,36 @@ index 000000000000..9face240aca1 + ctsrts = <0>,"=1"; + }; +}; +diff --git a/arch/arm/boot/dts/overlays/uart2-pi5-overlay.dts b/arch/arm/boot/dts/overlays/uart2-pi5-overlay.dts +new file mode 100755 +index 000000000000..1df956425d3a +--- /dev/null ++++ b/arch/arm/boot/dts/overlays/uart2-pi5-overlay.dts +@@ -0,0 +1,18 @@ ++/dts-v1/; ++/plugin/; ++ ++/{ ++ compatible = "brcm,bcm2712"; ++ ++ fragment@0 { ++ target = <&uart2>; ++ frag0: __overlay__ { ++ status = "okay"; ++ pinctrl-0 = <&uart2_pins>; ++ }; ++ }; ++ ++ __overrides__ { ++ ctsrts = <&frag0>,"pinctrl-0:4=",<&uart2_ctsrts_pins>; ++ }; ++}; diff --git a/arch/arm/boot/dts/overlays/uart3-overlay.dts b/arch/arm/boot/dts/overlays/uart3-overlay.dts new file mode 100644 -index 000000000000..ae9f9fe5ea1d +index 000000000000..5751d5b1a29e --- /dev/null +++ b/arch/arm/boot/dts/overlays/uart3-overlay.dts -@@ -0,0 +1,27 @@ +@@ -0,0 +1,25 @@ +/dts-v1/; +/plugin/; + @@ -34075,8 +47786,6 @@ index 000000000000..ae9f9fe5ea1d + fragment@0 { + target = <&uart3>; + __overlay__ { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&uart3_pins>; + status = "okay"; + }; + }; @@ -34093,12 +47802,36 @@ index 000000000000..ae9f9fe5ea1d + ctsrts = <0>,"=1"; + }; +}; +diff --git a/arch/arm/boot/dts/overlays/uart3-pi5-overlay.dts b/arch/arm/boot/dts/overlays/uart3-pi5-overlay.dts +new file mode 100755 +index 000000000000..d8ef51b403dd +--- /dev/null ++++ b/arch/arm/boot/dts/overlays/uart3-pi5-overlay.dts +@@ -0,0 +1,18 @@ ++/dts-v1/; ++/plugin/; ++ ++/{ ++ compatible = "brcm,bcm2712"; ++ ++ fragment@0 { ++ target = <&uart3>; ++ frag0: __overlay__ { ++ status = "okay"; ++ pinctrl-0 = <&uart3_pins>; ++ }; ++ }; ++ ++ __overrides__ { ++ ctsrts = <&frag0>,"pinctrl-0:4=",<&uart3_ctsrts_pins>; ++ }; ++}; diff --git a/arch/arm/boot/dts/overlays/uart4-overlay.dts b/arch/arm/boot/dts/overlays/uart4-overlay.dts new file mode 100644 -index 000000000000..ac004ffbadbf +index 000000000000..99def557b779 --- /dev/null +++ b/arch/arm/boot/dts/overlays/uart4-overlay.dts -@@ -0,0 +1,27 @@ +@@ -0,0 +1,25 @@ +/dts-v1/; +/plugin/; + @@ -34108,8 +47841,6 @@ index 000000000000..ac004ffbadbf + fragment@0 { + target = <&uart4>; + __overlay__ { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&uart4_pins>; + status = "okay"; + }; + }; @@ -34126,12 +47857,36 @@ index 000000000000..ac004ffbadbf + ctsrts = <0>,"=1"; + }; +}; +diff --git a/arch/arm/boot/dts/overlays/uart4-pi5-overlay.dts b/arch/arm/boot/dts/overlays/uart4-pi5-overlay.dts +new file mode 100755 +index 000000000000..7ce5be8cc95c +--- /dev/null ++++ b/arch/arm/boot/dts/overlays/uart4-pi5-overlay.dts +@@ -0,0 +1,18 @@ ++/dts-v1/; ++/plugin/; ++ ++/{ ++ compatible = "brcm,bcm2712"; ++ ++ fragment@0 { ++ target = <&uart4>; ++ frag0: __overlay__ { ++ status = "okay"; ++ pinctrl-0 = <&uart4_pins>; ++ }; ++ }; ++ ++ __overrides__ { ++ ctsrts = <&frag0>,"pinctrl-0:4=",<&uart4_ctsrts_pins>; ++ }; ++}; diff --git a/arch/arm/boot/dts/overlays/uart5-overlay.dts b/arch/arm/boot/dts/overlays/uart5-overlay.dts new file mode 100644 -index 000000000000..04eaf376effe +index 000000000000..649daea52e6b --- /dev/null +++ b/arch/arm/boot/dts/overlays/uart5-overlay.dts -@@ -0,0 +1,27 @@ +@@ -0,0 +1,25 @@ +/dts-v1/; +/plugin/; + @@ -34141,8 +47896,6 @@ index 000000000000..04eaf376effe + fragment@0 { + target = <&uart5>; + __overlay__ { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&uart5_pins>; + status = "okay"; + }; + }; @@ -34161,7 +47914,7 @@ index 000000000000..04eaf376effe +}; diff --git a/arch/arm/boot/dts/overlays/udrc-overlay.dts b/arch/arm/boot/dts/overlays/udrc-overlay.dts new file mode 100644 -index 000000000000..ae7c37996894 +index 000000000000..701f28e811bb --- /dev/null +++ b/arch/arm/boot/dts/overlays/udrc-overlay.dts @@ -0,0 +1,128 @@ @@ -34176,7 +47929,7 @@ index 000000000000..ae7c37996894 +/ { + compatible = "brcm,bcm2835"; + fragment@0 { -+ target = <&i2s>; ++ target = <&i2s_clk_producer>; + __overlay__ { + clocks = <&clocks BCM2835_CLOCK_PCM>; + clock-names = "pcm"; @@ -34238,7 +47991,7 @@ index 000000000000..ae7c37996894 + target = <&sound>; + snd: __overlay__ { + compatible = "simple-audio-card"; -+ i2s-controller = <&i2s>; ++ i2s-controller = <&i2s_clk_producer>; + status = "okay"; + + simple-audio-card,name = "udrc"; @@ -34260,7 +48013,7 @@ index 000000000000..ae7c37996894 + "Line Out", "LOL"; + + dailink0_master: simple-audio-card,cpu { -+ sound-dai = <&i2s>; ++ sound-dai = <&i2s_clk_producer>; + }; + + simple-audio-card,codec { @@ -34295,7 +48048,7 @@ index 000000000000..ae7c37996894 +}; diff --git a/arch/arm/boot/dts/overlays/ugreen-dabboard-overlay.dts b/arch/arm/boot/dts/overlays/ugreen-dabboard-overlay.dts new file mode 100644 -index 000000000000..fc8d9b118068 +index 000000000000..234f1f38225b --- /dev/null +++ b/arch/arm/boot/dts/overlays/ugreen-dabboard-overlay.dts @@ -0,0 +1,49 @@ @@ -34307,7 +48060,7 @@ index 000000000000..fc8d9b118068 + compatible = "brcm,bcm2835"; + + fragment@0 { -+ target = <&i2s>; ++ target = <&i2s_clk_consumer>; + __overlay__ { + status = "okay"; + }; @@ -34330,14 +48083,14 @@ index 000000000000..fc8d9b118068 + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "dabboard"; -+ simple-audio-card,bitclock-master = <&dailink0_slave>; -+ simple-audio-card,frame-master = <&dailink0_slave>; ++ simple-audio-card,bitclock-master = <&dailink0_master>; ++ simple-audio-card,frame-master = <&dailink0_master>; + simple-audio-card,widgets = "Microphone", "Microphone Jack"; + status = "okay"; + simple-audio-card,cpu { -+ sound-dai = <&i2s>; ++ sound-dai = <&i2s_clk_consumer>; + }; -+ dailink0_slave: simple-audio-card,codec { ++ dailink0_master: simple-audio-card,codec { + #sound-dai-cells = <0>; + sound-dai = <&dmic_codec>; + }; @@ -34350,7 +48103,7 @@ index 000000000000..fc8d9b118068 +}; diff --git a/arch/arm/boot/dts/overlays/upstream-overlay.dts b/arch/arm/boot/dts/overlays/upstream-overlay.dts new file mode 100644 -index 000000000000..2852bea52309 +index 000000000000..55a99736a33b --- /dev/null +++ b/arch/arm/boot/dts/overlays/upstream-overlay.dts @@ -0,0 +1,101 @@ @@ -34436,9 +48189,9 @@ index 000000000000..2852bea52309 + }; + }; + fragment@12 { -+ target = <&audio>; ++ target = <&chosen>; + __overlay__ { -+ brcm,disable-hdmi; ++ bootargs = "snd_bcm2835.enable_hdmi=0"; + }; + }; + fragment@13 { @@ -34457,7 +48210,7 @@ index 000000000000..2852bea52309 +}; diff --git a/arch/arm/boot/dts/overlays/upstream-pi4-overlay.dts b/arch/arm/boot/dts/overlays/upstream-pi4-overlay.dts new file mode 100644 -index 000000000000..f4328634542e +index 000000000000..1dc60ae6d967 --- /dev/null +++ b/arch/arm/boot/dts/overlays/upstream-pi4-overlay.dts @@ -0,0 +1,137 @@ @@ -34567,9 +48320,9 @@ index 000000000000..f4328634542e + }; + }; + fragment@16 { -+ target = <&audio>; ++ target-path = "/chosen"; + __overlay__ { -+ brcm,disable-hdmi; ++ bootargs = "snd_bcm2835.enable_hdmi=0"; + }; + }; + fragment@17 { @@ -34600,10 +48353,10 @@ index 000000000000..f4328634542e +}; diff --git a/arch/arm/boot/dts/overlays/vc4-fkms-v3d-overlay.dts b/arch/arm/boot/dts/overlays/vc4-fkms-v3d-overlay.dts new file mode 100644 -index 000000000000..ca344492bed8 +index 000000000000..d201edbe7003 --- /dev/null +++ b/arch/arm/boot/dts/overlays/vc4-fkms-v3d-overlay.dts -@@ -0,0 +1,40 @@ +@@ -0,0 +1,46 @@ +/* + * vc4-fkms-v3d-overlay.dts + */ @@ -34643,13 +48396,19 @@ index 000000000000..ca344492bed8 + status = "okay"; + }; + }; ++ fragment@5 { ++ target-path = "/chosen"; ++ __overlay__ { ++ bootargs = "clk_ignore_unused"; ++ }; ++ }; +}; diff --git a/arch/arm/boot/dts/overlays/vc4-fkms-v3d-pi4-overlay.dts b/arch/arm/boot/dts/overlays/vc4-fkms-v3d-pi4-overlay.dts new file mode 100644 -index 000000000000..7792ead0cbb3 +index 000000000000..1e10203dfd86 --- /dev/null +++ b/arch/arm/boot/dts/overlays/vc4-fkms-v3d-pi4-overlay.dts -@@ -0,0 +1,44 @@ +@@ -0,0 +1,50 @@ +/* + * vc4-fkms-v3d-overlay.dts + */ @@ -34660,7 +48419,7 @@ index 000000000000..7792ead0cbb3 +#include "cma-overlay.dts" + +&frag0 { -+ size = <((320-4)*1024*1024)>; ++ size = <((512-4)*1024*1024)>; +}; + +/ { @@ -34693,13 +48452,19 @@ index 000000000000..7792ead0cbb3 + status = "okay"; + }; + }; ++ fragment@5 { ++ target-path = "/chosen"; ++ __overlay__ { ++ bootargs = "clk_ignore_unused"; ++ }; ++ }; +}; diff --git a/arch/arm/boot/dts/overlays/vc4-kms-dpi-generic-overlay.dts b/arch/arm/boot/dts/overlays/vc4-kms-dpi-generic-overlay.dts new file mode 100644 -index 000000000000..1e5c5080592b +index 000000000000..8b006fcd9e58 --- /dev/null +++ b/arch/arm/boot/dts/overlays/vc4-kms-dpi-generic-overlay.dts -@@ -0,0 +1,74 @@ +@@ -0,0 +1,81 @@ +/* + * vc4-kms-dpi-generic-overlay.dts + */ @@ -34714,7 +48479,7 @@ index 000000000000..1e5c5080592b + + fragment@0 { + target = <&panel>; -+ __overlay__ { ++ panel_generic: __overlay__ { + compatible = "panel-dpi"; + + width-mm = <154>; @@ -34742,7 +48507,7 @@ index 000000000000..1e5c5080592b + + fragment@1 { + target = <&dpi>; -+ __overlay__ { ++ dpi_node_generic: __overlay__ { + pinctrl-0 = <&dpi_18bit_gpio0>; + }; + }; @@ -34765,13 +48530,345 @@ index 000000000000..1e5c5080592b + width-mm = <&panel>, "width-mm:0"; + height-mm = <&panel>, "height-mm:0"; + -+ rgb565 = <&panel>, "bus-format:0=0x1017", -+ <&dpi_node>, "pinctrl-0:0=",<&dpi_16bit_gpio0>; -+ rgb666-padhi = <&panel>, "bus-format:0=0x1015", -+ <&dpi_node>, "pinctrl-0:0=",<&dpi_18bit_cpadhi_gpio0>; -+ rgb888 = <&panel>, "bus-format:0=0x100a", -+ <&dpi_node>, "pinctrl-0:0=",<&dpi_gpio0>; -+ bus-format = <&panel>, "bus-format:0"; ++ rgb565 = <&panel_generic>, "bus-format:0=0x1017", ++ <&dpi_node_generic>, "pinctrl-0:0=",<&dpi_16bit_gpio0>; ++ rgb565-padhi = <&panel_generic>, "bus-format:0=0x1022", ++ <&dpi_node_generic>, "pinctrl-0:0=",<&dpi_16bit_cpadhi_gpio0>; ++ bgr666 = <&panel_generic>, "bus-format:0=0x1023"; ++ bgr666-padhi = <&panel_generic>, "bus-format:0=0x1024", ++ <&dpi_node_generic>, "pinctrl-0:0=",<&dpi_18bit_cpadhi_gpio0>; ++ rgb666-padhi = <&panel_generic>, "bus-format:0=0x1015", ++ <&dpi_node_generic>, "pinctrl-0:0=",<&dpi_18bit_cpadhi_gpio0>; ++ bgr888 = <&panel_generic>, "bus-format:0=0x1013", ++ <&dpi_node_generic>, "pinctrl-0:0=",<&dpi_gpio0>; ++ rgb888 = <&panel_generic>, "bus-format:0=0x100a", ++ <&dpi_node_generic>, "pinctrl-0:0=",<&dpi_gpio0>; ++ bus-format = <&panel_generic>, "bus-format:0"; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlays/vc4-kms-dpi-hyperpixel.dtsi b/arch/arm/boot/dts/overlays/vc4-kms-dpi-hyperpixel.dtsi +new file mode 100644 +index 000000000000..585402a3b9b4 +--- /dev/null ++++ b/arch/arm/boot/dts/overlays/vc4-kms-dpi-hyperpixel.dtsi +@@ -0,0 +1,94 @@ ++/* ++ * vc4-kms-dpi-hyperpixel4.dtsi ++ * Commmon initialisation for HyperPixel DPI displays ++ */ ++ ++#include ++#include ++ ++/ { ++ compatible = "brcm,bcm2835"; ++ ++ fragment@0 { ++ target-path = "/"; ++ __overlay__ { ++ spi { ++ compatible = "spi-gpio"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ pinctrl-0 = <&spi_pins>; ++ pinctrl-names = "default"; ++ ++ sck-gpios = <&gpio 27 GPIO_ACTIVE_HIGH>; ++ mosi-gpios = <&gpio 26 GPIO_ACTIVE_HIGH>; ++ cs-gpios = <&gpio 18 GPIO_ACTIVE_LOW>; ++ num-chipselects = <1>; ++ sck-idle-input; ++ ++ panel: display@0 { ++ reg = <0>; ++ /* 100 kHz */ ++ spi-max-frequency = <100000>; ++ backlight = <&backlight>; ++ rotation = <0>; ++ ++ port { ++ panel_in: endpoint { ++ remote-endpoint = <&dpi_out>; ++ }; ++ }; ++ }; ++ }; ++ ++ backlight: backlight { ++ compatible = "gpio-backlight"; ++ gpios = <&gpio 19 0>; ++ }; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&dpi>; ++ __overlay__ { ++ status = "okay"; ++ ++ pinctrl-names = "default"; ++ pinctrl-0 = <&dpi_18bit_cpadhi_gpio0>; ++ ++ port { ++ dpi_out: endpoint { ++ remote-endpoint = <&panel_in>; ++ }; ++ }; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&gpio>; ++ __overlay__ { ++ spi_pins: hyperpixel4_spi_pins { ++ brcm,pins = <27 18 26>; ++ brcm,pull = ; ++ brcm,function = <0>; ++ }; ++ }; ++ }; ++ ++ fragment@3 { ++ target-path = "/"; ++ __overlay__ { ++ i2c_gpio: i2c@0 { ++ compatible = "i2c-gpio"; ++ gpios = <&gpio 10 0 /* sda */ ++ &gpio 11 0>; /* scl */ ++ i2c-gpio,delay-us = <4>; /* ~100 kHz */ ++ #address-cells = <1>; ++ #size-cells = <0>; ++ }; ++ }; ++ }; ++ ++ __overrides__ { ++ rotate = <&panel>, "rotation:0"; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlays/vc4-kms-dpi-hyperpixel2r-overlay.dts b/arch/arm/boot/dts/overlays/vc4-kms-dpi-hyperpixel2r-overlay.dts +new file mode 100644 +index 000000000000..4cd9d6a55c48 +--- /dev/null ++++ b/arch/arm/boot/dts/overlays/vc4-kms-dpi-hyperpixel2r-overlay.dts +@@ -0,0 +1,114 @@ ++/* ++ * vc4-kms-dpi-hyperpixel2r-overlay.dts ++ */ ++ ++#include ++#include ++ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "brcm,bcm2835"; ++ ++ fragment@0 { ++ target-path = "/"; ++ __overlay__ { ++ spi { ++ compatible = "spi-gpio"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ pinctrl-0 = <&spi_pins>; ++ pinctrl-names = "default"; ++ ++ sck-gpios = <&gpio 11 GPIO_ACTIVE_HIGH>; ++ mosi-gpios = <&gpio 10 GPIO_ACTIVE_HIGH>; ++ cs-gpios = <&gpio 18 GPIO_ACTIVE_LOW>; ++ num-chipselects = <1>; ++ ++ panel: display@0 { ++ compatible = "pimoroni,hyperpixel2round"; ++ reg = <0>; ++ /* 100 kHz */ ++ spi-max-frequency = <100000>; ++ backlight = <&backlight>; ++ rotation = <0>; ++ ++ port { ++ panel_in: endpoint { ++ remote-endpoint = <&dpi_out>; ++ }; ++ }; ++ }; ++ }; ++ ++ backlight: backlight { ++ compatible = "gpio-backlight"; ++ gpios = <&gpio 19 0>; ++ }; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&dpi>; ++ __overlay__ { ++ status = "okay"; ++ ++ pinctrl-names = "default"; ++ pinctrl-0 = <&dpi_18bit_cpadhi_gpio0>; ++ ++ port { ++ dpi_out: endpoint { ++ remote-endpoint = <&panel_in>; ++ }; ++ }; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&gpio>; ++ __overlay__ { ++ spi_pins: hyperpixel4_spi_pins { ++ brcm,pins = <27 18 26>; ++ brcm,pull = ; ++ brcm,function = <0>; ++ }; ++ }; ++ }; ++ ++ fragment@3 { ++ target-path = "/"; ++ __overlay__ { ++ i2c_gpio: i2c@0 { ++ compatible = "i2c-gpio"; ++ status = "disabled"; ++ ++ gpios = <&gpio 10 GPIO_ACTIVE_HIGH /* sda */ ++ &gpio 11 GPIO_ACTIVE_HIGH>; /* scl */ ++ i2c-gpio,delay-us = <4>; /* ~100 kHz */ ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ polytouch: edt-ft5x06@15 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ compatible = "edt,edt-ft5406"; ++ reg = <0x15>; ++ interrupt-parent = <&gpio>; ++ interrupts = <27 0x02>; ++ touchscreen-size-x = <240>; ++ touchscreen-size-y = <240>; ++ }; ++ }; ++ }; ++ }; ++ ++ __overrides__ { ++ disable-touch = <0>,"-3"; ++ touchscreen-inverted-x = <&polytouch>,"touchscreen-inverted-x?"; ++ touchscreen-inverted-y = <&polytouch>,"touchscreen-inverted-y!"; ++ touchscreen-swapped-x-y = <&polytouch>,"touchscreen-swapped-x-y!"; ++ rotate = <&panel>, "rotation:0"; ++ }; ++ ++}; +diff --git a/arch/arm/boot/dts/overlays/vc4-kms-dpi-hyperpixel4-overlay.dts b/arch/arm/boot/dts/overlays/vc4-kms-dpi-hyperpixel4-overlay.dts +new file mode 100644 +index 000000000000..eafc25ad79ff +--- /dev/null ++++ b/arch/arm/boot/dts/overlays/vc4-kms-dpi-hyperpixel4-overlay.dts +@@ -0,0 +1,57 @@ ++/* ++ * vc4-kms-dpi-hyperpixel4sq-overlay.dts ++ */ ++ ++/dts-v1/; ++/plugin/; ++ ++#include "vc4-kms-dpi-hyperpixel.dtsi" ++ ++&panel { ++ compatible = "pimoroni,hyperpixel4"; ++}; ++ ++/ { ++ fragment@11 { ++ target = <&i2c_gpio>; ++ __overlay__ { ++ /* needed to avoid dtc warning */ ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ft6236_14: ft6236@14 { ++ compatible = "goodix,gt911"; ++ reg = <0x14>; ++ interrupt-parent = <&gpio>; ++ interrupts = <27 2>; ++ touchscreen-size-x = <480>; ++ touchscreen-size-y = <800>; ++ touchscreen-x-mm = <51>; ++ touchscreen-y-mm = <85>; ++ touchscreen-inverted-y; ++ touchscreen-swapped-x-y; ++ }; ++ ft6236_5d: ft6236@5d { ++ compatible = "goodix,gt911"; ++ reg = <0x5d>; ++ interrupt-parent = <&gpio>; ++ interrupts = <27 2>; ++ touchscreen-size-x = <480>; ++ touchscreen-size-y = <800>; ++ touchscreen-x-mm = <51>; ++ touchscreen-y-mm = <85>; ++ touchscreen-inverted-y; ++ touchscreen-swapped-x-y; ++ }; ++ }; ++ }; ++ ++ __overrides__ { ++ disable-touch = <0>,"-3-11"; ++ touchscreen-inverted-x = <&ft6236_14>,"touchscreen-inverted-x?", ++ <&ft6236_5d>,"touchscreen-inverted-x?"; ++ touchscreen-inverted-y = <&ft6236_14>,"touchscreen-inverted-y!", ++ <&ft6236_5d>,"touchscreen-inverted-y!"; ++ touchscreen-swapped-x-y = <&ft6236_14>,"touchscreen-swapped-x-y!", ++ <&ft6236_5d>,"touchscreen-swapped-x-y!"; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlays/vc4-kms-dpi-hyperpixel4sq-overlay.dts b/arch/arm/boot/dts/overlays/vc4-kms-dpi-hyperpixel4sq-overlay.dts +new file mode 100644 +index 000000000000..700046348ecf +--- /dev/null ++++ b/arch/arm/boot/dts/overlays/vc4-kms-dpi-hyperpixel4sq-overlay.dts +@@ -0,0 +1,36 @@ ++/* ++ * vc4-kms-dpi-hyperpixel4-overlay.dts ++ */ ++ ++/dts-v1/; ++/plugin/; ++ ++#include "vc4-kms-dpi-hyperpixel.dtsi" ++ ++&panel { ++ compatible = "pimoroni,hyperpixel4square"; ++}; ++ ++/ { ++ fragment@11 { ++ target = <&i2c_gpio>; ++ __overlay__ { ++ polytouch: edt-ft5x06@48 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ compatible = "edt,edt-ft5406"; ++ reg = <0x48>; ++ interrupt-parent = <&gpio>; ++ interrupts = <27 0x02>; ++ touchscreen-size-x = <720>; ++ touchscreen-size-y = <720>; ++ }; ++ }; ++ }; ++ __overrides__ { ++ disable-touch = <0>,"-3-11"; ++ touchscreen-inverted-x = <&polytouch>,"touchscreen-inverted-x?"; ++ touchscreen-inverted-y = <&polytouch>,"touchscreen-inverted-y!"; ++ touchscreen-swapped-x-y = <&polytouch>,"touchscreen-swapped-x-y!"; + }; +}; diff --git a/arch/arm/boot/dts/overlays/vc4-kms-dpi-panel-overlay.dts b/arch/arm/boot/dts/overlays/vc4-kms-dpi-panel-overlay.dts @@ -34851,7 +48948,7 @@ index 000000000000..ee9e2e8fd246 +}; diff --git a/arch/arm/boot/dts/overlays/vc4-kms-dpi.dtsi b/arch/arm/boot/dts/overlays/vc4-kms-dpi.dtsi new file mode 100644 -index 000000000000..f78fa48b19f9 +index 000000000000..67c884de2a8d --- /dev/null +++ b/arch/arm/boot/dts/overlays/vc4-kms-dpi.dtsi @@ -0,0 +1,111 @@ @@ -34923,7 +49020,7 @@ index 000000000000..f78fa48b19f9 + compatible = "pwm-backlight"; + brightness-levels = <0 6 8 12 16 24 32 40 48 64 96 128 160 192 224 255>; + default-brightness-level = <16>; -+ pwms = <&pwm 0 200000>; ++ pwms = <&pwm 0 200000 0>; + }; + }; + }; @@ -34949,9 +49046,9 @@ index 000000000000..f78fa48b19f9 + }; + + fragment@108 { -+ target = <&audio>; ++ target = <&chosen>; + __dormant__ { -+ brcm,disable-headphones; ++ bootargs = "snd_bcm2835.enable_headphones=0"; + }; + }; + @@ -34968,10 +49065,10 @@ index 000000000000..f78fa48b19f9 +}; diff --git a/arch/arm/boot/dts/overlays/vc4-kms-dsi-7inch-overlay.dts b/arch/arm/boot/dts/overlays/vc4-kms-dsi-7inch-overlay.dts new file mode 100644 -index 000000000000..5e1700d0367a +index 000000000000..302fa807d31d --- /dev/null +++ b/arch/arm/boot/dts/overlays/vc4-kms-dsi-7inch-overlay.dts -@@ -0,0 +1,118 @@ +@@ -0,0 +1,124 @@ +/* + * Device Tree overlay for RaspberryPi 7" Touchscreen panel + * @@ -34985,7 +49082,7 @@ index 000000000000..5e1700d0367a +/ { + /* No compatible as it will have come from edt-ft5406.dtsi */ + -+ fragment@0 { ++ dsi_frag: fragment@0 { + target = <&dsi1>; + __overlay__ { + #address-cells = <1>; @@ -35025,8 +49122,8 @@ index 000000000000..5e1700d0367a + fragment@1 { + target-path = "/"; + __overlay__ { -+ panel_disp1: panel_disp1@0 { -+ reg = <0>; ++ panel_disp: panel_disp@1 { ++ reg = <1>; + compatible = "raspberrypi,7inch-dsi", "simple-panel"; + backlight = <®_display>; + power-supply = <®_display>; @@ -35038,8 +49135,8 @@ index 000000000000..5e1700d0367a + }; + }; + -+ reg_bridge: reg_bridge@0 { -+ reg = <0>; ++ reg_bridge: reg_bridge@1 { ++ reg = <1>; + compatible = "regulator-fixed"; + regulator-name = "bridge_reg"; + gpio = <®_display 0 0>; @@ -35049,7 +49146,7 @@ index 000000000000..5e1700d0367a + }; + }; + -+ fragment@2 { ++ i2c_frag: fragment@2 { + target = <&i2c_csi_dsi>; + __overlay__ { + #address-cells = <1>; @@ -35087,7 +49184,381 @@ index 000000000000..5e1700d0367a + }; + + __overrides__ { -+ disable_touch = <0>, "-10-11-12"; ++ dsi0 = <&dsi_frag>, "target:0=",<&dsi0>, ++ <&i2c_frag>, "target:0=",<&i2c_csi_dsi0>, ++ <&ts_i2c_frag>, "target:0=",<&i2c_csi_dsi0>, ++ <&panel_disp>, "reg:0=0", ++ <®_bridge>, "reg:0=0", ++ <®_bridge>, "regulator-name=bridge_reg_0"; ++ disable_touch = <&ft5406>, "status=disabled"; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlays/vc4-kms-dsi-generic-overlay.dts b/arch/arm/boot/dts/overlays/vc4-kms-dsi-generic-overlay.dts +new file mode 100644 +index 000000000000..cf4ca5b6c75f +--- /dev/null ++++ b/arch/arm/boot/dts/overlays/vc4-kms-dsi-generic-overlay.dts +@@ -0,0 +1,106 @@ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "brcm,bcm2835"; ++ ++ dsi_frag: fragment@0 { ++ target = <&dsi1>; ++ __overlay__{ ++ status = "okay"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ port { ++ dsi_out:endpoint { ++ remote-endpoint = <&panel_dsi_port>; ++ }; ++ }; ++ panel: panel-dsi-generic@0 { ++ // See panel-dsi.yaml binding ++ // Using dummy name for panel model ++ compatible = "Generic,panel-dsi","panel-dsi"; ++ reg = <0>; ++ power-supply = <0>; ++ backlight = <0>; ++ dsi-color-format = "RGB888"; ++ mode = "MODE_VIDEO"; ++ width-mm = <0>; ++ height-mm = <0>; ++ ++ port { ++ panel_dsi_port: endpoint { ++ data-lanes = <1>; ++ remote-endpoint = <&dsi_out>; ++ }; ++ }; ++ ++ timing: panel-timing { ++ clock-frequency = <30000000>; ++ hactive = <840>; ++ vactive = <480>; ++ hback-porch = <44>; ++ hfront-porch = <46>; ++ hsync-len = <2>; ++ vback-porch = <18>; ++ vfront-porch = <16>; ++ vsync-len = <2>; ++ }; ++ }; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&panel_dsi_port>; ++ __dormant__ { ++ data-lanes = <1>; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&panel_dsi_port>; ++ __dormant__ { ++ data-lanes = <1 2>; ++ }; ++ }; ++ ++ fragment@3 { ++ target = <&panel_dsi_port>; ++ __dormant__ { ++ data-lanes = <1 2 3>; ++ }; ++ }; ++ ++ fragment@4 { ++ target = <&panel_dsi_port>; ++ __dormant__ { ++ data-lanes = <1 2 3 4>; ++ }; ++ }; ++ ++ __overrides__ { ++ dsi0 = <&dsi_frag>, "target:0=",<&dsi0>; ++ ++ clock-frequency = <&timing>, "clock-frequency:0"; ++ hactive = <&timing>, "hactive:0"; ++ hfp = <&timing>, "hfront-porch:0"; ++ hsync = <&timing>, "hsync-len:0"; ++ hbp = <&timing>, "hback-porch:0"; ++ vactive = <&timing>, "vactive:0"; ++ vfp = <&timing>, "vfront-porch:0"; ++ vsync = <&timing>, "vsync-len:0"; ++ vbp = <&timing>, "vback-porch:0"; ++ ++ width-mm = <&panel>, "width-mm:0"; ++ height-mm = <&panel>, "height-mm:0"; ++ ++ rgb565 = <&panel>, "dsi-color-format=RGB565"; ++ rgb666p = <&panel>, "dsi-color-format=RGB666_PACKED"; ++ rgb666 = <&panel>, "dsi-color-format=RGB666"; ++ rgb888 = <&panel>, "dsi-color-format=RGB888"; ++ one-lane = <0>,"+1"; ++ two-lane = <0>,"+2"; ++ three-lane = <0>,"+3"; ++ four-lane = <0>,"+4"; ++ }; ++ ++}; +diff --git a/arch/arm/boot/dts/overlays/vc4-kms-dsi-ili9881-5inch-overlay.dts b/arch/arm/boot/dts/overlays/vc4-kms-dsi-ili9881-5inch-overlay.dts +new file mode 100644 +index 000000000000..1985766c0e67 +--- /dev/null ++++ b/arch/arm/boot/dts/overlays/vc4-kms-dsi-ili9881-5inch-overlay.dts +@@ -0,0 +1,122 @@ ++/* ++ * vc4-kms-dsi-ili9881-5inch-overlay.dts ++ */ ++ ++/dts-v1/; ++/plugin/; ++ ++#include ++ ++/ { ++ compatible = "brcm,bcm2835"; ++ ++ i2c_frag: fragment@0 { ++ target = <&i2c_csi_dsi>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "okay"; ++ ++ display_mcu: display_mcu@45 ++ { ++ compatible = "raspberrypi,v2-touchscreen-panel-regulator"; ++ reg = <0x45>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ }; ++ ++ gt911: gt911@5d { ++ compatible = "goodix,gt911"; ++ reg = <0x5d>; ++ AVDD28-supply = <&touch_reg>; ++ touchscreen-size-x = <720>; ++ touchscreen-size-y = <1280>; ++ touchscreen-x-mm = <62>; ++ touchscreen-y-mm = <110>; ++ }; ++ }; ++ }; ++ ++ dsi_frag: fragment@1 { ++ target = <&dsi1>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "okay"; ++ ++ port { ++ dsi_out: endpoint { ++ remote-endpoint = <&panel_in>; ++ }; ++ }; ++ ++ dsi_panel: dsi_panel@0 { ++ reg = <0>; ++ compatible = "raspberrypi,dsi-5inch"; ++ reset-gpio = <&display_mcu 0 GPIO_ACTIVE_LOW>; ++ backlight = <&display_mcu>; ++ ++ port { ++ panel_in: endpoint { ++ remote-endpoint = <&dsi_out>; ++ }; ++ }; ++ }; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&i2c0if>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@3 { ++ target = <&i2c0mux>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@4 { ++ target-path = "/"; ++ __overlay__ { ++ touch_reg: touch_reg@1 { ++ reg = <1>; ++ compatible = "regulator-fixed"; ++ regulator-name = "touch_reg_1"; ++ gpio = <&display_mcu 1 GPIO_ACTIVE_HIGH>; ++ startup-delay-us = <50000>; ++ enable-active-high; ++ }; ++ }; ++ }; ++ ++ fragment@10 { ++ target = <>911>; ++ __dormant__ { ++ touchscreen-inverted-x; ++ }; ++ }; ++ ++ fragment@11 { ++ target = <>911>; ++ __dormant__ { ++ touchscreen-inverted-y; ++ }; ++ }; ++ ++ __overrides__ { ++ dsi0 = <&dsi_frag>, "target:0=",<&dsi0>, ++ <&i2c_frag>, "target:0=",<&i2c_csi_dsi0>, ++ <&touch_reg>, "reg:0=0", ++ <&touch_reg>, "regulator-name=touch_reg_0"; ++ sizex = <>911>,"touchscreen-size-x:0"; ++ sizey = <>911>,"touchscreen-size-y:0"; ++ invx = <0>, "+10"; ++ invy = <0>, "+11"; ++ swapxy = <>911>,"touchscreen-swapped-x-y?"; ++ disable_touch = <>911>, "status=disabled"; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlays/vc4-kms-dsi-ili9881-7inch-overlay.dts b/arch/arm/boot/dts/overlays/vc4-kms-dsi-ili9881-7inch-overlay.dts +new file mode 100644 +index 000000000000..d1eb31df1d69 +--- /dev/null ++++ b/arch/arm/boot/dts/overlays/vc4-kms-dsi-ili9881-7inch-overlay.dts +@@ -0,0 +1,122 @@ ++/* ++ * vc4-kms-dsi-ili9881-5inch-overlay.dts ++ */ ++ ++/dts-v1/; ++/plugin/; ++ ++#include ++ ++/ { ++ compatible = "brcm,bcm2835"; ++ ++ i2c_frag: fragment@0 { ++ target = <&i2c_csi_dsi>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "okay"; ++ ++ display_mcu: display_mcu@45 ++ { ++ compatible = "raspberrypi,v2-touchscreen-panel-regulator"; ++ reg = <0x45>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ }; ++ ++ gt911: gt911@5d { ++ compatible = "goodix,gt911"; ++ reg = <0x5d>; ++ AVDD28-supply = <&touch_reg>; ++ touchscreen-size-x = <720>; ++ touchscreen-size-y = <1280>; ++ touchscreen-x-mm = <90>; ++ touchscreen-y-mm = <151>; ++ }; ++ }; ++ }; ++ ++ dsi_frag: fragment@1 { ++ target = <&dsi1>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "okay"; ++ ++ port { ++ dsi_out: endpoint { ++ remote-endpoint = <&panel_in>; ++ }; ++ }; ++ ++ dsi_panel: dsi_panel@0 { ++ reg = <0>; ++ compatible = "raspberrypi,dsi-7inch"; ++ reset-gpio = <&display_mcu 0 GPIO_ACTIVE_LOW>; ++ backlight = <&display_mcu>; ++ ++ port { ++ panel_in: endpoint { ++ remote-endpoint = <&dsi_out>; ++ }; ++ }; ++ }; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&i2c0if>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@3 { ++ target = <&i2c0mux>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@4 { ++ target-path = "/"; ++ __overlay__ { ++ touch_reg: touch_reg@1 { ++ reg = <1>; ++ compatible = "regulator-fixed"; ++ regulator-name = "touch_reg_1"; ++ gpio = <&display_mcu 1 GPIO_ACTIVE_HIGH>; ++ startup-delay-us = <50000>; ++ enable-active-high; ++ }; ++ }; ++ }; ++ ++ fragment@10 { ++ target = <>911>; ++ __dormant__ { ++ touchscreen-inverted-x; ++ }; ++ }; ++ ++ fragment@11 { ++ target = <>911>; ++ __dormant__ { ++ touchscreen-inverted-y; ++ }; ++ }; ++ ++ __overrides__ { ++ dsi0 = <&dsi_frag>, "target:0=",<&dsi0>, ++ <&i2c_frag>, "target:0=",<&i2c_csi_dsi0>, ++ <&touch_reg>, "reg:0=0", ++ <&touch_reg>, "regulator-name=touch_reg_0"; ++ sizex = <>911>,"touchscreen-size-x:0"; ++ sizey = <>911>,"touchscreen-size-y:0"; ++ invx = <0>, "+10"; ++ invy = <0>, "+11"; ++ swapxy = <>911>,"touchscreen-swapped-x-y?"; ++ disable_touch = <>911>, "status=disabled"; + }; +}; diff --git a/arch/arm/boot/dts/overlays/vc4-kms-dsi-lt070me05000-overlay.dts b/arch/arm/boot/dts/overlays/vc4-kms-dsi-lt070me05000-overlay.dts @@ -35235,6 +49706,138 @@ index 000000000000..5dcd0f2243e2 + }; + }; +}; +diff --git a/arch/arm/boot/dts/overlays/vc4-kms-dsi-waveshare-panel-overlay.dts b/arch/arm/boot/dts/overlays/vc4-kms-dsi-waveshare-panel-overlay.dts +new file mode 100644 +index 000000000000..dfc92726d1bc +--- /dev/null ++++ b/arch/arm/boot/dts/overlays/vc4-kms-dsi-waveshare-panel-overlay.dts +@@ -0,0 +1,126 @@ ++/* ++ * Device Tree overlay for Waveshare DSI Touchscreens ++ * ++ */ ++ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "brcm,bcm2835"; ++ ++ dsi_frag: fragment@0 { ++ target = <&dsi1>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "okay"; ++ port { ++ dsi_out: endpoint { ++ remote-endpoint = <&panel_in>; ++ }; ++ }; ++ }; ++ }; ++ ++ fragment@1 { ++ target-path = "/"; ++ __overlay__ { ++ }; ++ }; ++ ++ i2c_frag: fragment@2 { ++ target = <&i2c_csi_dsi>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "okay"; ++ ++ panel: panel_disp1@45 { ++ reg = <0x45>; ++ compatible = "waveshare,10.1inch-panel"; ++ ++ port { ++ panel_in: endpoint { ++ remote-endpoint = <&dsi_out>; ++ }; ++ }; ++ }; ++ ++ touch: goodix@14 { ++ reg = <0x14>; ++ compatible = "goodix,gt911"; ++ }; ++ }; ++ }; ++ ++ fragment@3 { ++ target = <&i2c0if>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@4 { ++ target = <&i2c0mux>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@5 { ++ target = <&i2c_arm>; ++ __dormant__ { ++ status = "okay"; ++ }; ++ }; ++ ++ __overrides__ { ++ 2_8_inch = <&panel>, "compatible=waveshare,2.8inch-panel", ++ <&touch>, "touchscreen-size-x:0=480", ++ <&touch>, "touchscreen-size-y:0=640", ++ <&touch>, "touchscreen-inverted-y?", ++ <&touch>, "touchscreen-swapped-x-y?"; ++ 3_4_inch = <&panel>, "compatible=waveshare,3.4inch-panel", ++ <&touch>, "touchscreen-size-x:0=800", ++ <&touch>, "touchscreen-size-y:0=800"; ++ 4_0_inch = <&panel>, "compatible=waveshare,4.0inch-panel", ++ <&touch>, "touchscreen-size-x:0=800", ++ <&touch>, "touchscreen-size-y:0=480", ++ <&touch>, "touchscreen-inverted-x?", ++ <&touch>, "touchscreen-swapped-x-y?"; ++ 7_0_inchC = <&panel>, "compatible=waveshare,7.0inch-c-panel", ++ <&touch>, "touchscreen-size-x:0=800", ++ <&touch>, "touchscreen-size-y:0=480"; ++ 7_9_inch = <&panel>, "compatible=waveshare,7.9inch-panel", ++ <&touch>, "touchscreen-size-x:0=4096", ++ <&touch>, "touchscreen-size-y:0=4096", ++ <&touch>, "touchscreen-inverted-x?", ++ <&touch>, "touchscreen-swapped-x-y?"; ++ 8_0_inch = <&panel>, "compatible=waveshare,8.0inch-panel", ++ <&touch>, "touchscreen-size-x:0=800", ++ <&touch>, "touchscreen-size-y:0=1280", ++ <&touch>, "touchscreen-inverted-x?", ++ <&touch>, "touchscreen-swapped-x-y?"; ++ 10_1_inch = <&panel>, "compatible=waveshare,10.1inch-panel", ++ <&touch>, "touchscreen-size-x:0=800", ++ <&touch>, "touchscreen-size-y:0=1280", ++ <&touch>, "touchscreen-inverted-x?", ++ <&touch>, "touchscreen-swapped-x-y?"; ++ 11_9_inch = <&panel>, "compatible=waveshare,11.9inch-panel", ++ <&touch>, "touchscreen-inverted-x?", ++ <&touch>, "touchscreen-swapped-x-y?"; ++ 4_0_inchC = <&panel>, "compatible=waveshare,4inch-panel", ++ <&touch>, "touchscreen-size-x:0=720", ++ <&touch>, "touchscreen-size-y:0=720"; ++ i2c1 = <&i2c_frag>, "target:0=",<&i2c1>, ++ <0>, "-3-4+5"; ++ disable_touch = <&touch>, "status=disabled"; ++ rotation = <&panel>, "rotation:0"; ++ invx = <&touch>,"touchscreen-inverted-x?"; ++ invy = <&touch>,"touchscreen-inverted-y?"; ++ swapxy = <&touch>,"touchscreen-swapped-x-y?"; ++ dsi0 = <&dsi_frag>, "target:0=",<&dsi0>, ++ <&i2c_frag>, "target:0=",<&i2c_csi_dsi0>; ++ }; ++}; diff --git a/arch/arm/boot/dts/overlays/vc4-kms-kippah-7inch-overlay.dts b/arch/arm/boot/dts/overlays/vc4-kms-kippah-7inch-overlay.dts new file mode 100644 index 000000000000..4c1aa1c70158 @@ -35269,10 +49872,10 @@ index 000000000000..4c1aa1c70158 +}; diff --git a/arch/arm/boot/dts/overlays/vc4-kms-v3d-overlay.dts b/arch/arm/boot/dts/overlays/vc4-kms-v3d-overlay.dts new file mode 100644 -index 000000000000..351fc160e803 +index 000000000000..26a5bd71945d --- /dev/null +++ b/arch/arm/boot/dts/overlays/vc4-kms-v3d-overlay.dts -@@ -0,0 +1,123 @@ +@@ -0,0 +1,124 @@ +/* + * vc4-kms-v3d-overlay.dts + */ @@ -35384,9 +49987,9 @@ index 000000000000..351fc160e803 + }; + + fragment@14 { -+ target = <&audio>; ++ target = <&chosen>; + __overlay__ { -+ brcm,disable-hdmi; ++ bootargs = "snd_bcm2835.enable_hdmi=0"; + }; + }; + @@ -35394,14 +49997,15 @@ index 000000000000..351fc160e803 + audio = <0>,"!13"; + noaudio = <0>,"=13"; + composite = <0>, "=11"; ++ nohdmi = <0>, "-1-7"; + }; +}; diff --git a/arch/arm/boot/dts/overlays/vc4-kms-v3d-pi4-overlay.dts b/arch/arm/boot/dts/overlays/vc4-kms-v3d-pi4-overlay.dts new file mode 100644 -index 000000000000..76229cad7803 +index 000000000000..c1e53e3ed575 --- /dev/null +++ b/arch/arm/boot/dts/overlays/vc4-kms-v3d-pi4-overlay.dts -@@ -0,0 +1,197 @@ +@@ -0,0 +1,200 @@ +/* + * vc4-kms-v3d-pi4-overlay.dts + */ @@ -35414,7 +50018,7 @@ index 000000000000..76229cad7803 +#include "cma-overlay.dts" + +&frag0 { -+ size = <((320-4)*1024*1024)>; ++ size = <((512-4)*1024*1024)>; +}; + +/ { @@ -35547,9 +50151,9 @@ index 000000000000..76229cad7803 + }; + + fragment@19 { -+ target = <&audio>; ++ target-path = "/chosen"; + __overlay__ { -+ brcm,disable-hdmi; ++ bootargs = "snd_bcm2835.enable_hdmi=0"; + }; + }; + @@ -35597,14 +50201,170 @@ index 000000000000..76229cad7803 + <0>, "!16", + <0>, "=21", + <0>, "=22"; ++ nohdmi0 = <0>, "-1-3-8"; ++ nohdmi1 = <0>, "-2-4-10"; ++ nohdmi = <0>, "-1-2-3-4-8-10"; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlays/vc4-kms-v3d-pi5-overlay.dts b/arch/arm/boot/dts/overlays/vc4-kms-v3d-pi5-overlay.dts +new file mode 100644 +index 000000000000..3e976b18e2f1 +--- /dev/null ++++ b/arch/arm/boot/dts/overlays/vc4-kms-v3d-pi5-overlay.dts +@@ -0,0 +1,147 @@ ++// SPDX-License-Identifier: GPL-2.0 ++ ++#include "cma-overlay.dts" ++ ++&frag0 { ++ size = <((320-4)*1024*1024)>; ++}; ++ ++/ { ++ compatible = "brcm,bcm2712"; ++ ++ fragment@1 { ++ target = <&fb>; ++ __overlay__ { ++ status = "disabled"; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&aon_intr>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@3 { ++ target = <&ddc0>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@4 { ++ target = <&ddc1>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@5 { ++ target = <&hdmi0>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@6 { ++ target = <&hdmi1>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@7 { ++ target = <&hvs>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@8 { ++ target = <&mop>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@9 { ++ target = <&moplet>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@10 { ++ target = <&pixelvalve0>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@11 { ++ target = <&pixelvalve1>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@12 { ++ target = <&v3d>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@13 { ++ target = <&vec>; ++ frag13: __overlay__ { ++ status = "disabled"; ++ }; ++ }; ++ ++ fragment@14 { ++ target = <&hdmi0>; ++ __dormant__ { ++ dmas; ++ }; ++ }; ++ ++ fragment@15 { ++ target = <&hdmi1>; ++ __dormant__ { ++ dmas; ++ }; ++ }; ++ ++ fragment@16 { ++ target = <&disp_intr>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@17 { ++ target = <&vc4>; ++ __overlay__ { ++ /* IOMMU attaches here, where we allocate DMA buffers */ ++ iommus = <&iommu4>; ++ }; ++ }; ++ ++ __overrides__ { ++ audio = <0>,"!14"; ++ audio1 = <0>,"!15"; ++ noaudio = <0>,"=14", <0>,"=15"; ++ composite = <0>, "!3", ++ <0>, "!4", ++ <0>, "!5", ++ <0>, "!6", ++ <0>, "!10", ++ <0>, "!11", ++ <&frag13>, "status"; ++ nohdmi0 = <0>, "-3-5-10"; ++ nohdmi1 = <0>, "-4-6-11"; ++ nohdmi = <0>, "-3-4-5-6-10-11"; + }; +}; diff --git a/arch/arm/boot/dts/overlays/vc4-kms-vga666-overlay.dts b/arch/arm/boot/dts/overlays/vc4-kms-vga666-overlay.dts new file mode 100644 -index 000000000000..6e787099e861 +index 000000000000..c3a682d5b7d9 --- /dev/null +++ b/arch/arm/boot/dts/overlays/vc4-kms-vga666-overlay.dts -@@ -0,0 +1,100 @@ +@@ -0,0 +1,107 @@ +/* + * vc4-kms-vga666-overlay.dts + * Configures a FenLogic or similar VGA666 DPI adapter when using the @@ -35701,8 +50461,15 @@ index 000000000000..6e787099e861 + }; + }; + ++ fragment@5 { ++ target = <&i2c_vc>; ++ __dormant__ { ++ status = "okay"; ++ }; ++ }; ++ + __overrides__ { -+ ddc = <0>,"=2", <0>,"=3", <0>,"=4"; ++ ddc = <0>,"=2", <0>,"=3", <0>,"=4", <0>,"=5"; + }; +}; diff --git a/arch/arm/boot/dts/overlays/vga666-overlay.dts b/arch/arm/boot/dts/overlays/vga666-overlay.dts @@ -35811,6 +50578,27 @@ index 000000000000..f44e325bc1f2 + pullup; // Silently ignore unneeded parameter + }; +}; +diff --git a/arch/arm/boot/dts/overlays/w1-gpio-pi5-overlay.dts b/arch/arm/boot/dts/overlays/w1-gpio-pi5-overlay.dts +new file mode 100644 +index 000000000000..a408d3d62d40 +--- /dev/null ++++ b/arch/arm/boot/dts/overlays/w1-gpio-pi5-overlay.dts +@@ -0,0 +1,15 @@ ++/dts-v1/; ++/plugin/; ++ ++#include "w1-gpio-overlay.dts" ++ ++/ { ++ compatible = "brcm,bcm2712"; ++ ++ fragment@2 { ++ target = <&w1>; ++ __overlay__ { ++ raspberrypi,delay-needs-poll; ++ }; ++ }; ++}; diff --git a/arch/arm/boot/dts/overlays/w1-gpio-pullup-overlay.dts b/arch/arm/boot/dts/overlays/w1-gpio-pullup-overlay.dts new file mode 100644 index 000000000000..953c6a1aeab9 @@ -35859,6 +50647,27 @@ index 000000000000..953c6a1aeab9 + pullup; // Silently ignore unneeded parameter + }; +}; +diff --git a/arch/arm/boot/dts/overlays/w1-gpio-pullup-pi5-overlay.dts b/arch/arm/boot/dts/overlays/w1-gpio-pullup-pi5-overlay.dts +new file mode 100644 +index 000000000000..9d1fffb7e87c +--- /dev/null ++++ b/arch/arm/boot/dts/overlays/w1-gpio-pullup-pi5-overlay.dts +@@ -0,0 +1,15 @@ ++/dts-v1/; ++/plugin/; ++ ++#include "w1-gpio-pullup-overlay.dts" ++ ++/ { ++ compatible = "brcm,bcm2712"; ++ ++ fragment@2 { ++ target = <&w1>; ++ __overlay__ { ++ raspberrypi,delay-needs-poll; ++ }; ++ }; ++}; diff --git a/arch/arm/boot/dts/overlays/w5500-overlay.dts b/arch/arm/boot/dts/overlays/w5500-overlay.dts new file mode 100644 index 000000000000..4d3e66296753 @@ -35928,6 +50737,417 @@ index 000000000000..4d3e66296753 + <0>, "!0=1"; + }; +}; +diff --git a/arch/arm/boot/dts/overlays/watterott-display-overlay.dts b/arch/arm/boot/dts/overlays/watterott-display-overlay.dts +new file mode 100644 +index 000000000000..4388706d2c38 +--- /dev/null ++++ b/arch/arm/boot/dts/overlays/watterott-display-overlay.dts +@@ -0,0 +1,150 @@ ++/* ++ * Device Tree overlay for rpi-display by Watterott ++ * ++ */ ++ ++/dts-v1/; ++/plugin/; ++ ++/ { ++ compatible = "brcm,bcm2835"; ++ ++ fragment@0 { ++ target = <&spi0>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@1 { ++ target = <&spidev0>; ++ __overlay__ { ++ status = "disabled"; ++ }; ++ }; ++ ++ fragment@2 { ++ target = <&spidev1>; ++ __overlay__ { ++ status = "disabled"; ++ }; ++ }; ++ ++ fragment@3 { ++ target = <&gpio>; ++ __overlay__ { ++ rpi_display_pins: rpi_display_pins { ++ brcm,pins = <18 23 24 25>; ++ brcm,function = <1 1 1 0>; /* out out out in */ ++ brcm,pull = <0 0 0 2>; /* - - - up */ ++ }; ++ }; ++ }; ++ ++ fragment@4 { ++ target = <&spi0>; ++ __overlay__ { ++ /* needed to avoid dtc warning */ ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ rpidisplay: rpi-display@0{ ++ compatible = "ilitek,ili9341"; ++ reg = <0>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&rpi_display_pins>; ++ ++ spi-max-frequency = <32000000>; ++ rotate = <270>; ++ bgr; ++ fps = <30>; ++ buswidth = <8>; ++ reset-gpios = <&gpio 23 1>; ++ dc-gpios = <&gpio 24 0>; ++ led-gpios = <&gpio 18 0>; ++ debug = <0>; ++ }; ++ ++ rpidisplay_ts: rpi-display-ts@1 { ++ compatible = "ti,ads7846"; ++ reg = <1>; ++ ++ spi-max-frequency = <2000000>; ++ interrupts = <25 2>; /* high-to-low edge triggered */ ++ interrupt-parent = <&gpio>; ++ pendown-gpio = <&gpio 25 1>; ++ ti,x-plate-ohms = /bits/ 16 <60>; ++ ti,pressure-max = /bits/ 16 <255>; ++ }; ++ }; ++ }; ++ ++ fragment@10 { ++ target = <&rpidisplay>; ++ __dormant__ { ++ backlight = <&backlight_gpio>; ++ }; ++ }; ++ ++ fragment@11 { ++ target-path = "/"; ++ __dormant__ { ++ backlight_gpio: backlight_gpio { ++ compatible = "gpio-backlight"; ++ gpios = <&gpio 18 0>; /* GPIO_ACTIVE_HIGH */ ++ }; ++ }; ++ }; ++ ++ fragment@20 { ++ target = <&rpidisplay>; ++ __dormant__ { ++ backlight = <&backlight_pwm>; ++ }; ++ }; ++ ++ fragment@21 { ++ target-path = "/"; ++ __dormant__ { ++ backlight_pwm: backlight_pwm { ++ compatible = "pwm-backlight"; ++ brightness-levels = <0 6 8 12 16 24 32 40 48 64 96 128 160 192 224 255>; ++ default-brightness-level = <16>; ++ pwms = <&pwm 0 200000 0>; ++ }; ++ }; ++ }; ++ ++ fragment@22 { ++ target = <&pwm>; ++ __dormant__ { ++ assigned-clock-rates = <1000000>; ++ status = "okay"; ++ }; ++ }; ++ ++ fragment@23 { ++ target = <&chosen>; ++ __dormant__ { ++ bootargs = "snd_bcm2835.enable_headphones=0"; ++ }; ++ }; ++ ++ __overrides__ { ++ speed = <&rpidisplay>,"spi-max-frequency:0"; ++ rotate = <&rpidisplay>,"rotate:0", /* fbtft */ ++ <&rpidisplay>,"rotation:0"; /* drm */ ++ fps = <&rpidisplay>,"fps:0"; ++ debug = <&rpidisplay>,"debug:0"; ++ xohms = <&rpidisplay_ts>,"ti,x-plate-ohms;0"; ++ swapxy = <&rpidisplay_ts>,"ti,swap-xy?"; ++ backlight = <&rpidisplay>,"led-gpios:4", ++ <&rpi_display_pins>,"brcm,pins:0"; ++ drm = <&rpidisplay>, "compatible=multi-inno,mi0283qt", ++ <&rpidisplay>, "spi-max-frequency:0=70000000", ++ <&rpidisplay>, "reset-gpios:8=0", /* GPIO_ACTIVE_HIGH */ ++ <0>, "+10+11"; ++ backlight-pwm = <0>, "-10-11+20+21+22+23", ++ <&rpi_display_pins>, "brcm,function:0=2"; /* Alt5 */ ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlays/waveshare-can-fd-hat-mode-a-overlay.dts b/arch/arm/boot/dts/overlays/waveshare-can-fd-hat-mode-a-overlay.dts +new file mode 100644 +index 000000000000..59388cc3b0b9 +--- /dev/null ++++ b/arch/arm/boot/dts/overlays/waveshare-can-fd-hat-mode-a-overlay.dts +@@ -0,0 +1,140 @@ ++// redo: ovmerge -c spi1-1cs-overlay.dts,cs0_pin=26,cs0_spidev=false mcp251xfd-overlay.dts,spi0-0,interrupt=25 mcp251xfd-overlay.dts,spi1-0,interrupt=16 ++ ++// Device tree overlay for https://www.waveshare.com/2-ch-can-fd-hat.htm ++// in "Mode A" (default) configuration ++// for details see https://www.waveshare.com/wiki/2-CH_CAN_FD_HAT ++ ++/dts-v1/; ++/plugin/; ++ ++#include ++#include ++#include ++ ++/ { ++ compatible = "brcm,bcm2835"; ++ fragment@0 { ++ target = <&gpio>; ++ __overlay__ { ++ spi1_pins: spi1_pins { ++ brcm,pins = <19 20 21>; ++ brcm,function = <3>; ++ }; ++ spi1_cs_pins: spi1_cs_pins { ++ brcm,pins = <26>; ++ brcm,function = <1>; ++ }; ++ }; ++ }; ++ fragment@1 { ++ target = <&spi1>; ++ __overlay__ { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi1_pins &spi1_cs_pins>; ++ cs-gpios = <&gpio 26 1>; ++ status = "okay"; ++ spidev@0 { ++ compatible = "spidev"; ++ reg = <0>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ spi-max-frequency = <125000000>; ++ status = "disabled"; ++ }; ++ }; ++ }; ++ fragment@2 { ++ target = <&aux>; ++ __overlay__ { ++ status = "okay"; ++ }; ++ }; ++ fragment@3 { ++ target = <&spidev0>; ++ __overlay__ { ++ status = "disabled"; ++ }; ++ }; ++ fragment@4 { ++ target = <&gpio>; ++ __overlay__ { ++ mcp251xfd_pins: mcp251xfd_spi0_0_pins { ++ brcm,pins = <25>; ++ brcm,function = ; ++ }; ++ }; ++ }; ++ fragment@5 { ++ target-path = "/clocks"; ++ __overlay__ { ++ clk_mcp251xfd_osc: mcp251xfd-spi0-0-osc { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <40000000>; ++ }; ++ }; ++ }; ++ fragment@6 { ++ target = <&spi0>; ++ __overlay__ { ++ status = "okay"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ mcp251xfd@0 { ++ compatible = "microchip,mcp251xfd"; ++ reg = <0>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&mcp251xfd_pins>; ++ spi-max-frequency = <20000000>; ++ interrupt-parent = <&gpio>; ++ interrupts = <25 IRQ_TYPE_LEVEL_LOW>; ++ clocks = <&clk_mcp251xfd_osc>; ++ }; ++ }; ++ }; ++ fragment@7 { ++ target-path = "spi1/spidev@0"; ++ __overlay__ { ++ status = "disabled"; ++ }; ++ }; ++ fragment@8 { ++ target = <&gpio>; ++ __overlay__ { ++ mcp251xfd_pins_1: mcp251xfd_spi1_0_pins { ++ brcm,pins = <16>; ++ brcm,function = ; ++ }; ++ }; ++ }; ++ fragment@9 { ++ target-path = "/clocks"; ++ __overlay__ { ++ clk_mcp251xfd_osc_1: mcp251xfd-spi1-0-osc { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <40000000>; ++ }; ++ }; ++ }; ++ fragment@10 { ++ target = <&spi1>; ++ __overlay__ { ++ status = "okay"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ mcp251xfd@0 { ++ compatible = "microchip,mcp251xfd"; ++ reg = <0>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&mcp251xfd_pins_1>; ++ spi-max-frequency = <20000000>; ++ interrupt-parent = <&gpio>; ++ interrupts = <16 IRQ_TYPE_LEVEL_LOW>; ++ clocks = <&clk_mcp251xfd_osc_1>; ++ }; ++ }; ++ }; ++}; +diff --git a/arch/arm/boot/dts/overlays/waveshare-can-fd-hat-mode-b-overlay.dts b/arch/arm/boot/dts/overlays/waveshare-can-fd-hat-mode-b-overlay.dts +new file mode 100644 +index 000000000000..b2504922c8de +--- /dev/null ++++ b/arch/arm/boot/dts/overlays/waveshare-can-fd-hat-mode-b-overlay.dts +@@ -0,0 +1,103 @@ ++// redo: ovmerge -c mcp251xfd-overlay.dts,spi0-0,interrupt=25 mcp251xfd-overlay.dts,spi0-1,interrupt=16 ++ ++// Device tree overlay for https://www.waveshare.com/2-ch-can-fd-hat.htm ++// in "Mode B" (requried hardware modification) configuration ++// for details see https://www.waveshare.com/wiki/2-CH_CAN_FD_HAT ++ ++ ++/dts-v1/; ++/plugin/; ++ ++#include ++#include ++#include ++ ++/ { ++ compatible = "brcm,bcm2835"; ++ fragment@0 { ++ target = <&spidev0>; ++ __overlay__ { ++ status = "disabled"; ++ }; ++ }; ++ fragment@1 { ++ target = <&gpio>; ++ __overlay__ { ++ mcp251xfd_pins: mcp251xfd_spi0_0_pins { ++ brcm,pins = <25>; ++ brcm,function = ; ++ }; ++ }; ++ }; ++ fragment@2 { ++ target-path = "/clocks"; ++ __overlay__ { ++ clk_mcp251xfd_osc: mcp251xfd-spi0-0-osc { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <40000000>; ++ }; ++ }; ++ }; ++ fragment@3 { ++ target = <&spi0>; ++ __overlay__ { ++ status = "okay"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ mcp251xfd@0 { ++ compatible = "microchip,mcp251xfd"; ++ reg = <0>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&mcp251xfd_pins>; ++ spi-max-frequency = <20000000>; ++ interrupt-parent = <&gpio>; ++ interrupts = <25 IRQ_TYPE_LEVEL_LOW>; ++ clocks = <&clk_mcp251xfd_osc>; ++ }; ++ }; ++ }; ++ fragment@4 { ++ target = <&spidev1>; ++ __overlay__ { ++ status = "disabled"; ++ }; ++ }; ++ fragment@5 { ++ target = <&gpio>; ++ __overlay__ { ++ mcp251xfd_pins_1: mcp251xfd_spi0_1_pins { ++ brcm,pins = <16>; ++ brcm,function = ; ++ }; ++ }; ++ }; ++ fragment@6 { ++ target-path = "/clocks"; ++ __overlay__ { ++ clk_mcp251xfd_osc_1: mcp251xfd-spi0-1-osc { ++ #clock-cells = <0>; ++ compatible = "fixed-clock"; ++ clock-frequency = <40000000>; ++ }; ++ }; ++ }; ++ fragment@7 { ++ target = <&spi0>; ++ __overlay__ { ++ status = "okay"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ mcp251xfd@1 { ++ compatible = "microchip,mcp251xfd"; ++ reg = <1>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&mcp251xfd_pins_1>; ++ spi-max-frequency = <20000000>; ++ interrupt-parent = <&gpio>; ++ interrupts = <16 IRQ_TYPE_LEVEL_LOW>; ++ clocks = <&clk_mcp251xfd_osc_1>; ++ }; ++ }; ++ }; ++}; diff --git a/arch/arm/boot/dts/overlays/wittypi-overlay.dts b/arch/arm/boot/dts/overlays/wittypi-overlay.dts new file mode 100644 index 000000000000..71ce806186de @@ -35980,7 +51200,7 @@ index 000000000000..71ce806186de +}; diff --git a/arch/arm/boot/dts/overlays/wm8960-soundcard-overlay.dts b/arch/arm/boot/dts/overlays/wm8960-soundcard-overlay.dts new file mode 100644 -index 000000000000..289fa4dacdf1 +index 000000000000..3dd0b384079d --- /dev/null +++ b/arch/arm/boot/dts/overlays/wm8960-soundcard-overlay.dts @@ -0,0 +1,82 @@ @@ -35992,7 +51212,7 @@ index 000000000000..289fa4dacdf1 + compatible = "brcm,bcm2835"; + + fragment@0 { -+ target = <&i2s>; ++ target = <&i2s_clk_producer>; + __overlay__ { + status = "okay"; + }; @@ -36051,7 +51271,7 @@ index 000000000000..289fa4dacdf1 + "RINPUT2", "Mic Jack"; + + simple-audio-card,cpu { -+ sound-dai = <&i2s>; ++ sound-dai = <&i2s_clk_producer>; + }; + dailink0_slave: simple-audio-card,codec { + sound-dai = <&wm8960>; @@ -36068,10 +51288,10 @@ index 000000000000..289fa4dacdf1 +}; diff --git a/arch/arm/configs/bcm2709_defconfig b/arch/arm/configs/bcm2709_defconfig new file mode 100644 -index 000000000000..f2074da8a80d +index 000000000000..a45c2db93d69 --- /dev/null +++ b/arch/arm/configs/bcm2709_defconfig -@@ -0,0 +1,1533 @@ +@@ -0,0 +1,1583 @@ +CONFIG_LOCALVERSION="-v7" +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_SYSVIPC=y @@ -36079,6 +51299,7 @@ index 000000000000..f2074da8a80d +CONFIG_GENERIC_IRQ_DEBUGFS=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y ++CONFIG_BPF_SYSCALL=y +CONFIG_PREEMPT_VOLUNTARY=y +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_BSD_PROCESS_ACCT_V3=y @@ -36086,6 +51307,8 @@ index 000000000000..f2074da8a80d +CONFIG_TASK_DELAY_ACCT=y +CONFIG_TASK_XACCT=y +CONFIG_TASK_IO_ACCOUNTING=y ++CONFIG_PSI=y ++CONFIG_PSI_DEFAULT_DISABLED=y +CONFIG_IKCONFIG=m +CONFIG_IKCONFIG_PROC=y +CONFIG_MEMCG=y @@ -36102,9 +51325,7 @@ index 000000000000..f2074da8a80d +CONFIG_USER_NS=y +CONFIG_SCHED_AUTOGROUP=y +CONFIG_BLK_DEV_INITRD=y -+CONFIG_BPF_SYSCALL=y -+CONFIG_EMBEDDED=y -+# CONFIG_COMPAT_BRK is not set ++CONFIG_EXPERT=y +CONFIG_PROFILING=y +CONFIG_ARCH_BCM=y +CONFIG_ARCH_BCM2835=y @@ -36130,31 +51351,28 @@ index 000000000000..f2074da8a80d +CONFIG_KERNEL_MODE_NEON=y +# CONFIG_SUSPEND is not set +CONFIG_PM=y -+CONFIG_RASPBERRYPI_FIRMWARE=y -+CONFIG_CRYPTO_SHA1_ARM_NEON=m -+CONFIG_CRYPTO_AES_ARM=m -+CONFIG_CRYPTO_AES_ARM_BS=m -+CONFIG_OPROFILE=m +CONFIG_JUMP_LABEL=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODVERSIONS=y +CONFIG_MODULE_SRCVERSION_ALL=y ++CONFIG_MODULE_COMPRESS_XZ=y +CONFIG_PARTITION_ADVANCED=y +CONFIG_MAC_PARTITION=y +CONFIG_BINFMT_MISC=m -+CONFIG_CLEANCACHE=y -+CONFIG_FRONTSWAP=y -+CONFIG_CMA=y +CONFIG_ZSWAP=y +CONFIG_Z3FOLD=m -+CONFIG_ZSMALLOC=m ++# CONFIG_COMPAT_BRK is not set ++CONFIG_CMA=y ++CONFIG_LRU_GEN=y ++CONFIG_LRU_GEN_ENABLED=y +CONFIG_NET=y +CONFIG_PACKET=y -+CONFIG_UNIX=y +CONFIG_XFRM_USER=y ++CONFIG_XFRM_INTERFACE=m ++CONFIG_XFRM_SUB_POLICY=y ++CONFIG_XFRM_STATISTICS=y +CONFIG_NET_KEY=m -+CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_ADVANCED_ROUTER=y +CONFIG_IP_MULTIPLE_TABLES=y @@ -36197,7 +51415,6 @@ index 000000000000..f2074da8a80d +CONFIG_NETFILTER=y +CONFIG_BRIDGE_NETFILTER=m +CONFIG_NF_CONNTRACK=m -+CONFIG_NF_LOG_NETDEV=m +CONFIG_NF_CONNTRACK_ZONES=y +CONFIG_NF_CONNTRACK_EVENTS=y +CONFIG_NF_CONNTRACK_TIMESTAMP=y @@ -36218,7 +51435,6 @@ index 000000000000..f2074da8a80d +CONFIG_NFT_NUMGEN=m +CONFIG_NFT_CT=m +CONFIG_NFT_FLOW_OFFLOAD=m -+CONFIG_NFT_COUNTER=m +CONFIG_NFT_CONNLIMIT=m +CONFIG_NFT_LOG=m +CONFIG_NFT_LIMIT=m @@ -36226,16 +51442,17 @@ index 000000000000..f2074da8a80d +CONFIG_NFT_REDIR=m +CONFIG_NFT_NAT=m +CONFIG_NFT_TUNNEL=m -+CONFIG_NFT_OBJREF=m +CONFIG_NFT_QUEUE=m +CONFIG_NFT_QUOTA=m +CONFIG_NFT_REJECT=m +CONFIG_NFT_COMPAT=m +CONFIG_NFT_HASH=m +CONFIG_NFT_FIB_INET=m ++CONFIG_NFT_XFRM=m +CONFIG_NFT_SOCKET=m +CONFIG_NFT_OSF=m +CONFIG_NFT_TPROXY=m ++CONFIG_NFT_SYNPROXY=m +CONFIG_NFT_DUP_NETDEV=m +CONFIG_NFT_FWD_NETDEV=m +CONFIG_NFT_FIB_NETDEV=m @@ -36312,6 +51529,7 @@ index 000000000000..f2074da8a80d +CONFIG_IP_SET_HASH_NETIFACE=m +CONFIG_IP_SET_LIST_SET=m +CONFIG_IP_VS=m ++CONFIG_IP_VS_IPV6=y +CONFIG_IP_VS_PROTO_TCP=y +CONFIG_IP_VS_PROTO_UDP=y +CONFIG_IP_VS_PROTO_ESP=y @@ -36332,8 +51550,8 @@ index 000000000000..f2074da8a80d +CONFIG_NFT_DUP_IPV4=m +CONFIG_NFT_FIB_IPV4=m +CONFIG_NF_TABLES_ARP=y -+CONFIG_NF_FLOW_TABLE_IPV4=m +CONFIG_NF_LOG_ARP=m ++CONFIG_NF_LOG_IPV4=m +CONFIG_IP_NF_IPTABLES=m +CONFIG_IP_NF_MATCH_AH=m +CONFIG_IP_NF_MATCH_ECN=m @@ -36346,7 +51564,6 @@ index 000000000000..f2074da8a80d +CONFIG_IP_NF_TARGET_NETMAP=m +CONFIG_IP_NF_TARGET_REDIRECT=m +CONFIG_IP_NF_MANGLE=m -+CONFIG_IP_NF_TARGET_CLUSTERIP=m +CONFIG_IP_NF_TARGET_ECN=m +CONFIG_IP_NF_TARGET_TTL=m +CONFIG_IP_NF_RAW=m @@ -36355,7 +51572,6 @@ index 000000000000..f2074da8a80d +CONFIG_IP_NF_ARP_MANGLE=m +CONFIG_NFT_DUP_IPV6=m +CONFIG_NFT_FIB_IPV6=m -+CONFIG_NF_FLOW_TABLE_IPV6=m +CONFIG_IP6_NF_IPTABLES=m +CONFIG_IP6_NF_MATCH_AH=m +CONFIG_IP6_NF_MATCH_EUI64=m @@ -36379,7 +51595,6 @@ index 000000000000..f2074da8a80d +CONFIG_IP6_NF_TARGET_NPT=m +CONFIG_NF_TABLES_BRIDGE=m +CONFIG_NFT_BRIDGE_REJECT=m -+CONFIG_NF_LOG_BRIDGE=m +CONFIG_BRIDGE_NF_EBTABLES=m +CONFIG_BRIDGE_EBT_BROUTE=m +CONFIG_BRIDGE_EBT_T_FILTER=m @@ -36416,10 +51631,8 @@ index 000000000000..f2074da8a80d +CONFIG_IEEE802154_6LOWPAN=m +CONFIG_MAC802154=m +CONFIG_NET_SCHED=y -+CONFIG_NET_SCH_CBQ=m +CONFIG_NET_SCH_HTB=m +CONFIG_NET_SCH_HFSC=m -+CONFIG_NET_SCH_ATM=m +CONFIG_NET_SCH_PRIO=m +CONFIG_NET_SCH_MULTIQ=m +CONFIG_NET_SCH_RED=m @@ -36428,7 +51641,6 @@ index 000000000000..f2074da8a80d +CONFIG_NET_SCH_TEQL=m +CONFIG_NET_SCH_TBF=m +CONFIG_NET_SCH_GRED=m -+CONFIG_NET_SCH_DSMARK=m +CONFIG_NET_SCH_NETEM=m +CONFIG_NET_SCH_DRR=m +CONFIG_NET_SCH_MQPRIO=m @@ -36443,13 +51655,10 @@ index 000000000000..f2074da8a80d +CONFIG_NET_SCH_INGRESS=m +CONFIG_NET_SCH_PLUG=m +CONFIG_NET_CLS_BASIC=m -+CONFIG_NET_CLS_TCINDEX=m +CONFIG_NET_CLS_ROUTE4=m +CONFIG_NET_CLS_FW=m +CONFIG_NET_CLS_U32=m +CONFIG_CLS_U32_MARK=y -+CONFIG_NET_CLS_RSVP=m -+CONFIG_NET_CLS_RSVP6=m +CONFIG_NET_CLS_FLOW=m +CONFIG_NET_CLS_CGROUP=m +CONFIG_NET_EMATCH=y @@ -36487,13 +51696,6 @@ index 000000000000..f2074da8a80d +CONFIG_CAN=m +CONFIG_CAN_J1939=m +CONFIG_CAN_ISOTP=m -+CONFIG_CAN_VCAN=m -+CONFIG_CAN_SLCAN=m -+CONFIG_CAN_MCP251X=m -+CONFIG_CAN_MCP251XFD=m -+CONFIG_CAN_EMS_USB=m -+CONFIG_CAN_GS_USB=m -+CONFIG_CAN_PEAK_USB=m +CONFIG_BT=m +CONFIG_BT_RFCOMM=m +CONFIG_BT_RFCOMM_TTY=y @@ -36517,7 +51719,6 @@ index 000000000000..f2074da8a80d +CONFIG_CFG80211_WEXT=y +CONFIG_MAC80211=m +CONFIG_MAC80211_MESH=y -+CONFIG_WIMAX=m +CONFIG_RFKILL=m +CONFIG_RFKILL_INPUT=y +CONFIG_NET_9P=m @@ -36525,21 +51726,22 @@ index 000000000000..f2074da8a80d +CONFIG_UEVENT_HELPER=y +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y ++CONFIG_RASPBERRYPI_FIRMWARE=y +CONFIG_MTD=m +CONFIG_MTD_BLOCK=m +CONFIG_MTD_BLOCK2MTD=m ++CONFIG_MTD_SPI_NAND=m +CONFIG_MTD_SPI_NOR=m +CONFIG_MTD_UBI=m +CONFIG_OF_CONFIGFS=y +CONFIG_ZRAM=m +CONFIG_BLK_DEV_LOOP=y -+CONFIG_BLK_DEV_CRYPTOLOOP=m +CONFIG_BLK_DEV_DRBD=m +CONFIG_BLK_DEV_NBD=m +CONFIG_BLK_DEV_RAM=y -+CONFIG_CDROM_PKTCDVD=m +CONFIG_ATA_OVER_ETH=m +CONFIG_EEPROM_AT24=m ++CONFIG_EEPROM_AT25=m +CONFIG_TI_ST=m +CONFIG_SCSI=y +# CONFIG_SCSI_PROC_FS is not set @@ -36550,6 +51752,7 @@ index 000000000000..f2074da8a80d +CONFIG_SCSI_ISCSI_ATTRS=y +CONFIG_ISCSI_TCP=m +CONFIG_ISCSI_BOOT_SYSFS=m ++CONFIG_ATA=m +CONFIG_MD=y +CONFIG_MD_LINEAR=m +CONFIG_BLK_DEV_DM=m @@ -36561,7 +51764,9 @@ index 000000000000..f2074da8a80d +CONFIG_DM_LOG_USERSPACE=m +CONFIG_DM_RAID=m +CONFIG_DM_ZERO=m ++CONFIG_DM_MULTIPATH=m +CONFIG_DM_DELAY=m ++CONFIG_DM_INTEGRITY=m +CONFIG_NETDEVICES=y +CONFIG_BONDING=m +CONFIG_DUMMY=m @@ -36579,6 +51784,14 @@ index 000000000000..f2074da8a80d +CONFIG_QCA7000_UART=m +CONFIG_WIZNET_W5100=m +CONFIG_WIZNET_W5100_SPI=m ++CONFIG_CAN_VCAN=m ++CONFIG_CAN_SLCAN=m ++CONFIG_CAN_MCP251X=m ++CONFIG_CAN_MCP251XFD=m ++CONFIG_CAN_8DEV_USB=m ++CONFIG_CAN_EMS_USB=m ++CONFIG_CAN_GS_USB=m ++CONFIG_CAN_PEAK_USB=m +CONFIG_MDIO_BITBANG=m +CONFIG_PPP=m +CONFIG_PPP_BSDCOMP=m @@ -36658,6 +51871,7 @@ index 000000000000..f2074da8a80d +CONFIG_MT7601U=m +CONFIG_MT76x0U=m +CONFIG_MT76x2U=m ++CONFIG_MT7921U=m +CONFIG_RT2X00=m +CONFIG_RT2500USB=m +CONFIG_RT73USB=m @@ -36669,11 +51883,15 @@ index 000000000000..f2074da8a80d +CONFIG_RTL8187=m +CONFIG_RTL8192CU=m +CONFIG_RTL8XXXU=m ++CONFIG_RTW88=m ++CONFIG_RTW88_8822BU=m ++CONFIG_RTW88_8822CU=m ++CONFIG_RTW88_8723DU=m ++CONFIG_RTW88_8821CU=m +CONFIG_USB_ZD1201=m +CONFIG_ZD1211RW=m -+CONFIG_MAC80211_HWSIM=m +CONFIG_USB_NET_RNDIS_WLAN=m -+CONFIG_WIMAX_I2400M_USB=m ++CONFIG_MAC80211_HWSIM=m +CONFIG_IEEE802154_AT86RF230=m +CONFIG_IEEE802154_MRF24J40=m +CONFIG_IEEE802154_CC2520=m @@ -36695,6 +51913,7 @@ index 000000000000..f2074da8a80d +CONFIG_JOYSTICK_XPAD_LEDS=y +CONFIG_JOYSTICK_PSXPAD_SPI=m +CONFIG_JOYSTICK_PSXPAD_SPI_FF=y ++CONFIG_JOYSTICK_FSIA6B=m +CONFIG_JOYSTICK_RPISENSE=m +CONFIG_INPUT_TOUCHSCREEN=y +CONFIG_TOUCHSCREEN_ADS7846=m @@ -36705,7 +51924,10 @@ index 000000000000..f2074da8a80d +CONFIG_TOUCHSCREEN_EDT_FT5X06=m +CONFIG_TOUCHSCREEN_RASPBERRYPI_FW=m +CONFIG_TOUCHSCREEN_USB_COMPOSITE=m ++CONFIG_TOUCHSCREEN_TSC2007=m ++CONFIG_TOUCHSCREEN_TSC2007_IIO=y +CONFIG_TOUCHSCREEN_STMPE=m ++CONFIG_TOUCHSCREEN_IQS5XX=m +CONFIG_INPUT_MISC=y +CONFIG_INPUT_AD714X=m +CONFIG_INPUT_ATI_REMOTE2=m @@ -36720,11 +51942,8 @@ index 000000000000..f2074da8a80d +CONFIG_SERIO=m +CONFIG_SERIO_RAW=m +CONFIG_GAMEPORT=m -+CONFIG_GAMEPORT_NS558=m -+CONFIG_GAMEPORT_L4=m +CONFIG_BRCM_CHAR_DRIVERS=y +CONFIG_BCM_VCIO=y -+CONFIG_BCM2835_DEVGPIOMEM=y +# CONFIG_LEGACY_PTYS is not set +CONFIG_SERIAL_8250=y +# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set @@ -36743,10 +51962,10 @@ index 000000000000..f2074da8a80d +CONFIG_SERIAL_DEV_BUS=y +CONFIG_TTY_PRINTK=y +CONFIG_HW_RANDOM=y -+CONFIG_RAW_DRIVER=y +CONFIG_TCG_TPM=m +CONFIG_TCG_TIS_SPI=m -+CONFIG_RANDOM_TRUST_BOOTLOADER=y ++CONFIG_TCG_TIS_I2C=m ++CONFIG_RASPBERRYPI_GPIOMEM=m +CONFIG_I2C=y +CONFIG_I2C_CHARDEV=m +CONFIG_I2C_MUX_GPMUX=m @@ -36764,23 +51983,23 @@ index 000000000000..f2074da8a80d +CONFIG_SPI_GPIO=m +CONFIG_SPI_SPIDEV=m +CONFIG_SPI_SLAVE=y -+CONFIG_PPS=m +CONFIG_PPS_CLIENT_LDISC=m +CONFIG_PPS_CLIENT_GPIO=m +CONFIG_PINCTRL_MCP23S08=m +CONFIG_GPIO_SYSFS=y +CONFIG_GPIO_BCM_VIRT=y ++CONFIG_GPIO_MAX7300=m +CONFIG_GPIO_PCA953X=m +CONFIG_GPIO_PCA953X_IRQ=y +CONFIG_GPIO_PCF857X=m +CONFIG_GPIO_ARIZONA=m +CONFIG_GPIO_FSM=m +CONFIG_GPIO_STMPE=y ++CONFIG_GPIO_MAX7301=m +CONFIG_GPIO_MOCKUP=m +CONFIG_W1=m +CONFIG_W1_MASTER_DS2490=m +CONFIG_W1_MASTER_DS2482=m -+CONFIG_W1_MASTER_DS1WM=m +CONFIG_W1_MASTER_GPIO=m +CONFIG_W1_SLAVE_THERM=m +CONFIG_W1_SLAVE_SMEM=m @@ -36800,24 +52019,30 @@ index 000000000000..f2074da8a80d +CONFIG_RPI_POE_POWER=m +CONFIG_BATTERY_DS2760=m +CONFIG_BATTERY_MAX17040=m ++CONFIG_CHARGER_GPIO=m +CONFIG_BATTERY_GAUGE_LTC2941=m ++CONFIG_SENSORS_ADT7410=m ++CONFIG_SENSORS_AHT10=m ++CONFIG_SENSORS_DRIVETEMP=m +CONFIG_SENSORS_DS1621=m +CONFIG_SENSORS_GPIO_FAN=m +CONFIG_SENSORS_IIO_HWMON=m +CONFIG_SENSORS_JC42=m +CONFIG_SENSORS_LM75=m ++CONFIG_SENSORS_PWM_FAN=m +CONFIG_SENSORS_RASPBERRYPI_HWMON=m -+CONFIG_SENSORS_RPI_POE_FAN=m +CONFIG_SENSORS_SHT21=m +CONFIG_SENSORS_SHT3x=m ++CONFIG_SENSORS_SHT4x=m +CONFIG_SENSORS_SHTC1=m ++CONFIG_SENSORS_EMC2305=m +CONFIG_SENSORS_INA2XX=m +CONFIG_SENSORS_TMP102=m -+CONFIG_THERMAL=y +CONFIG_BCM2835_THERMAL=y +CONFIG_WATCHDOG=y +CONFIG_GPIO_WATCHDOG=m +CONFIG_BCM2835_WDT=y ++CONFIG_MFD_RASPBERRYPI_POE_HAT=m +CONFIG_MFD_STMPE=y +CONFIG_STMPE_SPI=y +CONFIG_MFD_ARIZONA_I2C=m @@ -36828,40 +52053,38 @@ index 000000000000..f2074da8a80d +CONFIG_REGULATOR_ARIZONA_LDO1=m +CONFIG_REGULATOR_ARIZONA_MICSUPP=m +CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_ATTINY=m ++CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_V2=m +CONFIG_RC_CORE=y -+CONFIG_LIRC=y +CONFIG_BPF_LIRC_MODE2=y ++CONFIG_LIRC=y +CONFIG_RC_DECODERS=y ++CONFIG_IR_IMON_DECODER=m ++CONFIG_IR_JVC_DECODER=m ++CONFIG_IR_MCE_KBD_DECODER=m +CONFIG_IR_NEC_DECODER=m +CONFIG_IR_RC5_DECODER=m +CONFIG_IR_RC6_DECODER=m -+CONFIG_IR_JVC_DECODER=m -+CONFIG_IR_SONY_DECODER=m +CONFIG_IR_SANYO_DECODER=m +CONFIG_IR_SHARP_DECODER=m -+CONFIG_IR_MCE_KBD_DECODER=m ++CONFIG_IR_SONY_DECODER=m +CONFIG_IR_XMP_DECODER=m -+CONFIG_IR_IMON_DECODER=m +CONFIG_RC_DEVICES=y -+CONFIG_RC_ATI_REMOTE=m -+CONFIG_IR_IMON=m -+CONFIG_IR_MCEUSB=m -+CONFIG_IR_REDRAT3=m -+CONFIG_IR_STREAMZAP=m -+CONFIG_IR_IGUANA=m -+CONFIG_IR_TTUSBIR=m -+CONFIG_RC_LOOPBACK=m +CONFIG_IR_GPIO_CIR=m +CONFIG_IR_GPIO_TX=m ++CONFIG_IR_IGUANA=m ++CONFIG_IR_IMON=m ++CONFIG_IR_MCEUSB=m +CONFIG_IR_PWM_TX=m ++CONFIG_IR_REDRAT3=m ++CONFIG_IR_STREAMZAP=m +CONFIG_IR_TOY=m ++CONFIG_IR_TTUSBIR=m ++CONFIG_RC_ATI_REMOTE=m ++CONFIG_RC_LOOPBACK=m +CONFIG_MEDIA_CEC_RC=y +CONFIG_MEDIA_SUPPORT=m +CONFIG_MEDIA_USB_SUPPORT=y -+CONFIG_USB_VIDEO_CLASS=m -+CONFIG_USB_M5602=m -+CONFIG_USB_STV06XX=m -+CONFIG_USB_GL860=m ++CONFIG_USB_GSPCA=m +CONFIG_USB_GSPCA_BENQ=m +CONFIG_USB_GSPCA_CONEX=m +CONFIG_USB_GSPCA_CPIA1=m @@ -36886,13 +52109,13 @@ index 000000000000..f2074da8a80d +CONFIG_USB_GSPCA_SN9C20X=m +CONFIG_USB_GSPCA_SONIXB=m +CONFIG_USB_GSPCA_SONIXJ=m ++CONFIG_USB_GSPCA_SPCA1528=m +CONFIG_USB_GSPCA_SPCA500=m +CONFIG_USB_GSPCA_SPCA501=m +CONFIG_USB_GSPCA_SPCA505=m +CONFIG_USB_GSPCA_SPCA506=m +CONFIG_USB_GSPCA_SPCA508=m +CONFIG_USB_GSPCA_SPCA561=m -+CONFIG_USB_GSPCA_SPCA1528=m +CONFIG_USB_GSPCA_SQ905=m +CONFIG_USB_GSPCA_SQ905C=m +CONFIG_USB_GSPCA_SQ930X=m @@ -36902,56 +52125,32 @@ index 000000000000..f2074da8a80d +CONFIG_USB_GSPCA_SUNPLUS=m +CONFIG_USB_GSPCA_T613=m +CONFIG_USB_GSPCA_TOPRO=m ++CONFIG_USB_GSPCA_TOUPTEK=m +CONFIG_USB_GSPCA_TV8532=m +CONFIG_USB_GSPCA_VC032X=m +CONFIG_USB_GSPCA_VICAM=m +CONFIG_USB_GSPCA_XIRLINK_CIT=m +CONFIG_USB_GSPCA_ZC3XX=m ++CONFIG_USB_GL860=m ++CONFIG_USB_M5602=m ++CONFIG_USB_STV06XX=m +CONFIG_USB_PWC=m -+CONFIG_VIDEO_CPIA2=m -+CONFIG_USB_ZR364XX=m -+CONFIG_USB_STKWEBCAM=m +CONFIG_USB_S2255=m +CONFIG_VIDEO_USBTV=m -+CONFIG_VIDEO_PVRUSB2=m -+CONFIG_VIDEO_HDPVR=m -+CONFIG_VIDEO_STK1160_COMMON=m ++CONFIG_USB_VIDEO_CLASS=m +CONFIG_VIDEO_GO7007=m +CONFIG_VIDEO_GO7007_USB=m +CONFIG_VIDEO_GO7007_USB_S2250_BOARD=m ++CONFIG_VIDEO_HDPVR=m ++CONFIG_VIDEO_PVRUSB2=m ++CONFIG_VIDEO_STK1160=m +CONFIG_VIDEO_AU0828=m +CONFIG_VIDEO_AU0828_RC=y +CONFIG_VIDEO_CX231XX=m +CONFIG_VIDEO_CX231XX_ALSA=m +CONFIG_VIDEO_CX231XX_DVB=m -+CONFIG_VIDEO_TM6000=m -+CONFIG_VIDEO_TM6000_ALSA=m -+CONFIG_VIDEO_TM6000_DVB=m -+CONFIG_DVB_USB=m -+CONFIG_DVB_USB_A800=m -+CONFIG_DVB_USB_DIBUSB_MB=m -+CONFIG_DVB_USB_DIBUSB_MB_FAULTY=y -+CONFIG_DVB_USB_DIBUSB_MC=m -+CONFIG_DVB_USB_DIB0700=m -+CONFIG_DVB_USB_UMT_010=m -+CONFIG_DVB_USB_CXUSB=m -+CONFIG_DVB_USB_M920X=m -+CONFIG_DVB_USB_DIGITV=m -+CONFIG_DVB_USB_VP7045=m -+CONFIG_DVB_USB_VP702X=m -+CONFIG_DVB_USB_GP8PSK=m -+CONFIG_DVB_USB_NOVA_T_USB2=m -+CONFIG_DVB_USB_TTUSB2=m -+CONFIG_DVB_USB_DTT200U=m -+CONFIG_DVB_USB_OPERA1=m -+CONFIG_DVB_USB_AF9005=m -+CONFIG_DVB_USB_AF9005_REMOTE=m -+CONFIG_DVB_USB_PCTV452E=m -+CONFIG_DVB_USB_DW2102=m -+CONFIG_DVB_USB_CINERGY_T2=m -+CONFIG_DVB_USB_DTV5100=m -+CONFIG_DVB_USB_AZ6027=m -+CONFIG_DVB_USB_TECHNISAT_USB2=m ++CONFIG_DVB_AS102=m ++CONFIG_DVB_B2C2_FLEXCOP_USB=m +CONFIG_DVB_USB_V2=m +CONFIG_DVB_USB_AF9015=m +CONFIG_DVB_USB_AF9035=m @@ -36959,68 +52158,113 @@ index 000000000000..f2074da8a80d +CONFIG_DVB_USB_AU6610=m +CONFIG_DVB_USB_AZ6007=m +CONFIG_DVB_USB_CE6230=m ++CONFIG_DVB_USB_DVBSKY=m +CONFIG_DVB_USB_EC168=m +CONFIG_DVB_USB_GL861=m +CONFIG_DVB_USB_LME2510=m +CONFIG_DVB_USB_MXL111SF=m +CONFIG_DVB_USB_RTL28XXU=m -+CONFIG_DVB_USB_DVBSKY=m ++CONFIG_DVB_USB=m ++CONFIG_DVB_USB_A800=m ++CONFIG_DVB_USB_AF9005=m ++CONFIG_DVB_USB_AF9005_REMOTE=m ++CONFIG_DVB_USB_AZ6027=m ++CONFIG_DVB_USB_CINERGY_T2=m ++CONFIG_DVB_USB_CXUSB=m ++CONFIG_DVB_USB_DIB0700=m ++CONFIG_DVB_USB_DIBUSB_MB=m ++CONFIG_DVB_USB_DIBUSB_MB_FAULTY=y ++CONFIG_DVB_USB_DIBUSB_MC=m ++CONFIG_DVB_USB_DIGITV=m ++CONFIG_DVB_USB_DTT200U=m ++CONFIG_DVB_USB_DTV5100=m ++CONFIG_DVB_USB_DW2102=m ++CONFIG_DVB_USB_GP8PSK=m ++CONFIG_DVB_USB_M920X=m ++CONFIG_DVB_USB_NOVA_T_USB2=m ++CONFIG_DVB_USB_OPERA1=m ++CONFIG_DVB_USB_PCTV452E=m ++CONFIG_DVB_USB_TECHNISAT_USB2=m ++CONFIG_DVB_USB_TTUSB2=m ++CONFIG_DVB_USB_UMT_010=m ++CONFIG_DVB_USB_VP702X=m ++CONFIG_DVB_USB_VP7045=m +CONFIG_SMS_USB_DRV=m -+CONFIG_DVB_B2C2_FLEXCOP_USB=m -+CONFIG_DVB_AS102=m +CONFIG_VIDEO_EM28XX=m +CONFIG_VIDEO_EM28XX_V4L2=m +CONFIG_VIDEO_EM28XX_ALSA=m +CONFIG_VIDEO_EM28XX_DVB=m ++CONFIG_RADIO_SAA7706H=m ++CONFIG_RADIO_SHARK=m ++CONFIG_RADIO_SHARK2=m ++CONFIG_RADIO_SI4713=m ++CONFIG_RADIO_TEA5764=m ++CONFIG_RADIO_TEF6862=m ++CONFIG_RADIO_WL1273=m ++CONFIG_USB_DSBR=m ++CONFIG_USB_KEENE=m ++CONFIG_USB_MA901=m ++CONFIG_USB_MR800=m +CONFIG_RADIO_SI470X=m +CONFIG_USB_SI470X=m +CONFIG_I2C_SI470X=m -+CONFIG_RADIO_SI4713=m +CONFIG_I2C_SI4713=m -+CONFIG_USB_MR800=m -+CONFIG_USB_DSBR=m -+CONFIG_RADIO_SHARK=m -+CONFIG_RADIO_SHARK2=m -+CONFIG_USB_KEENE=m -+CONFIG_USB_MA901=m -+CONFIG_RADIO_TEA5764=m -+CONFIG_RADIO_SAA7706H=m -+CONFIG_RADIO_TEF6862=m -+CONFIG_RADIO_WL1273=m +CONFIG_RADIO_WL128X=m +CONFIG_V4L_PLATFORM_DRIVERS=y ++CONFIG_VIDEO_MUX=m +CONFIG_VIDEO_BCM2835_UNICAM=m -+CONFIG_VIDEO_UDA1342=m ++CONFIG_VIDEO_ARDUCAM_64MP=m ++CONFIG_VIDEO_ARDUCAM_PIVARIETY=m ++CONFIG_VIDEO_IMX219=m ++CONFIG_VIDEO_IMX258=m ++CONFIG_VIDEO_IMX290=m ++CONFIG_VIDEO_IMX296=m ++CONFIG_VIDEO_IMX477=m ++CONFIG_VIDEO_IMX519=m ++CONFIG_VIDEO_IMX708=m ++CONFIG_VIDEO_MT9V011=m ++CONFIG_VIDEO_OV2311=m ++CONFIG_VIDEO_OV5647=m ++CONFIG_VIDEO_OV64A40=m ++CONFIG_VIDEO_OV7251=m ++CONFIG_VIDEO_OV7640=m ++CONFIG_VIDEO_OV9282=m ++CONFIG_VIDEO_AD5398=m ++CONFIG_VIDEO_AK7375=m ++CONFIG_VIDEO_BU64754=m ++CONFIG_VIDEO_DW9807_VCM=m +CONFIG_VIDEO_SONY_BTF_MPX=m ++CONFIG_VIDEO_UDA1342=m +CONFIG_VIDEO_ADV7180=m +CONFIG_VIDEO_TC358743=m +CONFIG_VIDEO_TVP5150=m +CONFIG_VIDEO_TW2804=m +CONFIG_VIDEO_TW9903=m +CONFIG_VIDEO_TW9906=m -+CONFIG_VIDEO_IMX219=m -+CONFIG_VIDEO_IMX290=m -+CONFIG_VIDEO_IMX477=m -+CONFIG_VIDEO_IMX519=m -+CONFIG_VIDEO_OV5647=m -+CONFIG_VIDEO_OV7251=m -+CONFIG_VIDEO_OV7640=m -+CONFIG_VIDEO_OV9281=m +CONFIG_VIDEO_IRS1125=m -+CONFIG_VIDEO_MT9V011=m ++CONFIG_VIDEO_I2C=m ++CONFIG_AUXDISPLAY=y ++CONFIG_HD44780=m +CONFIG_DRM=m +CONFIG_DRM_LOAD_EDID_FIRMWARE=y +CONFIG_DRM_UDL=m +CONFIG_DRM_PANEL_SIMPLE=m ++CONFIG_DRM_PANEL_ILITEK_ILI9806E=m +CONFIG_DRM_PANEL_JDI_LT070ME05000=m +CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN=m ++CONFIG_DRM_PANEL_SITRONIX_ST7701=m ++CONFIG_DRM_PANEL_TPO_Y17P=m ++CONFIG_DRM_PANEL_WAVESHARE_TOUCHSCREEN=m +CONFIG_DRM_DISPLAY_CONNECTOR=m +CONFIG_DRM_SIMPLE_BRIDGE=m +CONFIG_DRM_TOSHIBA_TC358762=m +CONFIG_DRM_VC4=m +CONFIG_DRM_VC4_HDMI_CEC=y ++CONFIG_DRM_PANEL_MIPI_DBI=m ++CONFIG_TINYDRM_HX8357D=m +CONFIG_TINYDRM_ILI9225=m +CONFIG_TINYDRM_ILI9341=m ++CONFIG_TINYDRM_ILI9486=m +CONFIG_TINYDRM_MI0283QT=m +CONFIG_TINYDRM_REPAPER=m +CONFIG_TINYDRM_ST7586=m @@ -37028,13 +52272,13 @@ index 000000000000..f2074da8a80d +CONFIG_DRM_GUD=m +CONFIG_FB=y +CONFIG_FB_BCM2708=y -+CONFIG_FB_UDL=m +CONFIG_FB_SIMPLE=y +CONFIG_FB_SSD1307=m +CONFIG_FB_RPISENSE=m ++CONFIG_BACKLIGHT_PWM=m +CONFIG_BACKLIGHT_RPI=m ++CONFIG_BACKLIGHT_LM3630A=m +CONFIG_BACKLIGHT_GPIO=m -+CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y +CONFIG_LOGO=y +# CONFIG_LOGO_LINUX_MONO is not set @@ -37044,6 +52288,7 @@ index 000000000000..f2074da8a80d +CONFIG_SND_OSSEMUL=y +CONFIG_SND_PCM_OSS=m +CONFIG_SND_HRTIMER=m ++CONFIG_SND_DYNAMIC_MINORS=y +CONFIG_SND_SEQUENCER=m +CONFIG_SND_SEQ_DUMMY=m +CONFIG_SND_DUMMY=m @@ -37098,6 +52343,7 @@ index 000000000000..f2074da8a80d +CONFIG_SND_BCM2708_SOC_ALLO_KATANA_DAC=m +CONFIG_SND_BCM2708_SOC_FE_PI_AUDIO=m +CONFIG_SND_PISOUND=m ++CONFIG_SND_DACBERRY400=m +CONFIG_SND_SOC_AD193X_SPI=m +CONFIG_SND_SOC_AD193X_I2C=m +CONFIG_SND_SOC_ADAU1701=m @@ -37108,6 +52354,7 @@ index 000000000000..f2074da8a80d +CONFIG_SND_SOC_MA120X0P=m +CONFIG_SND_SOC_MAX98357A=m +CONFIG_SND_SOC_SPDIF=m ++CONFIG_SND_SOC_TLV320AIC23_I2C=m +CONFIG_SND_SOC_WM8804_I2C=m +CONFIG_SND_SOC_WM8960=m +CONFIG_SND_SIMPLE_CARD=m @@ -37148,11 +52395,15 @@ index 000000000000..f2074da8a80d +CONFIG_HID_MICROSOFT=m +CONFIG_HID_MONTEREY=m +CONFIG_HID_MULTITOUCH=m ++CONFIG_HID_NINTENDO=m ++CONFIG_NINTENDO_FF=y +CONFIG_HID_NTRIG=m +CONFIG_HID_ORTEK=m +CONFIG_HID_PANTHERLORD=m +CONFIG_HID_PETALYNX=m +CONFIG_HID_PICOLCD=m ++CONFIG_HID_PLAYSTATION=m ++CONFIG_PLAYSTATION_FF=y +CONFIG_HID_ROCCAT=m +CONFIG_HID_SAMSUNG=m +CONFIG_HID_SONY=m @@ -37172,7 +52423,6 @@ index 000000000000..f2074da8a80d +CONFIG_HID_ZYDACRON=m +CONFIG_HID_PID=y +CONFIG_USB_HIDDEV=y -+CONFIG_I2C_HID=m +CONFIG_USB=y +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y +CONFIG_USB_MON=m @@ -37241,7 +52491,6 @@ index 000000000000..f2074da8a80d +CONFIG_USB_SERIAL_SYMBOL=m +CONFIG_USB_SERIAL_TI=m +CONFIG_USB_SERIAL_CYBERJACK=m -+CONFIG_USB_SERIAL_XIRCOM=m +CONFIG_USB_SERIAL_OPTION=m +CONFIG_USB_SERIAL_OMNINET=m +CONFIG_USB_SERIAL_OPTICON=m @@ -37259,7 +52508,6 @@ index 000000000000..f2074da8a80d +CONFIG_USB_CYPRESS_CY7C63=m +CONFIG_USB_CYTHERM=m +CONFIG_USB_IDMOUSE=m -+CONFIG_USB_FTDI_ELAN=m +CONFIG_USB_APPLEDISPLAY=m +CONFIG_USB_LD=m +CONFIG_USB_TRANCEVIBRATOR=m @@ -37272,7 +52520,8 @@ index 000000000000..f2074da8a80d +CONFIG_USB_CXACRU=m +CONFIG_USB_UEAGLEATM=m +CONFIG_USB_XUSBATM=m -+CONFIG_USB_GADGET=m ++CONFIG_NOP_USB_XCEIV=y ++CONFIG_USB_GADGET=y +CONFIG_USB_CONFIGFS=m +CONFIG_USB_CONFIGFS_SERIAL=y +CONFIG_USB_CONFIGFS_ACM=y @@ -37313,6 +52562,7 @@ index 000000000000..f2074da8a80d +CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MMC_SPI=m +CONFIG_LEDS_CLASS=y ++CONFIG_LEDS_CLASS_MULTICOLOR=m +CONFIG_LEDS_PCA9532=m +CONFIG_LEDS_GPIO=y +CONFIG_LEDS_PCA955X=m @@ -37324,7 +52574,6 @@ index 000000000000..f2074da8a80d +CONFIG_LEDS_TRIGGER_HEARTBEAT=y +CONFIG_LEDS_TRIGGER_BACKLIGHT=y +CONFIG_LEDS_TRIGGER_CPU=y -+CONFIG_LEDS_TRIGGER_GPIO=y +CONFIG_LEDS_TRIGGER_DEFAULT_ON=y +CONFIG_LEDS_TRIGGER_TRANSIENT=m +CONFIG_LEDS_TRIGGER_CAMERA=m @@ -37359,6 +52608,8 @@ index 000000000000..f2074da8a80d +CONFIG_RTC_DRV_RX8025=m +CONFIG_RTC_DRV_EM3027=m +CONFIG_RTC_DRV_RV3028=m ++CONFIG_RTC_DRV_RV3032=m ++CONFIG_RTC_DRV_RV8803=m +CONFIG_RTC_DRV_SD3078=m +CONFIG_RTC_DRV_M41T93=m +CONFIG_RTC_DRV_M41T94=m @@ -37379,16 +52630,14 @@ index 000000000000..f2074da8a80d +CONFIG_DMABUF_HEAPS=y +CONFIG_DMABUF_HEAPS_SYSTEM=y +CONFIG_DMABUF_HEAPS_CMA=y -+CONFIG_AUXDISPLAY=y -+CONFIG_HD44780=m +CONFIG_UIO=m +CONFIG_UIO_PDRV_GENIRQ=m +CONFIG_STAGING=y +CONFIG_PRISM2_USB=m +CONFIG_R8712U=m -+CONFIG_R8188EU=m +CONFIG_VT6656=m +CONFIG_STAGING_MEDIA=y ++CONFIG_STAGING_MEDIA_DEPRECATED=y +CONFIG_FB_TFT=m +CONFIG_FB_TFT_AGM1264K_FL=m +CONFIG_FB_TFT_BD663474=m @@ -37416,9 +52665,9 @@ index 000000000000..f2074da8a80d +CONFIG_FB_TFT_ST7789V=m +CONFIG_FB_TFT_TINYLCD=m +CONFIG_FB_TFT_TLS8204=m ++CONFIG_FB_TFT_UC1611=m +CONFIG_FB_TFT_UC1701=m +CONFIG_FB_TFT_UPD161704=m -+CONFIG_FB_TFT_WATTEROTT=m +CONFIG_BCM2835_VCHIQ=y +CONFIG_SND_BCM2835=m +CONFIG_VIDEO_BCM2835=m @@ -37429,32 +52678,40 @@ index 000000000000..f2074da8a80d +CONFIG_BCM2835_MBOX=y +# CONFIG_IOMMU_SUPPORT is not set +CONFIG_RASPBERRYPI_POWER=y -+CONFIG_EXTCON=m -+CONFIG_EXTCON_ARIZONA=m +CONFIG_IIO=m +CONFIG_IIO_BUFFER_CB=m ++CONFIG_IIO_SW_TRIGGER=m +CONFIG_MCP320X=m +CONFIG_MCP3422=m +CONFIG_TI_ADS1015=m +CONFIG_BME680=m +CONFIG_CCS811=m +CONFIG_SENSIRION_SGP30=m -+CONFIG_SPS30=m ++CONFIG_SPS30_I2C=m +CONFIG_MAX30102=m +CONFIG_DHT11=m +CONFIG_HDC100X=m +CONFIG_HTU21=m ++CONFIG_SI7020=m ++CONFIG_BOSCH_BNO055_I2C=m +CONFIG_INV_MPU6050_I2C=m +CONFIG_APDS9960=m +CONFIG_BH1750=m +CONFIG_TSL4531=m +CONFIG_VEML6070=m ++CONFIG_IIO_HRTIMER_TRIGGER=m ++CONFIG_IIO_INTERRUPT_TRIGGER=m ++CONFIG_IIO_SYSFS_TRIGGER=m +CONFIG_BMP280=m ++CONFIG_MS5637=m +CONFIG_MAXIM_THERMOCOUPLE=m +CONFIG_MAX31856=m ++CONFIG_PWM=y +CONFIG_PWM_BCM2835=m +CONFIG_PWM_PCA9685=m ++CONFIG_PWM_RASPBERRYPI_POE=m +CONFIG_RPI_AXIPERF=m ++CONFIG_MUX_GPIO=m +CONFIG_EXT4_FS=y +CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_EXT4_FS_SECURITY=y @@ -37481,13 +52738,12 @@ index 000000000000..f2074da8a80d +CONFIG_FANOTIFY=y +CONFIG_QFMT_V1=m +CONFIG_QFMT_V2=m -+CONFIG_AUTOFS4_FS=y ++CONFIG_AUTOFS_FS=y +CONFIG_FUSE_FS=m +CONFIG_CUSE=m +CONFIG_OVERLAY_FS=m +CONFIG_FSCACHE=y +CONFIG_FSCACHE_STATS=y -+CONFIG_FSCACHE_HISTOGRAM=y +CONFIG_CACHEFILES=y +CONFIG_ISO9660_FS=m +CONFIG_JOLIET=y @@ -37499,6 +52755,7 @@ index 000000000000..f2074da8a80d +CONFIG_EXFAT_FS=m +CONFIG_NTFS_FS=m +CONFIG_NTFS_RW=y ++CONFIG_NTFS3_FS=m +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_ECRYPT_FS=m @@ -37511,6 +52768,9 @@ index 000000000000..f2074da8a80d +CONFIG_SQUASHFS_XATTR=y +CONFIG_SQUASHFS_LZO=y +CONFIG_SQUASHFS_XZ=y ++CONFIG_PSTORE=y ++CONFIG_PSTORE_CONSOLE=y ++CONFIG_PSTORE_RAM=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3_ACL=y +CONFIG_NFS_V4=y @@ -37520,14 +52780,17 @@ index 000000000000..f2074da8a80d +CONFIG_ROOT_NFS=y +CONFIG_NFS_FSCACHE=y +CONFIG_NFSD=m ++CONFIG_NFSD_V2=y ++CONFIG_NFSD_V2_ACL=y +CONFIG_NFSD_V3_ACL=y +CONFIG_NFSD_V4=y ++CONFIG_CEPH_FS=m +CONFIG_CIFS=m -+CONFIG_CIFS_WEAK_PW_HASH=y +CONFIG_CIFS_UPCALL=y +CONFIG_CIFS_XATTR=y +CONFIG_CIFS_DFS_UPCALL=y +CONFIG_CIFS_FSCACHE=y ++CONFIG_SMB_SERVER=m +CONFIG_9P_FS=m +CONFIG_9P_FS_POSIX_ACL=y +CONFIG_NLS_DEFAULT="utf8" @@ -37569,29 +52832,37 @@ index 000000000000..f2074da8a80d +CONFIG_NLS_KOI8_R=m +CONFIG_NLS_KOI8_U=m +CONFIG_DLM=m ++CONFIG_KEY_DH_OPERATIONS=y +CONFIG_SECURITY=y +CONFIG_SECURITY_APPARMOR=y +CONFIG_LSM="" +CONFIG_CRYPTO_USER=m -+CONFIG_CRYPTO_CHACHA20POLY1305=m -+CONFIG_CRYPTO_ADIANTUM=m -+CONFIG_CRYPTO_XCBC=m -+CONFIG_CRYPTO_TGR192=m -+CONFIG_CRYPTO_WP512=m +CONFIG_CRYPTO_CAST5=m +CONFIG_CRYPTO_DES=y ++CONFIG_CRYPTO_TWOFISH=m ++CONFIG_CRYPTO_ADIANTUM=m ++CONFIG_CRYPTO_CHACHA20POLY1305=m ++CONFIG_CRYPTO_MD4=m ++CONFIG_CRYPTO_SHA512=m ++CONFIG_CRYPTO_WP512=m ++CONFIG_CRYPTO_XCBC=m +CONFIG_CRYPTO_LZ4=m +CONFIG_CRYPTO_USER_API_HASH=m +CONFIG_CRYPTO_USER_API_SKCIPHER=m +CONFIG_CRYPTO_USER_API_RNG=m +CONFIG_CRYPTO_USER_API_AEAD=m ++CONFIG_CRYPTO_SHA1_ARM_NEON=m ++CONFIG_CRYPTO_AES_ARM=m ++CONFIG_CRYPTO_AES_ARM_BS=m +# CONFIG_CRYPTO_HW is not set ++CONFIG_PKCS8_PRIVATE_KEY_PARSER=m +CONFIG_CRC_ITU_T=y +CONFIG_LIBCRC32C=y +CONFIG_DMA_CMA=y +CONFIG_CMA_SIZE_MBYTES=5 +CONFIG_PRINTK_TIME=y +CONFIG_BOOT_PRINTK_DELAY=y ++CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1f6 +CONFIG_KGDB=y +CONFIG_KGDB_KDB=y +CONFIG_KDB_KEYBOARD=y @@ -37601,16 +52872,15 @@ index 000000000000..f2074da8a80d +CONFIG_LATENCYTOP=y +CONFIG_FUNCTION_PROFILER=y +CONFIG_STACK_TRACER=y -+CONFIG_IRQSOFF_TRACER=y +CONFIG_SCHED_TRACER=y +CONFIG_BLK_DEV_IO_TRACE=y +# CONFIG_UPROBE_EVENTS is not set diff --git a/arch/arm/configs/bcm2711_defconfig b/arch/arm/configs/bcm2711_defconfig new file mode 100644 -index 000000000000..8f4ae82cade4 +index 000000000000..2bf13fd55bed --- /dev/null +++ b/arch/arm/configs/bcm2711_defconfig -@@ -0,0 +1,1557 @@ +@@ -0,0 +1,1610 @@ +CONFIG_LOCALVERSION="-v7l" +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_SYSVIPC=y @@ -37618,6 +52888,7 @@ index 000000000000..8f4ae82cade4 +CONFIG_GENERIC_IRQ_DEBUGFS=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y ++CONFIG_BPF_SYSCALL=y +CONFIG_PREEMPT_VOLUNTARY=y +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_BSD_PROCESS_ACCT_V3=y @@ -37625,6 +52896,8 @@ index 000000000000..8f4ae82cade4 +CONFIG_TASK_DELAY_ACCT=y +CONFIG_TASK_XACCT=y +CONFIG_TASK_IO_ACCOUNTING=y ++CONFIG_PSI=y ++CONFIG_PSI_DEFAULT_DISABLED=y +CONFIG_IKCONFIG=m +CONFIG_IKCONFIG_PROC=y +CONFIG_MEMCG=y @@ -37641,9 +52914,7 @@ index 000000000000..8f4ae82cade4 +CONFIG_USER_NS=y +CONFIG_SCHED_AUTOGROUP=y +CONFIG_BLK_DEV_INITRD=y -+CONFIG_BPF_SYSCALL=y -+CONFIG_EMBEDDED=y -+# CONFIG_COMPAT_BRK is not set ++CONFIG_EXPERT=y +CONFIG_PROFILING=y +CONFIG_ARCH_BCM=y +CONFIG_ARCH_BCM2835=y @@ -37669,32 +52940,28 @@ index 000000000000..8f4ae82cade4 +CONFIG_KERNEL_MODE_NEON=y +# CONFIG_SUSPEND is not set +CONFIG_PM=y -+CONFIG_RASPBERRYPI_FIRMWARE=y -+CONFIG_CRYPTO_SHA1_ARM_NEON=m -+CONFIG_CRYPTO_AES_ARM=m -+CONFIG_CRYPTO_AES_ARM_BS=m -+CONFIG_OPROFILE=m +CONFIG_JUMP_LABEL=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODVERSIONS=y +CONFIG_MODULE_SRCVERSION_ALL=y ++CONFIG_MODULE_COMPRESS_XZ=y +CONFIG_BLK_DEV_THROTTLING=y +CONFIG_PARTITION_ADVANCED=y +CONFIG_MAC_PARTITION=y +CONFIG_BINFMT_MISC=m -+CONFIG_CLEANCACHE=y -+CONFIG_FRONTSWAP=y -+CONFIG_CMA=y +CONFIG_ZSWAP=y +CONFIG_Z3FOLD=m -+CONFIG_ZSMALLOC=m ++# CONFIG_COMPAT_BRK is not set ++CONFIG_CMA=y ++CONFIG_LRU_GEN=y +CONFIG_NET=y +CONFIG_PACKET=y -+CONFIG_UNIX=y +CONFIG_XFRM_USER=y ++CONFIG_XFRM_INTERFACE=m ++CONFIG_XFRM_SUB_POLICY=y ++CONFIG_XFRM_STATISTICS=y +CONFIG_NET_KEY=m -+CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_ADVANCED_ROUTER=y +CONFIG_IP_MULTIPLE_TABLES=y @@ -37734,10 +53001,10 @@ index 000000000000..8f4ae82cade4 +CONFIG_IPV6_MROUTE=y +CONFIG_IPV6_MROUTE_MULTIPLE_TABLES=y +CONFIG_IPV6_PIMSM_V2=y ++CONFIG_NETWORK_PHY_TIMESTAMPING=y +CONFIG_NETFILTER=y +CONFIG_BRIDGE_NETFILTER=m +CONFIG_NF_CONNTRACK=m -+CONFIG_NF_LOG_NETDEV=m +CONFIG_NF_CONNTRACK_ZONES=y +CONFIG_NF_CONNTRACK_EVENTS=y +CONFIG_NF_CONNTRACK_TIMESTAMP=y @@ -37758,7 +53025,6 @@ index 000000000000..8f4ae82cade4 +CONFIG_NFT_NUMGEN=m +CONFIG_NFT_CT=m +CONFIG_NFT_FLOW_OFFLOAD=m -+CONFIG_NFT_COUNTER=m +CONFIG_NFT_CONNLIMIT=m +CONFIG_NFT_LOG=m +CONFIG_NFT_LIMIT=m @@ -37766,16 +53032,17 @@ index 000000000000..8f4ae82cade4 +CONFIG_NFT_REDIR=m +CONFIG_NFT_NAT=m +CONFIG_NFT_TUNNEL=m -+CONFIG_NFT_OBJREF=m +CONFIG_NFT_QUEUE=m +CONFIG_NFT_QUOTA=m +CONFIG_NFT_REJECT=m +CONFIG_NFT_COMPAT=m +CONFIG_NFT_HASH=m +CONFIG_NFT_FIB_INET=m ++CONFIG_NFT_XFRM=m +CONFIG_NFT_SOCKET=m +CONFIG_NFT_OSF=m +CONFIG_NFT_TPROXY=m ++CONFIG_NFT_SYNPROXY=m +CONFIG_NFT_DUP_NETDEV=m +CONFIG_NFT_FWD_NETDEV=m +CONFIG_NFT_FIB_NETDEV=m @@ -37852,6 +53119,7 @@ index 000000000000..8f4ae82cade4 +CONFIG_IP_SET_HASH_NETIFACE=m +CONFIG_IP_SET_LIST_SET=m +CONFIG_IP_VS=m ++CONFIG_IP_VS_IPV6=y +CONFIG_IP_VS_PROTO_TCP=y +CONFIG_IP_VS_PROTO_UDP=y +CONFIG_IP_VS_PROTO_ESP=y @@ -37872,8 +53140,8 @@ index 000000000000..8f4ae82cade4 +CONFIG_NFT_DUP_IPV4=m +CONFIG_NFT_FIB_IPV4=m +CONFIG_NF_TABLES_ARP=y -+CONFIG_NF_FLOW_TABLE_IPV4=m +CONFIG_NF_LOG_ARP=m ++CONFIG_NF_LOG_IPV4=m +CONFIG_IP_NF_IPTABLES=m +CONFIG_IP_NF_MATCH_AH=m +CONFIG_IP_NF_MATCH_ECN=m @@ -37886,7 +53154,6 @@ index 000000000000..8f4ae82cade4 +CONFIG_IP_NF_TARGET_NETMAP=m +CONFIG_IP_NF_TARGET_REDIRECT=m +CONFIG_IP_NF_MANGLE=m -+CONFIG_IP_NF_TARGET_CLUSTERIP=m +CONFIG_IP_NF_TARGET_ECN=m +CONFIG_IP_NF_TARGET_TTL=m +CONFIG_IP_NF_RAW=m @@ -37895,7 +53162,6 @@ index 000000000000..8f4ae82cade4 +CONFIG_IP_NF_ARP_MANGLE=m +CONFIG_NFT_DUP_IPV6=m +CONFIG_NFT_FIB_IPV6=m -+CONFIG_NF_FLOW_TABLE_IPV6=m +CONFIG_IP6_NF_IPTABLES=m +CONFIG_IP6_NF_MATCH_AH=m +CONFIG_IP6_NF_MATCH_EUI64=m @@ -37919,7 +53185,6 @@ index 000000000000..8f4ae82cade4 +CONFIG_IP6_NF_TARGET_NPT=m +CONFIG_NF_TABLES_BRIDGE=m +CONFIG_NFT_BRIDGE_REJECT=m -+CONFIG_NF_LOG_BRIDGE=m +CONFIG_BRIDGE_NF_EBTABLES=m +CONFIG_BRIDGE_EBT_BROUTE=m +CONFIG_BRIDGE_EBT_T_FILTER=m @@ -37956,10 +53221,8 @@ index 000000000000..8f4ae82cade4 +CONFIG_IEEE802154_6LOWPAN=m +CONFIG_MAC802154=m +CONFIG_NET_SCHED=y -+CONFIG_NET_SCH_CBQ=m +CONFIG_NET_SCH_HTB=m +CONFIG_NET_SCH_HFSC=m -+CONFIG_NET_SCH_ATM=m +CONFIG_NET_SCH_PRIO=m +CONFIG_NET_SCH_MULTIQ=m +CONFIG_NET_SCH_RED=m @@ -37968,7 +53231,6 @@ index 000000000000..8f4ae82cade4 +CONFIG_NET_SCH_TEQL=m +CONFIG_NET_SCH_TBF=m +CONFIG_NET_SCH_GRED=m -+CONFIG_NET_SCH_DSMARK=m +CONFIG_NET_SCH_NETEM=m +CONFIG_NET_SCH_DRR=m +CONFIG_NET_SCH_MQPRIO=m @@ -37983,13 +53245,10 @@ index 000000000000..8f4ae82cade4 +CONFIG_NET_SCH_INGRESS=m +CONFIG_NET_SCH_PLUG=m +CONFIG_NET_CLS_BASIC=m -+CONFIG_NET_CLS_TCINDEX=m +CONFIG_NET_CLS_ROUTE4=m +CONFIG_NET_CLS_FW=m +CONFIG_NET_CLS_U32=m +CONFIG_CLS_U32_MARK=y -+CONFIG_NET_CLS_RSVP=m -+CONFIG_NET_CLS_RSVP6=m +CONFIG_NET_CLS_FLOW=m +CONFIG_NET_CLS_CGROUP=m +CONFIG_NET_EMATCH=y @@ -38027,13 +53286,6 @@ index 000000000000..8f4ae82cade4 +CONFIG_CAN=m +CONFIG_CAN_J1939=m +CONFIG_CAN_ISOTP=m -+CONFIG_CAN_VCAN=m -+CONFIG_CAN_SLCAN=m -+CONFIG_CAN_MCP251X=m -+CONFIG_CAN_MCP251XFD=m -+CONFIG_CAN_EMS_USB=m -+CONFIG_CAN_GS_USB=m -+CONFIG_CAN_PEAK_USB=m +CONFIG_BT=m +CONFIG_BT_RFCOMM=m +CONFIG_BT_RFCOMM_TTY=y @@ -38057,7 +53309,6 @@ index 000000000000..8f4ae82cade4 +CONFIG_CFG80211_WEXT=y +CONFIG_MAC80211=m +CONFIG_MAC80211_MESH=y -+CONFIG_WIMAX=m +CONFIG_RFKILL=m +CONFIG_RFKILL_INPUT=y +CONFIG_NET_9P=m @@ -38070,22 +53321,23 @@ index 000000000000..8f4ae82cade4 +CONFIG_UEVENT_HELPER=y +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y ++CONFIG_RASPBERRYPI_FIRMWARE=y +CONFIG_MTD=m +CONFIG_MTD_BLOCK=m +CONFIG_MTD_BLOCK2MTD=m ++CONFIG_MTD_SPI_NAND=m +CONFIG_MTD_SPI_NOR=m +CONFIG_MTD_UBI=m +CONFIG_OF_CONFIGFS=y +CONFIG_ZRAM=m +CONFIG_BLK_DEV_LOOP=y -+CONFIG_BLK_DEV_CRYPTOLOOP=m +CONFIG_BLK_DEV_DRBD=m +CONFIG_BLK_DEV_NBD=m +CONFIG_BLK_DEV_RAM=y -+CONFIG_CDROM_PKTCDVD=m +CONFIG_ATA_OVER_ETH=m +CONFIG_BLK_DEV_NVME=y +CONFIG_EEPROM_AT24=m ++CONFIG_EEPROM_AT25=m +CONFIG_TI_ST=m +CONFIG_SCSI=y +# CONFIG_SCSI_PROC_FS is not set @@ -38106,11 +53358,14 @@ index 000000000000..8f4ae82cade4 +CONFIG_DM_SNAPSHOT=m +CONFIG_DM_THIN_PROVISIONING=m +CONFIG_DM_CACHE=m ++CONFIG_DM_WRITECACHE=m +CONFIG_DM_MIRROR=m +CONFIG_DM_LOG_USERSPACE=m +CONFIG_DM_RAID=m +CONFIG_DM_ZERO=m ++CONFIG_DM_MULTIPATH=m +CONFIG_DM_DELAY=m ++CONFIG_DM_INTEGRITY=m +CONFIG_NETDEVICES=y +CONFIG_BONDING=m +CONFIG_DUMMY=m @@ -38125,12 +53380,21 @@ index 000000000000..8f4ae82cade4 +CONFIG_NET_VRF=m +CONFIG_BCMGENET=y +CONFIG_ENC28J60=m ++CONFIG_LAN743X=m +CONFIG_QCA7000_SPI=m +CONFIG_QCA7000_UART=m +CONFIG_R8169=m +CONFIG_WIZNET_W5100=m +CONFIG_WIZNET_W5100_SPI=m +CONFIG_MICREL_PHY=y ++CONFIG_CAN_VCAN=m ++CONFIG_CAN_SLCAN=m ++CONFIG_CAN_MCP251X=m ++CONFIG_CAN_MCP251XFD=m ++CONFIG_CAN_8DEV_USB=m ++CONFIG_CAN_EMS_USB=m ++CONFIG_CAN_GS_USB=m ++CONFIG_CAN_PEAK_USB=m +CONFIG_MDIO_BITBANG=m +CONFIG_PPP=m +CONFIG_PPP_BSDCOMP=m @@ -38210,6 +53474,7 @@ index 000000000000..8f4ae82cade4 +CONFIG_MT7601U=m +CONFIG_MT76x0U=m +CONFIG_MT76x2U=m ++CONFIG_MT7921U=m +CONFIG_RT2X00=m +CONFIG_RT2500USB=m +CONFIG_RT73USB=m @@ -38221,11 +53486,15 @@ index 000000000000..8f4ae82cade4 +CONFIG_RTL8187=m +CONFIG_RTL8192CU=m +CONFIG_RTL8XXXU=m ++CONFIG_RTW88=m ++CONFIG_RTW88_8822BU=m ++CONFIG_RTW88_8822CU=m ++CONFIG_RTW88_8723DU=m ++CONFIG_RTW88_8821CU=m +CONFIG_USB_ZD1201=m +CONFIG_ZD1211RW=m -+CONFIG_MAC80211_HWSIM=m +CONFIG_USB_NET_RNDIS_WLAN=m -+CONFIG_WIMAX_I2400M_USB=m ++CONFIG_MAC80211_HWSIM=m +CONFIG_IEEE802154_AT86RF230=m +CONFIG_IEEE802154_MRF24J40=m +CONFIG_IEEE802154_CC2520=m @@ -38247,6 +53516,7 @@ index 000000000000..8f4ae82cade4 +CONFIG_JOYSTICK_XPAD_LEDS=y +CONFIG_JOYSTICK_PSXPAD_SPI=m +CONFIG_JOYSTICK_PSXPAD_SPI_FF=y ++CONFIG_JOYSTICK_FSIA6B=m +CONFIG_JOYSTICK_RPISENSE=m +CONFIG_INPUT_TOUCHSCREEN=y +CONFIG_TOUCHSCREEN_ADS7846=m @@ -38257,7 +53527,10 @@ index 000000000000..8f4ae82cade4 +CONFIG_TOUCHSCREEN_EDT_FT5X06=m +CONFIG_TOUCHSCREEN_RASPBERRYPI_FW=m +CONFIG_TOUCHSCREEN_USB_COMPOSITE=m ++CONFIG_TOUCHSCREEN_TSC2007=m ++CONFIG_TOUCHSCREEN_TSC2007_IIO=y +CONFIG_TOUCHSCREEN_STMPE=m ++CONFIG_TOUCHSCREEN_IQS5XX=m +CONFIG_INPUT_MISC=y +CONFIG_INPUT_AD714X=m +CONFIG_INPUT_ATI_REMOTE2=m @@ -38272,18 +53545,14 @@ index 000000000000..8f4ae82cade4 +CONFIG_SERIO=m +CONFIG_SERIO_RAW=m +CONFIG_GAMEPORT=m -+CONFIG_GAMEPORT_NS558=m -+CONFIG_GAMEPORT_L4=m +CONFIG_BRCM_CHAR_DRIVERS=y +CONFIG_BCM_VCIO=y -+CONFIG_BCM2835_DEVGPIOMEM=y -+CONFIG_RPIVID_MEM=m +# CONFIG_LEGACY_PTYS is not set +CONFIG_SERIAL_8250=y +# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set +CONFIG_SERIAL_8250_CONSOLE=y +# CONFIG_SERIAL_8250_DMA is not set -+CONFIG_SERIAL_8250_NR_UARTS=1 ++CONFIG_SERIAL_8250_NR_UARTS=5 +CONFIG_SERIAL_8250_RUNTIME_UARTS=0 +CONFIG_SERIAL_8250_EXTENDED=y +CONFIG_SERIAL_8250_SHARE_IRQ=y @@ -38296,10 +53565,13 @@ index 000000000000..8f4ae82cade4 +CONFIG_SERIAL_DEV_BUS=y +CONFIG_TTY_PRINTK=y +CONFIG_HW_RANDOM=y -+CONFIG_RAW_DRIVER=y +CONFIG_TCG_TPM=m +CONFIG_TCG_TIS_SPI=m -+CONFIG_RANDOM_TRUST_BOOTLOADER=y ++CONFIG_TCG_TIS_I2C=m ++CONFIG_XILLYBUS=m ++CONFIG_XILLYBUS_PCIE=m ++CONFIG_XILLYUSB=m ++CONFIG_RASPBERRYPI_GPIOMEM=m +CONFIG_I2C=y +CONFIG_I2C_CHARDEV=m +CONFIG_I2C_MUX_GPMUX=m @@ -38317,23 +53589,23 @@ index 000000000000..8f4ae82cade4 +CONFIG_SPI_GPIO=m +CONFIG_SPI_SPIDEV=m +CONFIG_SPI_SLAVE=y -+CONFIG_PPS=m +CONFIG_PPS_CLIENT_LDISC=m +CONFIG_PPS_CLIENT_GPIO=m +CONFIG_PINCTRL_MCP23S08=m +CONFIG_GPIO_SYSFS=y +CONFIG_GPIO_BCM_VIRT=y ++CONFIG_GPIO_MAX7300=m +CONFIG_GPIO_PCA953X=m +CONFIG_GPIO_PCA953X_IRQ=y +CONFIG_GPIO_PCF857X=m +CONFIG_GPIO_ARIZONA=m +CONFIG_GPIO_FSM=m +CONFIG_GPIO_STMPE=y ++CONFIG_GPIO_MAX7301=m +CONFIG_GPIO_MOCKUP=m +CONFIG_W1=m +CONFIG_W1_MASTER_DS2490=m +CONFIG_W1_MASTER_DS2482=m -+CONFIG_W1_MASTER_DS1WM=m +CONFIG_W1_MASTER_GPIO=m +CONFIG_W1_SLAVE_THERM=m +CONFIG_W1_SLAVE_SMEM=m @@ -38353,24 +53625,30 @@ index 000000000000..8f4ae82cade4 +CONFIG_RPI_POE_POWER=m +CONFIG_BATTERY_DS2760=m +CONFIG_BATTERY_MAX17040=m ++CONFIG_CHARGER_GPIO=m +CONFIG_BATTERY_GAUGE_LTC2941=m ++CONFIG_SENSORS_ADT7410=m ++CONFIG_SENSORS_AHT10=m ++CONFIG_SENSORS_DRIVETEMP=m +CONFIG_SENSORS_DS1621=m +CONFIG_SENSORS_GPIO_FAN=m +CONFIG_SENSORS_IIO_HWMON=m +CONFIG_SENSORS_JC42=m +CONFIG_SENSORS_LM75=m ++CONFIG_SENSORS_PWM_FAN=m +CONFIG_SENSORS_RASPBERRYPI_HWMON=m -+CONFIG_SENSORS_RPI_POE_FAN=m +CONFIG_SENSORS_SHT21=m +CONFIG_SENSORS_SHT3x=m ++CONFIG_SENSORS_SHT4x=m +CONFIG_SENSORS_SHTC1=m ++CONFIG_SENSORS_EMC2305=m +CONFIG_SENSORS_INA2XX=m +CONFIG_SENSORS_TMP102=m -+CONFIG_THERMAL=y +CONFIG_BCM2711_THERMAL=y +CONFIG_WATCHDOG=y +CONFIG_GPIO_WATCHDOG=m +CONFIG_BCM2835_WDT=y ++CONFIG_MFD_RASPBERRYPI_POE_HAT=m +CONFIG_MFD_STMPE=y +CONFIG_STMPE_SPI=y +CONFIG_MFD_ARIZONA_I2C=m @@ -38382,40 +53660,38 @@ index 000000000000..8f4ae82cade4 +CONFIG_REGULATOR_ARIZONA_MICSUPP=m +CONFIG_REGULATOR_GPIO=y +CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_ATTINY=m ++CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_V2=m +CONFIG_RC_CORE=y -+CONFIG_LIRC=y +CONFIG_BPF_LIRC_MODE2=y ++CONFIG_LIRC=y +CONFIG_RC_DECODERS=y ++CONFIG_IR_IMON_DECODER=m ++CONFIG_IR_JVC_DECODER=m ++CONFIG_IR_MCE_KBD_DECODER=m +CONFIG_IR_NEC_DECODER=m +CONFIG_IR_RC5_DECODER=m +CONFIG_IR_RC6_DECODER=m -+CONFIG_IR_JVC_DECODER=m -+CONFIG_IR_SONY_DECODER=m +CONFIG_IR_SANYO_DECODER=m +CONFIG_IR_SHARP_DECODER=m -+CONFIG_IR_MCE_KBD_DECODER=m ++CONFIG_IR_SONY_DECODER=m +CONFIG_IR_XMP_DECODER=m -+CONFIG_IR_IMON_DECODER=m +CONFIG_RC_DEVICES=y -+CONFIG_RC_ATI_REMOTE=m -+CONFIG_IR_IMON=m -+CONFIG_IR_MCEUSB=m -+CONFIG_IR_REDRAT3=m -+CONFIG_IR_STREAMZAP=m -+CONFIG_IR_IGUANA=m -+CONFIG_IR_TTUSBIR=m -+CONFIG_RC_LOOPBACK=m +CONFIG_IR_GPIO_CIR=m +CONFIG_IR_GPIO_TX=m ++CONFIG_IR_IGUANA=m ++CONFIG_IR_IMON=m ++CONFIG_IR_MCEUSB=m +CONFIG_IR_PWM_TX=m ++CONFIG_IR_REDRAT3=m ++CONFIG_IR_STREAMZAP=m +CONFIG_IR_TOY=m ++CONFIG_IR_TTUSBIR=m ++CONFIG_RC_ATI_REMOTE=m ++CONFIG_RC_LOOPBACK=m +CONFIG_MEDIA_CEC_RC=y +CONFIG_MEDIA_SUPPORT=m +CONFIG_MEDIA_USB_SUPPORT=y -+CONFIG_USB_VIDEO_CLASS=m -+CONFIG_USB_M5602=m -+CONFIG_USB_STV06XX=m -+CONFIG_USB_GL860=m ++CONFIG_USB_GSPCA=m +CONFIG_USB_GSPCA_BENQ=m +CONFIG_USB_GSPCA_CONEX=m +CONFIG_USB_GSPCA_CPIA1=m @@ -38440,13 +53716,13 @@ index 000000000000..8f4ae82cade4 +CONFIG_USB_GSPCA_SN9C20X=m +CONFIG_USB_GSPCA_SONIXB=m +CONFIG_USB_GSPCA_SONIXJ=m ++CONFIG_USB_GSPCA_SPCA1528=m +CONFIG_USB_GSPCA_SPCA500=m +CONFIG_USB_GSPCA_SPCA501=m +CONFIG_USB_GSPCA_SPCA505=m +CONFIG_USB_GSPCA_SPCA506=m +CONFIG_USB_GSPCA_SPCA508=m +CONFIG_USB_GSPCA_SPCA561=m -+CONFIG_USB_GSPCA_SPCA1528=m +CONFIG_USB_GSPCA_SQ905=m +CONFIG_USB_GSPCA_SQ905C=m +CONFIG_USB_GSPCA_SQ930X=m @@ -38456,56 +53732,32 @@ index 000000000000..8f4ae82cade4 +CONFIG_USB_GSPCA_SUNPLUS=m +CONFIG_USB_GSPCA_T613=m +CONFIG_USB_GSPCA_TOPRO=m ++CONFIG_USB_GSPCA_TOUPTEK=m +CONFIG_USB_GSPCA_TV8532=m +CONFIG_USB_GSPCA_VC032X=m +CONFIG_USB_GSPCA_VICAM=m +CONFIG_USB_GSPCA_XIRLINK_CIT=m +CONFIG_USB_GSPCA_ZC3XX=m ++CONFIG_USB_GL860=m ++CONFIG_USB_M5602=m ++CONFIG_USB_STV06XX=m +CONFIG_USB_PWC=m -+CONFIG_VIDEO_CPIA2=m -+CONFIG_USB_ZR364XX=m -+CONFIG_USB_STKWEBCAM=m +CONFIG_USB_S2255=m +CONFIG_VIDEO_USBTV=m -+CONFIG_VIDEO_PVRUSB2=m -+CONFIG_VIDEO_HDPVR=m -+CONFIG_VIDEO_STK1160_COMMON=m ++CONFIG_USB_VIDEO_CLASS=m +CONFIG_VIDEO_GO7007=m +CONFIG_VIDEO_GO7007_USB=m +CONFIG_VIDEO_GO7007_USB_S2250_BOARD=m ++CONFIG_VIDEO_HDPVR=m ++CONFIG_VIDEO_PVRUSB2=m ++CONFIG_VIDEO_STK1160=m +CONFIG_VIDEO_AU0828=m +CONFIG_VIDEO_AU0828_RC=y +CONFIG_VIDEO_CX231XX=m +CONFIG_VIDEO_CX231XX_ALSA=m +CONFIG_VIDEO_CX231XX_DVB=m -+CONFIG_VIDEO_TM6000=m -+CONFIG_VIDEO_TM6000_ALSA=m -+CONFIG_VIDEO_TM6000_DVB=m -+CONFIG_DVB_USB=m -+CONFIG_DVB_USB_A800=m -+CONFIG_DVB_USB_DIBUSB_MB=m -+CONFIG_DVB_USB_DIBUSB_MB_FAULTY=y -+CONFIG_DVB_USB_DIBUSB_MC=m -+CONFIG_DVB_USB_DIB0700=m -+CONFIG_DVB_USB_UMT_010=m -+CONFIG_DVB_USB_CXUSB=m -+CONFIG_DVB_USB_M920X=m -+CONFIG_DVB_USB_DIGITV=m -+CONFIG_DVB_USB_VP7045=m -+CONFIG_DVB_USB_VP702X=m -+CONFIG_DVB_USB_GP8PSK=m -+CONFIG_DVB_USB_NOVA_T_USB2=m -+CONFIG_DVB_USB_TTUSB2=m -+CONFIG_DVB_USB_DTT200U=m -+CONFIG_DVB_USB_OPERA1=m -+CONFIG_DVB_USB_AF9005=m -+CONFIG_DVB_USB_AF9005_REMOTE=m -+CONFIG_DVB_USB_PCTV452E=m -+CONFIG_DVB_USB_DW2102=m -+CONFIG_DVB_USB_CINERGY_T2=m -+CONFIG_DVB_USB_DTV5100=m -+CONFIG_DVB_USB_AZ6027=m -+CONFIG_DVB_USB_TECHNISAT_USB2=m ++CONFIG_DVB_AS102=m ++CONFIG_DVB_B2C2_FLEXCOP_USB=m +CONFIG_DVB_USB_V2=m +CONFIG_DVB_USB_AF9015=m +CONFIG_DVB_USB_AF9035=m @@ -38513,70 +53765,115 @@ index 000000000000..8f4ae82cade4 +CONFIG_DVB_USB_AU6610=m +CONFIG_DVB_USB_AZ6007=m +CONFIG_DVB_USB_CE6230=m ++CONFIG_DVB_USB_DVBSKY=m +CONFIG_DVB_USB_EC168=m +CONFIG_DVB_USB_GL861=m +CONFIG_DVB_USB_LME2510=m +CONFIG_DVB_USB_MXL111SF=m +CONFIG_DVB_USB_RTL28XXU=m -+CONFIG_DVB_USB_DVBSKY=m ++CONFIG_DVB_USB=m ++CONFIG_DVB_USB_A800=m ++CONFIG_DVB_USB_AF9005=m ++CONFIG_DVB_USB_AF9005_REMOTE=m ++CONFIG_DVB_USB_AZ6027=m ++CONFIG_DVB_USB_CINERGY_T2=m ++CONFIG_DVB_USB_CXUSB=m ++CONFIG_DVB_USB_DIB0700=m ++CONFIG_DVB_USB_DIBUSB_MB=m ++CONFIG_DVB_USB_DIBUSB_MB_FAULTY=y ++CONFIG_DVB_USB_DIBUSB_MC=m ++CONFIG_DVB_USB_DIGITV=m ++CONFIG_DVB_USB_DTT200U=m ++CONFIG_DVB_USB_DTV5100=m ++CONFIG_DVB_USB_DW2102=m ++CONFIG_DVB_USB_GP8PSK=m ++CONFIG_DVB_USB_M920X=m ++CONFIG_DVB_USB_NOVA_T_USB2=m ++CONFIG_DVB_USB_OPERA1=m ++CONFIG_DVB_USB_PCTV452E=m ++CONFIG_DVB_USB_TECHNISAT_USB2=m ++CONFIG_DVB_USB_TTUSB2=m ++CONFIG_DVB_USB_UMT_010=m ++CONFIG_DVB_USB_VP702X=m ++CONFIG_DVB_USB_VP7045=m +CONFIG_SMS_USB_DRV=m -+CONFIG_DVB_B2C2_FLEXCOP_USB=m -+CONFIG_DVB_AS102=m +CONFIG_VIDEO_EM28XX=m +CONFIG_VIDEO_EM28XX_V4L2=m +CONFIG_VIDEO_EM28XX_ALSA=m +CONFIG_VIDEO_EM28XX_DVB=m ++CONFIG_RADIO_SAA7706H=m ++CONFIG_RADIO_SHARK=m ++CONFIG_RADIO_SHARK2=m ++CONFIG_RADIO_SI4713=m ++CONFIG_RADIO_TEA5764=m ++CONFIG_RADIO_TEF6862=m ++CONFIG_RADIO_WL1273=m ++CONFIG_USB_DSBR=m ++CONFIG_USB_KEENE=m ++CONFIG_USB_MA901=m ++CONFIG_USB_MR800=m +CONFIG_RADIO_SI470X=m +CONFIG_USB_SI470X=m +CONFIG_I2C_SI470X=m -+CONFIG_RADIO_SI4713=m +CONFIG_I2C_SI4713=m -+CONFIG_USB_MR800=m -+CONFIG_USB_DSBR=m -+CONFIG_RADIO_SHARK=m -+CONFIG_RADIO_SHARK2=m -+CONFIG_USB_KEENE=m -+CONFIG_USB_MA901=m -+CONFIG_RADIO_TEA5764=m -+CONFIG_RADIO_SAA7706H=m -+CONFIG_RADIO_TEF6862=m -+CONFIG_RADIO_WL1273=m +CONFIG_RADIO_WL128X=m +CONFIG_V4L_PLATFORM_DRIVERS=y ++CONFIG_VIDEO_MUX=m +CONFIG_VIDEO_BCM2835_UNICAM=m -+CONFIG_VIDEO_UDA1342=m ++CONFIG_VIDEO_ARDUCAM_64MP=m ++CONFIG_VIDEO_ARDUCAM_PIVARIETY=m ++CONFIG_VIDEO_IMX219=m ++CONFIG_VIDEO_IMX258=m ++CONFIG_VIDEO_IMX290=m ++CONFIG_VIDEO_IMX296=m ++CONFIG_VIDEO_IMX477=m ++CONFIG_VIDEO_IMX519=m ++CONFIG_VIDEO_IMX708=m ++CONFIG_VIDEO_MT9V011=m ++CONFIG_VIDEO_OV2311=m ++CONFIG_VIDEO_OV5647=m ++CONFIG_VIDEO_OV64A40=m ++CONFIG_VIDEO_OV7251=m ++CONFIG_VIDEO_OV7640=m ++CONFIG_VIDEO_OV9282=m ++CONFIG_VIDEO_AD5398=m ++CONFIG_VIDEO_AK7375=m ++CONFIG_VIDEO_BU64754=m ++CONFIG_VIDEO_DW9807_VCM=m +CONFIG_VIDEO_SONY_BTF_MPX=m ++CONFIG_VIDEO_UDA1342=m +CONFIG_VIDEO_ADV7180=m +CONFIG_VIDEO_TC358743=m +CONFIG_VIDEO_TVP5150=m +CONFIG_VIDEO_TW2804=m +CONFIG_VIDEO_TW9903=m +CONFIG_VIDEO_TW9906=m -+CONFIG_VIDEO_IMX219=m -+CONFIG_VIDEO_IMX290=m -+CONFIG_VIDEO_IMX477=m -+CONFIG_VIDEO_IMX519=m -+CONFIG_VIDEO_OV5647=m -+CONFIG_VIDEO_OV7251=m -+CONFIG_VIDEO_OV7640=m -+CONFIG_VIDEO_OV9281=m +CONFIG_VIDEO_IRS1125=m -+CONFIG_VIDEO_MT9V011=m ++CONFIG_VIDEO_I2C=m ++CONFIG_AUXDISPLAY=y ++CONFIG_HD44780=m +CONFIG_DRM=m +CONFIG_DRM_LOAD_EDID_FIRMWARE=y +CONFIG_DRM_UDL=m +CONFIG_DRM_PANEL_SIMPLE=m ++CONFIG_DRM_PANEL_ILITEK_ILI9806E=m +CONFIG_DRM_PANEL_ILITEK_ILI9881C=m +CONFIG_DRM_PANEL_JDI_LT070ME05000=m +CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN=m ++CONFIG_DRM_PANEL_SITRONIX_ST7701=m ++CONFIG_DRM_PANEL_TPO_Y17P=m ++CONFIG_DRM_PANEL_WAVESHARE_TOUCHSCREEN=m +CONFIG_DRM_DISPLAY_CONNECTOR=m +CONFIG_DRM_SIMPLE_BRIDGE=m +CONFIG_DRM_TOSHIBA_TC358762=m +CONFIG_DRM_V3D=m +CONFIG_DRM_VC4=m +CONFIG_DRM_VC4_HDMI_CEC=y ++CONFIG_DRM_PANEL_MIPI_DBI=m ++CONFIG_TINYDRM_HX8357D=m +CONFIG_TINYDRM_ILI9225=m +CONFIG_TINYDRM_ILI9341=m ++CONFIG_TINYDRM_ILI9486=m +CONFIG_TINYDRM_MI0283QT=m +CONFIG_TINYDRM_REPAPER=m +CONFIG_TINYDRM_ST7586=m @@ -38584,14 +53881,13 @@ index 000000000000..8f4ae82cade4 +CONFIG_DRM_GUD=m +CONFIG_FB=y +CONFIG_FB_BCM2708=y -+CONFIG_FB_UDL=m +CONFIG_FB_SIMPLE=y +CONFIG_FB_SSD1307=m +CONFIG_FB_RPISENSE=m +CONFIG_BACKLIGHT_PWM=m +CONFIG_BACKLIGHT_RPI=m ++CONFIG_BACKLIGHT_LM3630A=m +CONFIG_BACKLIGHT_GPIO=m -+CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y +CONFIG_LOGO=y +# CONFIG_LOGO_LINUX_MONO is not set @@ -38601,6 +53897,7 @@ index 000000000000..8f4ae82cade4 +CONFIG_SND_OSSEMUL=y +CONFIG_SND_PCM_OSS=m +CONFIG_SND_HRTIMER=m ++CONFIG_SND_DYNAMIC_MINORS=y +CONFIG_SND_SEQUENCER=m +CONFIG_SND_SEQ_DUMMY=m +CONFIG_SND_DUMMY=m @@ -38655,6 +53952,7 @@ index 000000000000..8f4ae82cade4 +CONFIG_SND_BCM2708_SOC_ALLO_KATANA_DAC=m +CONFIG_SND_BCM2708_SOC_FE_PI_AUDIO=m +CONFIG_SND_PISOUND=m ++CONFIG_SND_DACBERRY400=m +CONFIG_SND_SOC_AD193X_SPI=m +CONFIG_SND_SOC_AD193X_I2C=m +CONFIG_SND_SOC_ADAU1701=m @@ -38665,6 +53963,7 @@ index 000000000000..8f4ae82cade4 +CONFIG_SND_SOC_MA120X0P=m +CONFIG_SND_SOC_MAX98357A=m +CONFIG_SND_SOC_SPDIF=m ++CONFIG_SND_SOC_TLV320AIC23_I2C=m +CONFIG_SND_SOC_WM8804_I2C=m +CONFIG_SND_SOC_WM8960=m +CONFIG_SND_SIMPLE_CARD=m @@ -38705,11 +54004,15 @@ index 000000000000..8f4ae82cade4 +CONFIG_HID_MICROSOFT=m +CONFIG_HID_MONTEREY=m +CONFIG_HID_MULTITOUCH=m ++CONFIG_HID_NINTENDO=m ++CONFIG_NINTENDO_FF=y +CONFIG_HID_NTRIG=m +CONFIG_HID_ORTEK=m +CONFIG_HID_PANTHERLORD=m +CONFIG_HID_PETALYNX=m +CONFIG_HID_PICOLCD=m ++CONFIG_HID_PLAYSTATION=m ++CONFIG_PLAYSTATION_FF=y +CONFIG_HID_ROCCAT=m +CONFIG_HID_SAMSUNG=m +CONFIG_HID_SONY=m @@ -38729,7 +54032,6 @@ index 000000000000..8f4ae82cade4 +CONFIG_HID_ZYDACRON=m +CONFIG_HID_PID=y +CONFIG_USB_HIDDEV=y -+CONFIG_I2C_HID=m +CONFIG_USB=y +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y +CONFIG_USB_MON=m @@ -38800,7 +54102,6 @@ index 000000000000..8f4ae82cade4 +CONFIG_USB_SERIAL_SYMBOL=m +CONFIG_USB_SERIAL_TI=m +CONFIG_USB_SERIAL_CYBERJACK=m -+CONFIG_USB_SERIAL_XIRCOM=m +CONFIG_USB_SERIAL_OPTION=m +CONFIG_USB_SERIAL_OMNINET=m +CONFIG_USB_SERIAL_OPTICON=m @@ -38818,7 +54119,6 @@ index 000000000000..8f4ae82cade4 +CONFIG_USB_CYPRESS_CY7C63=m +CONFIG_USB_CYTHERM=m +CONFIG_USB_IDMOUSE=m -+CONFIG_USB_FTDI_ELAN=m +CONFIG_USB_APPLEDISPLAY=m +CONFIG_USB_LD=m +CONFIG_USB_TRANCEVIBRATOR=m @@ -38874,6 +54174,7 @@ index 000000000000..8f4ae82cade4 +CONFIG_MMC_SDHCI_IPROC=y +CONFIG_MMC_SPI=m +CONFIG_LEDS_CLASS=y ++CONFIG_LEDS_CLASS_MULTICOLOR=m +CONFIG_LEDS_PCA9532=m +CONFIG_LEDS_GPIO=y +CONFIG_LEDS_PCA955X=m @@ -38885,7 +54186,6 @@ index 000000000000..8f4ae82cade4 +CONFIG_LEDS_TRIGGER_HEARTBEAT=y +CONFIG_LEDS_TRIGGER_BACKLIGHT=y +CONFIG_LEDS_TRIGGER_CPU=y -+CONFIG_LEDS_TRIGGER_GPIO=y +CONFIG_LEDS_TRIGGER_DEFAULT_ON=y +CONFIG_LEDS_TRIGGER_TRANSIENT=m +CONFIG_LEDS_TRIGGER_CAMERA=m @@ -38920,6 +54220,8 @@ index 000000000000..8f4ae82cade4 +CONFIG_RTC_DRV_RX8025=m +CONFIG_RTC_DRV_EM3027=m +CONFIG_RTC_DRV_RV3028=m ++CONFIG_RTC_DRV_RV3032=m ++CONFIG_RTC_DRV_RV8803=m +CONFIG_RTC_DRV_SD3078=m +CONFIG_RTC_DRV_M41T93=m +CONFIG_RTC_DRV_M41T94=m @@ -38940,17 +54242,15 @@ index 000000000000..8f4ae82cade4 +CONFIG_DMABUF_HEAPS=y +CONFIG_DMABUF_HEAPS_SYSTEM=y +CONFIG_DMABUF_HEAPS_CMA=y -+CONFIG_AUXDISPLAY=y -+CONFIG_HD44780=m +CONFIG_UIO=m +CONFIG_UIO_PDRV_GENIRQ=m +CONFIG_STAGING=y +CONFIG_PRISM2_USB=m +CONFIG_R8712U=m -+CONFIG_R8188EU=m +CONFIG_VT6656=m +CONFIG_STAGING_MEDIA=y +CONFIG_VIDEO_RPIVID=m ++CONFIG_STAGING_MEDIA_DEPRECATED=y +CONFIG_FB_TFT=m +CONFIG_FB_TFT_AGM1264K_FL=m +CONFIG_FB_TFT_BD663474=m @@ -38978,9 +54278,9 @@ index 000000000000..8f4ae82cade4 +CONFIG_FB_TFT_ST7789V=m +CONFIG_FB_TFT_TINYLCD=m +CONFIG_FB_TFT_TLS8204=m ++CONFIG_FB_TFT_UC1611=m +CONFIG_FB_TFT_UC1701=m +CONFIG_FB_TFT_UPD161704=m -+CONFIG_FB_TFT_WATTEROTT=m +CONFIG_BCM2835_VCHIQ=y +CONFIG_SND_BCM2835=m +CONFIG_VIDEO_BCM2835=m @@ -38991,32 +54291,41 @@ index 000000000000..8f4ae82cade4 +CONFIG_BCM2835_MBOX=y +# CONFIG_IOMMU_SUPPORT is not set +CONFIG_RASPBERRYPI_POWER=y -+CONFIG_EXTCON_ARIZONA=m +CONFIG_IIO=m +CONFIG_IIO_BUFFER_CB=m ++CONFIG_IIO_SW_TRIGGER=m +CONFIG_MCP320X=m +CONFIG_MCP3422=m +CONFIG_TI_ADS1015=m +CONFIG_BME680=m +CONFIG_CCS811=m +CONFIG_SENSIRION_SGP30=m -+CONFIG_SPS30=m ++CONFIG_SPS30_I2C=m +CONFIG_MAX30102=m +CONFIG_DHT11=m +CONFIG_HDC100X=m +CONFIG_HTU21=m ++CONFIG_SI7020=m ++CONFIG_BOSCH_BNO055_I2C=m +CONFIG_INV_MPU6050_I2C=m +CONFIG_APDS9960=m +CONFIG_BH1750=m +CONFIG_TSL4531=m +CONFIG_VEML6070=m ++CONFIG_IIO_HRTIMER_TRIGGER=m ++CONFIG_IIO_INTERRUPT_TRIGGER=m ++CONFIG_IIO_SYSFS_TRIGGER=m +CONFIG_BMP280=m ++CONFIG_MS5637=m +CONFIG_MAXIM_THERMOCOUPLE=m +CONFIG_MAX31856=m ++CONFIG_PWM=y +CONFIG_PWM_BCM2835=m +CONFIG_PWM_PCA9685=m ++CONFIG_PWM_RASPBERRYPI_POE=m +CONFIG_RPI_AXIPERF=m +CONFIG_NVMEM_RMEM=m ++CONFIG_MUX_GPIO=m +CONFIG_EXT4_FS=y +CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_EXT4_FS_SECURITY=y @@ -39043,13 +54352,12 @@ index 000000000000..8f4ae82cade4 +CONFIG_FANOTIFY=y +CONFIG_QFMT_V1=m +CONFIG_QFMT_V2=m -+CONFIG_AUTOFS4_FS=y ++CONFIG_AUTOFS_FS=y +CONFIG_FUSE_FS=m +CONFIG_CUSE=m +CONFIG_OVERLAY_FS=m +CONFIG_FSCACHE=y +CONFIG_FSCACHE_STATS=y -+CONFIG_FSCACHE_HISTOGRAM=y +CONFIG_CACHEFILES=y +CONFIG_ISO9660_FS=m +CONFIG_JOLIET=y @@ -39061,6 +54369,7 @@ index 000000000000..8f4ae82cade4 +CONFIG_EXFAT_FS=m +CONFIG_NTFS_FS=m +CONFIG_NTFS_RW=y ++CONFIG_NTFS3_FS=m +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_ECRYPT_FS=m @@ -39073,6 +54382,9 @@ index 000000000000..8f4ae82cade4 +CONFIG_SQUASHFS_XATTR=y +CONFIG_SQUASHFS_LZO=y +CONFIG_SQUASHFS_XZ=y ++CONFIG_PSTORE=y ++CONFIG_PSTORE_CONSOLE=y ++CONFIG_PSTORE_RAM=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3_ACL=y +CONFIG_NFS_V4=y @@ -39082,15 +54394,18 @@ index 000000000000..8f4ae82cade4 +CONFIG_ROOT_NFS=y +CONFIG_NFS_FSCACHE=y +CONFIG_NFSD=m ++CONFIG_NFSD_V2=y ++CONFIG_NFSD_V2_ACL=y +CONFIG_NFSD_V3_ACL=y +CONFIG_NFSD_V4=y ++CONFIG_CEPH_FS=m +CONFIG_CIFS=m -+CONFIG_CIFS_WEAK_PW_HASH=y +CONFIG_CIFS_UPCALL=y +CONFIG_CIFS_XATTR=y +CONFIG_CIFS_POSIX=y +CONFIG_CIFS_DFS_UPCALL=y +CONFIG_CIFS_FSCACHE=y ++CONFIG_SMB_SERVER=m +CONFIG_9P_FS=m +CONFIG_9P_FS_POSIX_ACL=y +CONFIG_NLS_DEFAULT="utf8" @@ -39132,29 +54447,38 @@ index 000000000000..8f4ae82cade4 +CONFIG_NLS_KOI8_R=m +CONFIG_NLS_KOI8_U=m +CONFIG_DLM=m ++CONFIG_KEY_DH_OPERATIONS=y +CONFIG_SECURITY=y +CONFIG_SECURITY_APPARMOR=y +CONFIG_LSM="" +CONFIG_CRYPTO_USER=m -+CONFIG_CRYPTO_CHACHA20POLY1305=m -+CONFIG_CRYPTO_ADIANTUM=m -+CONFIG_CRYPTO_XCBC=m -+CONFIG_CRYPTO_TGR192=m -+CONFIG_CRYPTO_WP512=m ++CONFIG_CRYPTO_AES=m +CONFIG_CRYPTO_CAST5=m +CONFIG_CRYPTO_DES=y ++CONFIG_CRYPTO_TWOFISH=m ++CONFIG_CRYPTO_ADIANTUM=m ++CONFIG_CRYPTO_CHACHA20POLY1305=m ++CONFIG_CRYPTO_MD4=m ++CONFIG_CRYPTO_SHA512=m ++CONFIG_CRYPTO_WP512=m ++CONFIG_CRYPTO_XCBC=m +CONFIG_CRYPTO_LZ4=m +CONFIG_CRYPTO_USER_API_HASH=m +CONFIG_CRYPTO_USER_API_SKCIPHER=m +CONFIG_CRYPTO_USER_API_RNG=m +CONFIG_CRYPTO_USER_API_AEAD=m ++CONFIG_CRYPTO_SHA1_ARM_NEON=m ++CONFIG_CRYPTO_AES_ARM=m ++CONFIG_CRYPTO_AES_ARM_BS=m +# CONFIG_CRYPTO_HW is not set ++CONFIG_PKCS8_PRIVATE_KEY_PARSER=m +CONFIG_CRC_ITU_T=y +CONFIG_LIBCRC32C=y +CONFIG_DMA_CMA=y +CONFIG_CMA_SIZE_MBYTES=5 +CONFIG_PRINTK_TIME=y +CONFIG_BOOT_PRINTK_DELAY=y ++CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1f6 +CONFIG_KGDB=y +CONFIG_KGDB_KDB=y +CONFIG_KDB_KEYBOARD=y @@ -39164,22 +54488,22 @@ index 000000000000..8f4ae82cade4 +CONFIG_LATENCYTOP=y +CONFIG_FUNCTION_PROFILER=y +CONFIG_STACK_TRACER=y -+CONFIG_IRQSOFF_TRACER=y +CONFIG_SCHED_TRACER=y +CONFIG_BLK_DEV_IO_TRACE=y +# CONFIG_UPROBE_EVENTS is not set diff --git a/arch/arm/configs/bcmrpi_defconfig b/arch/arm/configs/bcmrpi_defconfig new file mode 100644 -index 000000000000..b3ea44509d98 +index 000000000000..1c1ffb4ae498 --- /dev/null +++ b/arch/arm/configs/bcmrpi_defconfig -@@ -0,0 +1,1528 @@ +@@ -0,0 +1,1576 @@ +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_SYSVIPC=y +CONFIG_POSIX_MQUEUE=y +CONFIG_GENERIC_IRQ_DEBUGFS=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y ++CONFIG_BPF_SYSCALL=y +CONFIG_PREEMPT_VOLUNTARY=y +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_BSD_PROCESS_ACCT_V3=y @@ -39187,6 +54511,8 @@ index 000000000000..b3ea44509d98 +CONFIG_TASK_DELAY_ACCT=y +CONFIG_TASK_XACCT=y +CONFIG_TASK_IO_ACCOUNTING=y ++CONFIG_PSI=y ++CONFIG_PSI_DEFAULT_DISABLED=y +CONFIG_IKCONFIG=m +CONFIG_IKCONFIG_PROC=y +CONFIG_MEMCG=y @@ -39202,9 +54528,7 @@ index 000000000000..b3ea44509d98 +CONFIG_USER_NS=y +CONFIG_SCHED_AUTOGROUP=y +CONFIG_BLK_DEV_INITRD=y -+CONFIG_BPF_SYSCALL=y -+CONFIG_EMBEDDED=y -+# CONFIG_COMPAT_BRK is not set ++CONFIG_EXPERT=y +CONFIG_PROFILING=y +CONFIG_ARCH_MULTI_V6=y +# CONFIG_ARCH_MULTI_V7 is not set @@ -39227,30 +54551,28 @@ index 000000000000..b3ea44509d98 +CONFIG_VFP=y +# CONFIG_SUSPEND is not set +CONFIG_PM=y -+CONFIG_RASPBERRYPI_FIRMWARE=y -+CONFIG_CRYPTO_SHA1_ARM=m -+CONFIG_CRYPTO_AES_ARM=m -+CONFIG_OPROFILE=m +CONFIG_JUMP_LABEL=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODVERSIONS=y +CONFIG_MODULE_SRCVERSION_ALL=y ++CONFIG_MODULE_COMPRESS_XZ=y +CONFIG_PARTITION_ADVANCED=y +CONFIG_MAC_PARTITION=y +CONFIG_BINFMT_MISC=m -+CONFIG_CLEANCACHE=y -+CONFIG_FRONTSWAP=y -+CONFIG_CMA=y +CONFIG_ZSWAP=y +CONFIG_Z3FOLD=m -+CONFIG_ZSMALLOC=m ++# CONFIG_COMPAT_BRK is not set ++CONFIG_CMA=y ++CONFIG_LRU_GEN=y ++CONFIG_LRU_GEN_ENABLED=y +CONFIG_NET=y +CONFIG_PACKET=y -+CONFIG_UNIX=y +CONFIG_XFRM_USER=y ++CONFIG_XFRM_INTERFACE=m ++CONFIG_XFRM_SUB_POLICY=y ++CONFIG_XFRM_STATISTICS=y +CONFIG_NET_KEY=m -+CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_ADVANCED_ROUTER=y +CONFIG_IP_MULTIPLE_TABLES=y @@ -39293,7 +54615,6 @@ index 000000000000..b3ea44509d98 +CONFIG_NETFILTER=y +CONFIG_BRIDGE_NETFILTER=m +CONFIG_NF_CONNTRACK=m -+CONFIG_NF_LOG_NETDEV=m +CONFIG_NF_CONNTRACK_ZONES=y +CONFIG_NF_CONNTRACK_EVENTS=y +CONFIG_NF_CONNTRACK_TIMESTAMP=y @@ -39314,7 +54635,6 @@ index 000000000000..b3ea44509d98 +CONFIG_NFT_NUMGEN=m +CONFIG_NFT_CT=m +CONFIG_NFT_FLOW_OFFLOAD=m -+CONFIG_NFT_COUNTER=m +CONFIG_NFT_CONNLIMIT=m +CONFIG_NFT_LOG=m +CONFIG_NFT_LIMIT=m @@ -39322,16 +54642,17 @@ index 000000000000..b3ea44509d98 +CONFIG_NFT_REDIR=m +CONFIG_NFT_NAT=m +CONFIG_NFT_TUNNEL=m -+CONFIG_NFT_OBJREF=m +CONFIG_NFT_QUEUE=m +CONFIG_NFT_QUOTA=m +CONFIG_NFT_REJECT=m +CONFIG_NFT_COMPAT=m +CONFIG_NFT_HASH=m +CONFIG_NFT_FIB_INET=m ++CONFIG_NFT_XFRM=m +CONFIG_NFT_SOCKET=m +CONFIG_NFT_OSF=m +CONFIG_NFT_TPROXY=m ++CONFIG_NFT_SYNPROXY=m +CONFIG_NFT_DUP_NETDEV=m +CONFIG_NFT_FWD_NETDEV=m +CONFIG_NFT_FIB_NETDEV=m @@ -39408,6 +54729,7 @@ index 000000000000..b3ea44509d98 +CONFIG_IP_SET_HASH_NETIFACE=m +CONFIG_IP_SET_LIST_SET=m +CONFIG_IP_VS=m ++CONFIG_IP_VS_IPV6=y +CONFIG_IP_VS_PROTO_TCP=y +CONFIG_IP_VS_PROTO_UDP=y +CONFIG_IP_VS_PROTO_ESP=y @@ -39428,8 +54750,8 @@ index 000000000000..b3ea44509d98 +CONFIG_NFT_DUP_IPV4=m +CONFIG_NFT_FIB_IPV4=m +CONFIG_NF_TABLES_ARP=y -+CONFIG_NF_FLOW_TABLE_IPV4=m +CONFIG_NF_LOG_ARP=m ++CONFIG_NF_LOG_IPV4=m +CONFIG_IP_NF_IPTABLES=m +CONFIG_IP_NF_MATCH_AH=m +CONFIG_IP_NF_MATCH_ECN=m @@ -39442,7 +54764,6 @@ index 000000000000..b3ea44509d98 +CONFIG_IP_NF_TARGET_NETMAP=m +CONFIG_IP_NF_TARGET_REDIRECT=m +CONFIG_IP_NF_MANGLE=m -+CONFIG_IP_NF_TARGET_CLUSTERIP=m +CONFIG_IP_NF_TARGET_ECN=m +CONFIG_IP_NF_TARGET_TTL=m +CONFIG_IP_NF_RAW=m @@ -39451,7 +54772,6 @@ index 000000000000..b3ea44509d98 +CONFIG_IP_NF_ARP_MANGLE=m +CONFIG_NFT_DUP_IPV6=m +CONFIG_NFT_FIB_IPV6=m -+CONFIG_NF_FLOW_TABLE_IPV6=m +CONFIG_IP6_NF_IPTABLES=m +CONFIG_IP6_NF_MATCH_AH=m +CONFIG_IP6_NF_MATCH_EUI64=m @@ -39475,7 +54795,6 @@ index 000000000000..b3ea44509d98 +CONFIG_IP6_NF_TARGET_NPT=m +CONFIG_NF_TABLES_BRIDGE=m +CONFIG_NFT_BRIDGE_REJECT=m -+CONFIG_NF_LOG_BRIDGE=m +CONFIG_BRIDGE_NF_EBTABLES=m +CONFIG_BRIDGE_EBT_BROUTE=m +CONFIG_BRIDGE_EBT_T_FILTER=m @@ -39512,10 +54831,8 @@ index 000000000000..b3ea44509d98 +CONFIG_IEEE802154_6LOWPAN=m +CONFIG_MAC802154=m +CONFIG_NET_SCHED=y -+CONFIG_NET_SCH_CBQ=m +CONFIG_NET_SCH_HTB=m +CONFIG_NET_SCH_HFSC=m -+CONFIG_NET_SCH_ATM=m +CONFIG_NET_SCH_PRIO=m +CONFIG_NET_SCH_MULTIQ=m +CONFIG_NET_SCH_RED=m @@ -39524,7 +54841,6 @@ index 000000000000..b3ea44509d98 +CONFIG_NET_SCH_TEQL=m +CONFIG_NET_SCH_TBF=m +CONFIG_NET_SCH_GRED=m -+CONFIG_NET_SCH_DSMARK=m +CONFIG_NET_SCH_NETEM=m +CONFIG_NET_SCH_DRR=m +CONFIG_NET_SCH_MQPRIO=m @@ -39539,13 +54855,10 @@ index 000000000000..b3ea44509d98 +CONFIG_NET_SCH_INGRESS=m +CONFIG_NET_SCH_PLUG=m +CONFIG_NET_CLS_BASIC=m -+CONFIG_NET_CLS_TCINDEX=m +CONFIG_NET_CLS_ROUTE4=m +CONFIG_NET_CLS_FW=m +CONFIG_NET_CLS_U32=m +CONFIG_CLS_U32_MARK=y -+CONFIG_NET_CLS_RSVP=m -+CONFIG_NET_CLS_RSVP6=m +CONFIG_NET_CLS_FLOW=m +CONFIG_NET_CLS_CGROUP=m +CONFIG_NET_EMATCH=y @@ -39583,13 +54896,6 @@ index 000000000000..b3ea44509d98 +CONFIG_CAN=m +CONFIG_CAN_J1939=m +CONFIG_CAN_ISOTP=m -+CONFIG_CAN_VCAN=m -+CONFIG_CAN_SLCAN=m -+CONFIG_CAN_MCP251X=m -+CONFIG_CAN_MCP251XFD=m -+CONFIG_CAN_EMS_USB=m -+CONFIG_CAN_GS_USB=m -+CONFIG_CAN_PEAK_USB=m +CONFIG_BT=m +CONFIG_BT_RFCOMM=m +CONFIG_BT_RFCOMM_TTY=y @@ -39613,7 +54919,6 @@ index 000000000000..b3ea44509d98 +CONFIG_CFG80211_WEXT=y +CONFIG_MAC80211=m +CONFIG_MAC80211_MESH=y -+CONFIG_WIMAX=m +CONFIG_RFKILL=m +CONFIG_RFKILL_INPUT=y +CONFIG_NET_9P=m @@ -39621,21 +54926,22 @@ index 000000000000..b3ea44509d98 +CONFIG_UEVENT_HELPER=y +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y ++CONFIG_RASPBERRYPI_FIRMWARE=y +CONFIG_MTD=m +CONFIG_MTD_BLOCK=m +CONFIG_MTD_BLOCK2MTD=m ++CONFIG_MTD_SPI_NAND=m +CONFIG_MTD_SPI_NOR=m +CONFIG_MTD_UBI=m +CONFIG_OF_CONFIGFS=y +CONFIG_ZRAM=m +CONFIG_BLK_DEV_LOOP=y -+CONFIG_BLK_DEV_CRYPTOLOOP=m +CONFIG_BLK_DEV_DRBD=m +CONFIG_BLK_DEV_NBD=m +CONFIG_BLK_DEV_RAM=y -+CONFIG_CDROM_PKTCDVD=m +CONFIG_ATA_OVER_ETH=m +CONFIG_EEPROM_AT24=m ++CONFIG_EEPROM_AT25=m +CONFIG_TI_ST=m +CONFIG_SCSI=y +# CONFIG_SCSI_PROC_FS is not set @@ -39646,6 +54952,7 @@ index 000000000000..b3ea44509d98 +CONFIG_SCSI_ISCSI_ATTRS=y +CONFIG_ISCSI_TCP=m +CONFIG_ISCSI_BOOT_SYSFS=m ++CONFIG_ATA=m +CONFIG_MD=y +CONFIG_MD_LINEAR=m +CONFIG_BLK_DEV_DM=m @@ -39657,7 +54964,9 @@ index 000000000000..b3ea44509d98 +CONFIG_DM_LOG_USERSPACE=m +CONFIG_DM_RAID=m +CONFIG_DM_ZERO=m ++CONFIG_DM_MULTIPATH=m +CONFIG_DM_DELAY=m ++CONFIG_DM_INTEGRITY=m +CONFIG_NETDEVICES=y +CONFIG_BONDING=m +CONFIG_DUMMY=m @@ -39675,6 +54984,14 @@ index 000000000000..b3ea44509d98 +CONFIG_QCA7000_UART=m +CONFIG_WIZNET_W5100=m +CONFIG_WIZNET_W5100_SPI=m ++CONFIG_CAN_VCAN=m ++CONFIG_CAN_SLCAN=m ++CONFIG_CAN_MCP251X=m ++CONFIG_CAN_MCP251XFD=m ++CONFIG_CAN_8DEV_USB=m ++CONFIG_CAN_EMS_USB=m ++CONFIG_CAN_GS_USB=m ++CONFIG_CAN_PEAK_USB=m +CONFIG_MDIO_BITBANG=m +CONFIG_PPP=m +CONFIG_PPP_BSDCOMP=m @@ -39754,6 +55071,7 @@ index 000000000000..b3ea44509d98 +CONFIG_MT7601U=m +CONFIG_MT76x0U=m +CONFIG_MT76x2U=m ++CONFIG_MT7921U=m +CONFIG_RT2X00=m +CONFIG_RT2500USB=m +CONFIG_RT73USB=m @@ -39765,11 +55083,15 @@ index 000000000000..b3ea44509d98 +CONFIG_RTL8187=m +CONFIG_RTL8192CU=m +CONFIG_RTL8XXXU=m ++CONFIG_RTW88=m ++CONFIG_RTW88_8822BU=m ++CONFIG_RTW88_8822CU=m ++CONFIG_RTW88_8723DU=m ++CONFIG_RTW88_8821CU=m +CONFIG_USB_ZD1201=m +CONFIG_ZD1211RW=m -+CONFIG_MAC80211_HWSIM=m +CONFIG_USB_NET_RNDIS_WLAN=m -+CONFIG_WIMAX_I2400M_USB=m ++CONFIG_MAC80211_HWSIM=m +CONFIG_IEEE802154_AT86RF230=m +CONFIG_IEEE802154_MRF24J40=m +CONFIG_IEEE802154_CC2520=m @@ -39791,6 +55113,7 @@ index 000000000000..b3ea44509d98 +CONFIG_JOYSTICK_XPAD_LEDS=y +CONFIG_JOYSTICK_PSXPAD_SPI=m +CONFIG_JOYSTICK_PSXPAD_SPI_FF=y ++CONFIG_JOYSTICK_FSIA6B=m +CONFIG_JOYSTICK_RPISENSE=m +CONFIG_INPUT_TOUCHSCREEN=y +CONFIG_TOUCHSCREEN_ADS7846=m @@ -39801,7 +55124,10 @@ index 000000000000..b3ea44509d98 +CONFIG_TOUCHSCREEN_EDT_FT5X06=m +CONFIG_TOUCHSCREEN_RASPBERRYPI_FW=m +CONFIG_TOUCHSCREEN_USB_COMPOSITE=m ++CONFIG_TOUCHSCREEN_TSC2007=m ++CONFIG_TOUCHSCREEN_TSC2007_IIO=y +CONFIG_TOUCHSCREEN_STMPE=m ++CONFIG_TOUCHSCREEN_IQS5XX=m +CONFIG_INPUT_MISC=y +CONFIG_INPUT_AD714X=m +CONFIG_INPUT_ATI_REMOTE2=m @@ -39816,11 +55142,8 @@ index 000000000000..b3ea44509d98 +CONFIG_SERIO=m +CONFIG_SERIO_RAW=m +CONFIG_GAMEPORT=m -+CONFIG_GAMEPORT_NS558=m -+CONFIG_GAMEPORT_L4=m +CONFIG_BRCM_CHAR_DRIVERS=y +CONFIG_BCM_VCIO=y -+CONFIG_BCM2835_DEVGPIOMEM=y +# CONFIG_LEGACY_PTYS is not set +CONFIG_SERIAL_8250=y +# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set @@ -39839,10 +55162,10 @@ index 000000000000..b3ea44509d98 +CONFIG_SERIAL_DEV_BUS=y +CONFIG_TTY_PRINTK=y +CONFIG_HW_RANDOM=y -+CONFIG_RAW_DRIVER=y +CONFIG_TCG_TPM=m +CONFIG_TCG_TIS_SPI=m -+CONFIG_RANDOM_TRUST_BOOTLOADER=y ++CONFIG_TCG_TIS_I2C=m ++CONFIG_RASPBERRYPI_GPIOMEM=m +CONFIG_I2C=y +CONFIG_I2C_CHARDEV=m +CONFIG_I2C_MUX_GPMUX=m @@ -39860,22 +55183,22 @@ index 000000000000..b3ea44509d98 +CONFIG_SPI_GPIO=m +CONFIG_SPI_SPIDEV=m +CONFIG_SPI_SLAVE=y -+CONFIG_PPS=m +CONFIG_PPS_CLIENT_LDISC=m +CONFIG_PPS_CLIENT_GPIO=m +CONFIG_PINCTRL_MCP23S08=m +CONFIG_GPIO_SYSFS=y ++CONFIG_GPIO_MAX7300=m +CONFIG_GPIO_PCA953X=m +CONFIG_GPIO_PCA953X_IRQ=y +CONFIG_GPIO_PCF857X=m +CONFIG_GPIO_ARIZONA=m +CONFIG_GPIO_FSM=m +CONFIG_GPIO_STMPE=y ++CONFIG_GPIO_MAX7301=m +CONFIG_GPIO_MOCKUP=m +CONFIG_W1=m +CONFIG_W1_MASTER_DS2490=m +CONFIG_W1_MASTER_DS2482=m -+CONFIG_W1_MASTER_DS1WM=m +CONFIG_W1_MASTER_GPIO=m +CONFIG_W1_SLAVE_THERM=m +CONFIG_W1_SLAVE_SMEM=m @@ -39895,24 +55218,30 @@ index 000000000000..b3ea44509d98 +CONFIG_RPI_POE_POWER=m +CONFIG_BATTERY_DS2760=m +CONFIG_BATTERY_MAX17040=m ++CONFIG_CHARGER_GPIO=m +CONFIG_BATTERY_GAUGE_LTC2941=m ++CONFIG_SENSORS_ADT7410=m ++CONFIG_SENSORS_AHT10=m ++CONFIG_SENSORS_DRIVETEMP=m +CONFIG_SENSORS_DS1621=m +CONFIG_SENSORS_GPIO_FAN=m +CONFIG_SENSORS_IIO_HWMON=m +CONFIG_SENSORS_JC42=m +CONFIG_SENSORS_LM75=m ++CONFIG_SENSORS_PWM_FAN=m +CONFIG_SENSORS_RASPBERRYPI_HWMON=m -+CONFIG_SENSORS_RPI_POE_FAN=m +CONFIG_SENSORS_SHT21=m +CONFIG_SENSORS_SHT3x=m ++CONFIG_SENSORS_SHT4x=m +CONFIG_SENSORS_SHTC1=m ++CONFIG_SENSORS_EMC2305=m +CONFIG_SENSORS_INA2XX=m +CONFIG_SENSORS_TMP102=m -+CONFIG_THERMAL=y +CONFIG_BCM2835_THERMAL=y +CONFIG_WATCHDOG=y +CONFIG_GPIO_WATCHDOG=m +CONFIG_BCM2835_WDT=y ++CONFIG_MFD_RASPBERRYPI_POE_HAT=m +CONFIG_MFD_STMPE=y +CONFIG_STMPE_SPI=y +CONFIG_MFD_ARIZONA_I2C=m @@ -39923,40 +55252,38 @@ index 000000000000..b3ea44509d98 +CONFIG_REGULATOR_ARIZONA_LDO1=m +CONFIG_REGULATOR_ARIZONA_MICSUPP=m +CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_ATTINY=m ++CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_V2=m +CONFIG_RC_CORE=y -+CONFIG_LIRC=y +CONFIG_BPF_LIRC_MODE2=y ++CONFIG_LIRC=y +CONFIG_RC_DECODERS=y ++CONFIG_IR_IMON_DECODER=m ++CONFIG_IR_JVC_DECODER=m ++CONFIG_IR_MCE_KBD_DECODER=m +CONFIG_IR_NEC_DECODER=m +CONFIG_IR_RC5_DECODER=m +CONFIG_IR_RC6_DECODER=m -+CONFIG_IR_JVC_DECODER=m -+CONFIG_IR_SONY_DECODER=m +CONFIG_IR_SANYO_DECODER=m +CONFIG_IR_SHARP_DECODER=m -+CONFIG_IR_MCE_KBD_DECODER=m ++CONFIG_IR_SONY_DECODER=m +CONFIG_IR_XMP_DECODER=m -+CONFIG_IR_IMON_DECODER=m +CONFIG_RC_DEVICES=y -+CONFIG_RC_ATI_REMOTE=m -+CONFIG_IR_IMON=m -+CONFIG_IR_MCEUSB=m -+CONFIG_IR_REDRAT3=m -+CONFIG_IR_STREAMZAP=m -+CONFIG_IR_IGUANA=m -+CONFIG_IR_TTUSBIR=m -+CONFIG_RC_LOOPBACK=m +CONFIG_IR_GPIO_CIR=m +CONFIG_IR_GPIO_TX=m ++CONFIG_IR_IGUANA=m ++CONFIG_IR_IMON=m ++CONFIG_IR_MCEUSB=m +CONFIG_IR_PWM_TX=m ++CONFIG_IR_REDRAT3=m ++CONFIG_IR_STREAMZAP=m +CONFIG_IR_TOY=m ++CONFIG_IR_TTUSBIR=m ++CONFIG_RC_ATI_REMOTE=m ++CONFIG_RC_LOOPBACK=m +CONFIG_MEDIA_CEC_RC=y +CONFIG_MEDIA_SUPPORT=m +CONFIG_MEDIA_USB_SUPPORT=y -+CONFIG_USB_VIDEO_CLASS=m -+CONFIG_USB_M5602=m -+CONFIG_USB_STV06XX=m -+CONFIG_USB_GL860=m ++CONFIG_USB_GSPCA=m +CONFIG_USB_GSPCA_BENQ=m +CONFIG_USB_GSPCA_CONEX=m +CONFIG_USB_GSPCA_CPIA1=m @@ -39981,13 +55308,13 @@ index 000000000000..b3ea44509d98 +CONFIG_USB_GSPCA_SN9C20X=m +CONFIG_USB_GSPCA_SONIXB=m +CONFIG_USB_GSPCA_SONIXJ=m ++CONFIG_USB_GSPCA_SPCA1528=m +CONFIG_USB_GSPCA_SPCA500=m +CONFIG_USB_GSPCA_SPCA501=m +CONFIG_USB_GSPCA_SPCA505=m +CONFIG_USB_GSPCA_SPCA506=m +CONFIG_USB_GSPCA_SPCA508=m +CONFIG_USB_GSPCA_SPCA561=m -+CONFIG_USB_GSPCA_SPCA1528=m +CONFIG_USB_GSPCA_SQ905=m +CONFIG_USB_GSPCA_SQ905C=m +CONFIG_USB_GSPCA_SQ930X=m @@ -39997,56 +55324,32 @@ index 000000000000..b3ea44509d98 +CONFIG_USB_GSPCA_SUNPLUS=m +CONFIG_USB_GSPCA_T613=m +CONFIG_USB_GSPCA_TOPRO=m ++CONFIG_USB_GSPCA_TOUPTEK=m +CONFIG_USB_GSPCA_TV8532=m +CONFIG_USB_GSPCA_VC032X=m +CONFIG_USB_GSPCA_VICAM=m +CONFIG_USB_GSPCA_XIRLINK_CIT=m +CONFIG_USB_GSPCA_ZC3XX=m ++CONFIG_USB_GL860=m ++CONFIG_USB_M5602=m ++CONFIG_USB_STV06XX=m +CONFIG_USB_PWC=m -+CONFIG_VIDEO_CPIA2=m -+CONFIG_USB_ZR364XX=m -+CONFIG_USB_STKWEBCAM=m +CONFIG_USB_S2255=m +CONFIG_VIDEO_USBTV=m -+CONFIG_VIDEO_PVRUSB2=m -+CONFIG_VIDEO_HDPVR=m -+CONFIG_VIDEO_STK1160_COMMON=m ++CONFIG_USB_VIDEO_CLASS=m +CONFIG_VIDEO_GO7007=m +CONFIG_VIDEO_GO7007_USB=m +CONFIG_VIDEO_GO7007_USB_S2250_BOARD=m ++CONFIG_VIDEO_HDPVR=m ++CONFIG_VIDEO_PVRUSB2=m ++CONFIG_VIDEO_STK1160=m +CONFIG_VIDEO_AU0828=m +CONFIG_VIDEO_AU0828_RC=y +CONFIG_VIDEO_CX231XX=m +CONFIG_VIDEO_CX231XX_ALSA=m +CONFIG_VIDEO_CX231XX_DVB=m -+CONFIG_VIDEO_TM6000=m -+CONFIG_VIDEO_TM6000_ALSA=m -+CONFIG_VIDEO_TM6000_DVB=m -+CONFIG_DVB_USB=m -+CONFIG_DVB_USB_A800=m -+CONFIG_DVB_USB_DIBUSB_MB=m -+CONFIG_DVB_USB_DIBUSB_MB_FAULTY=y -+CONFIG_DVB_USB_DIBUSB_MC=m -+CONFIG_DVB_USB_DIB0700=m -+CONFIG_DVB_USB_UMT_010=m -+CONFIG_DVB_USB_CXUSB=m -+CONFIG_DVB_USB_M920X=m -+CONFIG_DVB_USB_DIGITV=m -+CONFIG_DVB_USB_VP7045=m -+CONFIG_DVB_USB_VP702X=m -+CONFIG_DVB_USB_GP8PSK=m -+CONFIG_DVB_USB_NOVA_T_USB2=m -+CONFIG_DVB_USB_TTUSB2=m -+CONFIG_DVB_USB_DTT200U=m -+CONFIG_DVB_USB_OPERA1=m -+CONFIG_DVB_USB_AF9005=m -+CONFIG_DVB_USB_AF9005_REMOTE=m -+CONFIG_DVB_USB_PCTV452E=m -+CONFIG_DVB_USB_DW2102=m -+CONFIG_DVB_USB_CINERGY_T2=m -+CONFIG_DVB_USB_DTV5100=m -+CONFIG_DVB_USB_AZ6027=m -+CONFIG_DVB_USB_TECHNISAT_USB2=m ++CONFIG_DVB_AS102=m ++CONFIG_DVB_B2C2_FLEXCOP_USB=m +CONFIG_DVB_USB_V2=m +CONFIG_DVB_USB_AF9015=m +CONFIG_DVB_USB_AF9035=m @@ -40054,68 +55357,113 @@ index 000000000000..b3ea44509d98 +CONFIG_DVB_USB_AU6610=m +CONFIG_DVB_USB_AZ6007=m +CONFIG_DVB_USB_CE6230=m ++CONFIG_DVB_USB_DVBSKY=m +CONFIG_DVB_USB_EC168=m +CONFIG_DVB_USB_GL861=m +CONFIG_DVB_USB_LME2510=m +CONFIG_DVB_USB_MXL111SF=m +CONFIG_DVB_USB_RTL28XXU=m -+CONFIG_DVB_USB_DVBSKY=m ++CONFIG_DVB_USB=m ++CONFIG_DVB_USB_A800=m ++CONFIG_DVB_USB_AF9005=m ++CONFIG_DVB_USB_AF9005_REMOTE=m ++CONFIG_DVB_USB_AZ6027=m ++CONFIG_DVB_USB_CINERGY_T2=m ++CONFIG_DVB_USB_CXUSB=m ++CONFIG_DVB_USB_DIB0700=m ++CONFIG_DVB_USB_DIBUSB_MB=m ++CONFIG_DVB_USB_DIBUSB_MB_FAULTY=y ++CONFIG_DVB_USB_DIBUSB_MC=m ++CONFIG_DVB_USB_DIGITV=m ++CONFIG_DVB_USB_DTT200U=m ++CONFIG_DVB_USB_DTV5100=m ++CONFIG_DVB_USB_DW2102=m ++CONFIG_DVB_USB_GP8PSK=m ++CONFIG_DVB_USB_M920X=m ++CONFIG_DVB_USB_NOVA_T_USB2=m ++CONFIG_DVB_USB_OPERA1=m ++CONFIG_DVB_USB_PCTV452E=m ++CONFIG_DVB_USB_TECHNISAT_USB2=m ++CONFIG_DVB_USB_TTUSB2=m ++CONFIG_DVB_USB_UMT_010=m ++CONFIG_DVB_USB_VP702X=m ++CONFIG_DVB_USB_VP7045=m +CONFIG_SMS_USB_DRV=m -+CONFIG_DVB_B2C2_FLEXCOP_USB=m -+CONFIG_DVB_AS102=m +CONFIG_VIDEO_EM28XX=m +CONFIG_VIDEO_EM28XX_V4L2=m +CONFIG_VIDEO_EM28XX_ALSA=m +CONFIG_VIDEO_EM28XX_DVB=m ++CONFIG_RADIO_SAA7706H=m ++CONFIG_RADIO_SHARK=m ++CONFIG_RADIO_SHARK2=m ++CONFIG_RADIO_SI4713=m ++CONFIG_RADIO_TEA5764=m ++CONFIG_RADIO_TEF6862=m ++CONFIG_RADIO_WL1273=m ++CONFIG_USB_DSBR=m ++CONFIG_USB_KEENE=m ++CONFIG_USB_MA901=m ++CONFIG_USB_MR800=m +CONFIG_RADIO_SI470X=m +CONFIG_USB_SI470X=m +CONFIG_I2C_SI470X=m -+CONFIG_RADIO_SI4713=m +CONFIG_I2C_SI4713=m -+CONFIG_USB_MR800=m -+CONFIG_USB_DSBR=m -+CONFIG_RADIO_SHARK=m -+CONFIG_RADIO_SHARK2=m -+CONFIG_USB_KEENE=m -+CONFIG_USB_MA901=m -+CONFIG_RADIO_TEA5764=m -+CONFIG_RADIO_SAA7706H=m -+CONFIG_RADIO_TEF6862=m -+CONFIG_RADIO_WL1273=m +CONFIG_RADIO_WL128X=m +CONFIG_V4L_PLATFORM_DRIVERS=y ++CONFIG_VIDEO_MUX=m +CONFIG_VIDEO_BCM2835_UNICAM=m -+CONFIG_VIDEO_UDA1342=m ++CONFIG_VIDEO_ARDUCAM_64MP=m ++CONFIG_VIDEO_ARDUCAM_PIVARIETY=m ++CONFIG_VIDEO_IMX219=m ++CONFIG_VIDEO_IMX258=m ++CONFIG_VIDEO_IMX290=m ++CONFIG_VIDEO_IMX296=m ++CONFIG_VIDEO_IMX477=m ++CONFIG_VIDEO_IMX519=m ++CONFIG_VIDEO_IMX708=m ++CONFIG_VIDEO_MT9V011=m ++CONFIG_VIDEO_OV2311=m ++CONFIG_VIDEO_OV5647=m ++CONFIG_VIDEO_OV64A40=m ++CONFIG_VIDEO_OV7251=m ++CONFIG_VIDEO_OV7640=m ++CONFIG_VIDEO_OV9282=m ++CONFIG_VIDEO_AD5398=m ++CONFIG_VIDEO_AK7375=m ++CONFIG_VIDEO_BU64754=m ++CONFIG_VIDEO_DW9807_VCM=m +CONFIG_VIDEO_SONY_BTF_MPX=m ++CONFIG_VIDEO_UDA1342=m +CONFIG_VIDEO_ADV7180=m +CONFIG_VIDEO_TC358743=m +CONFIG_VIDEO_TVP5150=m +CONFIG_VIDEO_TW2804=m +CONFIG_VIDEO_TW9903=m +CONFIG_VIDEO_TW9906=m -+CONFIG_VIDEO_IMX219=m -+CONFIG_VIDEO_IMX290=m -+CONFIG_VIDEO_IMX477=m -+CONFIG_VIDEO_IMX519=m -+CONFIG_VIDEO_OV5647=m -+CONFIG_VIDEO_OV7251=m -+CONFIG_VIDEO_OV7640=m -+CONFIG_VIDEO_OV9281=m +CONFIG_VIDEO_IRS1125=m -+CONFIG_VIDEO_MT9V011=m ++CONFIG_VIDEO_I2C=m ++CONFIG_AUXDISPLAY=y ++CONFIG_HD44780=m +CONFIG_DRM=m +CONFIG_DRM_LOAD_EDID_FIRMWARE=y +CONFIG_DRM_UDL=m +CONFIG_DRM_PANEL_SIMPLE=m ++CONFIG_DRM_PANEL_ILITEK_ILI9806E=m +CONFIG_DRM_PANEL_JDI_LT070ME05000=m +CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN=m ++CONFIG_DRM_PANEL_SITRONIX_ST7701=m ++CONFIG_DRM_PANEL_TPO_Y17P=m ++CONFIG_DRM_PANEL_WAVESHARE_TOUCHSCREEN=m +CONFIG_DRM_DISPLAY_CONNECTOR=m +CONFIG_DRM_SIMPLE_BRIDGE=m +CONFIG_DRM_TOSHIBA_TC358762=m +CONFIG_DRM_VC4=m +CONFIG_DRM_VC4_HDMI_CEC=y ++CONFIG_DRM_PANEL_MIPI_DBI=m ++CONFIG_TINYDRM_HX8357D=m +CONFIG_TINYDRM_ILI9225=m +CONFIG_TINYDRM_ILI9341=m ++CONFIG_TINYDRM_ILI9486=m +CONFIG_TINYDRM_MI0283QT=m +CONFIG_TINYDRM_REPAPER=m +CONFIG_TINYDRM_ST7586=m @@ -40123,13 +55471,13 @@ index 000000000000..b3ea44509d98 +CONFIG_DRM_GUD=m +CONFIG_FB=y +CONFIG_FB_BCM2708=y -+CONFIG_FB_UDL=m +CONFIG_FB_SIMPLE=y +CONFIG_FB_SSD1307=m +CONFIG_FB_RPISENSE=m ++CONFIG_BACKLIGHT_PWM=m +CONFIG_BACKLIGHT_RPI=m ++CONFIG_BACKLIGHT_LM3630A=m +CONFIG_BACKLIGHT_GPIO=m -+CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y +CONFIG_LOGO=y +# CONFIG_LOGO_LINUX_MONO is not set @@ -40139,6 +55487,7 @@ index 000000000000..b3ea44509d98 +CONFIG_SND_OSSEMUL=y +CONFIG_SND_PCM_OSS=m +CONFIG_SND_HRTIMER=m ++CONFIG_SND_DYNAMIC_MINORS=y +CONFIG_SND_SEQUENCER=m +CONFIG_SND_SEQ_DUMMY=m +CONFIG_SND_DUMMY=m @@ -40203,6 +55552,7 @@ index 000000000000..b3ea44509d98 +CONFIG_SND_SOC_MA120X0P=m +CONFIG_SND_SOC_MAX98357A=m +CONFIG_SND_SOC_SPDIF=m ++CONFIG_SND_SOC_TLV320AIC23_I2C=m +CONFIG_SND_SOC_WM8804_I2C=m +CONFIG_SND_SOC_WM8960=m +CONFIG_SND_SIMPLE_CARD=m @@ -40243,11 +55593,15 @@ index 000000000000..b3ea44509d98 +CONFIG_HID_MICROSOFT=m +CONFIG_HID_MONTEREY=m +CONFIG_HID_MULTITOUCH=m ++CONFIG_HID_NINTENDO=m ++CONFIG_NINTENDO_FF=y +CONFIG_HID_NTRIG=m +CONFIG_HID_ORTEK=m +CONFIG_HID_PANTHERLORD=m +CONFIG_HID_PETALYNX=m +CONFIG_HID_PICOLCD=m ++CONFIG_HID_PLAYSTATION=m ++CONFIG_PLAYSTATION_FF=y +CONFIG_HID_ROCCAT=m +CONFIG_HID_SAMSUNG=m +CONFIG_HID_SONY=m @@ -40267,7 +55621,6 @@ index 000000000000..b3ea44509d98 +CONFIG_HID_ZYDACRON=m +CONFIG_HID_PID=y +CONFIG_USB_HIDDEV=y -+CONFIG_I2C_HID=m +CONFIG_USB=y +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y +CONFIG_USB_MON=m @@ -40336,7 +55689,6 @@ index 000000000000..b3ea44509d98 +CONFIG_USB_SERIAL_SYMBOL=m +CONFIG_USB_SERIAL_TI=m +CONFIG_USB_SERIAL_CYBERJACK=m -+CONFIG_USB_SERIAL_XIRCOM=m +CONFIG_USB_SERIAL_OPTION=m +CONFIG_USB_SERIAL_OMNINET=m +CONFIG_USB_SERIAL_OPTICON=m @@ -40354,7 +55706,6 @@ index 000000000000..b3ea44509d98 +CONFIG_USB_CYPRESS_CY7C63=m +CONFIG_USB_CYTHERM=m +CONFIG_USB_IDMOUSE=m -+CONFIG_USB_FTDI_ELAN=m +CONFIG_USB_APPLEDISPLAY=m +CONFIG_USB_LD=m +CONFIG_USB_TRANCEVIBRATOR=m @@ -40367,7 +55718,8 @@ index 000000000000..b3ea44509d98 +CONFIG_USB_CXACRU=m +CONFIG_USB_UEAGLEATM=m +CONFIG_USB_XUSBATM=m -+CONFIG_USB_GADGET=m ++CONFIG_NOP_USB_XCEIV=y ++CONFIG_USB_GADGET=y +CONFIG_USB_CONFIGFS=m +CONFIG_USB_CONFIGFS_SERIAL=y +CONFIG_USB_CONFIGFS_ACM=y @@ -40408,6 +55760,7 @@ index 000000000000..b3ea44509d98 +CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MMC_SPI=m +CONFIG_LEDS_CLASS=y ++CONFIG_LEDS_CLASS_MULTICOLOR=m +CONFIG_LEDS_PCA9532=m +CONFIG_LEDS_GPIO=y +CONFIG_LEDS_PCA955X=m @@ -40419,7 +55772,6 @@ index 000000000000..b3ea44509d98 +CONFIG_LEDS_TRIGGER_HEARTBEAT=y +CONFIG_LEDS_TRIGGER_BACKLIGHT=y +CONFIG_LEDS_TRIGGER_CPU=y -+CONFIG_LEDS_TRIGGER_GPIO=y +CONFIG_LEDS_TRIGGER_DEFAULT_ON=y +CONFIG_LEDS_TRIGGER_TRANSIENT=m +CONFIG_LEDS_TRIGGER_CAMERA=m @@ -40454,6 +55806,8 @@ index 000000000000..b3ea44509d98 +CONFIG_RTC_DRV_RX8025=m +CONFIG_RTC_DRV_EM3027=m +CONFIG_RTC_DRV_RV3028=m ++CONFIG_RTC_DRV_RV3032=m ++CONFIG_RTC_DRV_RV8803=m +CONFIG_RTC_DRV_SD3078=m +CONFIG_RTC_DRV_M41T93=m +CONFIG_RTC_DRV_M41T94=m @@ -40474,16 +55828,14 @@ index 000000000000..b3ea44509d98 +CONFIG_DMABUF_HEAPS=y +CONFIG_DMABUF_HEAPS_SYSTEM=y +CONFIG_DMABUF_HEAPS_CMA=y -+CONFIG_AUXDISPLAY=y -+CONFIG_HD44780=m +CONFIG_UIO=m +CONFIG_UIO_PDRV_GENIRQ=m +CONFIG_STAGING=y +CONFIG_PRISM2_USB=m +CONFIG_R8712U=m -+CONFIG_R8188EU=m +CONFIG_VT6656=m +CONFIG_STAGING_MEDIA=y ++CONFIG_STAGING_MEDIA_DEPRECATED=y +CONFIG_FB_TFT=m +CONFIG_FB_TFT_AGM1264K_FL=m +CONFIG_FB_TFT_BD663474=m @@ -40511,9 +55863,9 @@ index 000000000000..b3ea44509d98 +CONFIG_FB_TFT_ST7789V=m +CONFIG_FB_TFT_TINYLCD=m +CONFIG_FB_TFT_TLS8204=m ++CONFIG_FB_TFT_UC1611=m +CONFIG_FB_TFT_UC1701=m +CONFIG_FB_TFT_UPD161704=m -+CONFIG_FB_TFT_WATTEROTT=m +CONFIG_BCM2835_VCHIQ=y +CONFIG_SND_BCM2835=m +CONFIG_VIDEO_BCM2835=m @@ -40524,32 +55876,40 @@ index 000000000000..b3ea44509d98 +CONFIG_BCM2835_MBOX=y +# CONFIG_IOMMU_SUPPORT is not set +CONFIG_RASPBERRYPI_POWER=y -+CONFIG_EXTCON=m -+CONFIG_EXTCON_ARIZONA=m +CONFIG_IIO=m +CONFIG_IIO_BUFFER_CB=m ++CONFIG_IIO_SW_TRIGGER=m +CONFIG_MCP320X=m +CONFIG_MCP3422=m +CONFIG_TI_ADS1015=m +CONFIG_BME680=m +CONFIG_CCS811=m +CONFIG_SENSIRION_SGP30=m -+CONFIG_SPS30=m ++CONFIG_SPS30_I2C=m +CONFIG_MAX30102=m +CONFIG_DHT11=m +CONFIG_HDC100X=m +CONFIG_HTU21=m ++CONFIG_SI7020=m ++CONFIG_BOSCH_BNO055_I2C=m +CONFIG_INV_MPU6050_I2C=m +CONFIG_APDS9960=m +CONFIG_BH1750=m +CONFIG_TSL4531=m +CONFIG_VEML6070=m ++CONFIG_IIO_HRTIMER_TRIGGER=m ++CONFIG_IIO_INTERRUPT_TRIGGER=m ++CONFIG_IIO_SYSFS_TRIGGER=m +CONFIG_BMP280=m ++CONFIG_MS5637=m +CONFIG_MAXIM_THERMOCOUPLE=m +CONFIG_MAX31856=m ++CONFIG_PWM=y +CONFIG_PWM_BCM2835=m +CONFIG_PWM_PCA9685=m ++CONFIG_PWM_RASPBERRYPI_POE=m +CONFIG_RPI_AXIPERF=m ++CONFIG_MUX_GPIO=m +CONFIG_EXT4_FS=y +CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_EXT4_FS_SECURITY=y @@ -40575,13 +55935,12 @@ index 000000000000..b3ea44509d98 +CONFIG_FANOTIFY=y +CONFIG_QFMT_V1=m +CONFIG_QFMT_V2=m -+CONFIG_AUTOFS4_FS=y ++CONFIG_AUTOFS_FS=y +CONFIG_FUSE_FS=m +CONFIG_CUSE=m +CONFIG_OVERLAY_FS=m +CONFIG_FSCACHE=y +CONFIG_FSCACHE_STATS=y -+CONFIG_FSCACHE_HISTOGRAM=y +CONFIG_CACHEFILES=y +CONFIG_ISO9660_FS=m +CONFIG_JOLIET=y @@ -40593,6 +55952,7 @@ index 000000000000..b3ea44509d98 +CONFIG_EXFAT_FS=m +CONFIG_NTFS_FS=m +CONFIG_NTFS_RW=y ++CONFIG_NTFS3_FS=m +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_ECRYPT_FS=m @@ -40605,6 +55965,9 @@ index 000000000000..b3ea44509d98 +CONFIG_SQUASHFS_XATTR=y +CONFIG_SQUASHFS_LZO=y +CONFIG_SQUASHFS_XZ=y ++CONFIG_PSTORE=y ++CONFIG_PSTORE_CONSOLE=y ++CONFIG_PSTORE_RAM=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3_ACL=y +CONFIG_NFS_V4=y @@ -40614,14 +55977,17 @@ index 000000000000..b3ea44509d98 +CONFIG_ROOT_NFS=y +CONFIG_NFS_FSCACHE=y +CONFIG_NFSD=m ++CONFIG_NFSD_V2=y ++CONFIG_NFSD_V2_ACL=y +CONFIG_NFSD_V3_ACL=y +CONFIG_NFSD_V4=y ++CONFIG_CEPH_FS=m +CONFIG_CIFS=m -+CONFIG_CIFS_WEAK_PW_HASH=y +CONFIG_CIFS_UPCALL=y +CONFIG_CIFS_XATTR=y +CONFIG_CIFS_DFS_UPCALL=y +CONFIG_CIFS_FSCACHE=y ++CONFIG_SMB_SERVER=m +CONFIG_9P_FS=m +CONFIG_9P_FS_POSIX_ACL=y +CONFIG_NLS_DEFAULT="utf8" @@ -40663,33 +56029,39 @@ index 000000000000..b3ea44509d98 +CONFIG_NLS_KOI8_R=m +CONFIG_NLS_KOI8_U=m +CONFIG_DLM=m ++CONFIG_KEY_DH_OPERATIONS=y +CONFIG_SECURITY=y +CONFIG_SECURITY_APPARMOR=y +CONFIG_LSM="" +CONFIG_CRYPTO_USER=m +CONFIG_CRYPTO_CRYPTD=m -+CONFIG_CRYPTO_CHACHA20POLY1305=m ++CONFIG_CRYPTO_CAST5=m ++CONFIG_CRYPTO_DES=y ++CONFIG_CRYPTO_TWOFISH=m ++CONFIG_CRYPTO_ADIANTUM=m +CONFIG_CRYPTO_CBC=y +CONFIG_CRYPTO_CTS=m +CONFIG_CRYPTO_XTS=m -+CONFIG_CRYPTO_ADIANTUM=m -+CONFIG_CRYPTO_XCBC=m -+CONFIG_CRYPTO_TGR192=m ++CONFIG_CRYPTO_CHACHA20POLY1305=m ++CONFIG_CRYPTO_MD4=m +CONFIG_CRYPTO_WP512=m -+CONFIG_CRYPTO_CAST5=m -+CONFIG_CRYPTO_DES=y ++CONFIG_CRYPTO_XCBC=m +CONFIG_CRYPTO_LZ4=m +CONFIG_CRYPTO_USER_API_HASH=m +CONFIG_CRYPTO_USER_API_SKCIPHER=m +CONFIG_CRYPTO_USER_API_RNG=m +CONFIG_CRYPTO_USER_API_AEAD=m ++CONFIG_CRYPTO_SHA1_ARM=m ++CONFIG_CRYPTO_AES_ARM=m +# CONFIG_CRYPTO_HW is not set ++CONFIG_PKCS8_PRIVATE_KEY_PARSER=m +CONFIG_CRC_ITU_T=y +CONFIG_LIBCRC32C=y +CONFIG_DMA_CMA=y +CONFIG_CMA_SIZE_MBYTES=5 +CONFIG_PRINTK_TIME=y +CONFIG_BOOT_PRINTK_DELAY=y ++CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1f6 +CONFIG_KGDB=y +CONFIG_KGDB_KDB=y +CONFIG_KDB_KEYBOARD=y @@ -40698,24 +56070,11 @@ index 000000000000..b3ea44509d98 +CONFIG_LATENCYTOP=y +CONFIG_FUNCTION_PROFILER=y +CONFIG_STACK_TRACER=y -+CONFIG_IRQSOFF_TRACER=y +CONFIG_SCHED_TRACER=y +CONFIG_BLK_DEV_IO_TRACE=y +# CONFIG_UPROBE_EVENTS is not set -diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig -index a611b0c1e540..ea2715c9f923 100644 ---- a/arch/arm/configs/multi_v7_defconfig -+++ b/arch/arm/configs/multi_v7_defconfig -@@ -1089,6 +1089,7 @@ CONFIG_ROCKCHIP_EFUSE=m - CONFIG_NVMEM_SUNXI_SID=y - CONFIG_NVMEM_VF610_OCOTP=y - CONFIG_MESON_MX_EFUSE=m -+CONFIG_NVMEM_RMEM=m - CONFIG_FSI=m - CONFIG_FSI_MASTER_GPIO=m - CONFIG_FSI_MASTER_HUB=m diff --git a/arch/arm/include/asm/cacheflush.h b/arch/arm/include/asm/cacheflush.h -index 2e24e765e6d3..3c285a257e89 100644 +index 1075534b0a2e..34c020563133 100644 --- a/arch/arm/include/asm/cacheflush.h +++ b/arch/arm/include/asm/cacheflush.h @@ -91,6 +91,21 @@ @@ -40826,10 +56185,10 @@ index 6c607c68f3ad..ba7fc0bc9a15 100644 + #endif diff --git a/arch/arm/include/asm/uaccess.h b/arch/arm/include/asm/uaccess.h -index da2a9e5fc59b..5e13b677fadd 100644 +index 2162ebc6c77a..e766a121555a 100644 --- a/arch/arm/include/asm/uaccess.h +++ b/arch/arm/include/asm/uaccess.h -@@ -509,6 +509,9 @@ do { \ +@@ -500,6 +500,9 @@ do { \ extern unsigned long __must_check arm_copy_from_user(void *to, const void __user *from, unsigned long n); @@ -40840,10 +56199,10 @@ index da2a9e5fc59b..5e13b677fadd 100644 raw_copy_from_user(void *to, const void __user *from, unsigned long n) { diff --git a/arch/arm/kernel/fiq.c b/arch/arm/kernel/fiq.c -index 91e37dfe0396..6f2cc6978443 100644 +index 9b51562b1f86..d7a1048763a2 100644 --- a/arch/arm/kernel/fiq.c +++ b/arch/arm/kernel/fiq.c -@@ -63,6 +63,8 @@ +@@ -64,6 +64,8 @@ static unsigned long dfl_fiq_insn; static struct pt_regs dfl_fiq_regs; @@ -40852,7 +56211,7 @@ index 91e37dfe0396..6f2cc6978443 100644 /* Default reacquire function * - we always relinquish FIQ control * - we always reacquire FIQ control -@@ -147,6 +149,8 @@ static int fiq_start; +@@ -148,6 +150,8 @@ static int fiq_start; void enable_fiq(int fiq) { @@ -40874,7 +56233,7 @@ index 8dd26e1a9bd6..eef484756af2 100644 + mov pc, r8 +ENDPROC(__FIQ_Branch) diff --git a/arch/arm/kernel/reboot.c b/arch/arm/kernel/reboot.c -index 0ce388f15422..63373adab475 100644 +index 3f0d5c3dae11..cfdbcc9826c0 100644 --- a/arch/arm/kernel/reboot.c +++ b/arch/arm/kernel/reboot.c @@ -102,9 +102,7 @@ void machine_shutdown(void) @@ -40889,10 +56248,10 @@ index 0ce388f15422..63373adab475 100644 /* diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c -index d7ae50b32c7b..fd6e4580d621 100644 +index 5cfc9c5056a7..0ea30401beaa 100644 --- a/arch/arm/kernel/setup.c +++ b/arch/arm/kernel/setup.c -@@ -1257,6 +1257,8 @@ static int c_show(struct seq_file *m, void *v) +@@ -1277,6 +1277,8 @@ static int c_show(struct seq_file *m, void *v) { int i, j; u32 cpuid; @@ -40901,7 +56260,7 @@ index d7ae50b32c7b..fd6e4580d621 100644 for_each_online_cpu(i) { /* -@@ -1316,6 +1318,14 @@ static int c_show(struct seq_file *m, void *v) +@@ -1336,6 +1338,14 @@ static int c_show(struct seq_file *m, void *v) seq_printf(m, "Revision\t: %04x\n", system_rev); seq_printf(m, "Serial\t\t: %s\n", system_serial); @@ -40917,7 +56276,7 @@ index d7ae50b32c7b..fd6e4580d621 100644 } diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile -index 6d2ba454f25b..8271cde92dec 100644 +index 650404be6768..7fd404d75064 100644 --- a/arch/arm/lib/Makefile +++ b/arch/arm/lib/Makefile @@ -7,8 +7,8 @@ @@ -41114,10 +56473,10 @@ index 000000000000..5d4bda19ad20 +92: +.endm diff --git a/arch/arm/lib/copy_from_user.S b/arch/arm/lib/copy_from_user.S -index f8016e3db65d..ab7bf28dbec0 100644 +index 270de7debd0f..2eda93fc22e6 100644 --- a/arch/arm/lib/copy_from_user.S +++ b/arch/arm/lib/copy_from_user.S -@@ -107,7 +107,8 @@ +@@ -104,7 +104,8 @@ UNWIND( .save {r0, r2, r3, \regs} ) .text @@ -41125,9 +56484,9 @@ index f8016e3db65d..ab7bf28dbec0 100644 +ENTRY(__copy_from_user_std) +WEAK(arm_copy_from_user) #ifdef CONFIG_CPU_SPECTRE - get_thread_info r3 - ldr r3, [r3, #TI_ADDR_LIMIT] -@@ -117,6 +118,7 @@ ENTRY(arm_copy_from_user) + ldr r3, =TASK_SIZE + uaccess_mask_range_ptr r1, r2, r3, ip +@@ -113,6 +114,7 @@ ENTRY(arm_copy_from_user) #include "copy_template.S" ENDPROC(arm_copy_from_user) @@ -41471,10 +56830,10 @@ index 000000000000..bf6e4edfc9d3 +ENDPROC(memcmp) diff --git a/arch/arm/lib/memcpy_rpi.S b/arch/arm/lib/memcpy_rpi.S new file mode 100644 -index 000000000000..77a1dbe28a18 +index 000000000000..d246f9f3903a --- /dev/null +++ b/arch/arm/lib/memcpy_rpi.S -@@ -0,0 +1,63 @@ +@@ -0,0 +1,65 @@ +/* +Copyright (c) 2013, Raspberry Pi Foundation +Copyright (c) 2013, RISC OS Open Ltd @@ -41535,7 +56894,9 @@ index 000000000000..77a1dbe28a18 + +ENTRY(mmiocpy) +ENTRY(memcpy) ++ENTRY(__memcpy) + memcpy 0 ++ENDPROC(__memcpy) +ENDPROC(memcpy) +ENDPROC(mmiocpy) diff --git a/arch/arm/lib/memcpymove.h b/arch/arm/lib/memcpymove.h @@ -42103,10 +57464,10 @@ index 000000000000..5715dfd95859 +ENDPROC(memmove) diff --git a/arch/arm/lib/memset_rpi.S b/arch/arm/lib/memset_rpi.S new file mode 100644 -index 000000000000..2a2d86759397 +index 000000000000..087d68ea5d18 --- /dev/null +++ b/arch/arm/lib/memset_rpi.S -@@ -0,0 +1,130 @@ +@@ -0,0 +1,132 @@ +/* +Copyright (c) 2013, Raspberry Pi Foundation +Copyright (c) 2013, RISC OS Open Ltd @@ -42161,6 +57522,7 @@ index 000000000000..2a2d86759397 + */ +ENTRY(mmioset) +ENTRY(memset) ++ENTRY(__memset) + + S .req a1 + DAT0 .req a2 @@ -42235,10 +57597,11 @@ index 000000000000..2a2d86759397 + .unreq DAT3 +ENDPROC(__memset64) +ENDPROC(__memset32) ++ENDPROC(__memset) +ENDPROC(memset) +ENDPROC(mmioset) diff --git a/arch/arm/lib/uaccess_with_memcpy.c b/arch/arm/lib/uaccess_with_memcpy.c -index 106f83a5ea6d..b483e5713039 100644 +index 2f6163f05e93..f5a5e2e1084a 100644 --- a/arch/arm/lib/uaccess_with_memcpy.c +++ b/arch/arm/lib/uaccess_with_memcpy.c @@ -19,6 +19,14 @@ @@ -42265,7 +57628,7 @@ index 106f83a5ea6d..b483e5713039 100644 return 0; /* -@@ -86,7 +94,46 @@ pin_page_for_write(const void __user *_addr, pte_t **ptep, spinlock_t **ptlp) +@@ -89,7 +97,46 @@ pin_page_for_write(const void __user *_addr, pte_t **ptep, spinlock_t **ptlp) return 1; } @@ -42313,7 +57676,7 @@ index 106f83a5ea6d..b483e5713039 100644 __copy_to_user_memcpy(void __user *to, const void *from, unsigned long n) { unsigned long ua_flags; -@@ -139,6 +186,57 @@ __copy_to_user_memcpy(void __user *to, const void *from, unsigned long n) +@@ -137,6 +184,52 @@ __copy_to_user_memcpy(void __user *to, const void *from, unsigned long n) return n; } @@ -42323,11 +57686,6 @@ index 106f83a5ea6d..b483e5713039 100644 + unsigned long ua_flags; + int atomic; + -+ if (unlikely(uaccess_kernel())) { -+ memcpy(to, (const void *)from, n); -+ return 0; -+ } -+ + /* the mmap semaphore is taken only if not in an atomic context */ + atomic = in_atomic(); + @@ -42371,7 +57729,7 @@ index 106f83a5ea6d..b483e5713039 100644 unsigned long arm_copy_to_user(void __user *to, const void *from, unsigned long n) { -@@ -149,7 +247,7 @@ arm_copy_to_user(void __user *to, const void *from, unsigned long n) +@@ -147,7 +240,7 @@ arm_copy_to_user(void __user *to, const void *from, unsigned long n) * With frame pointer disabled, tail call optimization kicks in * as well making this test almost invisible. */ @@ -42380,7 +57738,7 @@ index 106f83a5ea6d..b483e5713039 100644 unsigned long ua_flags = uaccess_save_and_enable(); n = __copy_to_user_std(to, from, n); uaccess_restore(ua_flags); -@@ -159,6 +257,32 @@ arm_copy_to_user(void __user *to, const void *from, unsigned long n) +@@ -157,6 +250,32 @@ arm_copy_to_user(void __user *to, const void *from, unsigned long n) } return n; } @@ -42414,14 +57772,13 @@ index 106f83a5ea6d..b483e5713039 100644 static unsigned long noinline __clear_user_memset(void __user *addr, unsigned long n) diff --git a/arch/arm/mach-bcm/Kconfig b/arch/arm/mach-bcm/Kconfig -index ae790908fc74..822125c5707a 100644 +index 8789d93a7c04..d3206a2a257b 100644 --- a/arch/arm/mach-bcm/Kconfig +++ b/arch/arm/mach-bcm/Kconfig -@@ -161,9 +161,12 @@ config ARCH_BCM2835 +@@ -159,9 +159,11 @@ config ARCH_BCM2835 select ARM_TIMER_SP804 select HAVE_ARM_ARCH_TIMER if ARCH_MULTI_V7 select BCM2835_TIMER -+ select BRCMSTB_L2_IRQ + select FIQ select PINCTRL select PINCTRL_BCM2835 @@ -42430,10 +57787,27 @@ index ae790908fc74..822125c5707a 100644 help This enables support for the Broadcom BCM2711 and BCM283x SoCs. This SoC is used in the Raspberry Pi and Roku 2 devices. -@@ -182,6 +185,13 @@ config ARCH_BCM_53573 +@@ -180,6 +182,30 @@ config ARCH_BCM_53573 The base chip is BCM53573 and there are some packaging modifications like BCM47189 and BCM47452. ++config ARCH_BCM_63XX ++ bool "Broadcom BCM63xx DSL SoC" ++ depends on ARCH_MULTI_V7 ++ select ARCH_HAS_RESET_CONTROLLER ++ select ARM_ERRATA_754322 ++ select ARM_ERRATA_764369 if SMP ++ select ARM_GIC ++ select ARM_GLOBAL_TIMER ++ select CACHE_L2X0 ++ select HAVE_ARM_ARCH_TIMER ++ select HAVE_ARM_TWD if SMP ++ select HAVE_ARM_SCU if SMP ++ help ++ This enables support for systems based on Broadcom DSL SoCs. ++ It currently supports the 'BCM63XX' ARM-based family, which includes ++ the BCM63138 variant. ++ +config BCM2835_FAST_MEMCPY + bool "Enable optimized __copy_to_user and __copy_from_user" + depends on ARCH_BCM2835 && ARCH_MULTI_V6 @@ -42441,8 +57815,8 @@ index ae790908fc74..822125c5707a 100644 + help + Optimized versions of __copy_to_user and __copy_from_user for Pi1. + - config ARCH_BCM_63XX - bool "Broadcom BCM63xx DSL SoC" + config ARCH_BRCMSTB + bool "Broadcom BCM7XXX based boards" depends on ARCH_MULTI_V7 diff --git a/arch/arm/mach-bcm/board_bcm2835.c b/arch/arm/mach-bcm/board_bcm2835.c index bfc556f76720..91a758c61f48 100644 @@ -42579,10 +57953,10 @@ index bfc556f76720..91a758c61f48 100644 + .smp = smp_ops(bcm2836_smp_ops), +MACHINE_END diff --git a/arch/arm/mm/cache-v6.S b/arch/arm/mm/cache-v6.S -index f0f65eb073e4..868011801521 100644 +index 250c83bf7158..abae7ff5defc 100644 --- a/arch/arm/mm/cache-v6.S +++ b/arch/arm/mm/cache-v6.S -@@ -198,7 +198,7 @@ ENTRY(v6_flush_kern_dcache_area) +@@ -200,7 +200,7 @@ ENTRY(v6_flush_kern_dcache_area) * - start - virtual start address of region * - end - virtual end address of region */ @@ -42591,7 +57965,7 @@ index f0f65eb073e4..868011801521 100644 #ifdef CONFIG_DMA_CACHE_RWFO ldrb r2, [r0] @ read for ownership strb r2, [r0] @ write for ownership -@@ -243,7 +243,7 @@ v6_dma_inv_range: +@@ -245,7 +245,7 @@ v6_dma_inv_range: * - start - virtual start address of region * - end - virtual end address of region */ @@ -42601,10 +57975,10 @@ index f0f65eb073e4..868011801521 100644 1: #ifdef CONFIG_DMA_CACHE_RWFO diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S -index 307f381eee71..b97282e76bca 100644 +index 127afe2096ba..6a16d88e2d36 100644 --- a/arch/arm/mm/cache-v7.S +++ b/arch/arm/mm/cache-v7.S -@@ -364,7 +364,8 @@ ENDPROC(v7_flush_kern_dcache_area) +@@ -361,7 +361,8 @@ ENDPROC(v7_flush_kern_dcache_area) * - start - virtual start address of region * - end - virtual end address of region */ @@ -42614,7 +57988,7 @@ index 307f381eee71..b97282e76bca 100644 dcache_line_size r2, r3 sub r3, r2, #1 tst r0, r3 -@@ -394,7 +395,8 @@ ENDPROC(v7_dma_inv_range) +@@ -391,7 +392,8 @@ ENDPROC(v7_dma_inv_range) * - start - virtual start address of region * - end - virtual end address of region */ @@ -42625,7 +57999,7 @@ index 307f381eee71..b97282e76bca 100644 sub r3, r2, #1 bic r0, r0, r3 diff --git a/arch/arm/mm/proc-macros.S b/arch/arm/mm/proc-macros.S -index d9f7dfe2a7ed..687d126d1c6c 100644 +index e43f6d716b4b..05d9b19b6b2e 100644 --- a/arch/arm/mm/proc-macros.S +++ b/arch/arm/mm/proc-macros.S @@ -334,6 +334,8 @@ ENTRY(\name\()_cache_fns) @@ -42652,10 +58026,10 @@ index e21249548e9f..33e4a9b8f1ba 100644 EXPORT_SYMBOL(cpu_cache); #endif diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S -index a0618f3e6836..b3a2fce22eac 100644 +index 203dff89ab1a..9290ae13a5bb 100644 --- a/arch/arm/mm/proc-v6.S +++ b/arch/arm/mm/proc-v6.S -@@ -70,10 +70,19 @@ ENDPROC(cpu_v6_reset) +@@ -72,10 +72,19 @@ ENDPROC(cpu_v6_reset) * * IRQs are already disabled. */ @@ -42679,7 +58053,7 @@ index a0618f3e6836..b3a2fce22eac 100644 ENTRY(cpu_v6_dcache_clean_area) diff --git a/arch/arm/vfp/vfpmodule.c b/arch/arm/vfp/vfpmodule.c -index 2cb355c1b5b7..1e2dcf81aefa 100644 +index 7e8773a2d99d..a1ff693e49bf 100644 --- a/arch/arm/vfp/vfpmodule.c +++ b/arch/arm/vfp/vfpmodule.c @@ -176,8 +176,11 @@ static int vfp_notifier(struct notifier_block *self, unsigned long cmd, void *v) @@ -42695,7 +58069,7 @@ index 2cb355c1b5b7..1e2dcf81aefa 100644 #endif /* -@@ -454,13 +457,16 @@ static int vfp_pm_suspend(void) +@@ -451,13 +454,16 @@ static int vfp_pm_suspend(void) /* if vfp is on, then save state for resumption */ if (fpexc & FPEXC_EN) { pr_debug("%s: saving vfp state\n", __func__); @@ -42713,7 +58087,7 @@ index 2cb355c1b5b7..1e2dcf81aefa 100644 vfp_save_state(vfp_current_hw_state[ti->cpu], fpexc); fmxr(FPEXC, fpexc); #endif -@@ -523,7 +529,8 @@ void vfp_sync_hwstate(struct thread_info *thread) +@@ -522,7 +528,8 @@ void vfp_sync_hwstate(struct thread_info *thread) /* * Save the last VFP state on this CPU. */ @@ -42746,8 +58120,8 @@ index 2cb355c1b5b7..1e2dcf81aefa 100644 hwstate->fpexc = fpexc; hwstate->fpinst = ufp_exc->fpinst; -@@ -726,7 +738,8 @@ void kernel_neon_begin(void) - cpu = get_cpu(); +@@ -830,7 +842,8 @@ void kernel_neon_begin(void) + cpu = __smp_processor_id(); fpexc = fmrx(FPEXC) | FPEXC_EN; - fmxr(FPEXC, fpexc); @@ -42756,49 +58130,52 @@ index 2cb355c1b5b7..1e2dcf81aefa 100644 /* * Save the userland NEON/VFP state. Under UP, -diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms -index dd6b7466fe28..2a7abe568db7 100644 ---- a/arch/arm64/Kconfig.platforms -+++ b/arch/arm64/Kconfig.platforms -@@ -39,6 +39,7 @@ config ARCH_BCM2835 - select ARM_AMBA - select ARM_GIC - select ARM_TIMER_SP804 -+ select BRCMSTB_L2_IRQ - help - This enables support for the Broadcom BCM2837 and BCM2711 SoC. - These SoCs are used in the Raspberry Pi 3 and 4 devices. +diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig +index 8def51744a10..942cc2f5340f 100644 +--- a/arch/arm64/Kconfig ++++ b/arch/arm64/Kconfig +@@ -123,7 +123,8 @@ config ARM64 + select CRC32 + select DCACHE_WORD_ACCESS + select DYNAMIC_FTRACE if FUNCTION_TRACER +- select DMA_BOUNCE_UNALIGNED_KMALLOC ++ # Disable this to save 64MB when DMA controllers can reach all of RAM ++ # select DMA_BOUNCE_UNALIGNED_KMALLOC + select DMA_DIRECT_REMAP + select EDAC_SUPPORT + select FRAME_POINTER diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile -index 9b1170658d60..cc6c25629057 100644 +index 30dd6347a929..a30874eddeae 100644 --- a/arch/arm64/boot/dts/Makefile +++ b/arch/arm64/boot/dts/Makefile -@@ -30,3 +30,5 @@ subdir-y += ti +@@ -33,3 +33,5 @@ subdir-y += tesla + subdir-y += ti subdir-y += toshiba subdir-y += xilinx - subdir-y += zte + +subdir-y += overlays diff --git a/arch/arm64/boot/dts/broadcom/Makefile b/arch/arm64/boot/dts/broadcom/Makefile -index cb7de8d99223..e7c2c4fd59a8 100644 +index 8b4591ddd27c..6dd8659a7d8a 100644 --- a/arch/arm64/boot/dts/broadcom/Makefile +++ b/arch/arm64/boot/dts/broadcom/Makefile -@@ -1,9 +1,21 @@ - # SPDX-License-Identifier: GPL-2.0 --dtb-$(CONFIG_ARCH_BCM2835) += bcm2711-rpi-4-b.dtb \ -- bcm2837-rpi-3-a-plus.dtb \ -+dtb-$(CONFIG_ARCH_BCM2835) += bcm2837-rpi-3-a-plus.dtb \ - bcm2837-rpi-3-b.dtb \ - bcm2837-rpi-3-b-plus.dtb \ - bcm2837-rpi-cm3-io3.dtb +@@ -12,6 +12,24 @@ dtb-$(CONFIG_ARCH_BCM2835) += bcm2711-rpi-400.dtb \ + bcm2837-rpi-cm3-io3.dtb \ + bcm2837-rpi-zero-2-w.dtb + +dtb-$(CONFIG_ARCH_BCM2835) += bcm2710-rpi-zero-2.dtb ++dtb-$(CONFIG_ARCH_BCM2835) += bcm2710-rpi-zero-2-w.dtb +dtb-$(CONFIG_ARCH_BCM2835) += bcm2710-rpi-2-b.dtb +dtb-$(CONFIG_ARCH_BCM2835) += bcm2710-rpi-3-b.dtb +dtb-$(CONFIG_ARCH_BCM2835) += bcm2710-rpi-3-b-plus.dtb -+dtb-$(CONFIG_ARCH_BCM2835) += bcm2711-rpi-4-b.dtb -+dtb-$(CONFIG_ARCH_BCM2835) += bcm2711-rpi-400.dtb +dtb-$(CONFIG_ARCH_BCM2835) += bcm2710-rpi-cm3.dtb +dtb-$(CONFIG_ARCH_BCM2835) += bcm2711-rpi-cm4.dtb - ++dtb-$(CONFIG_ARCH_BCM2835) += bcm2711-rpi-cm4s.dtb ++dtb-$(CONFIG_ARCH_BCM2835) += bcm2712-rpi-5-b.dtb ++dtb-$(CONFIG_ARCH_BCM2835) += bcm2712d0-rpi-5-b.dtb ++dtb-$(CONFIG_ARCH_BCM2835) += bcm2712-rpi-cm5-cm5io.dtb ++dtb-$(CONFIG_ARCH_BCM2835) += bcm2712-rpi-cm5-cm4io.dtb ++ + subdir-y += bcmbca subdir-y += northstar2 subdir-y += stingray + @@ -42808,61 +58185,92 @@ index cb7de8d99223..e7c2c4fd59a8 100644 +endif diff --git a/arch/arm64/boot/dts/broadcom/bcm2710-rpi-2-b.dts b/arch/arm64/boot/dts/broadcom/bcm2710-rpi-2-b.dts new file mode 100644 -index 000000000000..36ecea71f0ef +index 000000000000..9b2c0120842a --- /dev/null +++ b/arch/arm64/boot/dts/broadcom/bcm2710-rpi-2-b.dts @@ -0,0 +1 @@ -+#include "../../../../arm/boot/dts/bcm2710-rpi-2-b.dts" ++#include "arm/broadcom/bcm2710-rpi-2-b.dts" diff --git a/arch/arm64/boot/dts/broadcom/bcm2710-rpi-3-b-plus.dts b/arch/arm64/boot/dts/broadcom/bcm2710-rpi-3-b-plus.dts new file mode 100644 -index 000000000000..22fc6a82f2a9 +index 000000000000..bc869aeaee9b --- /dev/null +++ b/arch/arm64/boot/dts/broadcom/bcm2710-rpi-3-b-plus.dts @@ -0,0 +1 @@ -+#include "../../../../arm/boot/dts/bcm2710-rpi-3-b-plus.dts" ++#include "arm/broadcom/bcm2710-rpi-3-b-plus.dts" diff --git a/arch/arm64/boot/dts/broadcom/bcm2710-rpi-3-b.dts b/arch/arm64/boot/dts/broadcom/bcm2710-rpi-3-b.dts new file mode 100644 -index 000000000000..4cacc5b72ae3 +index 000000000000..263fc8db863a --- /dev/null +++ b/arch/arm64/boot/dts/broadcom/bcm2710-rpi-3-b.dts @@ -0,0 +1 @@ -+#include "../../../../arm/boot/dts/bcm2710-rpi-3-b.dts" ++#include "arm/broadcom/bcm2710-rpi-3-b.dts" diff --git a/arch/arm64/boot/dts/broadcom/bcm2710-rpi-cm3.dts b/arch/arm64/boot/dts/broadcom/bcm2710-rpi-cm3.dts new file mode 100644 -index 000000000000..e1e13784cff6 +index 000000000000..6beee41b0077 --- /dev/null +++ b/arch/arm64/boot/dts/broadcom/bcm2710-rpi-cm3.dts @@ -0,0 +1 @@ -+#include "../../../../arm/boot/dts/bcm2710-rpi-cm3.dts" ++#include "arm/broadcom/bcm2710-rpi-cm3.dts" +diff --git a/arch/arm64/boot/dts/broadcom/bcm2710-rpi-zero-2-w.dts b/arch/arm64/boot/dts/broadcom/bcm2710-rpi-zero-2-w.dts +new file mode 100644 +index 000000000000..65fa59a939b7 +--- /dev/null ++++ b/arch/arm64/boot/dts/broadcom/bcm2710-rpi-zero-2-w.dts +@@ -0,0 +1 @@ ++#include "arm/broadcom/bcm2710-rpi-zero-2-w.dts" diff --git a/arch/arm64/boot/dts/broadcom/bcm2710-rpi-zero-2.dts b/arch/arm64/boot/dts/broadcom/bcm2710-rpi-zero-2.dts new file mode 100644 -index 000000000000..f76f553599ef +index 000000000000..65fa59a939b7 --- /dev/null +++ b/arch/arm64/boot/dts/broadcom/bcm2710-rpi-zero-2.dts @@ -0,0 +1 @@ -+#include "../../../../arm/boot/dts/bcm2710-rpi-zero-2.dts" -diff --git a/arch/arm64/boot/dts/broadcom/bcm2711-rpi-4-b.dts b/arch/arm64/boot/dts/broadcom/bcm2711-rpi-4-b.dts -index d24c53682e44..bf69a4b0b172 100644 ---- a/arch/arm64/boot/dts/broadcom/bcm2711-rpi-4-b.dts -+++ b/arch/arm64/boot/dts/broadcom/bcm2711-rpi-4-b.dts -@@ -1,2 +1 @@ --// SPDX-License-Identifier: GPL-2.0 --#include "arm/bcm2711-rpi-4-b.dts" -+#include "../../../../arm/boot/dts/bcm2711-rpi-4-b.dts" -diff --git a/arch/arm64/boot/dts/broadcom/bcm2711-rpi-400.dts b/arch/arm64/boot/dts/broadcom/bcm2711-rpi-400.dts -new file mode 100644 -index 000000000000..90c2b5a195d4 ---- /dev/null -+++ b/arch/arm64/boot/dts/broadcom/bcm2711-rpi-400.dts -@@ -0,0 +1 @@ -+#include "../../../../arm/boot/dts/bcm2711-rpi-400.dts" ++#include "arm/broadcom/bcm2710-rpi-zero-2-w.dts" diff --git a/arch/arm64/boot/dts/broadcom/bcm2711-rpi-cm4.dts b/arch/arm64/boot/dts/broadcom/bcm2711-rpi-cm4.dts new file mode 100644 -index 000000000000..8064a58155f1 +index 000000000000..3e25a0e1797f --- /dev/null +++ b/arch/arm64/boot/dts/broadcom/bcm2711-rpi-cm4.dts @@ -0,0 +1 @@ -+#include "../../../../arm/boot/dts/bcm2711-rpi-cm4.dts" ++#include "arm/broadcom/bcm2711-rpi-cm4.dts" +diff --git a/arch/arm64/boot/dts/broadcom/bcm2711-rpi-cm4s.dts b/arch/arm64/boot/dts/broadcom/bcm2711-rpi-cm4s.dts +new file mode 100644 +index 000000000000..c72d752e7400 +--- /dev/null ++++ b/arch/arm64/boot/dts/broadcom/bcm2711-rpi-cm4s.dts +@@ -0,0 +1 @@ ++#include "arm/broadcom/bcm2711-rpi-cm4s.dts" +diff --git a/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts b/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts +new file mode 100644 +index 000000000000..1457e696f968 +--- /dev/null ++++ b/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts +@@ -0,0 +1,2 @@ ++// SPDX-License-Identifier: GPL-2.0 ++#include "arm/broadcom/bcm2712-rpi-5-b.dts" +diff --git a/arch/arm64/boot/dts/broadcom/bcm2712-rpi-cm5-cm4io.dts b/arch/arm64/boot/dts/broadcom/bcm2712-rpi-cm5-cm4io.dts +new file mode 100644 +index 000000000000..3815e40cc0aa +--- /dev/null ++++ b/arch/arm64/boot/dts/broadcom/bcm2712-rpi-cm5-cm4io.dts +@@ -0,0 +1,2 @@ ++// SPDX-License-Identifier: GPL-2.0 ++#include "arm/broadcom/bcm2712-rpi-cm5-cm4io.dts" +diff --git a/arch/arm64/boot/dts/broadcom/bcm2712-rpi-cm5-cm5io.dts b/arch/arm64/boot/dts/broadcom/bcm2712-rpi-cm5-cm5io.dts +new file mode 100644 +index 000000000000..e2215a3f6276 +--- /dev/null ++++ b/arch/arm64/boot/dts/broadcom/bcm2712-rpi-cm5-cm5io.dts +@@ -0,0 +1,2 @@ ++// SPDX-License-Identifier: GPL-2.0 ++#include "arm/broadcom/bcm2712-rpi-cm5-cm5io.dts" +diff --git a/arch/arm64/boot/dts/broadcom/bcm2712d0-rpi-5-b.dts b/arch/arm64/boot/dts/broadcom/bcm2712d0-rpi-5-b.dts +new file mode 100644 +index 000000000000..9b3ddbb8dafd +--- /dev/null ++++ b/arch/arm64/boot/dts/broadcom/bcm2712d0-rpi-5-b.dts +@@ -0,0 +1,2 @@ ++// SPDX-License-Identifier: GPL-2.0 ++#include "../../../../arm/boot/dts/broadcom/bcm2712d0-rpi-5-b.dts" diff --git a/arch/arm64/boot/dts/broadcom/bcm283x-rpi-csi1-2lane.dtsi b/arch/arm64/boot/dts/broadcom/bcm283x-rpi-csi1-2lane.dtsi new file mode 120000 index 000000000000..e5c400284467 @@ -42889,10 +58297,10 @@ index 000000000000..ded08646b6f6 \ No newline at end of file diff --git a/arch/arm64/configs/bcm2711_defconfig b/arch/arm64/configs/bcm2711_defconfig new file mode 100644 -index 000000000000..75333e69ef74 +index 000000000000..6ac8c83f6842 --- /dev/null +++ b/arch/arm64/configs/bcm2711_defconfig -@@ -0,0 +1,1566 @@ +@@ -0,0 +1,1672 @@ +CONFIG_LOCALVERSION="-v8" +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_SYSVIPC=y @@ -42900,11 +58308,17 @@ index 000000000000..75333e69ef74 +CONFIG_GENERIC_IRQ_DEBUGFS=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y ++CONFIG_BPF_SYSCALL=y ++CONFIG_BPF_JIT=y +CONFIG_PREEMPT=y +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_BSD_PROCESS_ACCT_V3=y ++CONFIG_TASKSTATS=y ++CONFIG_TASK_DELAY_ACCT=y +CONFIG_TASK_XACCT=y +CONFIG_TASK_IO_ACCOUNTING=y ++CONFIG_PSI=y ++CONFIG_PSI_DEFAULT_DISABLED=y +CONFIG_IKCONFIG=m +CONFIG_IKCONFIG_PROC=y +CONFIG_MEMCG=y @@ -42919,13 +58333,14 @@ index 000000000000..75333e69ef74 +CONFIG_CGROUP_BPF=y +CONFIG_NAMESPACES=y +CONFIG_USER_NS=y ++CONFIG_CHECKPOINT_RESTORE=y +CONFIG_SCHED_AUTOGROUP=y +CONFIG_BLK_DEV_INITRD=y -+CONFIG_BPF_SYSCALL=y -+CONFIG_EMBEDDED=y -+# CONFIG_COMPAT_BRK is not set ++CONFIG_EXPERT=y +CONFIG_PROFILING=y ++CONFIG_ARCH_BCM=y +CONFIG_ARCH_BCM2835=y ++CONFIG_ARCH_BRCMSTB=y +# CONFIG_CAVIUM_ERRATUM_22375 is not set +# CONFIG_CAVIUM_ERRATUM_23154 is not set +# CONFIG_CAVIUM_ERRATUM_27456 is not set @@ -42934,11 +58349,12 @@ index 000000000000..75333e69ef74 +CONFIG_SWP_EMULATION=y +CONFIG_CP15_BARRIER_EMULATION=y +CONFIG_SETEND_EMULATION=y ++CONFIG_RANDOMIZE_BASE=y +CONFIG_CMDLINE="console=ttyAMA0,115200 kgdboc=ttyAMA0,115200 root=/dev/mmcblk0p2 rootfstype=ext4 rootwait" +# CONFIG_SUSPEND is not set +CONFIG_PM=y ++CONFIG_PM_DEBUG=y +CONFIG_CPU_IDLE=y -+CONFIG_ARM_CPUIDLE=y +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_STAT=y +CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE=y @@ -42949,31 +58365,31 @@ index 000000000000..75333e69ef74 +CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y +CONFIG_CPUFREQ_DT=y +CONFIG_ARM_RASPBERRYPI_CPUFREQ=y -+CONFIG_RASPBERRYPI_FIRMWARE=y +CONFIG_VIRTUALIZATION=y +CONFIG_KVM=y -+CONFIG_CRYPTO_AES_ARM64_BS=m +CONFIG_JUMP_LABEL=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODVERSIONS=y +CONFIG_MODULE_SRCVERSION_ALL=y ++CONFIG_MODULE_COMPRESS_XZ=y +CONFIG_BLK_DEV_THROTTLING=y +CONFIG_PARTITION_ADVANCED=y +CONFIG_MAC_PARTITION=y +CONFIG_BINFMT_MISC=m -+CONFIG_CLEANCACHE=y -+CONFIG_FRONTSWAP=y -+CONFIG_CMA=y +CONFIG_ZSWAP=y +CONFIG_Z3FOLD=m -+CONFIG_ZSMALLOC=m ++# CONFIG_COMPAT_BRK is not set ++CONFIG_CMA=y ++CONFIG_LRU_GEN=y ++CONFIG_LRU_GEN_ENABLED=y +CONFIG_NET=y +CONFIG_PACKET=y -+CONFIG_UNIX=y -+CONFIG_XFRM_USER=y ++CONFIG_XFRM_USER=m ++CONFIG_XFRM_INTERFACE=m ++CONFIG_XFRM_SUB_POLICY=y ++CONFIG_XFRM_STATISTICS=y +CONFIG_NET_KEY=m -+CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_ADVANCED_ROUTER=y +CONFIG_IP_MULTIPLE_TABLES=y @@ -43013,10 +58429,11 @@ index 000000000000..75333e69ef74 +CONFIG_IPV6_MROUTE=y +CONFIG_IPV6_MROUTE_MULTIPLE_TABLES=y +CONFIG_IPV6_PIMSM_V2=y ++CONFIG_MPTCP=y ++CONFIG_NETWORK_PHY_TIMESTAMPING=y +CONFIG_NETFILTER=y +CONFIG_BRIDGE_NETFILTER=m +CONFIG_NF_CONNTRACK=m -+CONFIG_NF_LOG_NETDEV=m +CONFIG_NF_CONNTRACK_ZONES=y +CONFIG_NF_CONNTRACK_EVENTS=y +CONFIG_NF_CONNTRACK_TIMESTAMP=y @@ -43037,7 +58454,6 @@ index 000000000000..75333e69ef74 +CONFIG_NFT_NUMGEN=m +CONFIG_NFT_CT=m +CONFIG_NFT_FLOW_OFFLOAD=m -+CONFIG_NFT_COUNTER=m +CONFIG_NFT_CONNLIMIT=m +CONFIG_NFT_LOG=m +CONFIG_NFT_LIMIT=m @@ -43045,21 +58461,23 @@ index 000000000000..75333e69ef74 +CONFIG_NFT_REDIR=m +CONFIG_NFT_NAT=m +CONFIG_NFT_TUNNEL=m -+CONFIG_NFT_OBJREF=m +CONFIG_NFT_QUEUE=m +CONFIG_NFT_QUOTA=m +CONFIG_NFT_REJECT=m +CONFIG_NFT_COMPAT=m +CONFIG_NFT_HASH=m +CONFIG_NFT_FIB_INET=m ++CONFIG_NFT_XFRM=m +CONFIG_NFT_SOCKET=m +CONFIG_NFT_OSF=m +CONFIG_NFT_TPROXY=m ++CONFIG_NFT_SYNPROXY=m +CONFIG_NFT_DUP_NETDEV=m +CONFIG_NFT_FWD_NETDEV=m +CONFIG_NFT_FIB_NETDEV=m +CONFIG_NF_FLOW_TABLE_INET=m +CONFIG_NF_FLOW_TABLE=m ++CONFIG_NETFILTER_XTABLES_COMPAT=y +CONFIG_NETFILTER_XT_SET=m +CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m +CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m @@ -43131,6 +58549,7 @@ index 000000000000..75333e69ef74 +CONFIG_IP_SET_HASH_NETIFACE=m +CONFIG_IP_SET_LIST_SET=m +CONFIG_IP_VS=m ++CONFIG_IP_VS_IPV6=y +CONFIG_IP_VS_PROTO_TCP=y +CONFIG_IP_VS_PROTO_UDP=y +CONFIG_IP_VS_PROTO_ESP=y @@ -43151,8 +58570,8 @@ index 000000000000..75333e69ef74 +CONFIG_NFT_DUP_IPV4=m +CONFIG_NFT_FIB_IPV4=m +CONFIG_NF_TABLES_ARP=y -+CONFIG_NF_FLOW_TABLE_IPV4=m +CONFIG_NF_LOG_ARP=m ++CONFIG_NF_LOG_IPV4=m +CONFIG_IP_NF_IPTABLES=m +CONFIG_IP_NF_MATCH_AH=m +CONFIG_IP_NF_MATCH_ECN=m @@ -43165,7 +58584,6 @@ index 000000000000..75333e69ef74 +CONFIG_IP_NF_TARGET_NETMAP=m +CONFIG_IP_NF_TARGET_REDIRECT=m +CONFIG_IP_NF_MANGLE=m -+CONFIG_IP_NF_TARGET_CLUSTERIP=m +CONFIG_IP_NF_TARGET_ECN=m +CONFIG_IP_NF_TARGET_TTL=m +CONFIG_IP_NF_RAW=m @@ -43174,7 +58592,6 @@ index 000000000000..75333e69ef74 +CONFIG_IP_NF_ARP_MANGLE=m +CONFIG_NFT_DUP_IPV6=m +CONFIG_NFT_FIB_IPV6=m -+CONFIG_NF_FLOW_TABLE_IPV6=m +CONFIG_IP6_NF_IPTABLES=m +CONFIG_IP6_NF_MATCH_AH=m +CONFIG_IP6_NF_MATCH_EUI64=m @@ -43198,7 +58615,6 @@ index 000000000000..75333e69ef74 +CONFIG_IP6_NF_TARGET_NPT=m +CONFIG_NF_TABLES_BRIDGE=m +CONFIG_NFT_BRIDGE_REJECT=m -+CONFIG_NF_LOG_BRIDGE=m +CONFIG_BRIDGE_NF_EBTABLES=m +CONFIG_BRIDGE_EBT_BROUTE=m +CONFIG_BRIDGE_EBT_T_FILTER=m @@ -43235,10 +58651,8 @@ index 000000000000..75333e69ef74 +CONFIG_IEEE802154_6LOWPAN=m +CONFIG_MAC802154=m +CONFIG_NET_SCHED=y -+CONFIG_NET_SCH_CBQ=m +CONFIG_NET_SCH_HTB=m +CONFIG_NET_SCH_HFSC=m -+CONFIG_NET_SCH_ATM=m +CONFIG_NET_SCH_PRIO=m +CONFIG_NET_SCH_MULTIQ=m +CONFIG_NET_SCH_RED=m @@ -43247,7 +58661,6 @@ index 000000000000..75333e69ef74 +CONFIG_NET_SCH_TEQL=m +CONFIG_NET_SCH_TBF=m +CONFIG_NET_SCH_GRED=m -+CONFIG_NET_SCH_DSMARK=m +CONFIG_NET_SCH_NETEM=m +CONFIG_NET_SCH_DRR=m +CONFIG_NET_SCH_MQPRIO=m @@ -43262,15 +58675,13 @@ index 000000000000..75333e69ef74 +CONFIG_NET_SCH_INGRESS=m +CONFIG_NET_SCH_PLUG=m +CONFIG_NET_CLS_BASIC=m -+CONFIG_NET_CLS_TCINDEX=m +CONFIG_NET_CLS_ROUTE4=m +CONFIG_NET_CLS_FW=m +CONFIG_NET_CLS_U32=m +CONFIG_CLS_U32_MARK=y -+CONFIG_NET_CLS_RSVP=m -+CONFIG_NET_CLS_RSVP6=m +CONFIG_NET_CLS_FLOW=m +CONFIG_NET_CLS_CGROUP=m ++CONFIG_NET_CLS_BPF=y +CONFIG_NET_EMATCH=y +CONFIG_NET_EMATCH_CMP=m +CONFIG_NET_EMATCH_NBYTE=m @@ -43307,13 +58718,6 @@ index 000000000000..75333e69ef74 +CONFIG_CAN=m +CONFIG_CAN_J1939=m +CONFIG_CAN_ISOTP=m -+CONFIG_CAN_VCAN=m -+CONFIG_CAN_SLCAN=m -+CONFIG_CAN_MCP251X=m -+CONFIG_CAN_MCP251XFD=m -+CONFIG_CAN_EMS_USB=m -+CONFIG_CAN_GS_USB=m -+CONFIG_CAN_PEAK_USB=m +CONFIG_BT=m +CONFIG_BT_RFCOMM=m +CONFIG_BT_RFCOMM_TTY=y @@ -43337,32 +58741,38 @@ index 000000000000..75333e69ef74 +CONFIG_CFG80211_WEXT=y +CONFIG_MAC80211=m +CONFIG_MAC80211_MESH=y -+CONFIG_WIMAX=m +CONFIG_RFKILL=m +CONFIG_RFKILL_INPUT=y +CONFIG_NET_9P=m +CONFIG_NFC=m +CONFIG_PCI=y -+CONFIG_PCIE_BRCMSTB=y ++CONFIG_PCIEPORTBUS=y ++CONFIG_PCIEAER=y ++CONFIG_PCIEASPM_POWERSAVE=y ++CONFIG_PCIE_DPC=y +CONFIG_UEVENT_HELPER=y +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y ++# CONFIG_BRCMSTB_GISB_ARB is not set ++CONFIG_RASPBERRYPI_FIRMWARE=y ++# CONFIG_EFI_VARS_PSTORE is not set +CONFIG_MTD=m +CONFIG_MTD_BLOCK=m +CONFIG_MTD_BLOCK2MTD=m ++CONFIG_MTD_SPI_NAND=m +CONFIG_MTD_SPI_NOR=m +CONFIG_MTD_UBI=m +CONFIG_OF_CONFIGFS=y +CONFIG_ZRAM=m +CONFIG_BLK_DEV_LOOP=y -+CONFIG_BLK_DEV_CRYPTOLOOP=m +CONFIG_BLK_DEV_DRBD=m +CONFIG_BLK_DEV_NBD=m +CONFIG_BLK_DEV_RAM=y -+CONFIG_CDROM_PKTCDVD=m +CONFIG_ATA_OVER_ETH=m +CONFIG_BLK_DEV_NVME=y ++CONFIG_NVME_HWMON=y +CONFIG_EEPROM_AT24=m ++CONFIG_EEPROM_AT25=m +CONFIG_TI_ST=m +CONFIG_SCSI=y +# CONFIG_SCSI_PROC_FS is not set @@ -43383,11 +58793,14 @@ index 000000000000..75333e69ef74 +CONFIG_DM_SNAPSHOT=m +CONFIG_DM_THIN_PROVISIONING=m +CONFIG_DM_CACHE=m ++CONFIG_DM_WRITECACHE=m +CONFIG_DM_MIRROR=m +CONFIG_DM_LOG_USERSPACE=m +CONFIG_DM_RAID=m +CONFIG_DM_ZERO=m ++CONFIG_DM_MULTIPATH=m +CONFIG_DM_DELAY=m ++CONFIG_DM_INTEGRITY=m +CONFIG_NETDEVICES=y +CONFIG_BONDING=m +CONFIG_DUMMY=m @@ -43403,13 +58816,23 @@ index 000000000000..75333e69ef74 +CONFIG_NET_VRF=m +CONFIG_VSOCKMON=m +CONFIG_BCMGENET=y ++CONFIG_MACB=y +CONFIG_ENC28J60=m ++CONFIG_LAN743X=m +CONFIG_QCA7000_SPI=m +CONFIG_QCA7000_UART=m +CONFIG_R8169=m +CONFIG_WIZNET_W5100=m +CONFIG_WIZNET_W5100_SPI=m +CONFIG_MICREL_PHY=y ++CONFIG_CAN_VCAN=m ++CONFIG_CAN_SLCAN=m ++CONFIG_CAN_MCP251X=m ++CONFIG_CAN_MCP251XFD=m ++CONFIG_CAN_8DEV_USB=m ++CONFIG_CAN_EMS_USB=m ++CONFIG_CAN_GS_USB=m ++CONFIG_CAN_PEAK_USB=m +CONFIG_MDIO_BITBANG=m +CONFIG_PPP=m +CONFIG_PPP_BSDCOMP=m @@ -43489,6 +58912,7 @@ index 000000000000..75333e69ef74 +CONFIG_MT7601U=m +CONFIG_MT76x0U=m +CONFIG_MT76x2U=m ++CONFIG_MT7921U=m +CONFIG_RT2X00=m +CONFIG_RT2500USB=m +CONFIG_RT73USB=m @@ -43500,11 +58924,15 @@ index 000000000000..75333e69ef74 +CONFIG_RTL8187=m +CONFIG_RTL8192CU=m +CONFIG_RTL8XXXU=m ++CONFIG_RTW88=m ++CONFIG_RTW88_8822BU=m ++CONFIG_RTW88_8822CU=m ++CONFIG_RTW88_8723DU=m ++CONFIG_RTW88_8821CU=m +CONFIG_USB_ZD1201=m +CONFIG_ZD1211RW=m -+CONFIG_MAC80211_HWSIM=m +CONFIG_USB_NET_RNDIS_WLAN=m -+CONFIG_WIMAX_I2400M_USB=m ++CONFIG_MAC80211_HWSIM=m +CONFIG_IEEE802154_AT86RF230=m +CONFIG_IEEE802154_MRF24J40=m +CONFIG_IEEE802154_CC2520=m @@ -43526,6 +58954,7 @@ index 000000000000..75333e69ef74 +CONFIG_JOYSTICK_XPAD_LEDS=y +CONFIG_JOYSTICK_PSXPAD_SPI=m +CONFIG_JOYSTICK_PSXPAD_SPI_FF=y ++CONFIG_JOYSTICK_FSIA6B=m +CONFIG_JOYSTICK_RPISENSE=m +CONFIG_INPUT_TOUCHSCREEN=y +CONFIG_TOUCHSCREEN_ADS7846=m @@ -43536,7 +58965,10 @@ index 000000000000..75333e69ef74 +CONFIG_TOUCHSCREEN_EDT_FT5X06=m +CONFIG_TOUCHSCREEN_RASPBERRYPI_FW=m +CONFIG_TOUCHSCREEN_USB_COMPOSITE=m ++CONFIG_TOUCHSCREEN_TSC2007=m ++CONFIG_TOUCHSCREEN_TSC2007_IIO=y +CONFIG_TOUCHSCREEN_STMPE=m ++CONFIG_TOUCHSCREEN_IQS5XX=m +CONFIG_INPUT_MISC=y +CONFIG_INPUT_AD714X=m +CONFIG_INPUT_ATI_REMOTE2=m @@ -43551,18 +58983,14 @@ index 000000000000..75333e69ef74 +CONFIG_SERIO=m +CONFIG_SERIO_RAW=m +CONFIG_GAMEPORT=m -+CONFIG_GAMEPORT_NS558=m -+CONFIG_GAMEPORT_L4=m +CONFIG_BRCM_CHAR_DRIVERS=y +CONFIG_BCM_VCIO=y -+CONFIG_BCM2835_DEVGPIOMEM=y -+CONFIG_RPIVID_MEM=m +# CONFIG_LEGACY_PTYS is not set +CONFIG_SERIAL_8250=y +# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set +CONFIG_SERIAL_8250_CONSOLE=y +# CONFIG_SERIAL_8250_DMA is not set -+CONFIG_SERIAL_8250_NR_UARTS=1 ++CONFIG_SERIAL_8250_NR_UARTS=5 +CONFIG_SERIAL_8250_RUNTIME_UARTS=0 +CONFIG_SERIAL_8250_EXTENDED=y +CONFIG_SERIAL_8250_SHARE_IRQ=y @@ -43575,10 +59003,13 @@ index 000000000000..75333e69ef74 +CONFIG_SERIAL_DEV_BUS=y +CONFIG_TTY_PRINTK=y +CONFIG_HW_RANDOM=y -+CONFIG_RAW_DRIVER=y +CONFIG_TCG_TPM=m +CONFIG_TCG_TIS_SPI=m -+CONFIG_RANDOM_TRUST_BOOTLOADER=y ++CONFIG_TCG_TIS_I2C=m ++CONFIG_XILLYBUS=m ++CONFIG_XILLYBUS_PCIE=m ++CONFIG_XILLYUSB=m ++CONFIG_RASPBERRYPI_GPIOMEM=m +CONFIG_I2C=y +CONFIG_I2C_CHARDEV=m +CONFIG_I2C_MUX_GPMUX=m @@ -43587,32 +59018,38 @@ index 000000000000..75333e69ef74 +CONFIG_I2C_BCM2708=m +CONFIG_I2C_BCM2835=m +CONFIG_I2C_BRCMSTB=m ++CONFIG_I2C_DESIGNWARE_PLATFORM=m +CONFIG_I2C_GPIO=m +CONFIG_I2C_ROBOTFUZZ_OSIF=m +CONFIG_I2C_TINY_USB=m +CONFIG_SPI=y +CONFIG_SPI_BCM2835=m +CONFIG_SPI_BCM2835AUX=m ++CONFIG_SPI_DESIGNWARE=m ++CONFIG_SPI_DW_DMA=y ++CONFIG_SPI_DW_MMIO=m +CONFIG_SPI_GPIO=m +CONFIG_SPI_SPIDEV=m +CONFIG_SPI_SLAVE=y -+CONFIG_PPS=m +CONFIG_PPS_CLIENT_LDISC=m +CONFIG_PPS_CLIENT_GPIO=m +CONFIG_PINCTRL_MCP23S08=m ++CONFIG_PINCTRL_RP1=y ++CONFIG_PINCTRL_BCM2712=y +CONFIG_GPIO_SYSFS=y +CONFIG_GPIO_BCM_VIRT=y ++CONFIG_GPIO_MAX7300=m +CONFIG_GPIO_PCA953X=m +CONFIG_GPIO_PCA953X_IRQ=y +CONFIG_GPIO_PCF857X=m +CONFIG_GPIO_ARIZONA=m +CONFIG_GPIO_FSM=m +CONFIG_GPIO_STMPE=y ++CONFIG_GPIO_MAX7301=m +CONFIG_GPIO_MOCKUP=m +CONFIG_W1=m +CONFIG_W1_MASTER_DS2490=m +CONFIG_W1_MASTER_DS2482=m -+CONFIG_W1_MASTER_DS1WM=m +CONFIG_W1_MASTER_GPIO=m +CONFIG_W1_SLAVE_THERM=m +CONFIG_W1_SLAVE_SMEM=m @@ -43627,75 +59064,82 @@ index 000000000000..75333e69ef74 +CONFIG_W1_SLAVE_DS2781=m +CONFIG_W1_SLAVE_DS28E04=m +CONFIG_W1_SLAVE_DS28E17=m ++# CONFIG_POWER_RESET_BRCMSTB is not set +CONFIG_POWER_RESET_GPIO=y +CONFIG_RPI_POE_POWER=m +CONFIG_BATTERY_DS2760=m +CONFIG_BATTERY_MAX17040=m ++CONFIG_CHARGER_GPIO=m +CONFIG_BATTERY_GAUGE_LTC2941=m ++CONFIG_SENSORS_ADT7410=m ++CONFIG_SENSORS_AHT10=m ++CONFIG_SENSORS_DRIVETEMP=m +CONFIG_SENSORS_DS1621=m +CONFIG_SENSORS_GPIO_FAN=m +CONFIG_SENSORS_IIO_HWMON=m +CONFIG_SENSORS_JC42=m +CONFIG_SENSORS_LM75=m ++CONFIG_SENSORS_PWM_FAN=m +CONFIG_SENSORS_RASPBERRYPI_HWMON=m -+CONFIG_SENSORS_RPI_POE_FAN=m +CONFIG_SENSORS_SHT21=m +CONFIG_SENSORS_SHT3x=m ++CONFIG_SENSORS_SHT4x=m +CONFIG_SENSORS_SHTC1=m ++CONFIG_SENSORS_EMC2305=m +CONFIG_SENSORS_INA2XX=m +CONFIG_SENSORS_TMP102=m -+CONFIG_THERMAL=y ++CONFIG_SENSORS_RP1_ADC=m +CONFIG_BCM2711_THERMAL=y +CONFIG_BCM2835_THERMAL=y +CONFIG_WATCHDOG=y +CONFIG_GPIO_WATCHDOG=m +CONFIG_BCM2835_WDT=y ++CONFIG_MFD_RASPBERRYPI_POE_HAT=m +CONFIG_MFD_STMPE=y +CONFIG_STMPE_SPI=y +CONFIG_MFD_SYSCON=y +CONFIG_MFD_ARIZONA_I2C=m +CONFIG_MFD_ARIZONA_SPI=m +CONFIG_MFD_WM5102=y ++CONFIG_MFD_RP1=y +CONFIG_REGULATOR=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_REGULATOR_ARIZONA_LDO1=m +CONFIG_REGULATOR_ARIZONA_MICSUPP=m +CONFIG_REGULATOR_GPIO=y +CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_ATTINY=m ++CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_V2=m +CONFIG_RC_CORE=y -+CONFIG_LIRC=y +CONFIG_BPF_LIRC_MODE2=y ++CONFIG_LIRC=y +CONFIG_RC_DECODERS=y ++CONFIG_IR_IMON_DECODER=m ++CONFIG_IR_JVC_DECODER=m ++CONFIG_IR_MCE_KBD_DECODER=m +CONFIG_IR_NEC_DECODER=m +CONFIG_IR_RC5_DECODER=m +CONFIG_IR_RC6_DECODER=m -+CONFIG_IR_JVC_DECODER=m -+CONFIG_IR_SONY_DECODER=m +CONFIG_IR_SANYO_DECODER=m +CONFIG_IR_SHARP_DECODER=m -+CONFIG_IR_MCE_KBD_DECODER=m ++CONFIG_IR_SONY_DECODER=m +CONFIG_IR_XMP_DECODER=m -+CONFIG_IR_IMON_DECODER=m +CONFIG_RC_DEVICES=y -+CONFIG_RC_ATI_REMOTE=m -+CONFIG_IR_IMON=m -+CONFIG_IR_MCEUSB=m -+CONFIG_IR_REDRAT3=m -+CONFIG_IR_STREAMZAP=m -+CONFIG_IR_IGUANA=m -+CONFIG_IR_TTUSBIR=m -+CONFIG_RC_LOOPBACK=m +CONFIG_IR_GPIO_CIR=m +CONFIG_IR_GPIO_TX=m ++CONFIG_IR_IGUANA=m ++CONFIG_IR_IMON=m ++CONFIG_IR_MCEUSB=m +CONFIG_IR_PWM_TX=m ++CONFIG_IR_REDRAT3=m ++CONFIG_IR_STREAMZAP=m +CONFIG_IR_TOY=m ++CONFIG_IR_TTUSBIR=m ++CONFIG_RC_ATI_REMOTE=m ++CONFIG_RC_LOOPBACK=m +CONFIG_MEDIA_CEC_RC=y +CONFIG_MEDIA_SUPPORT=m +CONFIG_MEDIA_USB_SUPPORT=y -+CONFIG_USB_VIDEO_CLASS=m -+CONFIG_USB_M5602=m -+CONFIG_USB_STV06XX=m -+CONFIG_USB_GL860=m ++CONFIG_USB_GSPCA=m +CONFIG_USB_GSPCA_BENQ=m +CONFIG_USB_GSPCA_CONEX=m +CONFIG_USB_GSPCA_CPIA1=m @@ -43720,13 +59164,13 @@ index 000000000000..75333e69ef74 +CONFIG_USB_GSPCA_SN9C20X=m +CONFIG_USB_GSPCA_SONIXB=m +CONFIG_USB_GSPCA_SONIXJ=m ++CONFIG_USB_GSPCA_SPCA1528=m +CONFIG_USB_GSPCA_SPCA500=m +CONFIG_USB_GSPCA_SPCA501=m +CONFIG_USB_GSPCA_SPCA505=m +CONFIG_USB_GSPCA_SPCA506=m +CONFIG_USB_GSPCA_SPCA508=m +CONFIG_USB_GSPCA_SPCA561=m -+CONFIG_USB_GSPCA_SPCA1528=m +CONFIG_USB_GSPCA_SQ905=m +CONFIG_USB_GSPCA_SQ905C=m +CONFIG_USB_GSPCA_SQ930X=m @@ -43736,56 +59180,32 @@ index 000000000000..75333e69ef74 +CONFIG_USB_GSPCA_SUNPLUS=m +CONFIG_USB_GSPCA_T613=m +CONFIG_USB_GSPCA_TOPRO=m ++CONFIG_USB_GSPCA_TOUPTEK=m +CONFIG_USB_GSPCA_TV8532=m +CONFIG_USB_GSPCA_VC032X=m +CONFIG_USB_GSPCA_VICAM=m +CONFIG_USB_GSPCA_XIRLINK_CIT=m +CONFIG_USB_GSPCA_ZC3XX=m ++CONFIG_USB_GL860=m ++CONFIG_USB_M5602=m ++CONFIG_USB_STV06XX=m +CONFIG_USB_PWC=m -+CONFIG_VIDEO_CPIA2=m -+CONFIG_USB_ZR364XX=m -+CONFIG_USB_STKWEBCAM=m +CONFIG_USB_S2255=m +CONFIG_VIDEO_USBTV=m -+CONFIG_VIDEO_PVRUSB2=m -+CONFIG_VIDEO_HDPVR=m -+CONFIG_VIDEO_STK1160_COMMON=m ++CONFIG_USB_VIDEO_CLASS=m +CONFIG_VIDEO_GO7007=m +CONFIG_VIDEO_GO7007_USB=m +CONFIG_VIDEO_GO7007_USB_S2250_BOARD=m ++CONFIG_VIDEO_HDPVR=m ++CONFIG_VIDEO_PVRUSB2=m ++CONFIG_VIDEO_STK1160=m +CONFIG_VIDEO_AU0828=m +CONFIG_VIDEO_AU0828_RC=y +CONFIG_VIDEO_CX231XX=m +CONFIG_VIDEO_CX231XX_ALSA=m +CONFIG_VIDEO_CX231XX_DVB=m -+CONFIG_VIDEO_TM6000=m -+CONFIG_VIDEO_TM6000_ALSA=m -+CONFIG_VIDEO_TM6000_DVB=m -+CONFIG_DVB_USB=m -+CONFIG_DVB_USB_A800=m -+CONFIG_DVB_USB_DIBUSB_MB=m -+CONFIG_DVB_USB_DIBUSB_MB_FAULTY=y -+CONFIG_DVB_USB_DIBUSB_MC=m -+CONFIG_DVB_USB_DIB0700=m -+CONFIG_DVB_USB_UMT_010=m -+CONFIG_DVB_USB_CXUSB=m -+CONFIG_DVB_USB_M920X=m -+CONFIG_DVB_USB_DIGITV=m -+CONFIG_DVB_USB_VP7045=m -+CONFIG_DVB_USB_VP702X=m -+CONFIG_DVB_USB_GP8PSK=m -+CONFIG_DVB_USB_NOVA_T_USB2=m -+CONFIG_DVB_USB_TTUSB2=m -+CONFIG_DVB_USB_DTT200U=m -+CONFIG_DVB_USB_OPERA1=m -+CONFIG_DVB_USB_AF9005=m -+CONFIG_DVB_USB_AF9005_REMOTE=m -+CONFIG_DVB_USB_PCTV452E=m -+CONFIG_DVB_USB_DW2102=m -+CONFIG_DVB_USB_CINERGY_T2=m -+CONFIG_DVB_USB_DTV5100=m -+CONFIG_DVB_USB_AZ6027=m -+CONFIG_DVB_USB_TECHNISAT_USB2=m ++CONFIG_DVB_AS102=m ++CONFIG_DVB_B2C2_FLEXCOP_USB=m +CONFIG_DVB_USB_V2=m +CONFIG_DVB_USB_AF9015=m +CONFIG_DVB_USB_AF9035=m @@ -43793,75 +59213,125 @@ index 000000000000..75333e69ef74 +CONFIG_DVB_USB_AU6610=m +CONFIG_DVB_USB_AZ6007=m +CONFIG_DVB_USB_CE6230=m ++CONFIG_DVB_USB_DVBSKY=m +CONFIG_DVB_USB_EC168=m +CONFIG_DVB_USB_GL861=m +CONFIG_DVB_USB_LME2510=m +CONFIG_DVB_USB_MXL111SF=m +CONFIG_DVB_USB_RTL28XXU=m -+CONFIG_DVB_USB_DVBSKY=m ++CONFIG_DVB_USB=m ++CONFIG_DVB_USB_A800=m ++CONFIG_DVB_USB_AF9005=m ++CONFIG_DVB_USB_AF9005_REMOTE=m ++CONFIG_DVB_USB_AZ6027=m ++CONFIG_DVB_USB_CINERGY_T2=m ++CONFIG_DVB_USB_CXUSB=m ++CONFIG_DVB_USB_DIB0700=m ++CONFIG_DVB_USB_DIBUSB_MB=m ++CONFIG_DVB_USB_DIBUSB_MB_FAULTY=y ++CONFIG_DVB_USB_DIBUSB_MC=m ++CONFIG_DVB_USB_DIGITV=m ++CONFIG_DVB_USB_DTT200U=m ++CONFIG_DVB_USB_DTV5100=m ++CONFIG_DVB_USB_DW2102=m ++CONFIG_DVB_USB_GP8PSK=m ++CONFIG_DVB_USB_M920X=m ++CONFIG_DVB_USB_NOVA_T_USB2=m ++CONFIG_DVB_USB_OPERA1=m ++CONFIG_DVB_USB_PCTV452E=m ++CONFIG_DVB_USB_TECHNISAT_USB2=m ++CONFIG_DVB_USB_TTUSB2=m ++CONFIG_DVB_USB_UMT_010=m ++CONFIG_DVB_USB_VP702X=m ++CONFIG_DVB_USB_VP7045=m +CONFIG_SMS_USB_DRV=m -+CONFIG_DVB_B2C2_FLEXCOP_USB=m -+CONFIG_DVB_AS102=m +CONFIG_VIDEO_EM28XX=m +CONFIG_VIDEO_EM28XX_V4L2=m +CONFIG_VIDEO_EM28XX_ALSA=m +CONFIG_VIDEO_EM28XX_DVB=m ++CONFIG_RADIO_SAA7706H=m ++CONFIG_RADIO_SHARK=m ++CONFIG_RADIO_SHARK2=m ++CONFIG_RADIO_SI4713=m ++CONFIG_RADIO_TEA5764=m ++CONFIG_RADIO_TEF6862=m ++CONFIG_RADIO_WL1273=m ++CONFIG_USB_DSBR=m ++CONFIG_USB_KEENE=m ++CONFIG_USB_MA901=m ++CONFIG_USB_MR800=m +CONFIG_RADIO_SI470X=m +CONFIG_USB_SI470X=m +CONFIG_I2C_SI470X=m -+CONFIG_RADIO_SI4713=m +CONFIG_I2C_SI4713=m -+CONFIG_USB_MR800=m -+CONFIG_USB_DSBR=m -+CONFIG_RADIO_SHARK=m -+CONFIG_RADIO_SHARK2=m -+CONFIG_USB_KEENE=m -+CONFIG_USB_MA901=m -+CONFIG_RADIO_TEA5764=m -+CONFIG_RADIO_SAA7706H=m -+CONFIG_RADIO_TEF6862=m -+CONFIG_RADIO_WL1273=m +CONFIG_RADIO_WL128X=m +CONFIG_V4L_PLATFORM_DRIVERS=y ++CONFIG_VIDEO_MUX=m +CONFIG_VIDEO_BCM2835_UNICAM=m ++CONFIG_VIDEO_RASPBERRYPI_PISP_BE=m ++CONFIG_VIDEO_RP1_CFE=m +CONFIG_V4L_TEST_DRIVERS=y -+CONFIG_VIDEO_VIMC=m -+CONFIG_VIDEO_VIVID=m +CONFIG_VIDEO_VIM2M=m +CONFIG_VIDEO_VICODEC=m -+CONFIG_VIDEO_UDA1342=m ++CONFIG_VIDEO_VIMC=m ++CONFIG_VIDEO_VIVID=m ++CONFIG_VIDEO_ARDUCAM_64MP=m ++CONFIG_VIDEO_ARDUCAM_PIVARIETY=m ++CONFIG_VIDEO_IMX219=m ++CONFIG_VIDEO_IMX258=m ++CONFIG_VIDEO_IMX290=m ++CONFIG_VIDEO_IMX296=m ++CONFIG_VIDEO_IMX477=m ++CONFIG_VIDEO_IMX519=m ++CONFIG_VIDEO_IMX708=m ++CONFIG_VIDEO_MT9V011=m ++CONFIG_VIDEO_OV2311=m ++CONFIG_VIDEO_OV5647=m ++CONFIG_VIDEO_OV64A40=m ++CONFIG_VIDEO_OV7251=m ++CONFIG_VIDEO_OV7640=m ++CONFIG_VIDEO_OV9282=m ++CONFIG_VIDEO_AD5398=m ++CONFIG_VIDEO_AK7375=m ++CONFIG_VIDEO_BU64754=m ++CONFIG_VIDEO_DW9807_VCM=m +CONFIG_VIDEO_SONY_BTF_MPX=m ++CONFIG_VIDEO_UDA1342=m +CONFIG_VIDEO_ADV7180=m +CONFIG_VIDEO_TC358743=m +CONFIG_VIDEO_TVP5150=m +CONFIG_VIDEO_TW2804=m +CONFIG_VIDEO_TW9903=m +CONFIG_VIDEO_TW9906=m -+CONFIG_VIDEO_IMX219=m -+CONFIG_VIDEO_IMX290=m -+CONFIG_VIDEO_IMX477=m -+CONFIG_VIDEO_IMX519=m -+CONFIG_VIDEO_OV5647=m -+CONFIG_VIDEO_OV7251=m -+CONFIG_VIDEO_OV7640=m -+CONFIG_VIDEO_OV9281=m +CONFIG_VIDEO_IRS1125=m -+CONFIG_VIDEO_MT9V011=m ++CONFIG_VIDEO_I2C=m ++CONFIG_AUXDISPLAY=y ++CONFIG_HD44780=m +CONFIG_DRM=m +CONFIG_DRM_LOAD_EDID_FIRMWARE=y +CONFIG_DRM_UDL=m +CONFIG_DRM_PANEL_SIMPLE=m ++CONFIG_DRM_PANEL_ILITEK_ILI9806E=m +CONFIG_DRM_PANEL_ILITEK_ILI9881C=m +CONFIG_DRM_PANEL_JDI_LT070ME05000=m +CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN=m ++CONFIG_DRM_PANEL_SITRONIX_ST7701=m ++CONFIG_DRM_PANEL_TPO_Y17P=m ++CONFIG_DRM_PANEL_WAVESHARE_TOUCHSCREEN=m +CONFIG_DRM_DISPLAY_CONNECTOR=m +CONFIG_DRM_SIMPLE_BRIDGE=m +CONFIG_DRM_TOSHIBA_TC358762=m +CONFIG_DRM_V3D=m +CONFIG_DRM_VC4=m +CONFIG_DRM_VC4_HDMI_CEC=y ++CONFIG_DRM_RP1_DSI=m ++CONFIG_DRM_RP1_DPI=m ++CONFIG_DRM_RP1_VEC=m ++CONFIG_DRM_PANEL_MIPI_DBI=m ++CONFIG_TINYDRM_HX8357D=m +CONFIG_TINYDRM_ILI9225=m +CONFIG_TINYDRM_ILI9341=m ++CONFIG_TINYDRM_ILI9486=m +CONFIG_TINYDRM_MI0283QT=m +CONFIG_TINYDRM_REPAPER=m +CONFIG_TINYDRM_ST7586=m @@ -43869,14 +59339,13 @@ index 000000000000..75333e69ef74 +CONFIG_DRM_GUD=m +CONFIG_FB=y +CONFIG_FB_BCM2708=y -+CONFIG_FB_UDL=m +CONFIG_FB_SIMPLE=y +CONFIG_FB_SSD1307=m +CONFIG_FB_RPISENSE=m +CONFIG_BACKLIGHT_PWM=m +CONFIG_BACKLIGHT_RPI=m ++CONFIG_BACKLIGHT_LM3630A=m +CONFIG_BACKLIGHT_GPIO=m -+CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y +CONFIG_LOGO=y +# CONFIG_LOGO_LINUX_MONO is not set @@ -43886,6 +59355,7 @@ index 000000000000..75333e69ef74 +CONFIG_SND_OSSEMUL=y +CONFIG_SND_PCM_OSS=m +CONFIG_SND_HRTIMER=m ++CONFIG_SND_DYNAMIC_MINORS=y +CONFIG_SND_SEQUENCER=m +CONFIG_SND_SEQ_DUMMY=m +CONFIG_SND_DUMMY=m @@ -43940,6 +59410,9 @@ index 000000000000..75333e69ef74 +CONFIG_SND_BCM2708_SOC_ALLO_KATANA_DAC=m +CONFIG_SND_BCM2708_SOC_FE_PI_AUDIO=m +CONFIG_SND_PISOUND=m ++CONFIG_SND_DACBERRY400=m ++CONFIG_SND_DESIGNWARE_I2S=m ++CONFIG_SND_DESIGNWARE_PCM=y +CONFIG_SND_SOC_AD193X_SPI=m +CONFIG_SND_SOC_AD193X_I2C=m +CONFIG_SND_SOC_ADAU1701=m @@ -43950,6 +59423,7 @@ index 000000000000..75333e69ef74 +CONFIG_SND_SOC_MA120X0P=m +CONFIG_SND_SOC_MAX98357A=m +CONFIG_SND_SOC_SPDIF=m ++CONFIG_SND_SOC_TLV320AIC23_I2C=m +CONFIG_SND_SOC_WM8804_I2C=m +CONFIG_SND_SOC_WM8960=m +CONFIG_SND_SIMPLE_CARD=m @@ -43990,11 +59464,15 @@ index 000000000000..75333e69ef74 +CONFIG_HID_MICROSOFT=m +CONFIG_HID_MONTEREY=m +CONFIG_HID_MULTITOUCH=m ++CONFIG_HID_NINTENDO=m ++CONFIG_NINTENDO_FF=y +CONFIG_HID_NTRIG=m +CONFIG_HID_ORTEK=m +CONFIG_HID_PANTHERLORD=m +CONFIG_HID_PETALYNX=m +CONFIG_HID_PICOLCD=m ++CONFIG_HID_PLAYSTATION=m ++CONFIG_PLAYSTATION_FF=y +CONFIG_HID_ROCCAT=m +CONFIG_HID_SAMSUNG=m +CONFIG_HID_SONY=m @@ -44014,12 +59492,10 @@ index 000000000000..75333e69ef74 +CONFIG_HID_ZYDACRON=m +CONFIG_HID_PID=y +CONFIG_USB_HIDDEV=y -+CONFIG_I2C_HID=m +CONFIG_USB=y +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y +CONFIG_USB_MON=m +CONFIG_USB_XHCI_HCD=y -+CONFIG_USB_XHCI_PLATFORM=y +CONFIG_USB_DWCOTG=y +CONFIG_USB_PRINTER=m +CONFIG_USB_TMC=m @@ -44044,6 +59520,7 @@ index 000000000000..75333e69ef74 +CONFIG_USBIP_VHCI_HCD=m +CONFIG_USBIP_HOST=m +CONFIG_USBIP_VUDC=m ++CONFIG_USB_DWC3=y +CONFIG_USB_DWC2=m +CONFIG_USB_SERIAL=m +CONFIG_USB_SERIAL_GENERIC=y @@ -44085,7 +59562,6 @@ index 000000000000..75333e69ef74 +CONFIG_USB_SERIAL_SYMBOL=m +CONFIG_USB_SERIAL_TI=m +CONFIG_USB_SERIAL_CYBERJACK=m -+CONFIG_USB_SERIAL_XIRCOM=m +CONFIG_USB_SERIAL_OPTION=m +CONFIG_USB_SERIAL_OMNINET=m +CONFIG_USB_SERIAL_OPTICON=m @@ -44103,7 +59579,6 @@ index 000000000000..75333e69ef74 +CONFIG_USB_CYPRESS_CY7C63=m +CONFIG_USB_CYTHERM=m +CONFIG_USB_IDMOUSE=m -+CONFIG_USB_FTDI_ELAN=m +CONFIG_USB_APPLEDISPLAY=m +CONFIG_USB_LD=m +CONFIG_USB_TRANCEVIBRATOR=m @@ -44156,9 +59631,11 @@ index 000000000000..75333e69ef74 +CONFIG_MMC_BCM2835_SDHOST=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_PLTFM=y ++CONFIG_MMC_SDHCI_OF_DWCMSHC=m +CONFIG_MMC_SDHCI_IPROC=y +CONFIG_MMC_SPI=m +CONFIG_LEDS_CLASS=y ++CONFIG_LEDS_CLASS_MULTICOLOR=m +CONFIG_LEDS_PCA9532=m +CONFIG_LEDS_GPIO=y +CONFIG_LEDS_PCA955X=m @@ -44170,7 +59647,6 @@ index 000000000000..75333e69ef74 +CONFIG_LEDS_TRIGGER_HEARTBEAT=y +CONFIG_LEDS_TRIGGER_BACKLIGHT=y +CONFIG_LEDS_TRIGGER_CPU=y -+CONFIG_LEDS_TRIGGER_GPIO=y +CONFIG_LEDS_TRIGGER_DEFAULT_ON=y +CONFIG_LEDS_TRIGGER_TRANSIENT=m +CONFIG_LEDS_TRIGGER_CAMERA=m @@ -44205,6 +59681,8 @@ index 000000000000..75333e69ef74 +CONFIG_RTC_DRV_RX8025=m +CONFIG_RTC_DRV_EM3027=m +CONFIG_RTC_DRV_RV3028=m ++CONFIG_RTC_DRV_RV3032=m ++CONFIG_RTC_DRV_RV8803=m +CONFIG_RTC_DRV_SD3078=m +CONFIG_RTC_DRV_M41T93=m +CONFIG_RTC_DRV_M41T94=m @@ -44221,12 +59699,11 @@ index 000000000000..75333e69ef74 +CONFIG_RTC_DRV_RV3029C2=m +CONFIG_DMADEVICES=y +CONFIG_DMA_BCM2835=y ++CONFIG_DW_AXI_DMAC=y +CONFIG_DMA_BCM2708=y +CONFIG_DMABUF_HEAPS=y +CONFIG_DMABUF_HEAPS_SYSTEM=y +CONFIG_DMABUF_HEAPS_CMA=y -+CONFIG_AUXDISPLAY=y -+CONFIG_HD44780=m +CONFIG_UIO=m +CONFIG_UIO_PDRV_GENIRQ=m +CONFIG_VHOST_NET=m @@ -44235,11 +59712,10 @@ index 000000000000..75333e69ef74 +CONFIG_STAGING=y +CONFIG_PRISM2_USB=m +CONFIG_R8712U=m -+CONFIG_R8188EU=m +CONFIG_VT6656=m +CONFIG_STAGING_MEDIA=y +CONFIG_VIDEO_RPIVID=m -+CONFIG_ASHMEM=y ++CONFIG_STAGING_MEDIA_DEPRECATED=y +CONFIG_FB_TFT=m +CONFIG_FB_TFT_AGM1264K_FL=m +CONFIG_FB_TFT_BD663474=m @@ -44267,48 +59743,61 @@ index 000000000000..75333e69ef74 +CONFIG_FB_TFT_ST7789V=m +CONFIG_FB_TFT_TINYLCD=m +CONFIG_FB_TFT_TLS8204=m ++CONFIG_FB_TFT_UC1611=m +CONFIG_FB_TFT_UC1701=m +CONFIG_FB_TFT_UPD161704=m -+CONFIG_FB_TFT_WATTEROTT=m +CONFIG_BCM2835_VCHIQ=y +CONFIG_SND_BCM2835=m +CONFIG_VIDEO_BCM2835=m +CONFIG_VIDEO_CODEC_BCM2835=m +CONFIG_VIDEO_ISP_BCM2835=m ++CONFIG_COMMON_CLK_RP1=y ++CONFIG_COMMON_CLK_RP1_SDIO=y +CONFIG_CLK_RASPBERRYPI=y +CONFIG_MAILBOX=y +CONFIG_BCM2835_MBOX=y -+# CONFIG_IOMMU_SUPPORT is not set ++CONFIG_BCM2712_IOMMU=y +CONFIG_RASPBERRYPI_POWER=y -+CONFIG_EXTCON_ARIZONA=m +CONFIG_IIO=m +CONFIG_IIO_BUFFER_CB=m ++CONFIG_IIO_SW_TRIGGER=m +CONFIG_MCP320X=m +CONFIG_MCP3422=m +CONFIG_TI_ADS1015=m +CONFIG_BME680=m +CONFIG_CCS811=m +CONFIG_SENSIRION_SGP30=m -+CONFIG_SPS30=m ++CONFIG_SPS30_I2C=m +CONFIG_MAX30102=m +CONFIG_DHT11=m +CONFIG_HDC100X=m +CONFIG_HTU21=m ++CONFIG_SI7020=m ++CONFIG_BOSCH_BNO055_I2C=m +CONFIG_INV_MPU6050_I2C=m +CONFIG_APDS9960=m +CONFIG_BH1750=m +CONFIG_TSL4531=m +CONFIG_VEML6070=m ++CONFIG_IIO_HRTIMER_TRIGGER=m ++CONFIG_IIO_INTERRUPT_TRIGGER=m ++CONFIG_IIO_SYSFS_TRIGGER=m +CONFIG_BMP280=m ++CONFIG_MS5637=m +CONFIG_MAXIM_THERMOCOUPLE=m +CONFIG_MAX31856=m ++CONFIG_PWM=y +CONFIG_PWM_BCM2835=m ++CONFIG_PWM_BRCMSTB=y +CONFIG_PWM_PCA9685=m ++CONFIG_PWM_RASPBERRYPI_POE=m ++CONFIG_PWM_RP1=y ++CONFIG_BCM2712_MIP=y +CONFIG_RPI_AXIPERF=m -+CONFIG_ANDROID=y +CONFIG_ANDROID_BINDER_IPC=y +CONFIG_ANDROID_BINDERFS=y +CONFIG_NVMEM_RMEM=m ++CONFIG_MUX_GPIO=m +CONFIG_EXT4_FS=y +CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_EXT4_FS_SECURITY=y @@ -44335,13 +59824,12 @@ index 000000000000..75333e69ef74 +CONFIG_FANOTIFY=y +CONFIG_QFMT_V1=m +CONFIG_QFMT_V2=m -+CONFIG_AUTOFS4_FS=y ++CONFIG_AUTOFS_FS=y +CONFIG_FUSE_FS=m +CONFIG_CUSE=m +CONFIG_OVERLAY_FS=m +CONFIG_FSCACHE=y +CONFIG_FSCACHE_STATS=y -+CONFIG_FSCACHE_HISTOGRAM=y +CONFIG_CACHEFILES=y +CONFIG_ISO9660_FS=m +CONFIG_JOLIET=y @@ -44353,6 +59841,7 @@ index 000000000000..75333e69ef74 +CONFIG_EXFAT_FS=m +CONFIG_NTFS_FS=m +CONFIG_NTFS_RW=y ++CONFIG_NTFS3_FS=m +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_ECRYPT_FS=m @@ -44365,6 +59854,9 @@ index 000000000000..75333e69ef74 +CONFIG_SQUASHFS_XATTR=y +CONFIG_SQUASHFS_LZO=y +CONFIG_SQUASHFS_XZ=y ++CONFIG_PSTORE=y ++CONFIG_PSTORE_CONSOLE=y ++CONFIG_PSTORE_RAM=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3_ACL=y +CONFIG_NFS_V4=y @@ -44374,15 +59866,18 @@ index 000000000000..75333e69ef74 +CONFIG_ROOT_NFS=y +CONFIG_NFS_FSCACHE=y +CONFIG_NFSD=m ++CONFIG_NFSD_V2=y ++CONFIG_NFSD_V2_ACL=y +CONFIG_NFSD_V3_ACL=y +CONFIG_NFSD_V4=y ++CONFIG_CEPH_FS=m +CONFIG_CIFS=m -+CONFIG_CIFS_WEAK_PW_HASH=y +CONFIG_CIFS_UPCALL=y +CONFIG_CIFS_XATTR=y +CONFIG_CIFS_POSIX=y +CONFIG_CIFS_DFS_UPCALL=y +CONFIG_CIFS_FSCACHE=y ++CONFIG_SMB_SERVER=m +CONFIG_9P_FS=m +CONFIG_9P_FS_POSIX_ACL=y +CONFIG_NLS_DEFAULT="utf8" @@ -44424,29 +59919,48 @@ index 000000000000..75333e69ef74 +CONFIG_NLS_KOI8_R=m +CONFIG_NLS_KOI8_U=m +CONFIG_DLM=m ++CONFIG_KEY_DH_OPERATIONS=y +CONFIG_SECURITY=y +CONFIG_SECURITY_APPARMOR=y +CONFIG_LSM="" +CONFIG_CRYPTO_USER=m -+CONFIG_CRYPTO_CHACHA20POLY1305=m -+CONFIG_CRYPTO_ADIANTUM=m -+CONFIG_CRYPTO_XCBC=m -+CONFIG_CRYPTO_TGR192=m -+CONFIG_CRYPTO_WP512=m ++CONFIG_CRYPTO_CRYPTD=m ++CONFIG_CRYPTO_AES=m +CONFIG_CRYPTO_CAST5=m +CONFIG_CRYPTO_DES=y ++CONFIG_CRYPTO_TWOFISH=m ++CONFIG_CRYPTO_ADIANTUM=m ++CONFIG_CRYPTO_CBC=m ++CONFIG_CRYPTO_CHACHA20POLY1305=m ++CONFIG_CRYPTO_MD4=m ++CONFIG_CRYPTO_SHA512=m ++CONFIG_CRYPTO_WP512=m ++CONFIG_CRYPTO_XCBC=m +CONFIG_CRYPTO_LZ4=m +CONFIG_CRYPTO_USER_API_HASH=m +CONFIG_CRYPTO_USER_API_SKCIPHER=m +CONFIG_CRYPTO_USER_API_RNG=m +CONFIG_CRYPTO_USER_API_AEAD=m ++CONFIG_CRYPTO_GHASH_ARM64_CE=m ++CONFIG_CRYPTO_SHA1_ARM64_CE=m ++CONFIG_CRYPTO_SHA2_ARM64_CE=m ++CONFIG_CRYPTO_SHA512_ARM64_CE=m ++CONFIG_CRYPTO_SHA3_ARM64=m ++CONFIG_CRYPTO_SM3_ARM64_CE=m ++CONFIG_CRYPTO_AES_ARM64=m ++CONFIG_CRYPTO_AES_ARM64_CE_BLK=m ++CONFIG_CRYPTO_AES_ARM64_BS=m ++CONFIG_CRYPTO_SM4_ARM64_CE=m ++CONFIG_CRYPTO_AES_ARM64_CE_CCM=m +# CONFIG_CRYPTO_HW is not set ++CONFIG_PKCS8_PRIVATE_KEY_PARSER=m +CONFIG_CRC_ITU_T=y +CONFIG_LIBCRC32C=y +CONFIG_DMA_CMA=y +CONFIG_CMA_SIZE_MBYTES=5 +CONFIG_PRINTK_TIME=y +CONFIG_BOOT_PRINTK_DELAY=y ++CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1f6 +CONFIG_KGDB=y +CONFIG_KGDB_KDB=y +CONFIG_KDB_KEYBOARD=y @@ -44455,22 +59969,25 @@ index 000000000000..75333e69ef74 +CONFIG_LATENCYTOP=y +CONFIG_FUNCTION_PROFILER=y +CONFIG_STACK_TRACER=y -+CONFIG_IRQSOFF_TRACER=y +CONFIG_SCHED_TRACER=y +CONFIG_BLK_DEV_IO_TRACE=y +# CONFIG_UPROBE_EVENTS is not set -diff --git a/arch/arm64/configs/bcmrpi3_defconfig b/arch/arm64/configs/bcmrpi3_defconfig ++# CONFIG_STRICT_DEVMEM is not set +diff --git a/arch/arm64/configs/bcm2712_defconfig b/arch/arm64/configs/bcm2712_defconfig new file mode 100644 -index 000000000000..419813140a52 +index 000000000000..875b905be102 --- /dev/null -+++ b/arch/arm64/configs/bcmrpi3_defconfig -@@ -0,0 +1,1411 @@ -+CONFIG_LOCALVERSION="-v8" ++++ b/arch/arm64/configs/bcm2712_defconfig +@@ -0,0 +1,1675 @@ ++CONFIG_LOCALVERSION="-v8-16k" +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_SYSVIPC=y +CONFIG_POSIX_MQUEUE=y ++CONFIG_GENERIC_IRQ_DEBUGFS=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y ++CONFIG_BPF_SYSCALL=y ++CONFIG_BPF_JIT=y +CONFIG_PREEMPT=y +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_BSD_PROCESS_ACCT_V3=y @@ -44478,6 +59995,8 @@ index 000000000000..419813140a52 +CONFIG_TASK_DELAY_ACCT=y +CONFIG_TASK_XACCT=y +CONFIG_TASK_IO_ACCOUNTING=y ++CONFIG_PSI=y ++CONFIG_PSI_DEFAULT_DISABLED=y +CONFIG_IKCONFIG=m +CONFIG_IKCONFIG_PROC=y +CONFIG_MEMCG=y @@ -44492,19 +60011,18 @@ index 000000000000..419813140a52 +CONFIG_CGROUP_BPF=y +CONFIG_NAMESPACES=y +CONFIG_USER_NS=y ++CONFIG_CHECKPOINT_RESTORE=y +CONFIG_SCHED_AUTOGROUP=y +CONFIG_BLK_DEV_INITRD=y -+CONFIG_BPF_SYSCALL=y -+CONFIG_EMBEDDED=y -+# CONFIG_COMPAT_BRK is not set ++CONFIG_EXPERT=y +CONFIG_PROFILING=y ++CONFIG_ARCH_BCM=y +CONFIG_ARCH_BCM2835=y ++CONFIG_ARCH_BRCMSTB=y +# CONFIG_CAVIUM_ERRATUM_22375 is not set +# CONFIG_CAVIUM_ERRATUM_23154 is not set +# CONFIG_CAVIUM_ERRATUM_27456 is not set -+CONFIG_SCHED_MC=y -+CONFIG_NR_CPUS=4 -+CONFIG_HZ_1000=y ++CONFIG_ARM64_16K_PAGES=y +CONFIG_COMPAT=y +CONFIG_ARMV8_DEPRECATED=y +CONFIG_SWP_EMULATION=y @@ -44514,8 +60032,8 @@ index 000000000000..419813140a52 +CONFIG_CMDLINE="console=ttyAMA0,115200 kgdboc=ttyAMA0,115200 root=/dev/mmcblk0p2 rootfstype=ext4 rootwait" +# CONFIG_SUSPEND is not set +CONFIG_PM=y ++CONFIG_PM_DEBUG=y +CONFIG_CPU_IDLE=y -+CONFIG_ARM_CPUIDLE=y +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_STAT=y +CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE=y @@ -44526,28 +60044,33 @@ index 000000000000..419813140a52 +CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y +CONFIG_CPUFREQ_DT=y +CONFIG_ARM_RASPBERRYPI_CPUFREQ=y -+CONFIG_RASPBERRYPI_FIRMWARE=y -+CONFIG_CRYPTO_AES_ARM64_BS=m ++CONFIG_VIRTUALIZATION=y ++CONFIG_KVM=y +CONFIG_JUMP_LABEL=y ++CONFIG_ARCH_MMAP_RND_BITS=18 ++CONFIG_ARCH_MMAP_RND_COMPAT_BITS=11 +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODVERSIONS=y +CONFIG_MODULE_SRCVERSION_ALL=y ++CONFIG_MODULE_COMPRESS_XZ=y ++CONFIG_BLK_DEV_THROTTLING=y +CONFIG_PARTITION_ADVANCED=y +CONFIG_MAC_PARTITION=y -+CONFIG_BINFMT_MISC=y -+CONFIG_CLEANCACHE=y -+CONFIG_FRONTSWAP=y -+CONFIG_CMA=y ++CONFIG_BINFMT_MISC=m +CONFIG_ZSWAP=y +CONFIG_Z3FOLD=m -+CONFIG_ZSMALLOC=m ++# CONFIG_COMPAT_BRK is not set ++CONFIG_CMA=y ++CONFIG_LRU_GEN=y ++CONFIG_LRU_GEN_ENABLED=y +CONFIG_NET=y +CONFIG_PACKET=y -+CONFIG_UNIX=y -+CONFIG_XFRM_USER=y ++CONFIG_XFRM_USER=m ++CONFIG_XFRM_INTERFACE=m ++CONFIG_XFRM_SUB_POLICY=y ++CONFIG_XFRM_STATISTICS=y +CONFIG_NET_KEY=m -+CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_ADVANCED_ROUTER=y +CONFIG_IP_MULTIPLE_TABLES=y @@ -44563,6 +60086,7 @@ index 000000000000..419813140a52 +CONFIG_IP_MROUTE_MULTIPLE_TABLES=y +CONFIG_IP_PIMSM_V1=y +CONFIG_IP_PIMSM_V2=y ++CONFIG_NET_IPVTI=m +CONFIG_NET_FOU=m +CONFIG_INET_AH=m +CONFIG_INET_ESP=m @@ -44572,22 +60096,25 @@ index 000000000000..419813140a52 +CONFIG_TCP_CONG_BBR=m +CONFIG_IPV6=m +CONFIG_IPV6_ROUTER_PREF=y ++CONFIG_IPV6_ROUTE_INFO=y +CONFIG_INET6_AH=m +CONFIG_INET6_ESP=m +CONFIG_INET6_ESP_OFFLOAD=m +CONFIG_INET6_IPCOMP=m +CONFIG_IPV6_ILA=m +CONFIG_IPV6_VTI=m ++CONFIG_IPV6_SIT_6RD=y +CONFIG_IPV6_GRE=m +CONFIG_IPV6_MULTIPLE_TABLES=y +CONFIG_IPV6_SUBTREES=y +CONFIG_IPV6_MROUTE=y +CONFIG_IPV6_MROUTE_MULTIPLE_TABLES=y +CONFIG_IPV6_PIMSM_V2=y ++CONFIG_MPTCP=y ++CONFIG_NETWORK_PHY_TIMESTAMPING=y +CONFIG_NETFILTER=y +CONFIG_BRIDGE_NETFILTER=m +CONFIG_NF_CONNTRACK=m -+CONFIG_NF_LOG_NETDEV=m +CONFIG_NF_CONNTRACK_ZONES=y +CONFIG_NF_CONNTRACK_EVENTS=y +CONFIG_NF_CONNTRACK_TIMESTAMP=y @@ -44608,7 +60135,6 @@ index 000000000000..419813140a52 +CONFIG_NFT_NUMGEN=m +CONFIG_NFT_CT=m +CONFIG_NFT_FLOW_OFFLOAD=m -+CONFIG_NFT_COUNTER=m +CONFIG_NFT_CONNLIMIT=m +CONFIG_NFT_LOG=m +CONFIG_NFT_LIMIT=m @@ -44616,21 +60142,23 @@ index 000000000000..419813140a52 +CONFIG_NFT_REDIR=m +CONFIG_NFT_NAT=m +CONFIG_NFT_TUNNEL=m -+CONFIG_NFT_OBJREF=m +CONFIG_NFT_QUEUE=m +CONFIG_NFT_QUOTA=m +CONFIG_NFT_REJECT=m +CONFIG_NFT_COMPAT=m +CONFIG_NFT_HASH=m +CONFIG_NFT_FIB_INET=m ++CONFIG_NFT_XFRM=m +CONFIG_NFT_SOCKET=m +CONFIG_NFT_OSF=m +CONFIG_NFT_TPROXY=m ++CONFIG_NFT_SYNPROXY=m +CONFIG_NFT_DUP_NETDEV=m +CONFIG_NFT_FWD_NETDEV=m +CONFIG_NFT_FIB_NETDEV=m +CONFIG_NF_FLOW_TABLE_INET=m +CONFIG_NF_FLOW_TABLE=m ++CONFIG_NETFILTER_XTABLES_COMPAT=y +CONFIG_NETFILTER_XT_SET=m +CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m +CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m @@ -44702,6 +60230,7 @@ index 000000000000..419813140a52 +CONFIG_IP_SET_HASH_NETIFACE=m +CONFIG_IP_SET_LIST_SET=m +CONFIG_IP_VS=m ++CONFIG_IP_VS_IPV6=y +CONFIG_IP_VS_PROTO_TCP=y +CONFIG_IP_VS_PROTO_UDP=y +CONFIG_IP_VS_PROTO_ESP=y @@ -44722,8 +60251,1677 @@ index 000000000000..419813140a52 +CONFIG_NFT_DUP_IPV4=m +CONFIG_NFT_FIB_IPV4=m +CONFIG_NF_TABLES_ARP=y -+CONFIG_NF_FLOW_TABLE_IPV4=m +CONFIG_NF_LOG_ARP=m ++CONFIG_NF_LOG_IPV4=m ++CONFIG_IP_NF_IPTABLES=m ++CONFIG_IP_NF_MATCH_AH=m ++CONFIG_IP_NF_MATCH_ECN=m ++CONFIG_IP_NF_MATCH_RPFILTER=m ++CONFIG_IP_NF_MATCH_TTL=m ++CONFIG_IP_NF_FILTER=m ++CONFIG_IP_NF_TARGET_REJECT=m ++CONFIG_IP_NF_NAT=m ++CONFIG_IP_NF_TARGET_MASQUERADE=m ++CONFIG_IP_NF_TARGET_NETMAP=m ++CONFIG_IP_NF_TARGET_REDIRECT=m ++CONFIG_IP_NF_MANGLE=m ++CONFIG_IP_NF_TARGET_ECN=m ++CONFIG_IP_NF_TARGET_TTL=m ++CONFIG_IP_NF_RAW=m ++CONFIG_IP_NF_ARPTABLES=m ++CONFIG_IP_NF_ARPFILTER=m ++CONFIG_IP_NF_ARP_MANGLE=m ++CONFIG_NFT_DUP_IPV6=m ++CONFIG_NFT_FIB_IPV6=m ++CONFIG_IP6_NF_IPTABLES=m ++CONFIG_IP6_NF_MATCH_AH=m ++CONFIG_IP6_NF_MATCH_EUI64=m ++CONFIG_IP6_NF_MATCH_FRAG=m ++CONFIG_IP6_NF_MATCH_OPTS=m ++CONFIG_IP6_NF_MATCH_HL=m ++CONFIG_IP6_NF_MATCH_IPV6HEADER=m ++CONFIG_IP6_NF_MATCH_MH=m ++CONFIG_IP6_NF_MATCH_RPFILTER=m ++CONFIG_IP6_NF_MATCH_RT=m ++CONFIG_IP6_NF_MATCH_SRH=m ++CONFIG_IP6_NF_TARGET_HL=m ++CONFIG_IP6_NF_FILTER=m ++CONFIG_IP6_NF_TARGET_REJECT=m ++CONFIG_IP6_NF_TARGET_SYNPROXY=m ++CONFIG_IP6_NF_MANGLE=m ++CONFIG_IP6_NF_RAW=m ++CONFIG_IP6_NF_SECURITY=m ++CONFIG_IP6_NF_NAT=m ++CONFIG_IP6_NF_TARGET_MASQUERADE=m ++CONFIG_IP6_NF_TARGET_NPT=m ++CONFIG_NF_TABLES_BRIDGE=m ++CONFIG_NFT_BRIDGE_REJECT=m ++CONFIG_BRIDGE_NF_EBTABLES=m ++CONFIG_BRIDGE_EBT_BROUTE=m ++CONFIG_BRIDGE_EBT_T_FILTER=m ++CONFIG_BRIDGE_EBT_T_NAT=m ++CONFIG_BRIDGE_EBT_802_3=m ++CONFIG_BRIDGE_EBT_AMONG=m ++CONFIG_BRIDGE_EBT_ARP=m ++CONFIG_BRIDGE_EBT_IP=m ++CONFIG_BRIDGE_EBT_IP6=m ++CONFIG_BRIDGE_EBT_LIMIT=m ++CONFIG_BRIDGE_EBT_MARK=m ++CONFIG_BRIDGE_EBT_PKTTYPE=m ++CONFIG_BRIDGE_EBT_STP=m ++CONFIG_BRIDGE_EBT_VLAN=m ++CONFIG_BRIDGE_EBT_ARPREPLY=m ++CONFIG_BRIDGE_EBT_DNAT=m ++CONFIG_BRIDGE_EBT_MARK_T=m ++CONFIG_BRIDGE_EBT_REDIRECT=m ++CONFIG_BRIDGE_EBT_SNAT=m ++CONFIG_BRIDGE_EBT_LOG=m ++CONFIG_BRIDGE_EBT_NFLOG=m ++CONFIG_SCTP_COOKIE_HMAC_SHA1=y ++CONFIG_ATM=m ++CONFIG_L2TP=m ++CONFIG_L2TP_V3=y ++CONFIG_L2TP_IP=m ++CONFIG_L2TP_ETH=m ++CONFIG_BRIDGE=m ++CONFIG_VLAN_8021Q=m ++CONFIG_VLAN_8021Q_GVRP=y ++CONFIG_ATALK=m ++CONFIG_6LOWPAN=m ++CONFIG_IEEE802154=m ++CONFIG_IEEE802154_6LOWPAN=m ++CONFIG_MAC802154=m ++CONFIG_NET_SCHED=y ++CONFIG_NET_SCH_HTB=m ++CONFIG_NET_SCH_HFSC=m ++CONFIG_NET_SCH_PRIO=m ++CONFIG_NET_SCH_MULTIQ=m ++CONFIG_NET_SCH_RED=m ++CONFIG_NET_SCH_SFB=m ++CONFIG_NET_SCH_SFQ=m ++CONFIG_NET_SCH_TEQL=m ++CONFIG_NET_SCH_TBF=m ++CONFIG_NET_SCH_GRED=m ++CONFIG_NET_SCH_NETEM=m ++CONFIG_NET_SCH_DRR=m ++CONFIG_NET_SCH_MQPRIO=m ++CONFIG_NET_SCH_CHOKE=m ++CONFIG_NET_SCH_QFQ=m ++CONFIG_NET_SCH_CODEL=m ++CONFIG_NET_SCH_FQ_CODEL=m ++CONFIG_NET_SCH_CAKE=m ++CONFIG_NET_SCH_FQ=m ++CONFIG_NET_SCH_HHF=m ++CONFIG_NET_SCH_PIE=m ++CONFIG_NET_SCH_INGRESS=m ++CONFIG_NET_SCH_PLUG=m ++CONFIG_NET_CLS_BASIC=m ++CONFIG_NET_CLS_ROUTE4=m ++CONFIG_NET_CLS_FW=m ++CONFIG_NET_CLS_U32=m ++CONFIG_CLS_U32_MARK=y ++CONFIG_NET_CLS_FLOW=m ++CONFIG_NET_CLS_CGROUP=m ++CONFIG_NET_CLS_BPF=y ++CONFIG_NET_EMATCH=y ++CONFIG_NET_EMATCH_CMP=m ++CONFIG_NET_EMATCH_NBYTE=m ++CONFIG_NET_EMATCH_U32=m ++CONFIG_NET_EMATCH_META=m ++CONFIG_NET_EMATCH_TEXT=m ++CONFIG_NET_EMATCH_IPSET=m ++CONFIG_NET_CLS_ACT=y ++CONFIG_NET_ACT_POLICE=m ++CONFIG_NET_ACT_GACT=m ++CONFIG_GACT_PROB=y ++CONFIG_NET_ACT_MIRRED=m ++CONFIG_NET_ACT_IPT=m ++CONFIG_NET_ACT_NAT=m ++CONFIG_NET_ACT_PEDIT=m ++CONFIG_NET_ACT_SIMP=m ++CONFIG_NET_ACT_SKBEDIT=m ++CONFIG_NET_ACT_CSUM=m ++CONFIG_BATMAN_ADV=m ++CONFIG_OPENVSWITCH=m ++CONFIG_VSOCKETS=m ++CONFIG_CGROUP_NET_PRIO=y ++CONFIG_NET_PKTGEN=m ++CONFIG_HAMRADIO=y ++CONFIG_AX25=m ++CONFIG_NETROM=m ++CONFIG_ROSE=m ++CONFIG_MKISS=m ++CONFIG_6PACK=m ++CONFIG_BPQETHER=m ++CONFIG_BAYCOM_SER_FDX=m ++CONFIG_BAYCOM_SER_HDX=m ++CONFIG_YAM=m ++CONFIG_CAN=m ++CONFIG_CAN_J1939=m ++CONFIG_CAN_ISOTP=m ++CONFIG_BT=m ++CONFIG_BT_RFCOMM=m ++CONFIG_BT_RFCOMM_TTY=y ++CONFIG_BT_BNEP=m ++CONFIG_BT_BNEP_MC_FILTER=y ++CONFIG_BT_BNEP_PROTO_FILTER=y ++CONFIG_BT_HIDP=m ++CONFIG_BT_6LOWPAN=m ++CONFIG_BT_HCIBTUSB=m ++CONFIG_BT_HCIUART=m ++CONFIG_BT_HCIUART_3WIRE=y ++CONFIG_BT_HCIUART_BCM=y ++CONFIG_BT_HCIBCM203X=m ++CONFIG_BT_HCIBPA10X=m ++CONFIG_BT_HCIBFUSB=m ++CONFIG_BT_HCIVHCI=m ++CONFIG_BT_MRVL=m ++CONFIG_BT_MRVL_SDIO=m ++CONFIG_BT_ATH3K=m ++CONFIG_CFG80211=m ++CONFIG_CFG80211_WEXT=y ++CONFIG_MAC80211=m ++CONFIG_MAC80211_MESH=y ++CONFIG_RFKILL=m ++CONFIG_RFKILL_INPUT=y ++CONFIG_NET_9P=m ++CONFIG_NFC=m ++CONFIG_PCI=y ++CONFIG_PCIEPORTBUS=y ++CONFIG_PCIEAER=y ++CONFIG_PCIEASPM_POWERSAVE=y ++CONFIG_PCIE_DPC=y ++CONFIG_UEVENT_HELPER=y ++CONFIG_DEVTMPFS=y ++CONFIG_DEVTMPFS_MOUNT=y ++# CONFIG_BRCMSTB_GISB_ARB is not set ++CONFIG_RASPBERRYPI_FIRMWARE=y ++# CONFIG_EFI_VARS_PSTORE is not set ++CONFIG_MTD=m ++CONFIG_MTD_BLOCK=m ++CONFIG_MTD_BLOCK2MTD=m ++CONFIG_MTD_SPI_NAND=m ++CONFIG_MTD_SPI_NOR=m ++CONFIG_MTD_UBI=m ++CONFIG_OF_CONFIGFS=y ++CONFIG_ZRAM=m ++CONFIG_BLK_DEV_LOOP=y ++CONFIG_BLK_DEV_DRBD=m ++CONFIG_BLK_DEV_NBD=m ++CONFIG_BLK_DEV_RAM=y ++CONFIG_ATA_OVER_ETH=m ++CONFIG_BLK_DEV_NVME=y ++CONFIG_NVME_HWMON=y ++CONFIG_EEPROM_AT24=m ++CONFIG_EEPROM_AT25=m ++CONFIG_TI_ST=m ++CONFIG_SCSI=y ++# CONFIG_SCSI_PROC_FS is not set ++CONFIG_BLK_DEV_SD=y ++CONFIG_CHR_DEV_ST=m ++CONFIG_BLK_DEV_SR=m ++CONFIG_CHR_DEV_SG=m ++CONFIG_SCSI_ISCSI_ATTRS=y ++CONFIG_ISCSI_TCP=m ++CONFIG_ISCSI_BOOT_SYSFS=m ++CONFIG_ATA=m ++CONFIG_SATA_AHCI=m ++CONFIG_SATA_MV=m ++CONFIG_MD=y ++CONFIG_MD_LINEAR=m ++CONFIG_BLK_DEV_DM=m ++CONFIG_DM_CRYPT=m ++CONFIG_DM_SNAPSHOT=m ++CONFIG_DM_THIN_PROVISIONING=m ++CONFIG_DM_CACHE=m ++CONFIG_DM_WRITECACHE=m ++CONFIG_DM_MIRROR=m ++CONFIG_DM_LOG_USERSPACE=m ++CONFIG_DM_RAID=m ++CONFIG_DM_ZERO=m ++CONFIG_DM_MULTIPATH=m ++CONFIG_DM_DELAY=m ++CONFIG_DM_INTEGRITY=m ++CONFIG_NETDEVICES=y ++CONFIG_BONDING=m ++CONFIG_DUMMY=m ++CONFIG_WIREGUARD=m ++CONFIG_IFB=m ++CONFIG_MACVLAN=m ++CONFIG_MACVTAP=m ++CONFIG_IPVLAN=m ++CONFIG_VXLAN=m ++CONFIG_NETCONSOLE=m ++CONFIG_TUN=m ++CONFIG_VETH=m ++CONFIG_NET_VRF=m ++CONFIG_VSOCKMON=m ++CONFIG_BCMGENET=y ++CONFIG_MACB=y ++CONFIG_ENC28J60=m ++CONFIG_LAN743X=m ++CONFIG_QCA7000_SPI=m ++CONFIG_QCA7000_UART=m ++CONFIG_R8169=m ++CONFIG_WIZNET_W5100=m ++CONFIG_WIZNET_W5100_SPI=m ++CONFIG_MICREL_PHY=y ++CONFIG_CAN_VCAN=m ++CONFIG_CAN_SLCAN=m ++CONFIG_CAN_MCP251X=m ++CONFIG_CAN_MCP251XFD=m ++CONFIG_CAN_8DEV_USB=m ++CONFIG_CAN_EMS_USB=m ++CONFIG_CAN_GS_USB=m ++CONFIG_CAN_PEAK_USB=m ++CONFIG_MDIO_BITBANG=m ++CONFIG_PPP=m ++CONFIG_PPP_BSDCOMP=m ++CONFIG_PPP_DEFLATE=m ++CONFIG_PPP_FILTER=y ++CONFIG_PPP_MPPE=m ++CONFIG_PPP_MULTILINK=y ++CONFIG_PPPOATM=m ++CONFIG_PPPOE=m ++CONFIG_PPPOL2TP=m ++CONFIG_PPP_ASYNC=m ++CONFIG_PPP_SYNC_TTY=m ++CONFIG_SLIP=m ++CONFIG_SLIP_COMPRESSED=y ++CONFIG_SLIP_SMART=y ++CONFIG_USB_CATC=m ++CONFIG_USB_KAWETH=m ++CONFIG_USB_PEGASUS=m ++CONFIG_USB_RTL8150=m ++CONFIG_USB_RTL8152=y ++CONFIG_USB_LAN78XX=y ++CONFIG_USB_USBNET=y ++CONFIG_USB_NET_AX8817X=m ++CONFIG_USB_NET_AX88179_178A=m ++CONFIG_USB_NET_CDCETHER=m ++CONFIG_USB_NET_CDC_EEM=m ++CONFIG_USB_NET_CDC_NCM=m ++CONFIG_USB_NET_HUAWEI_CDC_NCM=m ++CONFIG_USB_NET_CDC_MBIM=m ++CONFIG_USB_NET_DM9601=m ++CONFIG_USB_NET_SR9700=m ++CONFIG_USB_NET_SR9800=m ++CONFIG_USB_NET_SMSC75XX=m ++CONFIG_USB_NET_SMSC95XX=y ++CONFIG_USB_NET_GL620A=m ++CONFIG_USB_NET_NET1080=m ++CONFIG_USB_NET_PLUSB=m ++CONFIG_USB_NET_MCS7830=m ++CONFIG_USB_NET_CDC_SUBSET=m ++CONFIG_USB_ALI_M5632=y ++CONFIG_USB_AN2720=y ++CONFIG_USB_EPSON2888=y ++CONFIG_USB_KC2190=y ++CONFIG_USB_NET_ZAURUS=m ++CONFIG_USB_NET_CX82310_ETH=m ++CONFIG_USB_NET_KALMIA=m ++CONFIG_USB_NET_QMI_WWAN=m ++CONFIG_USB_HSO=m ++CONFIG_USB_NET_INT51X1=m ++CONFIG_USB_IPHETH=m ++CONFIG_USB_SIERRA_NET=m ++CONFIG_USB_VL600=m ++CONFIG_USB_NET_AQC111=m ++CONFIG_ATH9K=m ++CONFIG_ATH9K_HTC=m ++CONFIG_CARL9170=m ++CONFIG_ATH6KL=m ++CONFIG_ATH6KL_USB=m ++CONFIG_AR5523=m ++CONFIG_AT76C50X_USB=m ++CONFIG_B43=m ++# CONFIG_B43_PHY_N is not set ++CONFIG_B43LEGACY=m ++CONFIG_BRCMFMAC=m ++CONFIG_BRCMFMAC_USB=y ++CONFIG_BRCMDBG=y ++CONFIG_HOSTAP=m ++CONFIG_P54_COMMON=m ++CONFIG_P54_USB=m ++CONFIG_LIBERTAS=m ++CONFIG_LIBERTAS_USB=m ++CONFIG_LIBERTAS_SDIO=m ++CONFIG_LIBERTAS_THINFIRM=m ++CONFIG_LIBERTAS_THINFIRM_USB=m ++CONFIG_MWIFIEX=m ++CONFIG_MWIFIEX_SDIO=m ++CONFIG_MT7601U=m ++CONFIG_MT76x0U=m ++CONFIG_MT76x2U=m ++CONFIG_MT7921U=m ++CONFIG_RT2X00=m ++CONFIG_RT2500USB=m ++CONFIG_RT73USB=m ++CONFIG_RT2800USB=m ++CONFIG_RT2800USB_RT3573=y ++CONFIG_RT2800USB_RT53XX=y ++CONFIG_RT2800USB_RT55XX=y ++CONFIG_RT2800USB_UNKNOWN=y ++CONFIG_RTL8187=m ++CONFIG_RTL8192CU=m ++CONFIG_RTL8XXXU=m ++CONFIG_RTW88=m ++CONFIG_RTW88_8822BU=m ++CONFIG_RTW88_8822CU=m ++CONFIG_RTW88_8723DU=m ++CONFIG_RTW88_8821CU=m ++CONFIG_USB_ZD1201=m ++CONFIG_ZD1211RW=m ++CONFIG_USB_NET_RNDIS_WLAN=m ++CONFIG_MAC80211_HWSIM=m ++CONFIG_IEEE802154_AT86RF230=m ++CONFIG_IEEE802154_MRF24J40=m ++CONFIG_IEEE802154_CC2520=m ++CONFIG_INPUT_MOUSEDEV=y ++CONFIG_INPUT_JOYDEV=m ++CONFIG_INPUT_EVDEV=y ++# CONFIG_KEYBOARD_ATKBD is not set ++CONFIG_KEYBOARD_GPIO=m ++CONFIG_KEYBOARD_TCA6416=m ++CONFIG_KEYBOARD_TCA8418=m ++CONFIG_KEYBOARD_MATRIX=m ++CONFIG_KEYBOARD_CAP11XX=m ++# CONFIG_INPUT_MOUSE is not set ++CONFIG_INPUT_JOYSTICK=y ++CONFIG_JOYSTICK_IFORCE=m ++CONFIG_JOYSTICK_IFORCE_USB=m ++CONFIG_JOYSTICK_XPAD=m ++CONFIG_JOYSTICK_XPAD_FF=y ++CONFIG_JOYSTICK_XPAD_LEDS=y ++CONFIG_JOYSTICK_PSXPAD_SPI=m ++CONFIG_JOYSTICK_PSXPAD_SPI_FF=y ++CONFIG_JOYSTICK_FSIA6B=m ++CONFIG_JOYSTICK_RPISENSE=m ++CONFIG_INPUT_TOUCHSCREEN=y ++CONFIG_TOUCHSCREEN_ADS7846=m ++CONFIG_TOUCHSCREEN_EGALAX=m ++CONFIG_TOUCHSCREEN_EXC3000=m ++CONFIG_TOUCHSCREEN_GOODIX=m ++CONFIG_TOUCHSCREEN_ILI210X=m ++CONFIG_TOUCHSCREEN_EDT_FT5X06=m ++CONFIG_TOUCHSCREEN_RASPBERRYPI_FW=m ++CONFIG_TOUCHSCREEN_USB_COMPOSITE=m ++CONFIG_TOUCHSCREEN_TSC2007=m ++CONFIG_TOUCHSCREEN_TSC2007_IIO=y ++CONFIG_TOUCHSCREEN_STMPE=m ++CONFIG_TOUCHSCREEN_IQS5XX=m ++CONFIG_INPUT_MISC=y ++CONFIG_INPUT_AD714X=m ++CONFIG_INPUT_ATI_REMOTE2=m ++CONFIG_INPUT_KEYSPAN_REMOTE=m ++CONFIG_INPUT_POWERMATE=m ++CONFIG_INPUT_YEALINK=m ++CONFIG_INPUT_CM109=m ++CONFIG_INPUT_UINPUT=m ++CONFIG_INPUT_GPIO_ROTARY_ENCODER=m ++CONFIG_INPUT_ADXL34X=m ++CONFIG_INPUT_CMA3000=m ++CONFIG_SERIO=m ++CONFIG_SERIO_RAW=m ++CONFIG_GAMEPORT=m ++CONFIG_BRCM_CHAR_DRIVERS=y ++CONFIG_BCM_VCIO=y ++# CONFIG_LEGACY_PTYS is not set ++CONFIG_SERIAL_8250=y ++# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set ++CONFIG_SERIAL_8250_CONSOLE=y ++# CONFIG_SERIAL_8250_DMA is not set ++CONFIG_SERIAL_8250_NR_UARTS=5 ++CONFIG_SERIAL_8250_RUNTIME_UARTS=0 ++CONFIG_SERIAL_8250_EXTENDED=y ++CONFIG_SERIAL_8250_SHARE_IRQ=y ++CONFIG_SERIAL_8250_BCM2835AUX=y ++CONFIG_SERIAL_OF_PLATFORM=y ++CONFIG_SERIAL_AMBA_PL011=y ++CONFIG_SERIAL_AMBA_PL011_CONSOLE=y ++CONFIG_SERIAL_SC16IS7XX=m ++CONFIG_SERIAL_SC16IS7XX_SPI=y ++CONFIG_SERIAL_DEV_BUS=y ++CONFIG_TTY_PRINTK=y ++CONFIG_HW_RANDOM=y ++CONFIG_TCG_TPM=m ++CONFIG_TCG_TIS_SPI=m ++CONFIG_TCG_TIS_I2C=m ++CONFIG_XILLYBUS=m ++CONFIG_XILLYBUS_PCIE=m ++CONFIG_XILLYUSB=m ++CONFIG_RASPBERRYPI_GPIOMEM=m ++CONFIG_I2C=y ++CONFIG_I2C_CHARDEV=m ++CONFIG_I2C_MUX_GPMUX=m ++CONFIG_I2C_MUX_PCA954x=m ++CONFIG_I2C_MUX_PINCTRL=m ++CONFIG_I2C_BCM2708=m ++CONFIG_I2C_BCM2835=m ++CONFIG_I2C_BRCMSTB=m ++CONFIG_I2C_DESIGNWARE_PLATFORM=m ++CONFIG_I2C_GPIO=m ++CONFIG_I2C_ROBOTFUZZ_OSIF=m ++CONFIG_I2C_TINY_USB=m ++CONFIG_SPI=y ++CONFIG_SPI_BCM2835=m ++CONFIG_SPI_BCM2835AUX=m ++CONFIG_SPI_DESIGNWARE=m ++CONFIG_SPI_DW_DMA=y ++CONFIG_SPI_DW_MMIO=m ++CONFIG_SPI_GPIO=m ++CONFIG_SPI_SPIDEV=m ++CONFIG_SPI_SLAVE=y ++CONFIG_PPS_CLIENT_LDISC=m ++CONFIG_PPS_CLIENT_GPIO=m ++CONFIG_PINCTRL_MCP23S08=m ++CONFIG_PINCTRL_RP1=y ++CONFIG_PINCTRL_BCM2712=y ++CONFIG_GPIO_SYSFS=y ++CONFIG_GPIO_BCM_VIRT=y ++CONFIG_GPIO_MAX7300=m ++CONFIG_GPIO_PCA953X=m ++CONFIG_GPIO_PCA953X_IRQ=y ++CONFIG_GPIO_PCF857X=m ++CONFIG_GPIO_ARIZONA=m ++CONFIG_GPIO_FSM=m ++CONFIG_GPIO_STMPE=y ++CONFIG_GPIO_MAX7301=m ++CONFIG_GPIO_MOCKUP=m ++CONFIG_W1=m ++CONFIG_W1_MASTER_DS2490=m ++CONFIG_W1_MASTER_DS2482=m ++CONFIG_W1_MASTER_GPIO=m ++CONFIG_W1_SLAVE_THERM=m ++CONFIG_W1_SLAVE_SMEM=m ++CONFIG_W1_SLAVE_DS2408=m ++CONFIG_W1_SLAVE_DS2413=m ++CONFIG_W1_SLAVE_DS2406=m ++CONFIG_W1_SLAVE_DS2423=m ++CONFIG_W1_SLAVE_DS2431=m ++CONFIG_W1_SLAVE_DS2433=m ++CONFIG_W1_SLAVE_DS2438=m ++CONFIG_W1_SLAVE_DS2780=m ++CONFIG_W1_SLAVE_DS2781=m ++CONFIG_W1_SLAVE_DS28E04=m ++CONFIG_W1_SLAVE_DS28E17=m ++# CONFIG_POWER_RESET_BRCMSTB is not set ++CONFIG_POWER_RESET_GPIO=y ++CONFIG_RPI_POE_POWER=m ++CONFIG_BATTERY_DS2760=m ++CONFIG_BATTERY_MAX17040=m ++CONFIG_CHARGER_GPIO=m ++CONFIG_BATTERY_GAUGE_LTC2941=m ++CONFIG_SENSORS_ADT7410=m ++CONFIG_SENSORS_AHT10=m ++CONFIG_SENSORS_DRIVETEMP=m ++CONFIG_SENSORS_DS1621=m ++CONFIG_SENSORS_GPIO_FAN=m ++CONFIG_SENSORS_IIO_HWMON=m ++CONFIG_SENSORS_JC42=m ++CONFIG_SENSORS_LM75=m ++CONFIG_SENSORS_PWM_FAN=m ++CONFIG_SENSORS_RASPBERRYPI_HWMON=m ++CONFIG_SENSORS_SHT21=m ++CONFIG_SENSORS_SHT3x=m ++CONFIG_SENSORS_SHT4x=m ++CONFIG_SENSORS_SHTC1=m ++CONFIG_SENSORS_EMC2305=m ++CONFIG_SENSORS_INA2XX=m ++CONFIG_SENSORS_TMP102=m ++CONFIG_SENSORS_RP1_ADC=m ++CONFIG_BCM2711_THERMAL=y ++CONFIG_BCM2835_THERMAL=y ++CONFIG_WATCHDOG=y ++CONFIG_GPIO_WATCHDOG=m ++CONFIG_BCM2835_WDT=y ++CONFIG_MFD_RASPBERRYPI_POE_HAT=m ++CONFIG_MFD_STMPE=y ++CONFIG_STMPE_SPI=y ++CONFIG_MFD_SYSCON=y ++CONFIG_MFD_ARIZONA_I2C=m ++CONFIG_MFD_ARIZONA_SPI=m ++CONFIG_MFD_WM5102=y ++CONFIG_MFD_RP1=y ++CONFIG_REGULATOR=y ++CONFIG_REGULATOR_FIXED_VOLTAGE=y ++CONFIG_REGULATOR_ARIZONA_LDO1=m ++CONFIG_REGULATOR_ARIZONA_MICSUPP=m ++CONFIG_REGULATOR_GPIO=y ++CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_ATTINY=m ++CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_V2=m ++CONFIG_RC_CORE=y ++CONFIG_BPF_LIRC_MODE2=y ++CONFIG_LIRC=y ++CONFIG_RC_DECODERS=y ++CONFIG_IR_IMON_DECODER=m ++CONFIG_IR_JVC_DECODER=m ++CONFIG_IR_MCE_KBD_DECODER=m ++CONFIG_IR_NEC_DECODER=m ++CONFIG_IR_RC5_DECODER=m ++CONFIG_IR_RC6_DECODER=m ++CONFIG_IR_SANYO_DECODER=m ++CONFIG_IR_SHARP_DECODER=m ++CONFIG_IR_SONY_DECODER=m ++CONFIG_IR_XMP_DECODER=m ++CONFIG_RC_DEVICES=y ++CONFIG_IR_GPIO_CIR=m ++CONFIG_IR_GPIO_TX=m ++CONFIG_IR_IGUANA=m ++CONFIG_IR_IMON=m ++CONFIG_IR_MCEUSB=m ++CONFIG_IR_PWM_TX=m ++CONFIG_IR_REDRAT3=m ++CONFIG_IR_STREAMZAP=m ++CONFIG_IR_TOY=m ++CONFIG_IR_TTUSBIR=m ++CONFIG_RC_ATI_REMOTE=m ++CONFIG_RC_LOOPBACK=m ++CONFIG_MEDIA_CEC_RC=y ++CONFIG_MEDIA_SUPPORT=m ++CONFIG_MEDIA_USB_SUPPORT=y ++CONFIG_USB_GSPCA=m ++CONFIG_USB_GSPCA_BENQ=m ++CONFIG_USB_GSPCA_CONEX=m ++CONFIG_USB_GSPCA_CPIA1=m ++CONFIG_USB_GSPCA_DTCS033=m ++CONFIG_USB_GSPCA_ETOMS=m ++CONFIG_USB_GSPCA_FINEPIX=m ++CONFIG_USB_GSPCA_JEILINJ=m ++CONFIG_USB_GSPCA_JL2005BCD=m ++CONFIG_USB_GSPCA_KINECT=m ++CONFIG_USB_GSPCA_KONICA=m ++CONFIG_USB_GSPCA_MARS=m ++CONFIG_USB_GSPCA_MR97310A=m ++CONFIG_USB_GSPCA_NW80X=m ++CONFIG_USB_GSPCA_OV519=m ++CONFIG_USB_GSPCA_OV534=m ++CONFIG_USB_GSPCA_OV534_9=m ++CONFIG_USB_GSPCA_PAC207=m ++CONFIG_USB_GSPCA_PAC7302=m ++CONFIG_USB_GSPCA_PAC7311=m ++CONFIG_USB_GSPCA_SE401=m ++CONFIG_USB_GSPCA_SN9C2028=m ++CONFIG_USB_GSPCA_SN9C20X=m ++CONFIG_USB_GSPCA_SONIXB=m ++CONFIG_USB_GSPCA_SONIXJ=m ++CONFIG_USB_GSPCA_SPCA1528=m ++CONFIG_USB_GSPCA_SPCA500=m ++CONFIG_USB_GSPCA_SPCA501=m ++CONFIG_USB_GSPCA_SPCA505=m ++CONFIG_USB_GSPCA_SPCA506=m ++CONFIG_USB_GSPCA_SPCA508=m ++CONFIG_USB_GSPCA_SPCA561=m ++CONFIG_USB_GSPCA_SQ905=m ++CONFIG_USB_GSPCA_SQ905C=m ++CONFIG_USB_GSPCA_SQ930X=m ++CONFIG_USB_GSPCA_STK014=m ++CONFIG_USB_GSPCA_STK1135=m ++CONFIG_USB_GSPCA_STV0680=m ++CONFIG_USB_GSPCA_SUNPLUS=m ++CONFIG_USB_GSPCA_T613=m ++CONFIG_USB_GSPCA_TOPRO=m ++CONFIG_USB_GSPCA_TOUPTEK=m ++CONFIG_USB_GSPCA_TV8532=m ++CONFIG_USB_GSPCA_VC032X=m ++CONFIG_USB_GSPCA_VICAM=m ++CONFIG_USB_GSPCA_XIRLINK_CIT=m ++CONFIG_USB_GSPCA_ZC3XX=m ++CONFIG_USB_GL860=m ++CONFIG_USB_M5602=m ++CONFIG_USB_STV06XX=m ++CONFIG_USB_PWC=m ++CONFIG_USB_S2255=m ++CONFIG_VIDEO_USBTV=m ++CONFIG_USB_VIDEO_CLASS=m ++CONFIG_VIDEO_GO7007=m ++CONFIG_VIDEO_GO7007_USB=m ++CONFIG_VIDEO_GO7007_USB_S2250_BOARD=m ++CONFIG_VIDEO_HDPVR=m ++CONFIG_VIDEO_PVRUSB2=m ++CONFIG_VIDEO_STK1160=m ++CONFIG_VIDEO_AU0828=m ++CONFIG_VIDEO_AU0828_RC=y ++CONFIG_VIDEO_CX231XX=m ++CONFIG_VIDEO_CX231XX_ALSA=m ++CONFIG_VIDEO_CX231XX_DVB=m ++CONFIG_DVB_AS102=m ++CONFIG_DVB_B2C2_FLEXCOP_USB=m ++CONFIG_DVB_USB_V2=m ++CONFIG_DVB_USB_AF9015=m ++CONFIG_DVB_USB_AF9035=m ++CONFIG_DVB_USB_ANYSEE=m ++CONFIG_DVB_USB_AU6610=m ++CONFIG_DVB_USB_AZ6007=m ++CONFIG_DVB_USB_CE6230=m ++CONFIG_DVB_USB_DVBSKY=m ++CONFIG_DVB_USB_EC168=m ++CONFIG_DVB_USB_GL861=m ++CONFIG_DVB_USB_LME2510=m ++CONFIG_DVB_USB_MXL111SF=m ++CONFIG_DVB_USB_RTL28XXU=m ++CONFIG_DVB_USB=m ++CONFIG_DVB_USB_A800=m ++CONFIG_DVB_USB_AF9005=m ++CONFIG_DVB_USB_AF9005_REMOTE=m ++CONFIG_DVB_USB_AZ6027=m ++CONFIG_DVB_USB_CINERGY_T2=m ++CONFIG_DVB_USB_CXUSB=m ++CONFIG_DVB_USB_DIB0700=m ++CONFIG_DVB_USB_DIBUSB_MB=m ++CONFIG_DVB_USB_DIBUSB_MB_FAULTY=y ++CONFIG_DVB_USB_DIBUSB_MC=m ++CONFIG_DVB_USB_DIGITV=m ++CONFIG_DVB_USB_DTT200U=m ++CONFIG_DVB_USB_DTV5100=m ++CONFIG_DVB_USB_DW2102=m ++CONFIG_DVB_USB_GP8PSK=m ++CONFIG_DVB_USB_M920X=m ++CONFIG_DVB_USB_NOVA_T_USB2=m ++CONFIG_DVB_USB_OPERA1=m ++CONFIG_DVB_USB_PCTV452E=m ++CONFIG_DVB_USB_TECHNISAT_USB2=m ++CONFIG_DVB_USB_TTUSB2=m ++CONFIG_DVB_USB_UMT_010=m ++CONFIG_DVB_USB_VP702X=m ++CONFIG_DVB_USB_VP7045=m ++CONFIG_SMS_USB_DRV=m ++CONFIG_VIDEO_EM28XX=m ++CONFIG_VIDEO_EM28XX_V4L2=m ++CONFIG_VIDEO_EM28XX_ALSA=m ++CONFIG_VIDEO_EM28XX_DVB=m ++CONFIG_RADIO_SAA7706H=m ++CONFIG_RADIO_SHARK=m ++CONFIG_RADIO_SHARK2=m ++CONFIG_RADIO_SI4713=m ++CONFIG_RADIO_TEA5764=m ++CONFIG_RADIO_TEF6862=m ++CONFIG_RADIO_WL1273=m ++CONFIG_USB_DSBR=m ++CONFIG_USB_KEENE=m ++CONFIG_USB_MA901=m ++CONFIG_USB_MR800=m ++CONFIG_RADIO_SI470X=m ++CONFIG_USB_SI470X=m ++CONFIG_I2C_SI470X=m ++CONFIG_I2C_SI4713=m ++CONFIG_RADIO_WL128X=m ++CONFIG_V4L_PLATFORM_DRIVERS=y ++CONFIG_VIDEO_MUX=m ++CONFIG_VIDEO_BCM2835_UNICAM=m ++CONFIG_VIDEO_RASPBERRYPI_PISP_BE=m ++CONFIG_VIDEO_RP1_CFE=m ++CONFIG_V4L_TEST_DRIVERS=y ++CONFIG_VIDEO_VIM2M=m ++CONFIG_VIDEO_VICODEC=m ++CONFIG_VIDEO_VIMC=m ++CONFIG_VIDEO_VIVID=m ++CONFIG_VIDEO_ARDUCAM_64MP=m ++CONFIG_VIDEO_ARDUCAM_PIVARIETY=m ++CONFIG_VIDEO_IMX219=m ++CONFIG_VIDEO_IMX258=m ++CONFIG_VIDEO_IMX290=m ++CONFIG_VIDEO_IMX296=m ++CONFIG_VIDEO_IMX477=m ++CONFIG_VIDEO_IMX519=m ++CONFIG_VIDEO_IMX708=m ++CONFIG_VIDEO_MT9V011=m ++CONFIG_VIDEO_OV2311=m ++CONFIG_VIDEO_OV5647=m ++CONFIG_VIDEO_OV64A40=m ++CONFIG_VIDEO_OV7251=m ++CONFIG_VIDEO_OV7640=m ++CONFIG_VIDEO_OV9282=m ++CONFIG_VIDEO_AD5398=m ++CONFIG_VIDEO_AK7375=m ++CONFIG_VIDEO_BU64754=m ++CONFIG_VIDEO_DW9807_VCM=m ++CONFIG_VIDEO_SONY_BTF_MPX=m ++CONFIG_VIDEO_UDA1342=m ++CONFIG_VIDEO_ADV7180=m ++CONFIG_VIDEO_TC358743=m ++CONFIG_VIDEO_TVP5150=m ++CONFIG_VIDEO_TW2804=m ++CONFIG_VIDEO_TW9903=m ++CONFIG_VIDEO_TW9906=m ++CONFIG_VIDEO_IRS1125=m ++CONFIG_VIDEO_I2C=m ++CONFIG_AUXDISPLAY=y ++CONFIG_HD44780=m ++CONFIG_DRM=m ++CONFIG_DRM_LOAD_EDID_FIRMWARE=y ++CONFIG_DRM_UDL=m ++CONFIG_DRM_PANEL_SIMPLE=m ++CONFIG_DRM_PANEL_ILITEK_ILI9806E=m ++CONFIG_DRM_PANEL_ILITEK_ILI9881C=m ++CONFIG_DRM_PANEL_JDI_LT070ME05000=m ++CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN=m ++CONFIG_DRM_PANEL_SITRONIX_ST7701=m ++CONFIG_DRM_PANEL_TPO_Y17P=m ++CONFIG_DRM_PANEL_WAVESHARE_TOUCHSCREEN=m ++CONFIG_DRM_DISPLAY_CONNECTOR=m ++CONFIG_DRM_SIMPLE_BRIDGE=m ++CONFIG_DRM_TOSHIBA_TC358762=m ++CONFIG_DRM_V3D=m ++CONFIG_DRM_VC4=m ++CONFIG_DRM_VC4_HDMI_CEC=y ++CONFIG_DRM_RP1_DSI=m ++CONFIG_DRM_RP1_DPI=m ++CONFIG_DRM_RP1_VEC=m ++CONFIG_DRM_PANEL_MIPI_DBI=m ++CONFIG_TINYDRM_HX8357D=m ++CONFIG_TINYDRM_ILI9225=m ++CONFIG_TINYDRM_ILI9341=m ++CONFIG_TINYDRM_ILI9486=m ++CONFIG_TINYDRM_MI0283QT=m ++CONFIG_TINYDRM_REPAPER=m ++CONFIG_TINYDRM_ST7586=m ++CONFIG_TINYDRM_ST7735R=m ++CONFIG_DRM_GUD=m ++CONFIG_FB=y ++CONFIG_FB_BCM2708=y ++CONFIG_FB_SIMPLE=y ++CONFIG_FB_SSD1307=m ++CONFIG_FB_RPISENSE=m ++CONFIG_BACKLIGHT_PWM=m ++CONFIG_BACKLIGHT_RPI=m ++CONFIG_BACKLIGHT_LM3630A=m ++CONFIG_BACKLIGHT_GPIO=m ++CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y ++CONFIG_LOGO=y ++# CONFIG_LOGO_LINUX_MONO is not set ++# CONFIG_LOGO_LINUX_VGA16 is not set ++CONFIG_SOUND=y ++CONFIG_SND=m ++CONFIG_SND_OSSEMUL=y ++CONFIG_SND_PCM_OSS=m ++CONFIG_SND_HRTIMER=m ++CONFIG_SND_DYNAMIC_MINORS=y ++CONFIG_SND_SEQUENCER=m ++CONFIG_SND_SEQ_DUMMY=m ++CONFIG_SND_DUMMY=m ++CONFIG_SND_ALOOP=m ++CONFIG_SND_VIRMIDI=m ++CONFIG_SND_MTPAV=m ++CONFIG_SND_SERIAL_U16550=m ++CONFIG_SND_MPU401=m ++CONFIG_SND_USB_AUDIO=m ++CONFIG_SND_USB_UA101=m ++CONFIG_SND_USB_CAIAQ=m ++CONFIG_SND_USB_CAIAQ_INPUT=y ++CONFIG_SND_USB_6FIRE=m ++CONFIG_SND_USB_HIFACE=m ++CONFIG_SND_USB_TONEPORT=m ++CONFIG_SND_SOC=m ++CONFIG_SND_BCM2835_SOC_I2S=m ++CONFIG_SND_BCM2708_SOC_CHIPDIP_DAC=m ++CONFIG_SND_BCM2708_SOC_GOOGLEVOICEHAT_SOUNDCARD=m ++CONFIG_SND_BCM2708_SOC_HIFIBERRY_DAC=m ++CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUS=m ++CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUSHD=m ++CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUSADC=m ++CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUSADCPRO=m ++CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUSDSP=m ++CONFIG_SND_BCM2708_SOC_HIFIBERRY_DIGI=m ++CONFIG_SND_BCM2708_SOC_HIFIBERRY_AMP=m ++CONFIG_SND_BCM2708_SOC_PIFI_40=m ++CONFIG_SND_BCM2708_SOC_RPI_CIRRUS=m ++CONFIG_SND_BCM2708_SOC_RPI_DAC=m ++CONFIG_SND_BCM2708_SOC_RPI_PROTO=m ++CONFIG_SND_BCM2708_SOC_JUSTBOOM_BOTH=m ++CONFIG_SND_BCM2708_SOC_JUSTBOOM_DAC=m ++CONFIG_SND_BCM2708_SOC_JUSTBOOM_DIGI=m ++CONFIG_SND_BCM2708_SOC_IQAUDIO_CODEC=m ++CONFIG_SND_BCM2708_SOC_IQAUDIO_DAC=m ++CONFIG_SND_BCM2708_SOC_IQAUDIO_DIGI=m ++CONFIG_SND_BCM2708_SOC_I_SABRE_Q2M=m ++CONFIG_SND_BCM2708_SOC_ADAU1977_ADC=m ++CONFIG_SND_AUDIOINJECTOR_PI_SOUNDCARD=m ++CONFIG_SND_AUDIOINJECTOR_OCTO_SOUNDCARD=m ++CONFIG_SND_AUDIOINJECTOR_ISOLATED_SOUNDCARD=m ++CONFIG_SND_AUDIOSENSE_PI=m ++CONFIG_SND_DIGIDAC1_SOUNDCARD=m ++CONFIG_SND_BCM2708_SOC_DIONAUDIO_LOCO=m ++CONFIG_SND_BCM2708_SOC_DIONAUDIO_LOCO_V2=m ++CONFIG_SND_BCM2708_SOC_ALLO_PIANO_DAC=m ++CONFIG_SND_BCM2708_SOC_ALLO_PIANO_DAC_PLUS=m ++CONFIG_SND_BCM2708_SOC_ALLO_BOSS_DAC=m ++CONFIG_SND_BCM2708_SOC_ALLO_BOSS2_DAC=m ++CONFIG_SND_BCM2708_SOC_ALLO_DIGIONE=m ++CONFIG_SND_BCM2708_SOC_ALLO_KATANA_DAC=m ++CONFIG_SND_BCM2708_SOC_FE_PI_AUDIO=m ++CONFIG_SND_PISOUND=m ++CONFIG_SND_DACBERRY400=m ++CONFIG_SND_DESIGNWARE_I2S=m ++CONFIG_SND_DESIGNWARE_PCM=y ++CONFIG_SND_SOC_AD193X_SPI=m ++CONFIG_SND_SOC_AD193X_I2C=m ++CONFIG_SND_SOC_ADAU1701=m ++CONFIG_SND_SOC_ADAU7002=m ++CONFIG_SND_SOC_AK4554=m ++CONFIG_SND_SOC_CS4265=m ++CONFIG_SND_SOC_ICS43432=m ++CONFIG_SND_SOC_MA120X0P=m ++CONFIG_SND_SOC_MAX98357A=m ++CONFIG_SND_SOC_SPDIF=m ++CONFIG_SND_SOC_TLV320AIC23_I2C=m ++CONFIG_SND_SOC_WM8804_I2C=m ++CONFIG_SND_SOC_WM8960=m ++CONFIG_SND_SIMPLE_CARD=m ++CONFIG_HID_BATTERY_STRENGTH=y ++CONFIG_HIDRAW=y ++CONFIG_UHID=m ++CONFIG_HID_A4TECH=m ++CONFIG_HID_ACRUX=m ++CONFIG_HID_APPLE=m ++CONFIG_HID_ASUS=m ++CONFIG_HID_BELKIN=m ++CONFIG_HID_BETOP_FF=m ++CONFIG_HID_BIGBEN_FF=m ++CONFIG_HID_CHERRY=m ++CONFIG_HID_CHICONY=m ++CONFIG_HID_CYPRESS=m ++CONFIG_HID_DRAGONRISE=m ++CONFIG_HID_EMS_FF=m ++CONFIG_HID_ELECOM=m ++CONFIG_HID_ELO=m ++CONFIG_HID_EZKEY=m ++CONFIG_HID_GEMBIRD=m ++CONFIG_HID_HOLTEK=m ++CONFIG_HID_KEYTOUCH=m ++CONFIG_HID_KYE=m ++CONFIG_HID_UCLOGIC=m ++CONFIG_HID_WALTOP=m ++CONFIG_HID_GYRATION=m ++CONFIG_HID_TWINHAN=m ++CONFIG_HID_KENSINGTON=m ++CONFIG_HID_LCPOWER=m ++CONFIG_HID_LOGITECH=m ++CONFIG_HID_LOGITECH_DJ=m ++CONFIG_LOGITECH_FF=y ++CONFIG_LOGIRUMBLEPAD2_FF=y ++CONFIG_LOGIG940_FF=y ++CONFIG_HID_MAGICMOUSE=m ++CONFIG_HID_MICROSOFT=m ++CONFIG_HID_MONTEREY=m ++CONFIG_HID_MULTITOUCH=m ++CONFIG_HID_NINTENDO=m ++CONFIG_NINTENDO_FF=y ++CONFIG_HID_NTRIG=m ++CONFIG_HID_ORTEK=m ++CONFIG_HID_PANTHERLORD=m ++CONFIG_HID_PETALYNX=m ++CONFIG_HID_PICOLCD=m ++CONFIG_HID_PLAYSTATION=m ++CONFIG_PLAYSTATION_FF=y ++CONFIG_HID_ROCCAT=m ++CONFIG_HID_SAMSUNG=m ++CONFIG_HID_SONY=m ++CONFIG_SONY_FF=y ++CONFIG_HID_SPEEDLINK=m ++CONFIG_HID_STEAM=m ++CONFIG_HID_SUNPLUS=m ++CONFIG_HID_GREENASIA=m ++CONFIG_HID_SMARTJOYPLUS=m ++CONFIG_HID_TOPSEED=m ++CONFIG_HID_THINGM=m ++CONFIG_HID_THRUSTMASTER=m ++CONFIG_HID_WACOM=m ++CONFIG_HID_WIIMOTE=m ++CONFIG_HID_XINMO=m ++CONFIG_HID_ZEROPLUS=m ++CONFIG_HID_ZYDACRON=m ++CONFIG_HID_PID=y ++CONFIG_USB_HIDDEV=y ++CONFIG_USB=y ++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y ++CONFIG_USB_MON=m ++CONFIG_USB_XHCI_HCD=y ++CONFIG_USB_DWCOTG=y ++CONFIG_USB_PRINTER=m ++CONFIG_USB_TMC=m ++CONFIG_USB_STORAGE=y ++CONFIG_USB_STORAGE_REALTEK=m ++CONFIG_USB_STORAGE_DATAFAB=m ++CONFIG_USB_STORAGE_FREECOM=m ++CONFIG_USB_STORAGE_ISD200=m ++CONFIG_USB_STORAGE_USBAT=m ++CONFIG_USB_STORAGE_SDDR09=m ++CONFIG_USB_STORAGE_SDDR55=m ++CONFIG_USB_STORAGE_JUMPSHOT=m ++CONFIG_USB_STORAGE_ALAUDA=m ++CONFIG_USB_STORAGE_ONETOUCH=m ++CONFIG_USB_STORAGE_KARMA=m ++CONFIG_USB_STORAGE_CYPRESS_ATACB=m ++CONFIG_USB_STORAGE_ENE_UB6250=m ++CONFIG_USB_UAS=y ++CONFIG_USB_MDC800=m ++CONFIG_USB_MICROTEK=m ++CONFIG_USBIP_CORE=m ++CONFIG_USBIP_VHCI_HCD=m ++CONFIG_USBIP_HOST=m ++CONFIG_USBIP_VUDC=m ++CONFIG_USB_DWC3=y ++CONFIG_USB_DWC2=m ++CONFIG_USB_SERIAL=m ++CONFIG_USB_SERIAL_GENERIC=y ++CONFIG_USB_SERIAL_AIRCABLE=m ++CONFIG_USB_SERIAL_ARK3116=m ++CONFIG_USB_SERIAL_BELKIN=m ++CONFIG_USB_SERIAL_CH341=m ++CONFIG_USB_SERIAL_WHITEHEAT=m ++CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m ++CONFIG_USB_SERIAL_CP210X=m ++CONFIG_USB_SERIAL_CYPRESS_M8=m ++CONFIG_USB_SERIAL_EMPEG=m ++CONFIG_USB_SERIAL_FTDI_SIO=m ++CONFIG_USB_SERIAL_VISOR=m ++CONFIG_USB_SERIAL_IPAQ=m ++CONFIG_USB_SERIAL_IR=m ++CONFIG_USB_SERIAL_EDGEPORT=m ++CONFIG_USB_SERIAL_EDGEPORT_TI=m ++CONFIG_USB_SERIAL_F81232=m ++CONFIG_USB_SERIAL_GARMIN=m ++CONFIG_USB_SERIAL_IPW=m ++CONFIG_USB_SERIAL_IUU=m ++CONFIG_USB_SERIAL_KEYSPAN_PDA=m ++CONFIG_USB_SERIAL_KEYSPAN=m ++CONFIG_USB_SERIAL_KLSI=m ++CONFIG_USB_SERIAL_KOBIL_SCT=m ++CONFIG_USB_SERIAL_MCT_U232=m ++CONFIG_USB_SERIAL_METRO=m ++CONFIG_USB_SERIAL_MOS7720=m ++CONFIG_USB_SERIAL_MOS7840=m ++CONFIG_USB_SERIAL_NAVMAN=m ++CONFIG_USB_SERIAL_PL2303=m ++CONFIG_USB_SERIAL_OTI6858=m ++CONFIG_USB_SERIAL_QCAUX=m ++CONFIG_USB_SERIAL_QUALCOMM=m ++CONFIG_USB_SERIAL_SPCP8X5=m ++CONFIG_USB_SERIAL_SAFE=m ++CONFIG_USB_SERIAL_SIERRAWIRELESS=m ++CONFIG_USB_SERIAL_SYMBOL=m ++CONFIG_USB_SERIAL_TI=m ++CONFIG_USB_SERIAL_CYBERJACK=m ++CONFIG_USB_SERIAL_OPTION=m ++CONFIG_USB_SERIAL_OMNINET=m ++CONFIG_USB_SERIAL_OPTICON=m ++CONFIG_USB_SERIAL_XSENS_MT=m ++CONFIG_USB_SERIAL_WISHBONE=m ++CONFIG_USB_SERIAL_SSU100=m ++CONFIG_USB_SERIAL_QT2=m ++CONFIG_USB_SERIAL_DEBUG=m ++CONFIG_USB_EMI62=m ++CONFIG_USB_EMI26=m ++CONFIG_USB_ADUTUX=m ++CONFIG_USB_SEVSEG=m ++CONFIG_USB_LEGOTOWER=m ++CONFIG_USB_LCD=m ++CONFIG_USB_CYPRESS_CY7C63=m ++CONFIG_USB_CYTHERM=m ++CONFIG_USB_IDMOUSE=m ++CONFIG_USB_APPLEDISPLAY=m ++CONFIG_USB_LD=m ++CONFIG_USB_TRANCEVIBRATOR=m ++CONFIG_USB_IOWARRIOR=m ++CONFIG_USB_TEST=m ++CONFIG_USB_ISIGHTFW=m ++CONFIG_USB_YUREX=m ++CONFIG_USB_ATM=m ++CONFIG_USB_SPEEDTOUCH=m ++CONFIG_USB_CXACRU=m ++CONFIG_USB_UEAGLEATM=m ++CONFIG_USB_XUSBATM=m ++CONFIG_NOP_USB_XCEIV=y ++CONFIG_USB_GADGET=y ++CONFIG_USB_CONFIGFS=m ++CONFIG_USB_CONFIGFS_SERIAL=y ++CONFIG_USB_CONFIGFS_ACM=y ++CONFIG_USB_CONFIGFS_OBEX=y ++CONFIG_USB_CONFIGFS_NCM=y ++CONFIG_USB_CONFIGFS_ECM=y ++CONFIG_USB_CONFIGFS_ECM_SUBSET=y ++CONFIG_USB_CONFIGFS_RNDIS=y ++CONFIG_USB_CONFIGFS_EEM=y ++CONFIG_USB_CONFIGFS_MASS_STORAGE=y ++CONFIG_USB_CONFIGFS_F_LB_SS=y ++CONFIG_USB_CONFIGFS_F_FS=y ++CONFIG_USB_CONFIGFS_F_UAC1=y ++CONFIG_USB_CONFIGFS_F_UAC2=y ++CONFIG_USB_CONFIGFS_F_MIDI=y ++CONFIG_USB_CONFIGFS_F_HID=y ++CONFIG_USB_CONFIGFS_F_UVC=y ++CONFIG_USB_CONFIGFS_F_PRINTER=y ++CONFIG_USB_ZERO=m ++CONFIG_USB_AUDIO=m ++CONFIG_USB_ETH=m ++CONFIG_USB_GADGETFS=m ++CONFIG_USB_MASS_STORAGE=m ++CONFIG_USB_G_SERIAL=m ++CONFIG_USB_MIDI_GADGET=m ++CONFIG_USB_G_PRINTER=m ++CONFIG_USB_CDC_COMPOSITE=m ++CONFIG_USB_G_ACM_MS=m ++CONFIG_USB_G_MULTI=m ++CONFIG_USB_G_HID=m ++CONFIG_USB_G_WEBCAM=m ++CONFIG_MMC=y ++CONFIG_MMC_BLOCK_MINORS=32 ++CONFIG_MMC_BCM2835_MMC=y ++CONFIG_MMC_BCM2835_DMA=y ++CONFIG_MMC_BCM2835_SDHOST=y ++CONFIG_MMC_SDHCI=y ++CONFIG_MMC_SDHCI_PLTFM=y ++CONFIG_MMC_SDHCI_OF_DWCMSHC=m ++CONFIG_MMC_SDHCI_IPROC=y ++CONFIG_MMC_SPI=m ++CONFIG_LEDS_CLASS=y ++CONFIG_LEDS_CLASS_MULTICOLOR=m ++CONFIG_LEDS_PCA9532=m ++CONFIG_LEDS_GPIO=y ++CONFIG_LEDS_PCA955X=m ++CONFIG_LEDS_PCA963X=m ++CONFIG_LEDS_PWM=y ++CONFIG_LEDS_IS31FL32XX=m ++CONFIG_LEDS_TRIGGER_TIMER=y ++CONFIG_LEDS_TRIGGER_ONESHOT=y ++CONFIG_LEDS_TRIGGER_HEARTBEAT=y ++CONFIG_LEDS_TRIGGER_BACKLIGHT=y ++CONFIG_LEDS_TRIGGER_CPU=y ++CONFIG_LEDS_TRIGGER_DEFAULT_ON=y ++CONFIG_LEDS_TRIGGER_TRANSIENT=m ++CONFIG_LEDS_TRIGGER_CAMERA=m ++CONFIG_LEDS_TRIGGER_INPUT=y ++CONFIG_LEDS_TRIGGER_PANIC=y ++CONFIG_LEDS_TRIGGER_NETDEV=m ++CONFIG_LEDS_TRIGGER_PATTERN=m ++CONFIG_LEDS_TRIGGER_ACTPWR=y ++CONFIG_ACCESSIBILITY=y ++CONFIG_SPEAKUP=m ++CONFIG_SPEAKUP_SYNTH_SOFT=m ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_DRV_ABX80X=m ++CONFIG_RTC_DRV_DS1307=m ++CONFIG_RTC_DRV_DS1374=m ++CONFIG_RTC_DRV_DS1672=m ++CONFIG_RTC_DRV_MAX6900=m ++CONFIG_RTC_DRV_RS5C372=m ++CONFIG_RTC_DRV_ISL1208=m ++CONFIG_RTC_DRV_ISL12022=m ++CONFIG_RTC_DRV_X1205=m ++CONFIG_RTC_DRV_PCF8523=m ++CONFIG_RTC_DRV_PCF85063=m ++CONFIG_RTC_DRV_PCF85363=m ++CONFIG_RTC_DRV_PCF8563=m ++CONFIG_RTC_DRV_PCF8583=m ++CONFIG_RTC_DRV_M41T80=m ++CONFIG_RTC_DRV_BQ32K=m ++CONFIG_RTC_DRV_S35390A=m ++CONFIG_RTC_DRV_FM3130=m ++CONFIG_RTC_DRV_RX8581=m ++CONFIG_RTC_DRV_RX8025=m ++CONFIG_RTC_DRV_EM3027=m ++CONFIG_RTC_DRV_RV3028=m ++CONFIG_RTC_DRV_RV3032=m ++CONFIG_RTC_DRV_RV8803=m ++CONFIG_RTC_DRV_SD3078=m ++CONFIG_RTC_DRV_M41T93=m ++CONFIG_RTC_DRV_M41T94=m ++CONFIG_RTC_DRV_DS1302=m ++CONFIG_RTC_DRV_DS1305=m ++CONFIG_RTC_DRV_DS1390=m ++CONFIG_RTC_DRV_R9701=m ++CONFIG_RTC_DRV_RX4581=m ++CONFIG_RTC_DRV_RS5C348=m ++CONFIG_RTC_DRV_MAX6902=m ++CONFIG_RTC_DRV_PCF2123=m ++CONFIG_RTC_DRV_DS3232=m ++CONFIG_RTC_DRV_PCF2127=m ++CONFIG_RTC_DRV_RV3029C2=m ++CONFIG_DMADEVICES=y ++CONFIG_DMA_BCM2835=y ++CONFIG_DW_AXI_DMAC=y ++CONFIG_DMA_BCM2708=y ++CONFIG_DMABUF_HEAPS=y ++CONFIG_DMABUF_HEAPS_SYSTEM=y ++CONFIG_DMABUF_HEAPS_CMA=y ++CONFIG_UIO=m ++CONFIG_UIO_PDRV_GENIRQ=m ++CONFIG_VHOST_NET=m ++CONFIG_VHOST_VSOCK=m ++CONFIG_VHOST_CROSS_ENDIAN_LEGACY=y ++CONFIG_STAGING=y ++CONFIG_PRISM2_USB=m ++CONFIG_R8712U=m ++CONFIG_VT6656=m ++CONFIG_STAGING_MEDIA=y ++CONFIG_VIDEO_RPIVID=m ++CONFIG_STAGING_MEDIA_DEPRECATED=y ++CONFIG_FB_TFT=m ++CONFIG_FB_TFT_AGM1264K_FL=m ++CONFIG_FB_TFT_BD663474=m ++CONFIG_FB_TFT_HX8340BN=m ++CONFIG_FB_TFT_HX8347D=m ++CONFIG_FB_TFT_HX8353D=m ++CONFIG_FB_TFT_HX8357D=m ++CONFIG_FB_TFT_ILI9163=m ++CONFIG_FB_TFT_ILI9320=m ++CONFIG_FB_TFT_ILI9325=m ++CONFIG_FB_TFT_ILI9340=m ++CONFIG_FB_TFT_ILI9341=m ++CONFIG_FB_TFT_ILI9481=m ++CONFIG_FB_TFT_ILI9486=m ++CONFIG_FB_TFT_PCD8544=m ++CONFIG_FB_TFT_RA8875=m ++CONFIG_FB_TFT_S6D02A1=m ++CONFIG_FB_TFT_S6D1121=m ++CONFIG_FB_TFT_SH1106=m ++CONFIG_FB_TFT_SSD1289=m ++CONFIG_FB_TFT_SSD1306=m ++CONFIG_FB_TFT_SSD1331=m ++CONFIG_FB_TFT_SSD1351=m ++CONFIG_FB_TFT_ST7735R=m ++CONFIG_FB_TFT_ST7789V=m ++CONFIG_FB_TFT_TINYLCD=m ++CONFIG_FB_TFT_TLS8204=m ++CONFIG_FB_TFT_UC1611=m ++CONFIG_FB_TFT_UC1701=m ++CONFIG_FB_TFT_UPD161704=m ++CONFIG_BCM2835_VCHIQ=y ++CONFIG_SND_BCM2835=m ++CONFIG_VIDEO_BCM2835=m ++CONFIG_VIDEO_CODEC_BCM2835=m ++CONFIG_VIDEO_ISP_BCM2835=m ++CONFIG_COMMON_CLK_RP1=y ++CONFIG_COMMON_CLK_RP1_SDIO=y ++CONFIG_CLK_RASPBERRYPI=y ++CONFIG_MAILBOX=y ++CONFIG_BCM2835_MBOX=y ++CONFIG_BCM2712_IOMMU=y ++CONFIG_RASPBERRYPI_POWER=y ++CONFIG_IIO=m ++CONFIG_IIO_BUFFER_CB=m ++CONFIG_IIO_SW_TRIGGER=m ++CONFIG_MCP320X=m ++CONFIG_MCP3422=m ++CONFIG_TI_ADS1015=m ++CONFIG_BME680=m ++CONFIG_CCS811=m ++CONFIG_SENSIRION_SGP30=m ++CONFIG_SPS30_I2C=m ++CONFIG_MAX30102=m ++CONFIG_DHT11=m ++CONFIG_HDC100X=m ++CONFIG_HTU21=m ++CONFIG_SI7020=m ++CONFIG_BOSCH_BNO055_I2C=m ++CONFIG_INV_MPU6050_I2C=m ++CONFIG_APDS9960=m ++CONFIG_BH1750=m ++CONFIG_TSL4531=m ++CONFIG_VEML6070=m ++CONFIG_IIO_HRTIMER_TRIGGER=m ++CONFIG_IIO_INTERRUPT_TRIGGER=m ++CONFIG_IIO_SYSFS_TRIGGER=m ++CONFIG_BMP280=m ++CONFIG_MS5637=m ++CONFIG_MAXIM_THERMOCOUPLE=m ++CONFIG_MAX31856=m ++CONFIG_PWM=y ++CONFIG_PWM_BCM2835=m ++CONFIG_PWM_BRCMSTB=y ++CONFIG_PWM_PCA9685=m ++CONFIG_PWM_RASPBERRYPI_POE=m ++CONFIG_PWM_RP1=y ++CONFIG_BCM2712_MIP=y ++CONFIG_RPI_AXIPERF=m ++CONFIG_ANDROID_BINDER_IPC=y ++CONFIG_ANDROID_BINDERFS=y ++CONFIG_NVMEM_RMEM=m ++CONFIG_MUX_GPIO=m ++CONFIG_EXT4_FS=y ++CONFIG_EXT4_FS_POSIX_ACL=y ++CONFIG_EXT4_FS_SECURITY=y ++CONFIG_REISERFS_FS=m ++CONFIG_REISERFS_FS_XATTR=y ++CONFIG_REISERFS_FS_POSIX_ACL=y ++CONFIG_REISERFS_FS_SECURITY=y ++CONFIG_JFS_FS=m ++CONFIG_JFS_POSIX_ACL=y ++CONFIG_JFS_SECURITY=y ++CONFIG_JFS_STATISTICS=y ++CONFIG_XFS_FS=m ++CONFIG_XFS_QUOTA=y ++CONFIG_XFS_POSIX_ACL=y ++CONFIG_XFS_RT=y ++CONFIG_GFS2_FS=m ++CONFIG_OCFS2_FS=m ++CONFIG_BTRFS_FS=m ++CONFIG_BTRFS_FS_POSIX_ACL=y ++CONFIG_NILFS2_FS=m ++CONFIG_F2FS_FS=y ++CONFIG_F2FS_FS_SECURITY=y ++CONFIG_FS_ENCRYPTION=y ++CONFIG_FANOTIFY=y ++CONFIG_QFMT_V1=m ++CONFIG_QFMT_V2=m ++CONFIG_AUTOFS_FS=y ++CONFIG_FUSE_FS=m ++CONFIG_CUSE=m ++CONFIG_OVERLAY_FS=m ++CONFIG_FSCACHE=y ++CONFIG_FSCACHE_STATS=y ++CONFIG_CACHEFILES=y ++CONFIG_ISO9660_FS=m ++CONFIG_JOLIET=y ++CONFIG_ZISOFS=y ++CONFIG_UDF_FS=m ++CONFIG_MSDOS_FS=y ++CONFIG_VFAT_FS=y ++CONFIG_FAT_DEFAULT_IOCHARSET="ascii" ++CONFIG_EXFAT_FS=m ++CONFIG_NTFS_FS=m ++CONFIG_NTFS_RW=y ++CONFIG_NTFS3_FS=m ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++CONFIG_ECRYPT_FS=m ++CONFIG_HFS_FS=m ++CONFIG_HFSPLUS_FS=m ++CONFIG_JFFS2_FS=m ++CONFIG_JFFS2_SUMMARY=y ++CONFIG_UBIFS_FS=m ++CONFIG_SQUASHFS=m ++CONFIG_SQUASHFS_XATTR=y ++CONFIG_SQUASHFS_LZO=y ++CONFIG_SQUASHFS_XZ=y ++CONFIG_PSTORE=y ++CONFIG_PSTORE_CONSOLE=y ++CONFIG_PSTORE_RAM=y ++CONFIG_NFS_FS=y ++CONFIG_NFS_V3_ACL=y ++CONFIG_NFS_V4=y ++CONFIG_NFS_SWAP=y ++CONFIG_NFS_V4_1=y ++CONFIG_NFS_V4_2=y ++CONFIG_ROOT_NFS=y ++CONFIG_NFS_FSCACHE=y ++CONFIG_NFSD=m ++CONFIG_NFSD_V2=y ++CONFIG_NFSD_V2_ACL=y ++CONFIG_NFSD_V3_ACL=y ++CONFIG_NFSD_V4=y ++CONFIG_CEPH_FS=m ++CONFIG_CIFS=m ++CONFIG_CIFS_UPCALL=y ++CONFIG_CIFS_XATTR=y ++CONFIG_CIFS_POSIX=y ++CONFIG_CIFS_DFS_UPCALL=y ++CONFIG_CIFS_FSCACHE=y ++CONFIG_SMB_SERVER=m ++CONFIG_9P_FS=m ++CONFIG_9P_FS_POSIX_ACL=y ++CONFIG_NLS_DEFAULT="utf8" ++CONFIG_NLS_CODEPAGE_437=y ++CONFIG_NLS_CODEPAGE_737=m ++CONFIG_NLS_CODEPAGE_775=m ++CONFIG_NLS_CODEPAGE_850=m ++CONFIG_NLS_CODEPAGE_852=m ++CONFIG_NLS_CODEPAGE_855=m ++CONFIG_NLS_CODEPAGE_857=m ++CONFIG_NLS_CODEPAGE_860=m ++CONFIG_NLS_CODEPAGE_861=m ++CONFIG_NLS_CODEPAGE_862=m ++CONFIG_NLS_CODEPAGE_863=m ++CONFIG_NLS_CODEPAGE_864=m ++CONFIG_NLS_CODEPAGE_865=m ++CONFIG_NLS_CODEPAGE_866=m ++CONFIG_NLS_CODEPAGE_869=m ++CONFIG_NLS_CODEPAGE_936=m ++CONFIG_NLS_CODEPAGE_950=m ++CONFIG_NLS_CODEPAGE_932=m ++CONFIG_NLS_CODEPAGE_949=m ++CONFIG_NLS_CODEPAGE_874=m ++CONFIG_NLS_ISO8859_8=m ++CONFIG_NLS_CODEPAGE_1250=m ++CONFIG_NLS_CODEPAGE_1251=m ++CONFIG_NLS_ASCII=y ++CONFIG_NLS_ISO8859_1=m ++CONFIG_NLS_ISO8859_2=m ++CONFIG_NLS_ISO8859_3=m ++CONFIG_NLS_ISO8859_4=m ++CONFIG_NLS_ISO8859_5=m ++CONFIG_NLS_ISO8859_6=m ++CONFIG_NLS_ISO8859_7=m ++CONFIG_NLS_ISO8859_9=m ++CONFIG_NLS_ISO8859_13=m ++CONFIG_NLS_ISO8859_14=m ++CONFIG_NLS_ISO8859_15=m ++CONFIG_NLS_KOI8_R=m ++CONFIG_NLS_KOI8_U=m ++CONFIG_DLM=m ++CONFIG_KEY_DH_OPERATIONS=y ++CONFIG_SECURITY=y ++CONFIG_SECURITY_APPARMOR=y ++CONFIG_LSM="" ++CONFIG_CRYPTO_USER=m ++CONFIG_CRYPTO_CRYPTD=m ++CONFIG_CRYPTO_AES=m ++CONFIG_CRYPTO_CAST5=m ++CONFIG_CRYPTO_DES=y ++CONFIG_CRYPTO_TWOFISH=m ++CONFIG_CRYPTO_ADIANTUM=m ++CONFIG_CRYPTO_CBC=m ++CONFIG_CRYPTO_CHACHA20POLY1305=m ++CONFIG_CRYPTO_MD4=m ++CONFIG_CRYPTO_SHA512=m ++CONFIG_CRYPTO_WP512=m ++CONFIG_CRYPTO_XCBC=m ++CONFIG_CRYPTO_LZ4=m ++CONFIG_CRYPTO_USER_API_HASH=m ++CONFIG_CRYPTO_USER_API_SKCIPHER=m ++CONFIG_CRYPTO_USER_API_RNG=m ++CONFIG_CRYPTO_USER_API_AEAD=m ++CONFIG_CRYPTO_GHASH_ARM64_CE=m ++CONFIG_CRYPTO_SHA1_ARM64_CE=m ++CONFIG_CRYPTO_SHA2_ARM64_CE=m ++CONFIG_CRYPTO_SHA512_ARM64_CE=m ++CONFIG_CRYPTO_SHA3_ARM64=m ++CONFIG_CRYPTO_SM3_ARM64_CE=m ++CONFIG_CRYPTO_AES_ARM64=m ++CONFIG_CRYPTO_AES_ARM64_CE_BLK=m ++CONFIG_CRYPTO_AES_ARM64_BS=m ++CONFIG_CRYPTO_SM4_ARM64_CE=m ++CONFIG_CRYPTO_AES_ARM64_CE_CCM=m ++# CONFIG_CRYPTO_HW is not set ++CONFIG_PKCS8_PRIVATE_KEY_PARSER=m ++CONFIG_CRC_ITU_T=y ++CONFIG_LIBCRC32C=y ++CONFIG_DMA_CMA=y ++CONFIG_CMA_SIZE_MBYTES=5 ++CONFIG_PRINTK_TIME=y ++CONFIG_BOOT_PRINTK_DELAY=y ++CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1f6 ++CONFIG_KGDB=y ++CONFIG_KGDB_KDB=y ++CONFIG_KDB_KEYBOARD=y ++CONFIG_DEBUG_MEMORY_INIT=y ++CONFIG_DETECT_HUNG_TASK=y ++CONFIG_LATENCYTOP=y ++CONFIG_FUNCTION_PROFILER=y ++CONFIG_STACK_TRACER=y ++CONFIG_SCHED_TRACER=y ++CONFIG_BLK_DEV_IO_TRACE=y ++# CONFIG_UPROBE_EVENTS is not set ++# CONFIG_STRICT_DEVMEM is not set +diff --git a/arch/arm64/configs/bcmrpi3_defconfig b/arch/arm64/configs/bcmrpi3_defconfig +new file mode 100644 +index 000000000000..ffa7195abfad +--- /dev/null ++++ b/arch/arm64/configs/bcmrpi3_defconfig +@@ -0,0 +1,1560 @@ ++CONFIG_LOCALVERSION="-v8" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_SYSVIPC=y ++CONFIG_POSIX_MQUEUE=y ++CONFIG_NO_HZ=y ++CONFIG_HIGH_RES_TIMERS=y ++CONFIG_BPF_SYSCALL=y ++CONFIG_PREEMPT=y ++CONFIG_BSD_PROCESS_ACCT=y ++CONFIG_BSD_PROCESS_ACCT_V3=y ++CONFIG_TASKSTATS=y ++CONFIG_TASK_DELAY_ACCT=y ++CONFIG_TASK_XACCT=y ++CONFIG_TASK_IO_ACCOUNTING=y ++CONFIG_PSI=y ++CONFIG_PSI_DEFAULT_DISABLED=y ++CONFIG_IKCONFIG=m ++CONFIG_IKCONFIG_PROC=y ++CONFIG_MEMCG=y ++CONFIG_BLK_CGROUP=y ++CONFIG_CFS_BANDWIDTH=y ++CONFIG_CGROUP_PIDS=y ++CONFIG_CGROUP_FREEZER=y ++CONFIG_CPUSETS=y ++CONFIG_CGROUP_DEVICE=y ++CONFIG_CGROUP_CPUACCT=y ++CONFIG_CGROUP_PERF=y ++CONFIG_CGROUP_BPF=y ++CONFIG_NAMESPACES=y ++CONFIG_USER_NS=y ++CONFIG_SCHED_AUTOGROUP=y ++CONFIG_BLK_DEV_INITRD=y ++CONFIG_EXPERT=y ++CONFIG_PROFILING=y ++CONFIG_ARCH_BCM=y ++CONFIG_ARCH_BCM2835=y ++# CONFIG_CAVIUM_ERRATUM_22375 is not set ++# CONFIG_CAVIUM_ERRATUM_23154 is not set ++# CONFIG_CAVIUM_ERRATUM_27456 is not set ++CONFIG_SCHED_MC=y ++CONFIG_NR_CPUS=4 ++CONFIG_HZ_1000=y ++CONFIG_COMPAT=y ++CONFIG_ARMV8_DEPRECATED=y ++CONFIG_SWP_EMULATION=y ++CONFIG_CP15_BARRIER_EMULATION=y ++CONFIG_SETEND_EMULATION=y ++CONFIG_RANDOMIZE_BASE=y ++CONFIG_CMDLINE="console=ttyAMA0,115200 kgdboc=ttyAMA0,115200 root=/dev/mmcblk0p2 rootfstype=ext4 rootwait" ++# CONFIG_SUSPEND is not set ++CONFIG_PM=y ++CONFIG_CPU_IDLE=y ++CONFIG_CPU_FREQ=y ++CONFIG_CPU_FREQ_STAT=y ++CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE=y ++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y ++CONFIG_CPU_FREQ_GOV_USERSPACE=y ++CONFIG_CPU_FREQ_GOV_ONDEMAND=y ++CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y ++CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y ++CONFIG_CPUFREQ_DT=y ++CONFIG_ARM_RASPBERRYPI_CPUFREQ=y ++CONFIG_JUMP_LABEL=y ++CONFIG_MODULES=y ++CONFIG_MODULE_UNLOAD=y ++CONFIG_MODVERSIONS=y ++CONFIG_MODULE_SRCVERSION_ALL=y ++CONFIG_MODULE_COMPRESS_XZ=y ++CONFIG_PARTITION_ADVANCED=y ++CONFIG_MAC_PARTITION=y ++CONFIG_BINFMT_MISC=y ++CONFIG_ZSWAP=y ++CONFIG_Z3FOLD=m ++# CONFIG_COMPAT_BRK is not set ++CONFIG_CMA=y ++CONFIG_LRU_GEN=y ++CONFIG_LRU_GEN_ENABLED=y ++CONFIG_NET=y ++CONFIG_PACKET=y ++CONFIG_XFRM_USER=y ++CONFIG_XFRM_INTERFACE=m ++CONFIG_XFRM_SUB_POLICY=y ++CONFIG_XFRM_STATISTICS=y ++CONFIG_NET_KEY=m ++CONFIG_IP_MULTICAST=y ++CONFIG_IP_ADVANCED_ROUTER=y ++CONFIG_IP_MULTIPLE_TABLES=y ++CONFIG_IP_ROUTE_MULTIPATH=y ++CONFIG_IP_ROUTE_VERBOSE=y ++CONFIG_IP_PNP=y ++CONFIG_IP_PNP_DHCP=y ++CONFIG_IP_PNP_RARP=y ++CONFIG_NET_IPIP=m ++CONFIG_NET_IPGRE_DEMUX=m ++CONFIG_NET_IPGRE=m ++CONFIG_IP_MROUTE=y ++CONFIG_IP_MROUTE_MULTIPLE_TABLES=y ++CONFIG_IP_PIMSM_V1=y ++CONFIG_IP_PIMSM_V2=y ++CONFIG_NET_FOU=m ++CONFIG_INET_AH=m ++CONFIG_INET_ESP=m ++CONFIG_INET_IPCOMP=m ++CONFIG_INET_DIAG=m ++CONFIG_TCP_CONG_ADVANCED=y ++CONFIG_TCP_CONG_BBR=m ++CONFIG_IPV6=m ++CONFIG_IPV6_ROUTER_PREF=y ++CONFIG_INET6_AH=m ++CONFIG_INET6_ESP=m ++CONFIG_INET6_ESP_OFFLOAD=m ++CONFIG_INET6_IPCOMP=m ++CONFIG_IPV6_ILA=m ++CONFIG_IPV6_VTI=m ++CONFIG_IPV6_GRE=m ++CONFIG_IPV6_MULTIPLE_TABLES=y ++CONFIG_IPV6_SUBTREES=y ++CONFIG_IPV6_MROUTE=y ++CONFIG_IPV6_MROUTE_MULTIPLE_TABLES=y ++CONFIG_IPV6_PIMSM_V2=y ++CONFIG_MPTCP=y ++CONFIG_NETFILTER=y ++CONFIG_BRIDGE_NETFILTER=m ++CONFIG_NF_CONNTRACK=m ++CONFIG_NF_CONNTRACK_ZONES=y ++CONFIG_NF_CONNTRACK_EVENTS=y ++CONFIG_NF_CONNTRACK_TIMESTAMP=y ++CONFIG_NF_CONNTRACK_AMANDA=m ++CONFIG_NF_CONNTRACK_FTP=m ++CONFIG_NF_CONNTRACK_H323=m ++CONFIG_NF_CONNTRACK_IRC=m ++CONFIG_NF_CONNTRACK_NETBIOS_NS=m ++CONFIG_NF_CONNTRACK_SNMP=m ++CONFIG_NF_CONNTRACK_PPTP=m ++CONFIG_NF_CONNTRACK_SANE=m ++CONFIG_NF_CONNTRACK_SIP=m ++CONFIG_NF_CONNTRACK_TFTP=m ++CONFIG_NF_CT_NETLINK=m ++CONFIG_NF_TABLES=m ++CONFIG_NF_TABLES_INET=y ++CONFIG_NF_TABLES_NETDEV=y ++CONFIG_NFT_NUMGEN=m ++CONFIG_NFT_CT=m ++CONFIG_NFT_FLOW_OFFLOAD=m ++CONFIG_NFT_CONNLIMIT=m ++CONFIG_NFT_LOG=m ++CONFIG_NFT_LIMIT=m ++CONFIG_NFT_MASQ=m ++CONFIG_NFT_REDIR=m ++CONFIG_NFT_NAT=m ++CONFIG_NFT_TUNNEL=m ++CONFIG_NFT_QUEUE=m ++CONFIG_NFT_QUOTA=m ++CONFIG_NFT_REJECT=m ++CONFIG_NFT_COMPAT=m ++CONFIG_NFT_HASH=m ++CONFIG_NFT_FIB_INET=m ++CONFIG_NFT_XFRM=m ++CONFIG_NFT_SOCKET=m ++CONFIG_NFT_OSF=m ++CONFIG_NFT_TPROXY=m ++CONFIG_NFT_SYNPROXY=m ++CONFIG_NFT_DUP_NETDEV=m ++CONFIG_NFT_FWD_NETDEV=m ++CONFIG_NFT_FIB_NETDEV=m ++CONFIG_NF_FLOW_TABLE_INET=m ++CONFIG_NF_FLOW_TABLE=m ++CONFIG_NETFILTER_XTABLES_COMPAT=y ++CONFIG_NETFILTER_XT_SET=m ++CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m ++CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m ++CONFIG_NETFILTER_XT_TARGET_CONNMARK=m ++CONFIG_NETFILTER_XT_TARGET_DSCP=m ++CONFIG_NETFILTER_XT_TARGET_HMARK=m ++CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m ++CONFIG_NETFILTER_XT_TARGET_LED=m ++CONFIG_NETFILTER_XT_TARGET_LOG=m ++CONFIG_NETFILTER_XT_TARGET_MARK=m ++CONFIG_NETFILTER_XT_TARGET_NFLOG=m ++CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m ++CONFIG_NETFILTER_XT_TARGET_NOTRACK=m ++CONFIG_NETFILTER_XT_TARGET_TEE=m ++CONFIG_NETFILTER_XT_TARGET_TPROXY=m ++CONFIG_NETFILTER_XT_TARGET_TRACE=m ++CONFIG_NETFILTER_XT_TARGET_TCPMSS=m ++CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m ++CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m ++CONFIG_NETFILTER_XT_MATCH_BPF=m ++CONFIG_NETFILTER_XT_MATCH_CLUSTER=m ++CONFIG_NETFILTER_XT_MATCH_COMMENT=m ++CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m ++CONFIG_NETFILTER_XT_MATCH_CONNLABEL=m ++CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m ++CONFIG_NETFILTER_XT_MATCH_CONNMARK=m ++CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m ++CONFIG_NETFILTER_XT_MATCH_CPU=m ++CONFIG_NETFILTER_XT_MATCH_DCCP=m ++CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m ++CONFIG_NETFILTER_XT_MATCH_DSCP=m ++CONFIG_NETFILTER_XT_MATCH_ESP=m ++CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m ++CONFIG_NETFILTER_XT_MATCH_HELPER=m ++CONFIG_NETFILTER_XT_MATCH_IPRANGE=m ++CONFIG_NETFILTER_XT_MATCH_IPVS=m ++CONFIG_NETFILTER_XT_MATCH_LENGTH=m ++CONFIG_NETFILTER_XT_MATCH_LIMIT=m ++CONFIG_NETFILTER_XT_MATCH_MAC=m ++CONFIG_NETFILTER_XT_MATCH_MARK=m ++CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m ++CONFIG_NETFILTER_XT_MATCH_NFACCT=m ++CONFIG_NETFILTER_XT_MATCH_OSF=m ++CONFIG_NETFILTER_XT_MATCH_OWNER=m ++CONFIG_NETFILTER_XT_MATCH_POLICY=m ++CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m ++CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m ++CONFIG_NETFILTER_XT_MATCH_QUOTA=m ++CONFIG_NETFILTER_XT_MATCH_RATEEST=m ++CONFIG_NETFILTER_XT_MATCH_REALM=m ++CONFIG_NETFILTER_XT_MATCH_RECENT=m ++CONFIG_NETFILTER_XT_MATCH_SOCKET=m ++CONFIG_NETFILTER_XT_MATCH_STATE=m ++CONFIG_NETFILTER_XT_MATCH_STATISTIC=m ++CONFIG_NETFILTER_XT_MATCH_STRING=m ++CONFIG_NETFILTER_XT_MATCH_TCPMSS=m ++CONFIG_NETFILTER_XT_MATCH_TIME=m ++CONFIG_NETFILTER_XT_MATCH_U32=m ++CONFIG_IP_SET=m ++CONFIG_IP_SET_BITMAP_IP=m ++CONFIG_IP_SET_BITMAP_IPMAC=m ++CONFIG_IP_SET_BITMAP_PORT=m ++CONFIG_IP_SET_HASH_IP=m ++CONFIG_IP_SET_HASH_IPPORT=m ++CONFIG_IP_SET_HASH_IPPORTIP=m ++CONFIG_IP_SET_HASH_IPPORTNET=m ++CONFIG_IP_SET_HASH_NET=m ++CONFIG_IP_SET_HASH_NETPORT=m ++CONFIG_IP_SET_HASH_NETIFACE=m ++CONFIG_IP_SET_LIST_SET=m ++CONFIG_IP_VS=m ++CONFIG_IP_VS_IPV6=y ++CONFIG_IP_VS_PROTO_TCP=y ++CONFIG_IP_VS_PROTO_UDP=y ++CONFIG_IP_VS_PROTO_ESP=y ++CONFIG_IP_VS_PROTO_AH=y ++CONFIG_IP_VS_PROTO_SCTP=y ++CONFIG_IP_VS_RR=m ++CONFIG_IP_VS_WRR=m ++CONFIG_IP_VS_LC=m ++CONFIG_IP_VS_WLC=m ++CONFIG_IP_VS_LBLC=m ++CONFIG_IP_VS_LBLCR=m ++CONFIG_IP_VS_DH=m ++CONFIG_IP_VS_SH=m ++CONFIG_IP_VS_SED=m ++CONFIG_IP_VS_NQ=m ++CONFIG_IP_VS_FTP=m ++CONFIG_IP_VS_PE_SIP=m ++CONFIG_NFT_DUP_IPV4=m ++CONFIG_NFT_FIB_IPV4=m ++CONFIG_NF_TABLES_ARP=y ++CONFIG_NF_LOG_ARP=m ++CONFIG_NF_LOG_IPV4=m +CONFIG_IP_NF_IPTABLES=m +CONFIG_IP_NF_MATCH_AH=m +CONFIG_IP_NF_MATCH_ECN=m @@ -44736,7 +61934,6 @@ index 000000000000..419813140a52 +CONFIG_IP_NF_TARGET_NETMAP=m +CONFIG_IP_NF_TARGET_REDIRECT=m +CONFIG_IP_NF_MANGLE=m -+CONFIG_IP_NF_TARGET_CLUSTERIP=m +CONFIG_IP_NF_TARGET_ECN=m +CONFIG_IP_NF_TARGET_TTL=m +CONFIG_IP_NF_RAW=m @@ -44745,7 +61942,6 @@ index 000000000000..419813140a52 +CONFIG_IP_NF_ARP_MANGLE=m +CONFIG_NFT_DUP_IPV6=m +CONFIG_NFT_FIB_IPV6=m -+CONFIG_NF_FLOW_TABLE_IPV6=m +CONFIG_IP6_NF_IPTABLES=m +CONFIG_IP6_NF_MATCH_AH=m +CONFIG_IP6_NF_MATCH_EUI64=m @@ -44769,7 +61965,6 @@ index 000000000000..419813140a52 +CONFIG_IP6_NF_TARGET_NPT=m +CONFIG_NF_TABLES_BRIDGE=m +CONFIG_NFT_BRIDGE_REJECT=m -+CONFIG_NF_LOG_BRIDGE=m +CONFIG_BRIDGE_NF_EBTABLES=m +CONFIG_BRIDGE_EBT_BROUTE=m +CONFIG_BRIDGE_EBT_T_FILTER=m @@ -44806,7 +62001,6 @@ index 000000000000..419813140a52 +CONFIG_IEEE802154_6LOWPAN=m +CONFIG_MAC802154=m +CONFIG_NET_SCHED=y -+CONFIG_NET_SCH_CBQ=m +CONFIG_NET_SCH_HTB=m +CONFIG_NET_SCH_HFSC=m +CONFIG_NET_SCH_PRIO=m @@ -44817,7 +62011,6 @@ index 000000000000..419813140a52 +CONFIG_NET_SCH_TEQL=m +CONFIG_NET_SCH_TBF=m +CONFIG_NET_SCH_GRED=m -+CONFIG_NET_SCH_DSMARK=m +CONFIG_NET_SCH_NETEM=m +CONFIG_NET_SCH_DRR=m +CONFIG_NET_SCH_MQPRIO=m @@ -44830,13 +62023,10 @@ index 000000000000..419813140a52 +CONFIG_NET_SCH_INGRESS=m +CONFIG_NET_SCH_PLUG=m +CONFIG_NET_CLS_BASIC=m -+CONFIG_NET_CLS_TCINDEX=m +CONFIG_NET_CLS_ROUTE4=m +CONFIG_NET_CLS_FW=m +CONFIG_NET_CLS_U32=m +CONFIG_CLS_U32_MARK=y -+CONFIG_NET_CLS_RSVP=m -+CONFIG_NET_CLS_RSVP6=m +CONFIG_NET_CLS_FLOW=m +CONFIG_NET_CLS_CGROUP=m +CONFIG_NET_EMATCH=y @@ -44875,11 +62065,6 @@ index 000000000000..419813140a52 +CONFIG_CAN=m +CONFIG_CAN_J1939=m +CONFIG_CAN_ISOTP=m -+CONFIG_CAN_VCAN=m -+CONFIG_CAN_MCP251X=m -+CONFIG_CAN_MCP251XFD=m -+CONFIG_CAN_EMS_USB=m -+CONFIG_CAN_PEAK_USB=m +CONFIG_BT=m +CONFIG_BT_RFCOMM=m +CONFIG_BT_RFCOMM_TTY=y @@ -44903,7 +62088,6 @@ index 000000000000..419813140a52 +CONFIG_CFG80211_WEXT=y +CONFIG_MAC80211=m +CONFIG_MAC80211_MESH=y -+CONFIG_WIMAX=m +CONFIG_RFKILL=m +CONFIG_RFKILL_INPUT=y +CONFIG_NET_9P=m @@ -44911,19 +62095,21 @@ index 000000000000..419813140a52 +CONFIG_UEVENT_HELPER=y +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y ++CONFIG_RASPBERRYPI_FIRMWARE=y ++# CONFIG_EFI_VARS_PSTORE is not set +CONFIG_MTD=m +CONFIG_MTD_BLOCK=m ++CONFIG_MTD_SPI_NAND=m +CONFIG_MTD_UBI=m +CONFIG_OF_CONFIGFS=y +CONFIG_ZRAM=m +CONFIG_BLK_DEV_LOOP=y -+CONFIG_BLK_DEV_CRYPTOLOOP=m +CONFIG_BLK_DEV_DRBD=m +CONFIG_BLK_DEV_NBD=m +CONFIG_BLK_DEV_RAM=y -+CONFIG_CDROM_PKTCDVD=m +CONFIG_ATA_OVER_ETH=m +CONFIG_EEPROM_AT24=m ++CONFIG_EEPROM_AT25=m +CONFIG_TI_ST=m +CONFIG_SCSI=y +# CONFIG_SCSI_PROC_FS is not set @@ -44934,6 +62120,7 @@ index 000000000000..419813140a52 +CONFIG_SCSI_ISCSI_ATTRS=y +CONFIG_ISCSI_TCP=m +CONFIG_ISCSI_BOOT_SYSFS=m ++CONFIG_ATA=m +CONFIG_MD=y +CONFIG_MD_LINEAR=m +CONFIG_BLK_DEV_DM=m @@ -44945,7 +62132,9 @@ index 000000000000..419813140a52 +CONFIG_DM_LOG_USERSPACE=m +CONFIG_DM_RAID=m +CONFIG_DM_ZERO=m ++CONFIG_DM_MULTIPATH=m +CONFIG_DM_DELAY=m ++CONFIG_DM_INTEGRITY=m +CONFIG_NETDEVICES=y +CONFIG_BONDING=m +CONFIG_DUMMY=m @@ -44965,6 +62154,12 @@ index 000000000000..419813140a52 +CONFIG_QCA7000_UART=m +CONFIG_WIZNET_W5100=m +CONFIG_WIZNET_W5100_SPI=m ++CONFIG_CAN_VCAN=m ++CONFIG_CAN_MCP251X=m ++CONFIG_CAN_MCP251XFD=m ++CONFIG_CAN_8DEV_USB=m ++CONFIG_CAN_EMS_USB=m ++CONFIG_CAN_PEAK_USB=m +CONFIG_MDIO_BITBANG=m +CONFIG_PPP=m +CONFIG_PPP_BSDCOMP=m @@ -45043,6 +62238,7 @@ index 000000000000..419813140a52 +CONFIG_MT7601U=m +CONFIG_MT76x0U=m +CONFIG_MT76x2U=m ++CONFIG_MT7921U=m +CONFIG_RT2X00=m +CONFIG_RT2500USB=m +CONFIG_RT73USB=m @@ -45053,11 +62249,15 @@ index 000000000000..419813140a52 +CONFIG_RT2800USB_UNKNOWN=y +CONFIG_RTL8187=m +CONFIG_RTL8192CU=m ++CONFIG_RTW88=m ++CONFIG_RTW88_8822BU=m ++CONFIG_RTW88_8822CU=m ++CONFIG_RTW88_8723DU=m ++CONFIG_RTW88_8821CU=m +CONFIG_USB_ZD1201=m +CONFIG_ZD1211RW=m -+CONFIG_MAC80211_HWSIM=m +CONFIG_USB_NET_RNDIS_WLAN=m -+CONFIG_WIMAX_I2400M_USB=m ++CONFIG_MAC80211_HWSIM=m +CONFIG_IEEE802154_AT86RF230=m +CONFIG_IEEE802154_MRF24J40=m +CONFIG_IEEE802154_CC2520=m @@ -45076,15 +62276,24 @@ index 000000000000..419813140a52 +CONFIG_JOYSTICK_XPAD=m +CONFIG_JOYSTICK_XPAD_FF=y +CONFIG_JOYSTICK_XPAD_LEDS=y ++CONFIG_JOYSTICK_PSXPAD_SPI=m ++CONFIG_JOYSTICK_PSXPAD_SPI_FF=y ++CONFIG_JOYSTICK_FSIA6B=m +CONFIG_JOYSTICK_RPISENSE=m +CONFIG_INPUT_TOUCHSCREEN=y +CONFIG_TOUCHSCREEN_ADS7846=m +CONFIG_TOUCHSCREEN_EGALAX=m ++CONFIG_TOUCHSCREEN_EXC3000=m ++CONFIG_TOUCHSCREEN_GOODIX=m +CONFIG_TOUCHSCREEN_ILI210X=m +CONFIG_TOUCHSCREEN_EKTF2127=m ++CONFIG_TOUCHSCREEN_EDT_FT5X06=m +CONFIG_TOUCHSCREEN_RASPBERRYPI_FW=m +CONFIG_TOUCHSCREEN_USB_COMPOSITE=m ++CONFIG_TOUCHSCREEN_TSC2007=m ++CONFIG_TOUCHSCREEN_TSC2007_IIO=y +CONFIG_TOUCHSCREEN_STMPE=m ++CONFIG_TOUCHSCREEN_IQS5XX=m +CONFIG_INPUT_MISC=y +CONFIG_INPUT_AD714X=m +CONFIG_INPUT_ATI_REMOTE2=m @@ -45099,12 +62308,8 @@ index 000000000000..419813140a52 +CONFIG_SERIO=m +CONFIG_SERIO_RAW=m +CONFIG_GAMEPORT=m -+CONFIG_GAMEPORT_NS558=m -+CONFIG_GAMEPORT_L4=m +CONFIG_BRCM_CHAR_DRIVERS=y +CONFIG_BCM_VCIO=y -+CONFIG_BCM2835_DEVGPIOMEM=y -+# CONFIG_BCM2835_SMI_DEV is not set +# CONFIG_LEGACY_PTYS is not set +CONFIG_SERIAL_8250=y +# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set @@ -45123,39 +62328,43 @@ index 000000000000..419813140a52 +CONFIG_SERIAL_DEV_BUS=y +CONFIG_TTY_PRINTK=y +CONFIG_HW_RANDOM=y -+CONFIG_RAW_DRIVER=y +CONFIG_TCG_TPM=m +CONFIG_TCG_TIS_SPI=m -+CONFIG_RANDOM_TRUST_BOOTLOADER=y ++CONFIG_TCG_TIS_I2C=m ++CONFIG_RASPBERRYPI_GPIOMEM=m +CONFIG_I2C=y +CONFIG_I2C_CHARDEV=m -+CONFIG_I2C_MUX=m +CONFIG_I2C_MUX_GPMUX=m +CONFIG_I2C_MUX_PCA954x=m +CONFIG_I2C_MUX_PINCTRL=m +CONFIG_I2C_BCM2708=m +CONFIG_I2C_BCM2835=m -+# CONFIG_I2C_BRCMSTB is not set +CONFIG_I2C_GPIO=m ++CONFIG_I2C_ROBOTFUZZ_OSIF=m ++CONFIG_I2C_TINY_USB=m +CONFIG_SPI=y +CONFIG_SPI_BCM2835=m +CONFIG_SPI_BCM2835AUX=m -+CONFIG_SPI_SPIDEV=y -+CONFIG_PPS=m ++CONFIG_SPI_GPIO=m ++CONFIG_SPI_SPIDEV=m ++CONFIG_SPI_SLAVE=y +CONFIG_PPS_CLIENT_LDISC=m +CONFIG_PPS_CLIENT_GPIO=m ++CONFIG_PINCTRL_MCP23S08=m +CONFIG_GPIO_SYSFS=y +CONFIG_GPIO_BCM_VIRT=y ++CONFIG_GPIO_MAX7300=m +CONFIG_GPIO_PCA953X=m +CONFIG_GPIO_PCA953X_IRQ=y ++CONFIG_GPIO_PCF857X=m +CONFIG_GPIO_ARIZONA=m +CONFIG_GPIO_FSM=m +CONFIG_GPIO_STMPE=y ++CONFIG_GPIO_MAX7301=m +CONFIG_GPIO_MOCKUP=m +CONFIG_W1=m +CONFIG_W1_MASTER_DS2490=m +CONFIG_W1_MASTER_DS2482=m -+CONFIG_W1_MASTER_DS1WM=m +CONFIG_W1_MASTER_GPIO=m +CONFIG_W1_SLAVE_THERM=m +CONFIG_W1_SLAVE_SMEM=m @@ -45165,6 +62374,7 @@ index 000000000000..419813140a52 +CONFIG_W1_SLAVE_DS2423=m +CONFIG_W1_SLAVE_DS2431=m +CONFIG_W1_SLAVE_DS2433=m ++CONFIG_W1_SLAVE_DS2438=m +CONFIG_W1_SLAVE_DS2780=m +CONFIG_W1_SLAVE_DS2781=m +CONFIG_W1_SLAVE_DS28E04=m @@ -45173,58 +62383,74 @@ index 000000000000..419813140a52 +CONFIG_RPI_POE_POWER=m +CONFIG_BATTERY_DS2760=m +CONFIG_BATTERY_MAX17040=m ++CONFIG_CHARGER_GPIO=m ++CONFIG_BATTERY_GAUGE_LTC2941=m ++CONFIG_SENSORS_ADT7410=m ++CONFIG_SENSORS_AHT10=m ++CONFIG_SENSORS_DRIVETEMP=m ++CONFIG_SENSORS_DS1621=m ++CONFIG_SENSORS_GPIO_FAN=m +CONFIG_SENSORS_IIO_HWMON=m ++CONFIG_SENSORS_JC42=m +CONFIG_SENSORS_LM75=m ++CONFIG_SENSORS_PWM_FAN=m +CONFIG_SENSORS_RASPBERRYPI_HWMON=m -+CONFIG_SENSORS_RPI_POE_FAN=m +CONFIG_SENSORS_SHT21=m ++CONFIG_SENSORS_SHT3x=m ++CONFIG_SENSORS_SHT4x=m +CONFIG_SENSORS_SHTC1=m ++CONFIG_SENSORS_EMC2305=m +CONFIG_SENSORS_INA2XX=m -+CONFIG_THERMAL=y ++CONFIG_SENSORS_TMP102=m +CONFIG_BCM2835_THERMAL=y +CONFIG_WATCHDOG=y ++CONFIG_GPIO_WATCHDOG=m +CONFIG_BCM2835_WDT=y ++CONFIG_MFD_RASPBERRYPI_POE_HAT=m +CONFIG_MFD_STMPE=y +CONFIG_STMPE_SPI=y ++CONFIG_MFD_SYSCON=y +CONFIG_MFD_ARIZONA_I2C=m +CONFIG_MFD_ARIZONA_SPI=m +CONFIG_MFD_WM5102=y +CONFIG_REGULATOR=y ++CONFIG_REGULATOR_FIXED_VOLTAGE=y ++CONFIG_REGULATOR_ARIZONA_LDO1=m ++CONFIG_REGULATOR_ARIZONA_MICSUPP=m ++CONFIG_REGULATOR_GPIO=y +CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_ATTINY=m ++CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_V2=m +CONFIG_RC_CORE=y -+CONFIG_LIRC=y +CONFIG_BPF_LIRC_MODE2=y ++CONFIG_LIRC=y +CONFIG_RC_DECODERS=y ++CONFIG_IR_IMON_DECODER=m ++CONFIG_IR_JVC_DECODER=m ++CONFIG_IR_MCE_KBD_DECODER=m +CONFIG_IR_NEC_DECODER=m +CONFIG_IR_RC5_DECODER=m +CONFIG_IR_RC6_DECODER=m -+CONFIG_IR_JVC_DECODER=m -+CONFIG_IR_SONY_DECODER=m +CONFIG_IR_SANYO_DECODER=m +CONFIG_IR_SHARP_DECODER=m -+CONFIG_IR_MCE_KBD_DECODER=m ++CONFIG_IR_SONY_DECODER=m +CONFIG_IR_XMP_DECODER=m -+CONFIG_IR_IMON_DECODER=m +CONFIG_RC_DEVICES=y -+CONFIG_RC_ATI_REMOTE=m -+CONFIG_IR_IMON=m -+CONFIG_IR_MCEUSB=m -+CONFIG_IR_REDRAT3=m -+CONFIG_IR_STREAMZAP=m -+CONFIG_IR_IGUANA=m -+CONFIG_IR_TTUSBIR=m -+CONFIG_RC_LOOPBACK=m +CONFIG_IR_GPIO_CIR=m +CONFIG_IR_GPIO_TX=m ++CONFIG_IR_IGUANA=m ++CONFIG_IR_IMON=m ++CONFIG_IR_MCEUSB=m +CONFIG_IR_PWM_TX=m ++CONFIG_IR_REDRAT3=m ++CONFIG_IR_STREAMZAP=m +CONFIG_IR_TOY=m ++CONFIG_IR_TTUSBIR=m ++CONFIG_RC_ATI_REMOTE=m ++CONFIG_RC_LOOPBACK=m +CONFIG_MEDIA_CEC_RC=y +CONFIG_MEDIA_SUPPORT=m +CONFIG_MEDIA_USB_SUPPORT=y -+CONFIG_USB_VIDEO_CLASS=m -+CONFIG_USB_M5602=m -+CONFIG_USB_STV06XX=m -+CONFIG_USB_GL860=m ++CONFIG_USB_GSPCA=m +CONFIG_USB_GSPCA_BENQ=m +CONFIG_USB_GSPCA_CONEX=m +CONFIG_USB_GSPCA_CPIA1=m @@ -45249,13 +62475,13 @@ index 000000000000..419813140a52 +CONFIG_USB_GSPCA_SN9C20X=m +CONFIG_USB_GSPCA_SONIXB=m +CONFIG_USB_GSPCA_SONIXJ=m ++CONFIG_USB_GSPCA_SPCA1528=m +CONFIG_USB_GSPCA_SPCA500=m +CONFIG_USB_GSPCA_SPCA501=m +CONFIG_USB_GSPCA_SPCA505=m +CONFIG_USB_GSPCA_SPCA506=m +CONFIG_USB_GSPCA_SPCA508=m +CONFIG_USB_GSPCA_SPCA561=m -+CONFIG_USB_GSPCA_SPCA1528=m +CONFIG_USB_GSPCA_SQ905=m +CONFIG_USB_GSPCA_SQ905C=m +CONFIG_USB_GSPCA_SQ930X=m @@ -45265,103 +62491,133 @@ index 000000000000..419813140a52 +CONFIG_USB_GSPCA_SUNPLUS=m +CONFIG_USB_GSPCA_T613=m +CONFIG_USB_GSPCA_TOPRO=m ++CONFIG_USB_GSPCA_TOUPTEK=m +CONFIG_USB_GSPCA_TV8532=m +CONFIG_USB_GSPCA_VC032X=m +CONFIG_USB_GSPCA_VICAM=m +CONFIG_USB_GSPCA_XIRLINK_CIT=m +CONFIG_USB_GSPCA_ZC3XX=m ++CONFIG_USB_GL860=m ++CONFIG_USB_M5602=m ++CONFIG_USB_STV06XX=m +CONFIG_USB_PWC=m -+CONFIG_VIDEO_CPIA2=m -+CONFIG_USB_ZR364XX=m -+CONFIG_USB_STKWEBCAM=m +CONFIG_USB_S2255=m +CONFIG_VIDEO_USBTV=m -+CONFIG_VIDEO_PVRUSB2=m -+CONFIG_VIDEO_HDPVR=m -+CONFIG_VIDEO_STK1160_COMMON=m ++CONFIG_USB_VIDEO_CLASS=m +CONFIG_VIDEO_GO7007=m +CONFIG_VIDEO_GO7007_USB=m +CONFIG_VIDEO_GO7007_USB_S2250_BOARD=m ++CONFIG_VIDEO_HDPVR=m ++CONFIG_VIDEO_PVRUSB2=m ++CONFIG_VIDEO_STK1160=m +CONFIG_VIDEO_AU0828=m ++CONFIG_DVB_AS102=m ++CONFIG_DVB_B2C2_FLEXCOP_USB=m +CONFIG_DVB_USB_V2=m +CONFIG_DVB_USB_AF9035=m +CONFIG_DVB_USB_ANYSEE=m +CONFIG_DVB_USB_AU6610=m +CONFIG_DVB_USB_AZ6007=m +CONFIG_DVB_USB_CE6230=m ++CONFIG_DVB_USB_DVBSKY=m +CONFIG_DVB_USB_EC168=m +CONFIG_DVB_USB_GL861=m +CONFIG_DVB_USB_MXL111SF=m -+CONFIG_DVB_USB_DVBSKY=m +CONFIG_SMS_USB_DRV=m -+CONFIG_DVB_B2C2_FLEXCOP_USB=m -+CONFIG_DVB_AS102=m +CONFIG_VIDEO_EM28XX=m +CONFIG_VIDEO_EM28XX_V4L2=m +CONFIG_VIDEO_EM28XX_ALSA=m +CONFIG_VIDEO_EM28XX_DVB=m ++CONFIG_RADIO_SAA7706H=m ++CONFIG_RADIO_SHARK=m ++CONFIG_RADIO_SHARK2=m ++CONFIG_RADIO_SI4713=m ++CONFIG_RADIO_TEA5764=m ++CONFIG_RADIO_TEF6862=m ++CONFIG_RADIO_WL1273=m ++CONFIG_USB_DSBR=m ++CONFIG_USB_KEENE=m ++CONFIG_USB_MA901=m ++CONFIG_USB_MR800=m +CONFIG_RADIO_SI470X=m +CONFIG_USB_SI470X=m +CONFIG_I2C_SI470X=m -+CONFIG_RADIO_SI4713=m +CONFIG_I2C_SI4713=m -+CONFIG_USB_MR800=m -+CONFIG_USB_DSBR=m -+CONFIG_RADIO_SHARK=m -+CONFIG_RADIO_SHARK2=m -+CONFIG_USB_KEENE=m -+CONFIG_USB_MA901=m -+CONFIG_RADIO_TEA5764=m -+CONFIG_RADIO_SAA7706H=m -+CONFIG_RADIO_TEF6862=m -+CONFIG_RADIO_WL1273=m +CONFIG_RADIO_WL128X=m +CONFIG_V4L_PLATFORM_DRIVERS=y ++CONFIG_VIDEO_MUX=m +CONFIG_VIDEO_BCM2835_UNICAM=m +CONFIG_V4L_TEST_DRIVERS=y -+CONFIG_VIDEO_VIMC=m -+CONFIG_VIDEO_VIVID=m +CONFIG_VIDEO_VIM2M=m +CONFIG_VIDEO_VICODEC=m -+CONFIG_VIDEO_UDA1342=m ++CONFIG_VIDEO_VIMC=m ++CONFIG_VIDEO_VIVID=m ++CONFIG_VIDEO_ARDUCAM_64MP=m ++CONFIG_VIDEO_ARDUCAM_PIVARIETY=m ++CONFIG_VIDEO_IMX219=m ++CONFIG_VIDEO_IMX258=m ++CONFIG_VIDEO_IMX290=m ++CONFIG_VIDEO_IMX296=m ++CONFIG_VIDEO_IMX477=m ++CONFIG_VIDEO_IMX519=m ++CONFIG_VIDEO_IMX708=m ++CONFIG_VIDEO_MT9V011=m ++CONFIG_VIDEO_OV2311=m ++CONFIG_VIDEO_OV5647=m ++CONFIG_VIDEO_OV64A40=m ++CONFIG_VIDEO_OV7251=m ++CONFIG_VIDEO_OV7640=m ++CONFIG_VIDEO_OV9282=m ++CONFIG_VIDEO_AD5398=m ++CONFIG_VIDEO_AK7375=m ++CONFIG_VIDEO_BU64754=m ++CONFIG_VIDEO_DW9807_VCM=m +CONFIG_VIDEO_SONY_BTF_MPX=m ++CONFIG_VIDEO_UDA1342=m +CONFIG_VIDEO_ADV7180=m +CONFIG_VIDEO_TC358743=m +CONFIG_VIDEO_TVP5150=m +CONFIG_VIDEO_TW2804=m +CONFIG_VIDEO_TW9903=m +CONFIG_VIDEO_TW9906=m -+CONFIG_VIDEO_IMX219=m -+CONFIG_VIDEO_IMX290=m -+CONFIG_VIDEO_IMX477=m -+CONFIG_VIDEO_IMX519=m -+CONFIG_VIDEO_OV5647=m -+CONFIG_VIDEO_OV7251=m -+CONFIG_VIDEO_OV7640=m -+CONFIG_VIDEO_OV9281=m +CONFIG_VIDEO_IRS1125=m -+CONFIG_VIDEO_MT9V011=m ++CONFIG_VIDEO_I2C=m +CONFIG_DRM=m +CONFIG_DRM_LOAD_EDID_FIRMWARE=y +CONFIG_DRM_UDL=m +CONFIG_DRM_PANEL_SIMPLE=m ++CONFIG_DRM_PANEL_ILITEK_ILI9806E=m ++CONFIG_DRM_PANEL_ILITEK_ILI9881C=m +CONFIG_DRM_PANEL_JDI_LT070ME05000=m +CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN=m ++CONFIG_DRM_PANEL_SITRONIX_ST7701=m ++CONFIG_DRM_PANEL_TPO_Y17P=m ++CONFIG_DRM_PANEL_WAVESHARE_TOUCHSCREEN=m +CONFIG_DRM_DISPLAY_CONNECTOR=m +CONFIG_DRM_SIMPLE_BRIDGE=m +CONFIG_DRM_TOSHIBA_TC358762=m +CONFIG_DRM_VC4=m +CONFIG_DRM_VC4_HDMI_CEC=y ++CONFIG_DRM_PANEL_MIPI_DBI=m ++CONFIG_TINYDRM_HX8357D=m ++CONFIG_TINYDRM_ILI9225=m ++CONFIG_TINYDRM_ILI9341=m ++CONFIG_TINYDRM_ILI9486=m ++CONFIG_TINYDRM_MI0283QT=m ++CONFIG_TINYDRM_REPAPER=m ++CONFIG_TINYDRM_ST7586=m ++CONFIG_TINYDRM_ST7735R=m +CONFIG_DRM_GUD=m +CONFIG_FB=y +CONFIG_FB_BCM2708=y -+CONFIG_FB_UDL=m +CONFIG_FB_SIMPLE=y +CONFIG_FB_SSD1307=m +CONFIG_FB_RPISENSE=m ++CONFIG_BACKLIGHT_PWM=m +CONFIG_BACKLIGHT_RPI=m ++CONFIG_BACKLIGHT_LM3630A=m +CONFIG_BACKLIGHT_GPIO=m -+CONFIG_FRAMEBUFFER_CONSOLE=y ++CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y +CONFIG_LOGO=y +# CONFIG_LOGO_LINUX_MONO is not set +# CONFIG_LOGO_LINUX_VGA16 is not set @@ -45370,6 +62626,7 @@ index 000000000000..419813140a52 +CONFIG_SND_OSSEMUL=y +CONFIG_SND_PCM_OSS=m +CONFIG_SND_HRTIMER=m ++CONFIG_SND_DYNAMIC_MINORS=y +CONFIG_SND_SEQUENCER=m +CONFIG_SND_SEQ_DUMMY=m +CONFIG_SND_DUMMY=m @@ -45383,10 +62640,12 @@ index 000000000000..419813140a52 +CONFIG_SND_USB_CAIAQ=m +CONFIG_SND_USB_CAIAQ_INPUT=y +CONFIG_SND_USB_6FIRE=m ++CONFIG_SND_USB_HIFACE=m +CONFIG_SND_USB_TONEPORT=m +CONFIG_SND_SOC=m +CONFIG_SND_BCM2835_SOC_I2S=m +CONFIG_SND_BCM2708_SOC_CHIPDIP_DAC=m ++CONFIG_SND_BCM2708_SOC_GOOGLEVOICEHAT_SOUNDCARD=m +CONFIG_SND_BCM2708_SOC_HIFIBERRY_DAC=m +CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUS=m +CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUSHD=m @@ -45396,6 +62655,7 @@ index 000000000000..419813140a52 +CONFIG_SND_BCM2708_SOC_HIFIBERRY_DIGI=m +CONFIG_SND_BCM2708_SOC_HIFIBERRY_AMP=m +CONFIG_SND_BCM2708_SOC_PIFI_40=m ++CONFIG_SND_BCM2708_SOC_RPI_CIRRUS=m +CONFIG_SND_BCM2708_SOC_RPI_DAC=m +CONFIG_SND_BCM2708_SOC_RPI_PROTO=m +CONFIG_SND_BCM2708_SOC_JUSTBOOM_BOTH=m @@ -45407,31 +62667,45 @@ index 000000000000..419813140a52 +CONFIG_SND_BCM2708_SOC_I_SABRE_Q2M=m +CONFIG_SND_BCM2708_SOC_ADAU1977_ADC=m +CONFIG_SND_AUDIOINJECTOR_PI_SOUNDCARD=m ++CONFIG_SND_AUDIOINJECTOR_OCTO_SOUNDCARD=m +CONFIG_SND_AUDIOINJECTOR_ISOLATED_SOUNDCARD=m +CONFIG_SND_AUDIOSENSE_PI=m +CONFIG_SND_DIGIDAC1_SOUNDCARD=m +CONFIG_SND_BCM2708_SOC_DIONAUDIO_LOCO=m ++CONFIG_SND_BCM2708_SOC_DIONAUDIO_LOCO_V2=m +CONFIG_SND_BCM2708_SOC_ALLO_PIANO_DAC=m ++CONFIG_SND_BCM2708_SOC_ALLO_PIANO_DAC_PLUS=m ++CONFIG_SND_BCM2708_SOC_ALLO_BOSS_DAC=m +CONFIG_SND_BCM2708_SOC_ALLO_BOSS2_DAC=m ++CONFIG_SND_BCM2708_SOC_ALLO_DIGIONE=m ++CONFIG_SND_BCM2708_SOC_ALLO_KATANA_DAC=m ++CONFIG_SND_BCM2708_SOC_FE_PI_AUDIO=m +CONFIG_SND_PISOUND=m ++CONFIG_SND_DACBERRY400=m +CONFIG_SND_SOC_AD193X_SPI=m +CONFIG_SND_SOC_AD193X_I2C=m +CONFIG_SND_SOC_ADAU1701=m ++CONFIG_SND_SOC_ADAU7002=m +CONFIG_SND_SOC_AK4554=m +CONFIG_SND_SOC_CS4265=m +CONFIG_SND_SOC_ICS43432=m +CONFIG_SND_SOC_MA120X0P=m +CONFIG_SND_SOC_MAX98357A=m ++CONFIG_SND_SOC_SPDIF=m ++CONFIG_SND_SOC_TLV320AIC23_I2C=m +CONFIG_SND_SOC_WM8804_I2C=m +CONFIG_SND_SOC_WM8960=m +CONFIG_SND_SIMPLE_CARD=m ++CONFIG_HID_BATTERY_STRENGTH=y +CONFIG_HIDRAW=y +CONFIG_UHID=m +CONFIG_HID_A4TECH=m +CONFIG_HID_ACRUX=m +CONFIG_HID_APPLE=m ++CONFIG_HID_ASUS=m +CONFIG_HID_BELKIN=m +CONFIG_HID_BETOP_FF=m ++CONFIG_HID_BIGBEN_FF=m +CONFIG_HID_CHERRY=m +CONFIG_HID_CHICONY=m +CONFIG_HID_CYPRESS=m @@ -45459,14 +62733,19 @@ index 000000000000..419813140a52 +CONFIG_HID_MICROSOFT=m +CONFIG_HID_MONTEREY=m +CONFIG_HID_MULTITOUCH=m ++CONFIG_HID_NINTENDO=m ++CONFIG_NINTENDO_FF=y +CONFIG_HID_NTRIG=m +CONFIG_HID_ORTEK=m +CONFIG_HID_PANTHERLORD=m +CONFIG_HID_PETALYNX=m +CONFIG_HID_PICOLCD=m ++CONFIG_HID_PLAYSTATION=m ++CONFIG_PLAYSTATION_FF=y +CONFIG_HID_ROCCAT=m +CONFIG_HID_SAMSUNG=m +CONFIG_HID_SONY=m ++CONFIG_SONY_FF=y +CONFIG_HID_SPEEDLINK=m +CONFIG_HID_STEAM=m +CONFIG_HID_SUNPLUS=m @@ -45482,7 +62761,6 @@ index 000000000000..419813140a52 +CONFIG_HID_ZYDACRON=m +CONFIG_HID_PID=y +CONFIG_USB_HIDDEV=y -+CONFIG_I2C_HID=m +CONFIG_USB=y +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y +CONFIG_USB_MON=m @@ -45510,6 +62788,7 @@ index 000000000000..419813140a52 +CONFIG_USBIP_VHCI_HCD=m +CONFIG_USBIP_HOST=m +CONFIG_USB_DWC2=y ++CONFIG_USB_DWC2_HOST=y +CONFIG_USB_SERIAL=m +CONFIG_USB_SERIAL_GENERIC=y +CONFIG_USB_SERIAL_AIRCABLE=m @@ -45550,7 +62829,6 @@ index 000000000000..419813140a52 +CONFIG_USB_SERIAL_SYMBOL=m +CONFIG_USB_SERIAL_TI=m +CONFIG_USB_SERIAL_CYBERJACK=m -+CONFIG_USB_SERIAL_XIRCOM=m +CONFIG_USB_SERIAL_OPTION=m +CONFIG_USB_SERIAL_OMNINET=m +CONFIG_USB_SERIAL_OPTICON=m @@ -45568,7 +62846,6 @@ index 000000000000..419813140a52 +CONFIG_USB_CYPRESS_CY7C63=m +CONFIG_USB_CYTHERM=m +CONFIG_USB_IDMOUSE=m -+CONFIG_USB_FTDI_ELAN=m +CONFIG_USB_APPLEDISPLAY=m +CONFIG_USB_LD=m +CONFIG_USB_TRANCEVIBRATOR=m @@ -45581,7 +62858,41 @@ index 000000000000..419813140a52 +CONFIG_USB_CXACRU=m +CONFIG_USB_UEAGLEATM=m +CONFIG_USB_XUSBATM=m -+CONFIG_USB_GADGET=m ++CONFIG_NOP_USB_XCEIV=y ++CONFIG_USB_GADGET=y ++CONFIG_U_SERIAL_CONSOLE=y ++CONFIG_USB_CONFIGFS=m ++CONFIG_USB_CONFIGFS_SERIAL=y ++CONFIG_USB_CONFIGFS_ACM=y ++CONFIG_USB_CONFIGFS_OBEX=y ++CONFIG_USB_CONFIGFS_NCM=y ++CONFIG_USB_CONFIGFS_ECM=y ++CONFIG_USB_CONFIGFS_ECM_SUBSET=y ++CONFIG_USB_CONFIGFS_RNDIS=y ++CONFIG_USB_CONFIGFS_EEM=y ++CONFIG_USB_CONFIGFS_MASS_STORAGE=y ++CONFIG_USB_CONFIGFS_F_LB_SS=y ++CONFIG_USB_CONFIGFS_F_FS=y ++CONFIG_USB_CONFIGFS_F_UAC1=y ++CONFIG_USB_CONFIGFS_F_UAC1_LEGACY=y ++CONFIG_USB_CONFIGFS_F_UAC2=y ++CONFIG_USB_CONFIGFS_F_MIDI=y ++CONFIG_USB_CONFIGFS_F_HID=y ++CONFIG_USB_CONFIGFS_F_UVC=y ++CONFIG_USB_CONFIGFS_F_PRINTER=y ++CONFIG_USB_ZERO=m ++CONFIG_USB_AUDIO=m ++CONFIG_USB_ETH=m ++CONFIG_USB_GADGETFS=m ++CONFIG_USB_MASS_STORAGE=m ++CONFIG_USB_G_SERIAL=m ++CONFIG_USB_MIDI_GADGET=m ++CONFIG_USB_G_PRINTER=m ++CONFIG_USB_CDC_COMPOSITE=m ++CONFIG_USB_G_ACM_MS=m ++CONFIG_USB_G_MULTI=m ++CONFIG_USB_G_HID=m ++CONFIG_USB_G_WEBCAM=m +CONFIG_MMC=y +CONFIG_MMC_BLOCK_MINORS=32 +CONFIG_MMC_BCM2835_MMC=y @@ -45592,6 +62903,7 @@ index 000000000000..419813140a52 +CONFIG_MMC_SDHCI_IPROC=m +CONFIG_MMC_SPI=m +CONFIG_LEDS_CLASS=y ++CONFIG_LEDS_CLASS_MULTICOLOR=m +CONFIG_LEDS_PCA9532=m +CONFIG_LEDS_GPIO=y +CONFIG_LEDS_PCA955X=m @@ -45603,7 +62915,6 @@ index 000000000000..419813140a52 +CONFIG_LEDS_TRIGGER_HEARTBEAT=y +CONFIG_LEDS_TRIGGER_BACKLIGHT=y +CONFIG_LEDS_TRIGGER_CPU=y -+CONFIG_LEDS_TRIGGER_GPIO=y +CONFIG_LEDS_TRIGGER_DEFAULT_ON=y +CONFIG_LEDS_TRIGGER_TRANSIENT=m +CONFIG_LEDS_TRIGGER_CAMERA=m @@ -45638,6 +62949,8 @@ index 000000000000..419813140a52 +CONFIG_RTC_DRV_RX8025=m +CONFIG_RTC_DRV_EM3027=m +CONFIG_RTC_DRV_RV3028=m ++CONFIG_RTC_DRV_RV3032=m ++CONFIG_RTC_DRV_RV8803=m +CONFIG_RTC_DRV_SD3078=m +CONFIG_RTC_DRV_M41T93=m +CONFIG_RTC_DRV_M41T94=m @@ -45664,10 +62977,9 @@ index 000000000000..419813140a52 +CONFIG_STAGING=y +CONFIG_PRISM2_USB=m +CONFIG_R8712U=m -+CONFIG_R8188EU=m +CONFIG_VT6656=m +CONFIG_STAGING_MEDIA=y -+CONFIG_ASHMEM=y ++CONFIG_STAGING_MEDIA_DEPRECATED=y +CONFIG_FB_TFT=m +CONFIG_FB_TFT_AGM1264K_FL=m +CONFIG_FB_TFT_BD663474=m @@ -45692,11 +63004,12 @@ index 000000000000..419813140a52 +CONFIG_FB_TFT_SSD1331=m +CONFIG_FB_TFT_SSD1351=m +CONFIG_FB_TFT_ST7735R=m ++CONFIG_FB_TFT_ST7789V=m +CONFIG_FB_TFT_TINYLCD=m +CONFIG_FB_TFT_TLS8204=m ++CONFIG_FB_TFT_UC1611=m +CONFIG_FB_TFT_UC1701=m +CONFIG_FB_TFT_UPD161704=m -+CONFIG_FB_TFT_WATTEROTT=m +CONFIG_BCM2835_VCHIQ=y +CONFIG_SND_BCM2835=m +CONFIG_VIDEO_BCM2835=m @@ -45707,28 +63020,43 @@ index 000000000000..419813140a52 +CONFIG_BCM2835_MBOX=y +# CONFIG_IOMMU_SUPPORT is not set +CONFIG_RASPBERRYPI_POWER=y -+CONFIG_EXTCON=m -+CONFIG_EXTCON_ARIZONA=m +CONFIG_IIO=m +CONFIG_IIO_BUFFER_CB=m ++CONFIG_IIO_SW_TRIGGER=m +CONFIG_MCP320X=m +CONFIG_MCP3422=m ++CONFIG_TI_ADS1015=m +CONFIG_BME680=m +CONFIG_CCS811=m +CONFIG_SENSIRION_SGP30=m -+CONFIG_SPS30=m ++CONFIG_SPS30_I2C=m +CONFIG_MAX30102=m +CONFIG_DHT11=m ++CONFIG_HDC100X=m +CONFIG_HTU21=m ++CONFIG_SI7020=m ++CONFIG_BOSCH_BNO055_I2C=m ++CONFIG_INV_MPU6050_I2C=m +CONFIG_APDS9960=m +CONFIG_BH1750=m ++CONFIG_TSL4531=m ++CONFIG_VEML6070=m ++CONFIG_IIO_HRTIMER_TRIGGER=m ++CONFIG_IIO_INTERRUPT_TRIGGER=m ++CONFIG_IIO_SYSFS_TRIGGER=m ++CONFIG_BMP280=m ++CONFIG_MS5637=m +CONFIG_MAXIM_THERMOCOUPLE=m +CONFIG_MAX31856=m ++CONFIG_PWM=y +CONFIG_PWM_BCM2835=m +CONFIG_PWM_PCA9685=m -+CONFIG_ANDROID=y ++CONFIG_PWM_RASPBERRYPI_POE=m ++CONFIG_RPI_AXIPERF=m +CONFIG_ANDROID_BINDER_IPC=y +CONFIG_ANDROID_BINDERFS=y ++CONFIG_NVMEM_RMEM=m ++CONFIG_MUX_GPIO=m +CONFIG_EXT4_FS=y +CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_EXT4_FS_SECURITY=y @@ -45755,13 +63083,12 @@ index 000000000000..419813140a52 +CONFIG_FANOTIFY=y +CONFIG_QFMT_V1=m +CONFIG_QFMT_V2=m -+CONFIG_AUTOFS4_FS=y ++CONFIG_AUTOFS_FS=y +CONFIG_FUSE_FS=m +CONFIG_CUSE=m +CONFIG_OVERLAY_FS=m +CONFIG_FSCACHE=y +CONFIG_FSCACHE_STATS=y -+CONFIG_FSCACHE_HISTOGRAM=y +CONFIG_CACHEFILES=y +CONFIG_ISO9660_FS=m +CONFIG_JOLIET=y @@ -45773,6 +63100,7 @@ index 000000000000..419813140a52 +CONFIG_EXFAT_FS=m +CONFIG_NTFS_FS=m +CONFIG_NTFS_RW=y ++CONFIG_NTFS3_FS=m +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_ECRYPT_FS=m @@ -45785,6 +63113,9 @@ index 000000000000..419813140a52 +CONFIG_SQUASHFS_XATTR=y +CONFIG_SQUASHFS_LZO=y +CONFIG_SQUASHFS_XZ=y ++CONFIG_PSTORE=y ++CONFIG_PSTORE_CONSOLE=y ++CONFIG_PSTORE_RAM=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3_ACL=y +CONFIG_NFS_V4=y @@ -45794,14 +63125,18 @@ index 000000000000..419813140a52 +CONFIG_ROOT_NFS=y +CONFIG_NFS_FSCACHE=y +CONFIG_NFSD=m ++CONFIG_NFSD_V2=y ++CONFIG_NFSD_V2_ACL=y +CONFIG_NFSD_V3_ACL=y +CONFIG_NFSD_V4=y ++CONFIG_CEPH_FS=m +CONFIG_CIFS=m -+CONFIG_CIFS_WEAK_PW_HASH=y +CONFIG_CIFS_UPCALL=y +CONFIG_CIFS_XATTR=y ++CONFIG_CIFS_POSIX=y +CONFIG_CIFS_DFS_UPCALL=y +CONFIG_CIFS_FSCACHE=y ++CONFIG_SMB_SERVER=m +CONFIG_9P_FS=m +CONFIG_9P_FS_POSIX_ACL=y +CONFIG_NLS_DEFAULT="utf8" @@ -45843,28 +63178,37 @@ index 000000000000..419813140a52 +CONFIG_NLS_KOI8_R=m +CONFIG_NLS_KOI8_U=m +CONFIG_DLM=m ++CONFIG_KEY_DH_OPERATIONS=y +CONFIG_SECURITY=y +CONFIG_SECURITY_APPARMOR=y +CONFIG_LSM="" +CONFIG_CRYPTO_USER=m -+CONFIG_CRYPTO_CHACHA20POLY1305=m -+CONFIG_CRYPTO_ADIANTUM=m -+CONFIG_CRYPTO_XCBC=m -+CONFIG_CRYPTO_TGR192=m -+CONFIG_CRYPTO_WP512=m ++CONFIG_CRYPTO_CRYPTD=m +CONFIG_CRYPTO_CAST5=m +CONFIG_CRYPTO_DES=y ++CONFIG_CRYPTO_TWOFISH=m ++CONFIG_CRYPTO_ADIANTUM=m ++CONFIG_CRYPTO_CHACHA20POLY1305=m ++CONFIG_CRYPTO_MD4=m ++CONFIG_CRYPTO_SHA512=m ++CONFIG_CRYPTO_WP512=m ++CONFIG_CRYPTO_XCBC=m +CONFIG_CRYPTO_LZ4=m +CONFIG_CRYPTO_USER_API_HASH=m +CONFIG_CRYPTO_USER_API_SKCIPHER=m +CONFIG_CRYPTO_USER_API_RNG=m +CONFIG_CRYPTO_USER_API_AEAD=m ++CONFIG_CRYPTO_AES_ARM64=m ++CONFIG_CRYPTO_AES_ARM64_BS=m ++# CONFIG_CRYPTO_HW is not set ++CONFIG_PKCS8_PRIVATE_KEY_PARSER=m +CONFIG_CRC_ITU_T=y +CONFIG_LIBCRC32C=y +CONFIG_DMA_CMA=y +CONFIG_CMA_SIZE_MBYTES=5 +CONFIG_PRINTK_TIME=y +CONFIG_BOOT_PRINTK_DELAY=y ++CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1f6 +CONFIG_KGDB=y +CONFIG_KGDB_KDB=y +CONFIG_KDB_KEYBOARD=y @@ -45873,33 +63217,22 @@ index 000000000000..419813140a52 +CONFIG_LATENCYTOP=y +CONFIG_FUNCTION_PROFILER=y +CONFIG_STACK_TRACER=y -+CONFIG_IRQSOFF_TRACER=y +CONFIG_SCHED_TRACER=y +CONFIG_BLK_DEV_IO_TRACE=y -diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig -index 5e7d86cf5dfa..73caaa8ceb96 100644 ---- a/arch/arm64/configs/defconfig -+++ b/arch/arm64/configs/defconfig -@@ -1027,6 +1027,7 @@ CONFIG_ROCKCHIP_EFUSE=y - CONFIG_NVMEM_SUNXI_SID=y - CONFIG_UNIPHIER_EFUSE=y - CONFIG_MESON_EFUSE=m -+CONFIG_NVMEM_RMEM=m - CONFIG_FPGA=y - CONFIG_FPGA_MGR_STRATIX10_SOC=m - CONFIG_FPGA_BRIDGE=m ++# CONFIG_UPROBE_EVENTS is not set diff --git a/arch/arm64/crypto/aes-cipher-glue.c b/arch/arm64/crypto/aes-cipher-glue.c -index 8caf6dfefce8..2c5772889bdf 100644 +index 4ec55e568941..bfaa0f1d3cc6 100644 --- a/arch/arm64/crypto/aes-cipher-glue.c +++ b/arch/arm64/crypto/aes-cipher-glue.c -@@ -9,6 +9,16 @@ - #include +@@ -9,6 +9,17 @@ + #include #include +MODULE_ALIAS_CRYPTO("ecb(aes)"); +MODULE_ALIAS_CRYPTO("cbc(aes)"); +MODULE_ALIAS_CRYPTO("ctr(aes)"); +MODULE_ALIAS_CRYPTO("xts(aes)"); ++MODULE_ALIAS_CRYPTO("xctr(aes)"); +MODULE_ALIAS_CRYPTO("cts(cbc(aes))"); +MODULE_ALIAS_CRYPTO("essiv(cbc(aes),sha256)"); +MODULE_ALIAS_CRYPTO("cmac(aes)"); @@ -45910,12 +63243,12 @@ index 8caf6dfefce8..2c5772889bdf 100644 asmlinkage void __aes_arm64_decrypt(u32 *rk, u8 *out, const u8 *in, int rounds); diff --git a/arch/arm64/crypto/aes-glue.c b/arch/arm64/crypto/aes-glue.c -index 3de1dc918ad4..d6a1f5d13af0 100644 +index 162787c7aa86..0b9626c8789e 100644 --- a/arch/arm64/crypto/aes-glue.c +++ b/arch/arm64/crypto/aes-glue.c -@@ -55,17 +55,17 @@ MODULE_DESCRIPTION("AES-ECB/CBC/CTR/XTS using ARMv8 Crypto Extensions"); +@@ -57,18 +57,18 @@ MODULE_DESCRIPTION("AES-ECB/CBC/CTR/XTS/XCTR using ARMv8 Crypto Extensions"); #define aes_mac_update neon_aes_mac_update - MODULE_DESCRIPTION("AES-ECB/CBC/CTR/XTS using ARMv8 NEON"); + MODULE_DESCRIPTION("AES-ECB/CBC/CTR/XTS/XCTR using ARMv8 NEON"); #endif -#if defined(USE_V8_CRYPTO_EXTENSIONS) || !IS_ENABLED(CONFIG_CRYPTO_AES_ARM64_BS) +#if defined(USE_V8_CRYPTO_EXTENSIONS) @@ -45923,6 +63256,7 @@ index 3de1dc918ad4..d6a1f5d13af0 100644 MODULE_ALIAS_CRYPTO("cbc(aes)"); MODULE_ALIAS_CRYPTO("ctr(aes)"); MODULE_ALIAS_CRYPTO("xts(aes)"); + MODULE_ALIAS_CRYPTO("xctr(aes)"); -#endif MODULE_ALIAS_CRYPTO("cts(cbc(aes))"); MODULE_ALIAS_CRYPTO("essiv(cbc(aes),sha256)"); @@ -45934,7 +63268,7 @@ index 3de1dc918ad4..d6a1f5d13af0 100644 MODULE_AUTHOR("Ard Biesheuvel "); MODULE_LICENSE("GPL v2"); diff --git a/arch/arm64/crypto/aes-neonbs-glue.c b/arch/arm64/crypto/aes-neonbs-glue.c -index fb507d569922..cc52829d426a 100644 +index 467ac2f768ac..813ae2bbbd52 100644 --- a/arch/arm64/crypto/aes-neonbs-glue.c +++ b/arch/arm64/crypto/aes-neonbs-glue.c @@ -18,11 +18,6 @@ @@ -45950,12 +63284,12 @@ index fb507d569922..cc52829d426a 100644 asmlinkage void aesbs_ecb_encrypt(u8 out[], u8 const in[], u8 const rk[], diff --git a/arch/arm64/kernel/armv8_deprecated.c b/arch/arm64/kernel/armv8_deprecated.c -index ba0d6b35461b..750f7239e86c 100644 +index fd0f291e215e..b843b686affd 100644 --- a/arch/arm64/kernel/armv8_deprecated.c +++ b/arch/arm64/kernel/armv8_deprecated.c -@@ -182,10 +182,15 @@ static void __init register_insn_emulation(struct insn_emulation_ops *ops) +@@ -539,9 +539,14 @@ static void __init register_insn_emulation(struct insn_emulation *insn) - switch (ops->status) { + switch (insn->status) { case INSN_DEPRECATED: +#if 0 insn->current_mode = INSN_EMULATE; @@ -45964,13 +63298,12 @@ index ba0d6b35461b..750f7239e86c 100644 +#else + insn->current_mode = INSN_HW; + run_all_cpu_set_hw_mode(insn, true); - insn->max = INSN_HW; +#endif + insn->max = INSN_HW; break; case INSN_OBSOLETE: - insn->current_mode = INSN_UNDEF; diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c -index e658b7a17d9b..37713bc17336 100644 +index eecedf5b67fa..33ac8dfb30ca 100644 --- a/arch/arm64/kernel/cpuinfo.c +++ b/arch/arm64/kernel/cpuinfo.c @@ -17,6 +17,7 @@ @@ -45981,7 +63314,7 @@ index e658b7a17d9b..37713bc17336 100644 #include #include #include -@@ -138,6 +139,10 @@ static int c_show(struct seq_file *m, void *v) +@@ -178,6 +179,10 @@ static int c_show(struct seq_file *m, void *v) { int i, j; bool aarch32 = personality(current->personality) == PER_LINUX32; @@ -45992,12 +63325,10 @@ index e658b7a17d9b..37713bc17336 100644 for_each_online_cpu(i) { struct cpuinfo_arm64 *cpuinfo = &per_cpu(cpu_data, i); -@@ -198,6 +203,26 @@ static int c_show(struct seq_file *m, void *v) +@@ -238,6 +243,24 @@ static int c_show(struct seq_file *m, void *v) seq_printf(m, "CPU revision\t: %d\n\n", MIDR_REVISION(midr)); } -+ seq_printf(m, "Hardware\t: BCM2835\n"); -+ + np = of_find_node_by_path("/system"); + if (np) { + if (!of_property_read_u32(np, "linux,revision", &revision)) @@ -46019,30 +63350,84 @@ index e658b7a17d9b..37713bc17336 100644 return 0; } -diff --git a/drivers/bluetooth/btusb.c b/drivers/bluetooth/btusb.c -index 538232b4c42a..3e78f429fc49 100644 ---- a/drivers/bluetooth/btusb.c -+++ b/drivers/bluetooth/btusb.c -@@ -436,6 +436,14 @@ static const struct usb_device_id blacklist_table[] = { - { USB_DEVICE(0x0bda, 0xb009), .driver_info = BTUSB_REALTEK }, - { USB_DEVICE(0x2ff8, 0xb011), .driver_info = BTUSB_REALTEK }, +diff --git a/arch/arm64/kernel/process.c b/arch/arm64/kernel/process.c +index 068e5bb2661b..0465e6645537 100644 +--- a/arch/arm64/kernel/process.c ++++ b/arch/arm64/kernel/process.c +@@ -96,9 +96,7 @@ void machine_shutdown(void) + */ + void machine_halt(void) + { +- local_irq_disable(); +- smp_send_stop(); +- while (1); ++ machine_power_off(); + } + + /* +diff --git a/arch/arm64/kernel/setup.c b/arch/arm64/kernel/setup.c +index 95cb22c083c8..d8cdca9144ba 100644 +--- a/arch/arm64/kernel/setup.c ++++ b/arch/arm64/kernel/setup.c +@@ -269,9 +269,9 @@ static void __init request_standard_resources(void) + size_t res_size; + + kernel_code.start = __pa_symbol(_stext); +- kernel_code.end = __pa_symbol(__init_begin - 1); ++ kernel_code.end = __pa_symbol(__init_begin) - 1; + kernel_data.start = __pa_symbol(_sdata); +- kernel_data.end = __pa_symbol(_end - 1); ++ kernel_data.end = __pa_symbol(_end) - 1; + insert_resource(&iomem_resource, &kernel_code); + insert_resource(&iomem_resource, &kernel_data); + +diff --git a/drivers/bluetooth/btbcm.c b/drivers/bluetooth/btbcm.c +index 0a5445ac5e1b..3029004fa262 100644 +--- a/drivers/bluetooth/btbcm.c ++++ b/drivers/bluetooth/btbcm.c +@@ -24,12 +24,15 @@ + #define BDADDR_BCM20702A1 (&(bdaddr_t) {{0x00, 0x00, 0xa0, 0x02, 0x70, 0x20}}) + #define BDADDR_BCM2076B1 (&(bdaddr_t) {{0x79, 0x56, 0x00, 0xa0, 0x76, 0x20}}) + #define BDADDR_BCM43430A0 (&(bdaddr_t) {{0xac, 0x1f, 0x12, 0xa0, 0x43, 0x43}}) +-#define BDADDR_BCM43430A1 (&(bdaddr_t) {{0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa}}) ++#define BDADDR_BCM43430A1 (&(bdaddr_t) {{0xac, 0x1f, 0x12, 0xa1, 0x43, 0x43}}) ++#define BDADDR_BCM43430B0 (&(bdaddr_t) {{0xac, 0x1f, 0x37, 0xb0, 0x43, 0x43}}) + #define BDADDR_BCM4324B3 (&(bdaddr_t) {{0x00, 0x00, 0x00, 0xb3, 0x24, 0x43}}) + #define BDADDR_BCM4330B1 (&(bdaddr_t) {{0x00, 0x00, 0x00, 0xb1, 0x30, 0x43}}) + #define BDADDR_BCM4334B0 (&(bdaddr_t) {{0x00, 0x00, 0x00, 0xb0, 0x34, 0x43}}) ++#define BDADDR_BCM4345C0 (&(bdaddr_t) {{0xac, 0x1f, 0x00, 0xc0, 0x45, 0x43}}) + #define BDADDR_BCM4345C5 (&(bdaddr_t) {{0xac, 0x1f, 0x00, 0xc5, 0x45, 0x43}}) + #define BDADDR_BCM43341B (&(bdaddr_t) {{0xac, 0x1f, 0x00, 0x1b, 0x34, 0x43}}) ++#define BDADDR_BCM43438 (&(bdaddr_t) {{0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa}}) + + #define BCM_FW_NAME_LEN 64 + #define BCM_FW_NAME_COUNT_MAX 4 +@@ -126,9 +129,12 @@ int btbcm_check_bdaddr(struct hci_dev *hdev) + !bacmp(&bda->bdaddr, BDADDR_BCM4324B3) || + !bacmp(&bda->bdaddr, BDADDR_BCM4330B1) || + !bacmp(&bda->bdaddr, BDADDR_BCM4334B0) || ++ !bacmp(&bda->bdaddr, BDADDR_BCM4345C0) || + !bacmp(&bda->bdaddr, BDADDR_BCM4345C5) || + !bacmp(&bda->bdaddr, BDADDR_BCM43430A0) || + !bacmp(&bda->bdaddr, BDADDR_BCM43430A1) || ++ !bacmp(&bda->bdaddr, BDADDR_BCM43430B0) || ++ !bacmp(&bda->bdaddr, BDADDR_BCM43438) || + !bacmp(&bda->bdaddr, BDADDR_BCM43341B)) { + /* Try falling back to BDADDR EFI variable */ + if (btbcm_set_bdaddr_from_efi(hdev) != 0) { +@@ -514,6 +520,7 @@ static const struct bcm_subver_table bcm_uart_subver_table[] = { + { 0x4106, "BCM4335A0" }, /* 002.001.006 */ + { 0x410c, "BCM43430B0" }, /* 002.001.012 */ + { 0x2119, "BCM4373A0" }, /* 001.001.025 */ ++ { 0x2310, "BCM4343A2" }, /* 001.003.016 */ + { } + }; -+ /* Additional Realtek 8761B Bluetooth devices */ -+ { USB_DEVICE(0x2357, 0x0604), .driver_info = BTUSB_REALTEK | -+ BTUSB_WIDEBAND_SPEECH }, -+ -+ /* Additional Realtek 8761BU Bluetooth devices */ -+ { USB_DEVICE(0x0b05, 0x190e), .driver_info = BTUSB_REALTEK | -+ BTUSB_WIDEBAND_SPEECH }, -+ - /* Additional Realtek 8821AE Bluetooth devices */ - { USB_DEVICE(0x0b05, 0x17dc), .driver_info = BTUSB_REALTEK }, - { USB_DEVICE(0x13d3, 0x3414), .driver_info = BTUSB_REALTEK }, diff --git a/drivers/bluetooth/hci_h5.c b/drivers/bluetooth/hci_h5.c -index 996729e78105..6d179e455721 100644 +index 71e748a9477e..c58c16817e97 100644 --- a/drivers/bluetooth/hci_h5.c +++ b/drivers/bluetooth/hci_h5.c -@@ -343,7 +343,8 @@ static void h5_handle_internal_rx(struct hci_uart *hu) +@@ -357,7 +357,8 @@ static void h5_handle_internal_rx(struct hci_uart *hu) h5_link_control(hu, conf_req, 3); } else if (memcmp(data, conf_req, 2) == 0) { h5_link_control(hu, conf_rsp, 2); @@ -46053,7 +63438,7 @@ index 996729e78105..6d179e455721 100644 if (H5_HDR_LEN(hdr) > 2) h5->tx_win = (data[2] & 0x07); diff --git a/drivers/char/Kconfig b/drivers/char/Kconfig -index f75f9e3ea324..636e68e4eaeb 100644 +index 625af75833fc..96c3c37b7577 100644 --- a/drivers/char/Kconfig +++ b/drivers/char/Kconfig @@ -5,6 +5,8 @@ @@ -46065,23 +63450,35 @@ index f75f9e3ea324..636e68e4eaeb 100644 source "drivers/tty/Kconfig" config TTY_PRINTK +@@ -422,4 +424,12 @@ config ADI + and SSM (Silicon Secured Memory). Intended consumers of this + driver include crash and makedumpfile. + ++config RASPBERRYPI_GPIOMEM ++ tristate "Rootless GPIO access via mmap() on Raspberry Pi boards" ++ default n ++ help ++ Provides users with root-free access to the GPIO registers ++ on the board. Calling mmap(/dev/gpiomem) will map the GPIO ++ register page to the user's pointer. ++ + endmenu diff --git a/drivers/char/Makefile b/drivers/char/Makefile -index 362d4a9cd4cf..eea88cef9829 100644 +index c5f532e412f1..2ae16025a64b 100644 --- a/drivers/char/Makefile +++ b/drivers/char/Makefile -@@ -47,5 +47,6 @@ obj-$(CONFIG_PS3_FLASH) += ps3flash.o - obj-$(CONFIG_XILLYBUS) += xillybus/ +@@ -44,3 +44,5 @@ obj-$(CONFIG_PS3_FLASH) += ps3flash.o + obj-$(CONFIG_XILLYBUS_CLASS) += xillybus/ obj-$(CONFIG_POWERNV_OP_PANEL) += powernv-op-panel.o obj-$(CONFIG_ADI) += adi.o +obj-$(CONFIG_BRCM_CHAR_DRIVERS) += broadcom/ - obj-$(CONFIG_PIN_MEMORY_DEV) += pin_memory.o - obj-$(CONFIG_HISI_SVM) += svm.o ++obj-$(CONFIG_RASPBERRYPI_GPIOMEM) += raspberrypi-gpiomem.o diff --git a/drivers/char/broadcom/Kconfig b/drivers/char/broadcom/Kconfig new file mode 100644 -index 000000000000..e555e841b8db +index 000000000000..29d880d47282 --- /dev/null +++ b/drivers/char/broadcom/Kconfig -@@ -0,0 +1,49 @@ +@@ -0,0 +1,33 @@ +# +# Broadcom char driver config +# @@ -46107,14 +63504,6 @@ index 000000000000..e555e841b8db + +endif + -+config BCM2835_DEVGPIOMEM -+ tristate "/dev/gpiomem rootless GPIO access via mmap() on the BCM2835" -+ default m -+ help -+ Provides users with root-free access to the GPIO registers -+ on the 2835. Calling mmap(/dev/gpiomem) will map the GPIO -+ register page to the user's pointer. -+ +config BCM2835_SMI_DEV + tristate "Character device driver for BCM2835 Secondary Memory Interface" + depends on BCM2835_SMI @@ -46123,292 +63512,18 @@ index 000000000000..e555e841b8db + This driver provides a character device interface (ioctl + read/write) to + Broadcom's Secondary Memory interface. The low-level functionality is provided + by the SMI driver itself. -+ -+config RPIVID_MEM -+ tristate "Character device driver for the Raspberry Pi RPIVid video decoder hardware" -+ default n -+ help -+ This driver provides a character device interface for memory-map operations -+ so userspace tools can access the control and status registers of the -+ Raspberry Pi RPiVid video decoder hardware. diff --git a/drivers/char/broadcom/Makefile b/drivers/char/broadcom/Makefile new file mode 100644 -index 000000000000..a302fb3ff91a +index 000000000000..2ae3e9d411e9 --- /dev/null +++ b/drivers/char/broadcom/Makefile -@@ -0,0 +1,5 @@ +@@ -0,0 +1,3 @@ +obj-$(CONFIG_BCM2708_VCMEM) += vc_mem.o +obj-$(CONFIG_BCM_VCIO) += vcio.o -+obj-$(CONFIG_BCM2835_DEVGPIOMEM)+= bcm2835-gpiomem.o +obj-$(CONFIG_BCM2835_SMI_DEV) += bcm2835_smi_dev.o -+obj-$(CONFIG_RPIVID_MEM) += rpivid-mem.o -diff --git a/drivers/char/broadcom/bcm2835-gpiomem.c b/drivers/char/broadcom/bcm2835-gpiomem.c -new file mode 100644 -index 000000000000..f5e7f1ba8fb6 ---- /dev/null -+++ b/drivers/char/broadcom/bcm2835-gpiomem.c -@@ -0,0 +1,258 @@ -+/** -+ * GPIO memory device driver -+ * -+ * Creates a chardev /dev/gpiomem which will provide user access to -+ * the BCM2835's GPIO registers when it is mmap()'d. -+ * No longer need root for user GPIO access, but without relaxing permissions -+ * on /dev/mem. -+ * -+ * Written by Luke Wren -+ * Copyright (c) 2015, Raspberry Pi (Trading) Ltd. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions, and the following disclaimer, -+ * without modification. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. The names of the above-listed copyright holders may not be used -+ * to endorse or promote products derived from this software without -+ * specific prior written permission. -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") version 2, as published by the Free -+ * Software Foundation. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS -+ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, -+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR -+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, -+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#define DEVICE_NAME "bcm2835-gpiomem" -+#define DRIVER_NAME "gpiomem-bcm2835" -+#define DEVICE_MINOR 0 -+ -+struct bcm2835_gpiomem_instance { -+ unsigned long gpio_regs_phys; -+ struct device *dev; -+}; -+ -+static struct cdev bcm2835_gpiomem_cdev; -+static dev_t bcm2835_gpiomem_devid; -+static struct class *bcm2835_gpiomem_class; -+static struct device *bcm2835_gpiomem_dev; -+static struct bcm2835_gpiomem_instance *inst; -+ -+ -+/**************************************************************************** -+* -+* GPIO mem chardev file ops -+* -+***************************************************************************/ -+ -+static int bcm2835_gpiomem_open(struct inode *inode, struct file *file) -+{ -+ int dev = iminor(inode); -+ int ret = 0; -+ -+ if (dev != DEVICE_MINOR) { -+ dev_err(inst->dev, "Unknown minor device: %d", dev); -+ ret = -ENXIO; -+ } -+ return ret; -+} -+ -+static int bcm2835_gpiomem_release(struct inode *inode, struct file *file) -+{ -+ int dev = iminor(inode); -+ int ret = 0; -+ -+ if (dev != DEVICE_MINOR) { -+ dev_err(inst->dev, "Unknown minor device %d", dev); -+ ret = -ENXIO; -+ } -+ return ret; -+} -+ -+static const struct vm_operations_struct bcm2835_gpiomem_vm_ops = { -+#ifdef CONFIG_HAVE_IOREMAP_PROT -+ .access = generic_access_phys -+#endif -+}; -+ -+static int bcm2835_gpiomem_mmap(struct file *file, struct vm_area_struct *vma) -+{ -+ /* Ignore what the user says - they're getting the GPIO regs -+ whether they like it or not! */ -+ unsigned long gpio_page = inst->gpio_regs_phys >> PAGE_SHIFT; -+ -+ vma->vm_page_prot = phys_mem_access_prot(file, gpio_page, -+ PAGE_SIZE, -+ vma->vm_page_prot); -+ vma->vm_ops = &bcm2835_gpiomem_vm_ops; -+ if (remap_pfn_range(vma, vma->vm_start, -+ gpio_page, -+ PAGE_SIZE, -+ vma->vm_page_prot)) { -+ return -EAGAIN; -+ } -+ return 0; -+} -+ -+static const struct file_operations -+bcm2835_gpiomem_fops = { -+ .owner = THIS_MODULE, -+ .open = bcm2835_gpiomem_open, -+ .release = bcm2835_gpiomem_release, -+ .mmap = bcm2835_gpiomem_mmap, -+}; -+ -+ -+ /**************************************************************************** -+* -+* Probe and remove functions -+* -+***************************************************************************/ -+ -+ -+static int bcm2835_gpiomem_probe(struct platform_device *pdev) -+{ -+ int err; -+ void *ptr_err; -+ struct device *dev = &pdev->dev; -+ struct resource *ioresource; -+ -+ /* Allocate buffers and instance data */ -+ -+ inst = kzalloc(sizeof(struct bcm2835_gpiomem_instance), GFP_KERNEL); -+ -+ if (!inst) { -+ err = -ENOMEM; -+ goto failed_inst_alloc; -+ } -+ -+ inst->dev = dev; -+ -+ ioresource = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ if (ioresource) { -+ inst->gpio_regs_phys = ioresource->start; -+ } else { -+ dev_err(inst->dev, "failed to get IO resource"); -+ err = -ENOENT; -+ goto failed_get_resource; -+ } -+ -+ /* Create character device entries */ -+ -+ err = alloc_chrdev_region(&bcm2835_gpiomem_devid, -+ DEVICE_MINOR, 1, DEVICE_NAME); -+ if (err != 0) { -+ dev_err(inst->dev, "unable to allocate device number"); -+ goto failed_alloc_chrdev; -+ } -+ cdev_init(&bcm2835_gpiomem_cdev, &bcm2835_gpiomem_fops); -+ bcm2835_gpiomem_cdev.owner = THIS_MODULE; -+ err = cdev_add(&bcm2835_gpiomem_cdev, bcm2835_gpiomem_devid, 1); -+ if (err != 0) { -+ dev_err(inst->dev, "unable to register device"); -+ goto failed_cdev_add; -+ } -+ -+ /* Create sysfs entries */ -+ -+ bcm2835_gpiomem_class = class_create(THIS_MODULE, DEVICE_NAME); -+ ptr_err = bcm2835_gpiomem_class; -+ if (IS_ERR(ptr_err)) -+ goto failed_class_create; -+ -+ bcm2835_gpiomem_dev = device_create(bcm2835_gpiomem_class, NULL, -+ bcm2835_gpiomem_devid, NULL, -+ "gpiomem"); -+ ptr_err = bcm2835_gpiomem_dev; -+ if (IS_ERR(ptr_err)) -+ goto failed_device_create; -+ -+ dev_info(inst->dev, "Initialised: Registers at 0x%08lx", -+ inst->gpio_regs_phys); -+ -+ return 0; -+ -+failed_device_create: -+ class_destroy(bcm2835_gpiomem_class); -+failed_class_create: -+ cdev_del(&bcm2835_gpiomem_cdev); -+ err = PTR_ERR(ptr_err); -+failed_cdev_add: -+ unregister_chrdev_region(bcm2835_gpiomem_devid, 1); -+failed_alloc_chrdev: -+failed_get_resource: -+ kfree(inst); -+failed_inst_alloc: -+ dev_err(inst->dev, "could not load bcm2835_gpiomem"); -+ return err; -+} -+ -+static int bcm2835_gpiomem_remove(struct platform_device *pdev) -+{ -+ struct device *dev = inst->dev; -+ -+ kfree(inst); -+ device_destroy(bcm2835_gpiomem_class, bcm2835_gpiomem_devid); -+ class_destroy(bcm2835_gpiomem_class); -+ cdev_del(&bcm2835_gpiomem_cdev); -+ unregister_chrdev_region(bcm2835_gpiomem_devid, 1); -+ -+ dev_info(dev, "GPIO mem driver removed - OK"); -+ return 0; -+} -+ -+ /**************************************************************************** -+* -+* Register the driver with device tree -+* -+***************************************************************************/ -+ -+static const struct of_device_id bcm2835_gpiomem_of_match[] = { -+ {.compatible = "brcm,bcm2835-gpiomem",}, -+ { /* sentinel */ }, -+}; -+ -+MODULE_DEVICE_TABLE(of, bcm2835_gpiomem_of_match); -+ -+static struct platform_driver bcm2835_gpiomem_driver = { -+ .probe = bcm2835_gpiomem_probe, -+ .remove = bcm2835_gpiomem_remove, -+ .driver = { -+ .name = DRIVER_NAME, -+ .owner = THIS_MODULE, -+ .of_match_table = bcm2835_gpiomem_of_match, -+ }, -+}; -+ -+module_platform_driver(bcm2835_gpiomem_driver); -+ -+MODULE_ALIAS("platform:gpiomem-bcm2835"); -+MODULE_LICENSE("GPL"); -+MODULE_DESCRIPTION("gpiomem driver for accessing GPIO from userspace"); -+MODULE_AUTHOR("Luke Wren "); diff --git a/drivers/char/broadcom/bcm2835_smi_dev.c b/drivers/char/broadcom/bcm2835_smi_dev.c new file mode 100644 -index 000000000000..34976fa4ed59 +index 000000000000..905f50218cc9 --- /dev/null +++ b/drivers/char/broadcom/bcm2835_smi_dev.c @@ -0,0 +1,409 @@ @@ -46747,7 +63862,7 @@ index 000000000000..34976fa4ed59 + + /* Create sysfs entries */ + -+ bcm2835_smi_class = class_create(THIS_MODULE, DEVICE_NAME); ++ bcm2835_smi_class = class_create(DEVICE_NAME); + ptr_err = bcm2835_smi_class; + if (IS_ERR(ptr_err)) + goto failed_class_create; @@ -46821,288 +63936,12 @@ index 000000000000..34976fa4ed59 +MODULE_DESCRIPTION( + "Character device driver for BCM2835's secondary memory interface"); +MODULE_AUTHOR("Luke Wren "); -diff --git a/drivers/char/broadcom/rpivid-mem.c b/drivers/char/broadcom/rpivid-mem.c -new file mode 100644 -index 000000000000..9f38083f4cb6 ---- /dev/null -+++ b/drivers/char/broadcom/rpivid-mem.c -@@ -0,0 +1,270 @@ -+// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause -+/** -+ * rpivid-mem.c - character device access to the RPiVid decoder registers -+ * -+ * Based on bcm2835-gpiomem.c. Provides IO memory access to the decoder -+ * register blocks such that ffmpeg plugins can access the hardware. -+ * -+ * Jonathan Bell -+ * Copyright (c) 2019, Raspberry Pi (Trading) Ltd. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions -+ * are met: -+ * 1. Redistributions of source code must retain the above copyright -+ * notice, this list of conditions, and the following disclaimer, -+ * without modification. -+ * 2. Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * 3. The names of the above-listed copyright holders may not be used -+ * to endorse or promote products derived from this software without -+ * specific prior written permission. -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") version 2, as published by the Free -+ * Software Foundation. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS -+ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, -+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR -+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, -+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR -+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#define DRIVER_NAME "rpivid-mem" -+#define DEVICE_MINOR 0 -+ -+struct rpivid_mem_priv { -+ dev_t devid; -+ struct class *class; -+ struct cdev rpivid_mem_cdev; -+ unsigned long regs_phys; -+ unsigned long mem_window_len; -+ struct device *dev; -+ const char *name; -+}; -+ -+static int rpivid_mem_open(struct inode *inode, struct file *file) -+{ -+ int dev = iminor(inode); -+ int ret = 0; -+ struct rpivid_mem_priv *priv; -+ -+ if (dev != DEVICE_MINOR && dev != DEVICE_MINOR + 1) -+ ret = -ENXIO; -+ -+ priv = container_of(inode->i_cdev, struct rpivid_mem_priv, -+ rpivid_mem_cdev); -+ if (!priv) -+ return -EINVAL; -+ file->private_data = priv; -+ return ret; -+} -+ -+static int rpivid_mem_release(struct inode *inode, struct file *file) -+{ -+ int dev = iminor(inode); -+ int ret = 0; -+ -+ if (dev != DEVICE_MINOR && dev != DEVICE_MINOR + 1) -+ ret = -ENXIO; -+ -+ return ret; -+} -+ -+static const struct vm_operations_struct rpivid_mem_vm_ops = { -+#ifdef CONFIG_HAVE_IOREMAP_PROT -+ .access = generic_access_phys -+#endif -+}; -+ -+static int rpivid_mem_mmap(struct file *file, struct vm_area_struct *vma) -+{ -+ struct rpivid_mem_priv *priv; -+ unsigned long pages; -+ unsigned long len; -+ -+ priv = file->private_data; -+ pages = priv->regs_phys >> PAGE_SHIFT; -+ /* -+ * The address decode is far larger than the actual number of registers. -+ * Just map the whole lot in. -+ */ -+ len = min(vma->vm_end - vma->vm_start, priv->mem_window_len); -+ vma->vm_page_prot = phys_mem_access_prot(file, pages, len, -+ vma->vm_page_prot); -+ vma->vm_ops = &rpivid_mem_vm_ops; -+ if (remap_pfn_range(vma, vma->vm_start, -+ pages, len, -+ vma->vm_page_prot)) { -+ return -EAGAIN; -+ } -+ return 0; -+} -+ -+static const struct file_operations -+rpivid_mem_fops = { -+ .owner = THIS_MODULE, -+ .open = rpivid_mem_open, -+ .release = rpivid_mem_release, -+ .mmap = rpivid_mem_mmap, -+}; -+ -+static const struct of_device_id rpivid_mem_of_match[]; -+static int rpivid_mem_probe(struct platform_device *pdev) -+{ -+ int err; -+ const struct of_device_id *id; -+ struct device *dev = &pdev->dev; -+ struct resource *ioresource; -+ struct rpivid_mem_priv *priv; -+ -+ /* Allocate buffers and instance data */ -+ -+ priv = kzalloc(sizeof(struct rpivid_mem_priv), GFP_KERNEL); -+ -+ if (!priv) { -+ err = -ENOMEM; -+ goto failed_inst_alloc; -+ } -+ platform_set_drvdata(pdev, priv); -+ -+ priv->dev = dev; -+ id = of_match_device(rpivid_mem_of_match, dev); -+ if (!id) -+ return -EINVAL; -+ priv->name = id->data; -+ -+ ioresource = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ if (ioresource) { -+ priv->regs_phys = ioresource->start; -+ priv->mem_window_len = (ioresource->end + 1) - ioresource->start; -+ } else { -+ dev_err(priv->dev, "failed to get IO resource"); -+ err = -ENOENT; -+ goto failed_get_resource; -+ } -+ -+ /* Create character device entries */ -+ -+ err = alloc_chrdev_region(&priv->devid, -+ DEVICE_MINOR, 2, priv->name); -+ if (err != 0) { -+ dev_err(priv->dev, "unable to allocate device number"); -+ goto failed_alloc_chrdev; -+ } -+ cdev_init(&priv->rpivid_mem_cdev, &rpivid_mem_fops); -+ priv->rpivid_mem_cdev.owner = THIS_MODULE; -+ err = cdev_add(&priv->rpivid_mem_cdev, priv->devid, 2); -+ if (err != 0) { -+ dev_err(priv->dev, "unable to register device"); -+ goto failed_cdev_add; -+ } -+ -+ /* Create sysfs entries */ -+ -+ priv->class = class_create(THIS_MODULE, priv->name); -+ if (IS_ERR(priv->class)) { -+ err = PTR_ERR(priv->class); -+ goto failed_class_create; -+ } -+ -+ dev = device_create(priv->class, NULL, priv->devid, NULL, priv->name); -+ if (IS_ERR(dev)) { -+ err = PTR_ERR(dev); -+ goto failed_device_create; -+ } -+ -+ dev_info(priv->dev, "%s initialised: Registers at 0x%08lx length 0x%08lx", -+ priv->name, priv->regs_phys, priv->mem_window_len); -+ -+ return 0; -+ -+failed_device_create: -+ class_destroy(priv->class); -+failed_class_create: -+ cdev_del(&priv->rpivid_mem_cdev); -+failed_cdev_add: -+ unregister_chrdev_region(priv->devid, 1); -+failed_alloc_chrdev: -+failed_get_resource: -+ kfree(priv); -+failed_inst_alloc: -+ dev_err(&pdev->dev, "could not load rpivid_mem"); -+ return err; -+} -+ -+static int rpivid_mem_remove(struct platform_device *pdev) -+{ -+ struct device *dev = &pdev->dev; -+ struct rpivid_mem_priv *priv = platform_get_drvdata(pdev); -+ -+ device_destroy(priv->class, priv->devid); -+ class_destroy(priv->class); -+ cdev_del(&priv->rpivid_mem_cdev); -+ unregister_chrdev_region(priv->devid, 1); -+ kfree(priv); -+ -+ dev_info(dev, "%s driver removed - OK", priv->name); -+ return 0; -+} -+ -+static const struct of_device_id rpivid_mem_of_match[] = { -+ { -+ .compatible = "raspberrypi,rpivid-hevc-decoder", -+ .data = "rpivid-hevcmem", -+ }, -+ { -+ .compatible = "raspberrypi,rpivid-h264-decoder", -+ .data = "rpivid-h264mem", -+ }, -+ { -+ .compatible = "raspberrypi,rpivid-vp9-decoder", -+ .data = "rpivid-vp9mem", -+ }, -+ /* The "intc" is included as this block of hardware contains the -+ * "frame done" status flags. -+ */ -+ { -+ .compatible = "raspberrypi,rpivid-local-intc", -+ .data = "rpivid-intcmem", -+ }, -+ { /* sentinel */ }, -+}; -+ -+MODULE_DEVICE_TABLE(of, rpivid_mem_of_match); -+ -+static struct platform_driver rpivid_mem_driver = { -+ .probe = rpivid_mem_probe, -+ .remove = rpivid_mem_remove, -+ .driver = { -+ .name = DRIVER_NAME, -+ .owner = THIS_MODULE, -+ .of_match_table = rpivid_mem_of_match, -+ }, -+}; -+ -+module_platform_driver(rpivid_mem_driver); -+ -+MODULE_ALIAS("platform:rpivid-mem"); -+MODULE_LICENSE("GPL"); -+MODULE_DESCRIPTION("Driver for accessing RPiVid decoder registers from userspace"); -+MODULE_AUTHOR("Jonathan Bell "); diff --git a/drivers/char/broadcom/vc_mem.c b/drivers/char/broadcom/vc_mem.c new file mode 100644 -index 000000000000..195b61a4387c +index 000000000000..5e99ac59aaea --- /dev/null +++ b/drivers/char/broadcom/vc_mem.c -@@ -0,0 +1,373 @@ +@@ -0,0 +1,632 @@ +/* + * Copyright 2010 - 2011 Broadcom Corporation. All rights reserved. + * @@ -47128,9 +63967,21 @@ index 000000000000..195b61a4387c +#include +#include +#include ++#include ++#include ++#include + +#define DRIVER_NAME "vc-mem" + ++/* N.B. These use a different magic value for compatibility with bmc7208_fb */ ++#define VC_MEM_IOC_DMACOPY _IOW('z', 0x22, struct vc_mem_dmacopy) ++#define VC_MEM_IOC_DMACOPY32 _IOW('z', 0x22, struct vc_mem_dmacopy32) ++ ++/* address with no aliases */ ++#define INTALIAS_NORMAL(x) ((x) & ~0xc0000000) ++/* cache coherent but non-allocating in L1 and L2 */ ++#define INTALIAS_L1L2_NONALLOCATING(x) (((x) & ~0xc0000000) | 0x80000000) ++ +/* Device (/dev) related variables */ +static dev_t vc_mem_devnum; +static struct class *vc_mem_class; @@ -47141,6 +63992,20 @@ index 000000000000..195b61a4387c +static struct dentry *vc_mem_debugfs_entry; +#endif + ++struct vc_mem_dmacopy { ++ void *dst; ++ __u32 src; ++ __u32 length; ++}; ++ ++#ifdef CONFIG_COMPAT ++struct vc_mem_dmacopy32 { ++ compat_uptr_t dst; ++ __u32 src; ++ __u32 length; ++}; ++#endif ++ +/* + * Videocore memory addresses and size + * @@ -47167,6 +64032,20 @@ index 000000000000..195b61a4387c +static uint mem_size; +static uint mem_base; + ++struct vc_mem_dma { ++ struct device *dev; ++ int dma_chan; ++ int dma_irq; ++ void __iomem *dma_chan_base; ++ wait_queue_head_t dma_waitq; ++ void *cb_base; /* DMA control blocks */ ++ dma_addr_t cb_handle; ++}; ++ ++struct { u32 base, length; } gpu_mem; ++static struct mutex dma_mutex; ++static struct vc_mem_dma vc_mem_dma; ++ +static int +vc_mem_open(struct inode *inode, struct file *file) +{ @@ -47204,6 +64083,189 @@ index 000000000000..195b61a4387c +} +EXPORT_SYMBOL_GPL(vc_mem_get_current_size); + ++static int ++vc_mem_dma_init(void) ++{ ++ struct vc_mem_dma *vcdma = &vc_mem_dma; ++ struct platform_device *pdev; ++ struct device_node *fwnode; ++ struct rpi_firmware *fw; ++ struct device *dev; ++ u32 revision; ++ int rc; ++ ++ if (vcdma->dev) ++ return 0; ++ ++ fwnode = of_find_node_by_path("/system"); ++ rc = of_property_read_u32(fwnode, "linux,revision", &revision); ++ revision = (revision >> 12) & 0xf; ++ if (revision != 1 && revision != 2) { ++ /* Only BCM2709 and BCM2710 may have logs where the ARMs ++ * can't see them. ++ */ ++ return -ENXIO; ++ } ++ ++ fwnode = rpi_firmware_find_node(); ++ if (!fwnode) ++ return -ENXIO; ++ ++ pdev = of_find_device_by_node(fwnode); ++ dev = &pdev->dev; ++ ++ rc = dma_coerce_mask_and_coherent(dev, DMA_BIT_MASK(32)); ++ if (rc) ++ return rc; ++ ++ fw = rpi_firmware_get(fwnode); ++ if (!fw) ++ return -ENXIO; ++ rc = rpi_firmware_property(fw, RPI_FIRMWARE_GET_VC_MEMORY, ++ &gpu_mem, sizeof(gpu_mem)); ++ if (rc) ++ return rc; ++ ++ gpu_mem.base = INTALIAS_NORMAL(gpu_mem.base); ++ ++ if (!gpu_mem.base || !gpu_mem.length) { ++ dev_err(dev, "%s: unable to determine gpu memory (%x,%x)\n", ++ __func__, gpu_mem.base, gpu_mem.length); ++ return -EFAULT; ++ } ++ ++ vcdma->cb_base = dma_alloc_wc(dev, SZ_4K, &vcdma->cb_handle, GFP_KERNEL); ++ if (!vcdma->cb_base) { ++ dev_err(dev, "failed to allocate DMA CBs\n"); ++ return -ENOMEM; ++ } ++ ++ rc = bcm_dma_chan_alloc(BCM_DMA_FEATURE_BULK, ++ &vcdma->dma_chan_base, ++ &vcdma->dma_irq); ++ if (rc < 0) { ++ dev_err(dev, "failed to allocate a DMA channel\n"); ++ goto free_cb; ++ } ++ ++ vcdma->dma_chan = rc; ++ ++ init_waitqueue_head(&vcdma->dma_waitq); ++ ++ vcdma->dev = dev; ++ ++ return 0; ++ ++free_cb: ++ dma_free_wc(dev, SZ_4K, vcdma->cb_base, vcdma->cb_handle); ++ ++ return rc; ++} ++ ++static void ++vc_mem_dma_uninit(void) ++{ ++ struct vc_mem_dma *vcdma = &vc_mem_dma; ++ ++ if (vcdma->dev) { ++ bcm_dma_chan_free(vcdma->dma_chan); ++ dma_free_wc(vcdma->dev, SZ_4K, vcdma->cb_base, vcdma->cb_handle); ++ vcdma->dev = NULL; ++ } ++} ++ ++static int dma_memcpy(struct vc_mem_dma *vcdma, dma_addr_t dst, dma_addr_t src, ++ int size) ++{ ++ struct bcm2708_dma_cb *cb = vcdma->cb_base; ++ int burst_size = (vcdma->dma_chan == 0) ? 8 : 2; ++ ++ cb->info = BCM2708_DMA_BURST(burst_size) | BCM2708_DMA_S_WIDTH | ++ BCM2708_DMA_S_INC | BCM2708_DMA_D_WIDTH | ++ BCM2708_DMA_D_INC; ++ cb->dst = dst; ++ cb->src = src; ++ cb->length = size; ++ cb->stride = 0; ++ cb->pad[0] = 0; ++ cb->pad[1] = 0; ++ cb->next = 0; ++ ++ bcm_dma_start(vcdma->dma_chan_base, vcdma->cb_handle); ++ bcm_dma_wait_idle(vcdma->dma_chan_base); ++ ++ return 0; ++} ++ ++static long vc_mem_copy(struct vc_mem_dmacopy *ioparam) ++{ ++ struct vc_mem_dma *vcdma = &vc_mem_dma; ++ size_t size = PAGE_SIZE; ++ const u32 dma_xfer_chunk = 256; ++ u32 *buf = NULL; ++ dma_addr_t bus_addr; ++ long rc = 0; ++ size_t offset; ++ ++ /* restrict this to root user */ ++ if (!uid_eq(current_euid(), GLOBAL_ROOT_UID)) ++ return -EFAULT; ++ ++ if (mutex_lock_interruptible(&dma_mutex)) ++ return -EINTR; ++ ++ rc = vc_mem_dma_init(); ++ if (rc) ++ goto out; ++ ++ vcdma = &vc_mem_dma; ++ ++ if (INTALIAS_NORMAL(ioparam->src) < gpu_mem.base || ++ INTALIAS_NORMAL(ioparam->src) >= gpu_mem.base + gpu_mem.length) { ++ pr_err("%s: invalid memory access %x (%x-%x)", __func__, ++ INTALIAS_NORMAL(ioparam->src), gpu_mem.base, ++ gpu_mem.base + gpu_mem.length); ++ rc = -EFAULT; ++ goto out; ++ } ++ ++ buf = dma_alloc_coherent(vcdma->dev, PAGE_ALIGN(size), &bus_addr, ++ GFP_ATOMIC); ++ if (!buf) { ++ rc = -ENOMEM; ++ goto out; ++ } ++ ++ for (offset = 0; offset < ioparam->length; offset += size) { ++ size_t remaining = ioparam->length - offset; ++ size_t s = min(size, remaining); ++ u8 *p = (u8 *)((uintptr_t)ioparam->src + offset); ++ u8 *q = (u8 *)ioparam->dst + offset; ++ ++ rc = dma_memcpy(vcdma, bus_addr, ++ INTALIAS_L1L2_NONALLOCATING((u32)(uintptr_t)p), ++ (s + dma_xfer_chunk - 1) & ~(dma_xfer_chunk - 1)); ++ if (rc) { ++ dev_err(vcdma->dev, "dma_memcpy failed\n"); ++ break; ++ } ++ if (copy_to_user(q, buf, s) != 0) { ++ pr_err("%s: copy_to_user failed\n", __func__); ++ rc = -EFAULT; ++ break; ++ } ++ } ++ ++out: ++ if (buf) ++ dma_free_coherent(vcdma->dev, PAGE_ALIGN(size), buf, ++ bus_addr); ++ ++ mutex_unlock(&dma_mutex); ++ ++ return rc; ++} ++ +static long +vc_mem_ioctl(struct file *file, unsigned int cmd, unsigned long arg) +{ @@ -47268,6 +64330,21 @@ index 000000000000..195b61a4387c + } + break; + } ++ case VC_MEM_IOC_DMACOPY: ++ { ++ struct vc_mem_dmacopy ioparam; ++ /* Get the parameter data. ++ */ ++ if (copy_from_user ++ (&ioparam, (void *)arg, sizeof(ioparam))) { ++ pr_err("%s: copy_from_user failed\n", __func__); ++ rc = -EFAULT; ++ break; ++ } ++ ++ rc = vc_mem_copy(&ioparam); ++ break; ++ } + default: + { + return -ENOTTY; @@ -47298,6 +64375,24 @@ index 000000000000..195b61a4387c + + break; + ++ case VC_MEM_IOC_DMACOPY32: ++ { ++ struct vc_mem_dmacopy32 param32; ++ struct vc_mem_dmacopy param; ++ /* Get the parameter data. ++ */ ++ if (copy_from_user(¶m32, (void *)arg, sizeof(param32))) { ++ pr_err("%s: copy_from_user failed\n", __func__); ++ rc = -EFAULT; ++ break; ++ } ++ param.dst = compat_ptr(param32.dst); ++ param.src = param32.src; ++ param.length = param32.length; ++ rc = vc_mem_copy(¶m); ++ break; ++ } ++ + default: + rc = vc_mem_ioctl(file, cmd, arg); + break; @@ -47415,7 +64510,7 @@ index 000000000000..195b61a4387c + goto out_unregister; + } + -+ vc_mem_class = class_create(THIS_MODULE, DRIVER_NAME); ++ vc_mem_class = class_create(DRIVER_NAME); + if (IS_ERR(vc_mem_class)) { + rc = PTR_ERR(vc_mem_class); + pr_err("%s: class_create failed (rc=%d)\n", __func__, rc); @@ -47435,6 +64530,7 @@ index 000000000000..195b61a4387c + vc_mem_debugfs_init(dev); +#endif + ++ mutex_init(&dma_mutex); + vc_mem_inited = 1; + return 0; + @@ -47457,14 +64553,16 @@ index 000000000000..195b61a4387c +{ + pr_debug("%s: called\n", __func__); + ++ vc_mem_dma_uninit(); + if (vc_mem_inited) { -+#if CONFIG_DEBUG_FS ++#ifdef CONFIG_DEBUG_FS + vc_mem_debugfs_deinit(); +#endif + device_destroy(vc_mem_class, vc_mem_devnum); + class_destroy(vc_mem_class); + cdev_del(&vc_mem_cdev); + unregister_chrdev_region(vc_mem_devnum, 1); ++ vc_mem_inited = 0; + } +} + @@ -47669,10 +64767,10 @@ index 000000000000..ac314617229c +MODULE_LICENSE("GPL"); +MODULE_ALIAS("platform:rpi-vcio"); diff --git a/drivers/char/hw_random/Kconfig b/drivers/char/hw_random/Kconfig -index dda4a9dfad2e..c66453d718d8 100644 +index 7c486989dd04..4ebc94573195 100644 --- a/drivers/char/hw_random/Kconfig +++ b/drivers/char/hw_random/Kconfig -@@ -104,7 +104,7 @@ config HW_RANDOM_IPROC_RNG200 +@@ -105,7 +105,7 @@ config HW_RANDOM_IPROC_RNG200 default HW_RANDOM help This driver provides kernel-side support for the RNG200 @@ -47682,10 +64780,58 @@ index dda4a9dfad2e..c66453d718d8 100644 To compile this driver as a module, choose M here: the module will be called iproc-rng200 diff --git a/drivers/char/hw_random/bcm2835-rng.c b/drivers/char/hw_random/bcm2835-rng.c -index 1a7c43b43c6b..ee47667d0710 100644 +index 4c08efe7f375..84c964b63324 100644 --- a/drivers/char/hw_random/bcm2835-rng.c +++ b/drivers/char/hw_random/bcm2835-rng.c -@@ -102,8 +102,10 @@ static int bcm2835_rng_init(struct hwrng *rng) +@@ -13,6 +13,7 @@ + #include + #include + #include ++#include + + #define RNG_CTRL 0x0 + #define RNG_STATUS 0x4 +@@ -27,6 +28,9 @@ + + #define RNG_INT_OFF 0x1 + ++#define RNG_FIFO_WORDS 4 ++#define RNG_US_PER_WORD 34 /* Tuned for throughput */ ++ + struct bcm2835_rng_priv { + struct hwrng rng; + void __iomem *base; +@@ -63,19 +67,23 @@ static inline void rng_writel(struct bcm2835_rng_priv *priv, u32 val, + static int bcm2835_rng_read(struct hwrng *rng, void *buf, size_t max, + bool wait) + { ++ u32 retries = 1000000/(RNG_FIFO_WORDS * RNG_US_PER_WORD); + struct bcm2835_rng_priv *priv = to_rng_priv(rng); + u32 max_words = max / sizeof(u32); + u32 num_words, count; + +- while ((rng_readl(priv, RNG_STATUS) >> 24) == 0) { +- if (!wait) ++ num_words = rng_readl(priv, RNG_STATUS) >> 24; ++ ++ while (!num_words) { ++ if (!wait || !retries) + return 0; +- hwrng_yield(rng); ++ retries--; ++ usleep_range((u32)RNG_US_PER_WORD, ++ (u32)RNG_US_PER_WORD * RNG_FIFO_WORDS); ++ num_words = rng_readl(priv, RNG_STATUS) >> 24; + } + +- num_words = rng_readl(priv, RNG_STATUS) >> 24; +- if (num_words > max_words) +- num_words = max_words; ++ num_words = min(num_words, max_words); + + for (count = 0; count < num_words; count++) + ((u32 *)buf)[count] = rng_readl(priv, RNG_DATA); +@@ -105,8 +113,10 @@ static int bcm2835_rng_init(struct hwrng *rng) } /* set warm-up count & enable */ @@ -47699,18 +64845,26 @@ index 1a7c43b43c6b..ee47667d0710 100644 return ret; } diff --git a/drivers/char/hw_random/iproc-rng200.c b/drivers/char/hw_random/iproc-rng200.c -index 01583faf9893..2a92ea658096 100644 +index 440fe28bddc0..33bc28f429f6 100644 --- a/drivers/char/hw_random/iproc-rng200.c +++ b/drivers/char/hw_random/iproc-rng200.c -@@ -29,6 +29,7 @@ +@@ -13,6 +13,7 @@ + #include + #include + #include ++#include + #include + #include + +@@ -20,6 +21,7 @@ + #define RNG_CTRL_OFFSET 0x00 #define RNG_CTRL_RNG_RBGEN_MASK 0x00001FFF #define RNG_CTRL_RNG_RBGEN_ENABLE 0x00000001 - #define RNG_CTRL_RNG_RBGEN_DISABLE 0x00000000 +#define RNG_CTRL_RNG_DIV_CTRL_SHIFT 13 #define RNG_SOFT_RESET_OFFSET 0x04 #define RNG_SOFT_RESET 0x00000001 -@@ -36,16 +37,23 @@ +@@ -27,16 +29,23 @@ #define RBG_SOFT_RESET_OFFSET 0x08 #define RBG_SOFT_RESET 0x00000001 @@ -47734,7 +64888,7 @@ index 01583faf9893..2a92ea658096 100644 struct iproc_rng200_dev { struct hwrng rng; -@@ -166,6 +174,64 @@ static int iproc_rng200_init(struct hwrng *rng) +@@ -157,6 +166,64 @@ static int iproc_rng200_init(struct hwrng *rng) return 0; } @@ -47799,9 +64953,9 @@ index 01583faf9893..2a92ea658096 100644 static void iproc_rng200_cleanup(struct hwrng *rng) { struct iproc_rng200_dev *priv = to_rng_priv(rng); -@@ -195,11 +261,17 @@ static int iproc_rng200_probe(struct platform_device *pdev) - return PTR_ERR(priv->base); - } +@@ -183,11 +250,17 @@ static int iproc_rng200_probe(struct platform_device *pdev) + + dev_set_drvdata(dev, priv); - priv->rng.name = "iproc-rng200"; - priv->rng.read = iproc_rng200_read; @@ -47820,11 +64974,348 @@ index 01583faf9893..2a92ea658096 100644 /* Register driver */ ret = devm_hwrng_register(dev, &priv->rng); if (ret) { +diff --git a/drivers/char/random.c b/drivers/char/random.c +index b9ae54c243a9..09a441d24065 100644 +--- a/drivers/char/random.c ++++ b/drivers/char/random.c +@@ -843,6 +843,14 @@ void __init random_init_early(const char *command_line) + unsigned long entropy[BLAKE2S_BLOCK_SIZE / sizeof(long)]; + size_t i, longs, arch_bits; + ++ /* ++ * If we were initialized by the bootloader before jump labels are ++ * initialized, then we should enable the static branch here, where ++ * it's guaranteed that jump labels have been initialized. ++ */ ++ if (!static_branch_likely(&crng_is_ready) && crng_init >= CRNG_READY) ++ crng_set_ready(NULL); ++ + #if defined(LATENT_ENTROPY_PLUGIN) + static const u8 compiletime_seed[BLAKE2S_BLOCK_SIZE] __initconst __latent_entropy; + _mix_pool_bytes(compiletime_seed, sizeof(compiletime_seed)); +diff --git a/drivers/char/raspberrypi-gpiomem.c b/drivers/char/raspberrypi-gpiomem.c +new file mode 100644 +index 000000000000..8606f39a1434 +--- /dev/null ++++ b/drivers/char/raspberrypi-gpiomem.c +@@ -0,0 +1,276 @@ ++// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause ++/** ++ * raspberrypi-gpiomem.c ++ * ++ * Provides MMIO access to discontiguous section of Device memory as a linear ++ * user mapping. Successor to bcm2835-gpiomem.c. ++ * ++ * Copyright (c) 2023, Raspberry Pi Ltd. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define DRIVER_NAME "rpi-gpiomem" ++#define DEVICE_MINOR 0 ++ ++/* ++ * Sensible max for a hypothetical "gpio" controller that splits pads, ++ * IO controls, GPIO in/out/enable, and function selection into different ++ * ranges. Most use only one or two. ++ */ ++#define MAX_RANGES 4 ++ ++struct io_windows { ++ unsigned long phys_base; ++ unsigned long len; ++}; ++ ++struct rpi_gpiomem_priv { ++ dev_t devid; ++ struct class *class; ++ struct cdev rpi_gpiomem_cdev; ++ struct device *dev; ++ const char *name; ++ unsigned int nr_wins; ++ struct io_windows iowins[4]; ++}; ++ ++static int rpi_gpiomem_open(struct inode *inode, struct file *file) ++{ ++ int dev = iminor(inode); ++ int ret = 0; ++ struct rpi_gpiomem_priv *priv; ++ ++ if (dev != DEVICE_MINOR) ++ ret = -ENXIO; ++ ++ priv = container_of(inode->i_cdev, struct rpi_gpiomem_priv, ++ rpi_gpiomem_cdev); ++ if (!priv) ++ return -EINVAL; ++ file->private_data = priv; ++ return ret; ++} ++ ++static int rpi_gpiomem_release(struct inode *inode, struct file *file) ++{ ++ int dev = iminor(inode); ++ int ret = 0; ++ ++ if (dev != DEVICE_MINOR) ++ ret = -ENXIO; ++ ++ return ret; ++} ++ ++static const struct vm_operations_struct rpi_gpiomem_vm_ops = { ++#ifdef CONFIG_HAVE_IOREMAP_PROT ++ .access = generic_access_phys ++#endif ++}; ++ ++static int rpi_gpiomem_mmap(struct file *file, struct vm_area_struct *vma) ++{ ++ int i; ++ struct rpi_gpiomem_priv *priv; ++ unsigned long base; ++ unsigned long len = 0; ++ unsigned long offset; ++ ++ priv = file->private_data; ++ /* ++ * Userspace must provide a virtual address space at least ++ * the size of the concatenated ranges. ++ */ ++ for (i = 0; i < priv->nr_wins; i++) ++ len += priv->iowins[i].len; ++ if (len > vma->vm_end - vma->vm_start + 1) ++ return -EINVAL; ++ ++ vma->vm_ops = &rpi_gpiomem_vm_ops; ++ offset = vma->vm_start; ++ for (i = 0; i < priv->nr_wins; i++) { ++ base = priv->iowins[i].phys_base >> PAGE_SHIFT; ++ len = priv->iowins[i].len; ++ vma->vm_page_prot = phys_mem_access_prot(file, base, len, ++ vma->vm_page_prot); ++ if (remap_pfn_range(vma, offset, ++ base, len, ++ vma->vm_page_prot)) ++ break; ++ offset += len; ++ } ++ ++ if (i < priv->nr_wins) ++ return -EAGAIN; ++ ++ return 0; ++} ++ ++static const struct file_operations rpi_gpiomem_fops = { ++ .owner = THIS_MODULE, ++ .open = rpi_gpiomem_open, ++ .release = rpi_gpiomem_release, ++ .mmap = rpi_gpiomem_mmap, ++}; ++ ++static const struct of_device_id rpi_gpiomem_of_match[]; ++ ++static int rpi_gpiomem_probe(struct platform_device *pdev) ++{ ++ int err, i; ++ const struct of_device_id *id; ++ struct device *dev = &pdev->dev; ++ struct device_node *node = dev->of_node; ++ struct resource *ioresource; ++ struct rpi_gpiomem_priv *priv; ++ ++ /* Allocate buffers and instance data */ ++ ++ priv = kzalloc(sizeof(struct rpi_gpiomem_priv), GFP_KERNEL); ++ ++ if (!priv) { ++ err = -ENOMEM; ++ goto failed_inst_alloc; ++ } ++ platform_set_drvdata(pdev, priv); ++ ++ priv->dev = dev; ++ id = of_match_device(rpi_gpiomem_of_match, dev); ++ if (!id) ++ return -EINVAL; ++ ++ /* ++ * Device node naming - for legacy (bcm2835) DT bindings, the driver ++ * created the node based on a hardcoded name - for new bindings, ++ * take the node name from DT. ++ */ ++ if (id == &rpi_gpiomem_of_match[0]) { ++ priv->name = "gpiomem"; ++ } else { ++ err = of_property_read_string(node, "chardev-name", &priv->name); ++ if (err) ++ return -EINVAL; ++ } ++ ++ /* ++ * Go find the register ranges associated with this instance ++ */ ++ for (i = 0; i < MAX_RANGES; i++) { ++ ioresource = platform_get_resource(pdev, IORESOURCE_MEM, i); ++ if (!ioresource && i == 0) { ++ dev_err(priv->dev, "failed to get IO resource - no ranges available\n"); ++ err = -ENOENT; ++ goto failed_get_resource; ++ } ++ if (!ioresource) ++ break; ++ ++ priv->iowins[i].phys_base = ioresource->start; ++ priv->iowins[i].len = (ioresource->end + 1) - ioresource->start; ++ dev_info(&pdev->dev, "window base 0x%08lx size 0x%08lx\n", ++ priv->iowins[i].phys_base, priv->iowins[i].len); ++ priv->nr_wins++; ++ } ++ ++ /* Create character device entries */ ++ ++ err = alloc_chrdev_region(&priv->devid, ++ DEVICE_MINOR, 1, priv->name); ++ if (err != 0) { ++ dev_err(priv->dev, "unable to allocate device number"); ++ goto failed_alloc_chrdev; ++ } ++ cdev_init(&priv->rpi_gpiomem_cdev, &rpi_gpiomem_fops); ++ priv->rpi_gpiomem_cdev.owner = THIS_MODULE; ++ err = cdev_add(&priv->rpi_gpiomem_cdev, priv->devid, 1); ++ if (err != 0) { ++ dev_err(priv->dev, "unable to register device"); ++ goto failed_cdev_add; ++ } ++ ++ /* Create sysfs entries */ ++ ++ priv->class = class_create(priv->name); ++ if (IS_ERR(priv->class)) { ++ err = PTR_ERR(priv->class); ++ goto failed_class_create; ++ } ++ ++ dev = device_create(priv->class, NULL, priv->devid, NULL, priv->name); ++ if (IS_ERR(dev)) { ++ err = PTR_ERR(dev); ++ goto failed_device_create; ++ } ++ ++ dev_info(priv->dev, "initialised %u regions as /dev/%s\n", ++ priv->nr_wins, priv->name); ++ ++ return 0; ++ ++failed_device_create: ++ class_destroy(priv->class); ++failed_class_create: ++ cdev_del(&priv->rpi_gpiomem_cdev); ++failed_cdev_add: ++ unregister_chrdev_region(priv->devid, 1); ++failed_alloc_chrdev: ++failed_get_resource: ++ kfree(priv); ++failed_inst_alloc: ++ dev_err(&pdev->dev, "could not load rpi_gpiomem"); ++ return err; ++} ++ ++static int rpi_gpiomem_remove(struct platform_device *pdev) ++{ ++ struct device *dev = &pdev->dev; ++ struct rpi_gpiomem_priv *priv = platform_get_drvdata(pdev); ++ ++ device_destroy(priv->class, priv->devid); ++ class_destroy(priv->class); ++ cdev_del(&priv->rpi_gpiomem_cdev); ++ unregister_chrdev_region(priv->devid, 1); ++ kfree(priv); ++ ++ dev_info(dev, "%s driver removed - OK", priv->name); ++ return 0; ++} ++ ++static const struct of_device_id rpi_gpiomem_of_match[] = { ++ { ++ .compatible = "brcm,bcm2835-gpiomem", ++ }, ++ { ++ .compatible = "raspberrypi,gpiomem", ++ }, ++ { /* sentinel */ }, ++}; ++ ++MODULE_DEVICE_TABLE(of, rpi_gpiomem_of_match); ++ ++static struct platform_driver rpi_gpiomem_driver = { ++ .probe = rpi_gpiomem_probe, ++ .remove = rpi_gpiomem_remove, ++ .driver = { ++ .name = DRIVER_NAME, ++ .owner = THIS_MODULE, ++ .of_match_table = rpi_gpiomem_of_match, ++ }, ++}; ++ ++module_platform_driver(rpi_gpiomem_driver); ++ ++MODULE_ALIAS("platform:rpi-gpiomem"); ++MODULE_LICENSE("Dual BSD/GPL"); ++MODULE_DESCRIPTION("Driver for accessing GPIOs from userspace"); ++MODULE_AUTHOR("Jonathan Bell "); +diff --git a/drivers/char/tpm/tpm_tis_spi_main.c b/drivers/char/tpm/tpm_tis_spi_main.c +index c5c3197ee29f..02700cb16f90 100644 +--- a/drivers/char/tpm/tpm_tis_spi_main.c ++++ b/drivers/char/tpm/tpm_tis_spi_main.c +@@ -347,7 +347,11 @@ static struct spi_driver tpm_tis_spi_driver = { + .pm = &tpm_tis_pm, + .of_match_table = of_match_ptr(of_tis_spi_match), + .acpi_match_table = ACPI_PTR(acpi_tis_spi_match), ++#ifdef CONFIG_IMA ++ .probe_type = PROBE_FORCE_SYNCHRONOUS, ++#else + .probe_type = PROBE_PREFER_ASYNCHRONOUS, ++#endif + }, + .probe = tpm_tis_spi_driver_probe, + .remove = tpm_tis_spi_remove, diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig -index c715d4681a0b..32f8921307bd 100644 +index c30099866174..9d3e03565ed6 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig -@@ -86,6 +86,12 @@ config COMMON_CLK_HI655X +@@ -88,6 +88,19 @@ config COMMON_CLK_RK808 + These multi-function devices have two fixed-rate oscillators, clocked at 32KHz each. + Clkout1 is always on, Clkout2 can off by control register. + ++config COMMON_CLK_RP1 ++ tristate "Raspberry Pi RP1-based clock support" ++ depends on PCI || COMPILE_TEST ++ depends on COMMON_CLK ++ help ++ Enable common clock framework support for Raspberry Pi RP1 ++ ++config COMMON_CLK_RP1_SDIO ++ tristate "Clock driver for the RP1 SDIO interfaces" ++ depends on MFD_RP1 ++ help ++ SDIO clock driver for the RP1 support chip ++ + config COMMON_CLK_HI655X + tristate "Clock driver for Hi655x" if EXPERT + depends on (MFD_HI655X_PMIC || COMPILE_TEST) +@@ -98,6 +111,12 @@ config COMMON_CLK_HI655X multi-function device has one fixed-rate oscillator, clocked at 32KHz. @@ -47838,31 +65329,32 @@ index c715d4681a0b..32f8921307bd 100644 tristate "Clock driver controlled via SCMI interface" depends on ARM_SCMI_PROTOCOL || COMPILE_TEST diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile -index da8fcf147eb1..f78099e1d9e7 100644 +index 18969cbd4bb1..0cec77182970 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile -@@ -18,6 +18,7 @@ endif - - # hardware specific clock types - # please keep this section sorted lexicographically by file path name -+obj-$(CONFIG_SND_BCM2708_SOC_ALLO_BOSS_DAC) += clk-allo-dac.o - obj-$(CONFIG_MACH_ASM9260) += clk-asm9260.o - obj-$(CONFIG_COMMON_CLK_AXI_CLKGEN) += clk-axi-clkgen.o - obj-$(CONFIG_ARCH_AXXIA) += clk-axm5516.o -@@ -37,6 +38,8 @@ obj-$(CONFIG_MACH_ASPEED_G6) += clk-ast2600.o - obj-$(CONFIG_ARCH_HIGHBANK) += clk-highbank.o - obj-$(CONFIG_CLK_HSDK) += clk-hsdk-pll.o +@@ -45,6 +45,8 @@ obj-$(CONFIG_COMMON_CLK_LAN966X) += clk-lan966x.o obj-$(CONFIG_COMMON_CLK_LOCHNAGAR) += clk-lochnagar.o + obj-$(CONFIG_MACH_LOONGSON32) += clk-loongson1.o + obj-$(CONFIG_COMMON_CLK_LOONGSON2) += clk-loongson2.o +obj-$(CONFIG_COMMON_CLK_HIFIBERRY_DACPRO) += clk-hifiberry-dacpro.o +obj-$(CONFIG_COMMON_CLK_HIFIBERRY_DACPLUSHD) += clk-hifiberry-dachd.o obj-$(CONFIG_COMMON_CLK_MAX77686) += clk-max77686.o obj-$(CONFIG_COMMON_CLK_MAX9485) += clk-max9485.o obj-$(CONFIG_ARCH_MILBEAUT_M10V) += clk-milbeaut.o +@@ -57,6 +59,8 @@ obj-$(CONFIG_CLK_LS1028A_PLLDIG) += clk-plldig.o + obj-$(CONFIG_COMMON_CLK_PWM) += clk-pwm.o + obj-$(CONFIG_CLK_QORIQ) += clk-qoriq.o + obj-$(CONFIG_COMMON_CLK_RK808) += clk-rk808.o ++obj-$(CONFIG_COMMON_CLK_RP1) += clk-rp1.o ++obj-$(CONFIG_COMMON_CLK_RP1_SDIO) += clk-rp1-sdio.o + obj-$(CONFIG_COMMON_CLK_HI655X) += clk-hi655x.o + obj-$(CONFIG_COMMON_CLK_S2MPS11) += clk-s2mps11.o + obj-$(CONFIG_COMMON_CLK_SCMI) += clk-scmi.o diff --git a/drivers/clk/bcm/clk-bcm2835.c b/drivers/clk/bcm/clk-bcm2835.c -index 178886823b90..7e74aafddbf8 100644 +index fb04734afc80..eecb2daa423f 100644 --- a/drivers/clk/bcm/clk-bcm2835.c +++ b/drivers/clk/bcm/clk-bcm2835.c -@@ -35,6 +35,7 @@ +@@ -36,6 +36,7 @@ #include #include #include @@ -47870,7 +65362,7 @@ index 178886823b90..7e74aafddbf8 100644 #define CM_PASSWORD 0x5a000000 -@@ -295,6 +296,8 @@ +@@ -296,6 +297,8 @@ #define SOC_BCM2711 BIT(1) #define SOC_ALL (SOC_BCM2835 | SOC_BCM2711) @@ -47879,7 +65371,7 @@ index 178886823b90..7e74aafddbf8 100644 /* * Names of clocks used within the driver that need to be replaced * with an external parent's name. This array is in the order that -@@ -313,6 +316,7 @@ static const char *const cprman_parent_names[] = { +@@ -314,6 +317,7 @@ static const char *const cprman_parent_names[] = { struct bcm2835_cprman { struct device *dev; void __iomem *regs; @@ -47887,7 +65379,7 @@ index 178886823b90..7e74aafddbf8 100644 spinlock_t regs_lock; /* spinlock for all clocks */ unsigned int soc; -@@ -640,15 +644,17 @@ static int bcm2835_pll_on(struct clk_hw *hw) +@@ -643,15 +647,17 @@ static int bcm2835_pll_on(struct clk_hw *hw) spin_unlock(&cprman->regs_lock); /* Wait for the PLL to lock. */ @@ -47913,8 +65405,8 @@ index 178886823b90..7e74aafddbf8 100644 } cprman_write(cprman, data->a2w_ctrl_reg, -@@ -1011,6 +1017,30 @@ static unsigned long bcm2835_clock_get_rate(struct clk_hw *hw, - return bcm2835_clock_rate_from_divisor(clock, parent_rate, div); +@@ -1039,6 +1045,30 @@ static unsigned long bcm2835_clock_get_rate(struct clk_hw *hw, + return rate; } +static unsigned long bcm2835_clock_get_rate_vpu(struct clk_hw *hw, @@ -47944,7 +65436,7 @@ index 178886823b90..7e74aafddbf8 100644 static void bcm2835_clock_wait_busy(struct bcm2835_clock *clock) { struct bcm2835_cprman *cprman = clock->cprman; -@@ -1069,8 +1099,10 @@ static int bcm2835_clock_on(struct clk_hw *hw) +@@ -1097,8 +1127,10 @@ static int bcm2835_clock_on(struct clk_hw *hw) return 0; } @@ -47957,7 +65449,7 @@ index 178886823b90..7e74aafddbf8 100644 { struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw); struct bcm2835_cprman *cprman = clock->cprman; -@@ -1080,15 +1112,24 @@ static int bcm2835_clock_set_rate(struct clk_hw *hw, +@@ -1108,15 +1140,24 @@ static int bcm2835_clock_set_rate(struct clk_hw *hw, spin_lock(&cprman->regs_lock); @@ -47990,7 +65482,7 @@ index 178886823b90..7e74aafddbf8 100644 ctl |= (div & CM_DIV_FRAC_MASK) ? CM_FRAC : 0; cprman_write(cprman, data->ctl_reg, ctl); -@@ -1099,6 +1140,12 @@ static int bcm2835_clock_set_rate(struct clk_hw *hw, +@@ -1127,6 +1168,12 @@ static int bcm2835_clock_set_rate(struct clk_hw *hw, return 0; } @@ -48003,7 +65495,7 @@ index 178886823b90..7e74aafddbf8 100644 static bool bcm2835_clk_is_pllc(struct clk_hw *hw) { -@@ -1282,6 +1329,7 @@ static const struct clk_ops bcm2835_clock_clk_ops = { +@@ -1310,6 +1357,7 @@ static const struct clk_ops bcm2835_clock_clk_ops = { .unprepare = bcm2835_clock_off, .recalc_rate = bcm2835_clock_get_rate, .set_rate = bcm2835_clock_set_rate, @@ -48011,7 +65503,7 @@ index 178886823b90..7e74aafddbf8 100644 .determine_rate = bcm2835_clock_determine_rate, .set_parent = bcm2835_clock_set_parent, .get_parent = bcm2835_clock_get_parent, -@@ -1299,7 +1347,7 @@ static int bcm2835_vpu_clock_is_on(struct clk_hw *hw) +@@ -1327,7 +1375,7 @@ static int bcm2835_vpu_clock_is_on(struct clk_hw *hw) */ static const struct clk_ops bcm2835_vpu_clock_clk_ops = { .is_prepared = bcm2835_vpu_clock_is_on, @@ -48020,7 +65512,7 @@ index 178886823b90..7e74aafddbf8 100644 .set_rate = bcm2835_clock_set_rate, .determine_rate = bcm2835_clock_determine_rate, .set_parent = bcm2835_clock_set_parent, -@@ -1307,6 +1355,8 @@ static const struct clk_ops bcm2835_vpu_clock_clk_ops = { +@@ -1335,6 +1383,8 @@ static const struct clk_ops bcm2835_vpu_clock_clk_ops = { .debug_init = bcm2835_clock_debug_init, }; @@ -48029,7 +65521,7 @@ index 178886823b90..7e74aafddbf8 100644 static struct clk_hw *bcm2835_register_pll(struct bcm2835_cprman *cprman, const void *data) { -@@ -1324,6 +1374,9 @@ static struct clk_hw *bcm2835_register_pll(struct bcm2835_cprman *cprman, +@@ -1352,6 +1402,9 @@ static struct clk_hw *bcm2835_register_pll(struct bcm2835_cprman *cprman, init.ops = &bcm2835_pll_clk_ops; init.flags = pll_data->flags | CLK_IGNORE_UNUSED; @@ -48039,7 +65531,7 @@ index 178886823b90..7e74aafddbf8 100644 pll = kzalloc(sizeof(*pll), GFP_KERNEL); if (!pll) return NULL; -@@ -1379,6 +1432,13 @@ bcm2835_register_pll_divider(struct bcm2835_cprman *cprman, +@@ -1407,6 +1460,13 @@ bcm2835_register_pll_divider(struct bcm2835_cprman *cprman, divider->div.hw.init = &init; divider->div.table = NULL; @@ -48053,7 +65545,7 @@ index 178886823b90..7e74aafddbf8 100644 divider->cprman = cprman; divider->data = divider_data; -@@ -1432,6 +1492,15 @@ static struct clk_hw *bcm2835_register_clock(struct bcm2835_cprman *cprman, +@@ -1460,6 +1520,15 @@ static struct clk_hw *bcm2835_register_clock(struct bcm2835_cprman *cprman, init.name = clock_data->name; init.flags = clock_data->flags | CLK_IGNORE_UNUSED; @@ -48069,7 +65561,7 @@ index 178886823b90..7e74aafddbf8 100644 /* * Pass the CLK_SET_RATE_PARENT flag if we are allowed to propagate * rate changes on at least of the parents. -@@ -1443,7 +1512,6 @@ static struct clk_hw *bcm2835_register_clock(struct bcm2835_cprman *cprman, +@@ -1471,7 +1540,6 @@ static struct clk_hw *bcm2835_register_clock(struct bcm2835_cprman *cprman, init.ops = &bcm2835_vpu_clock_clk_ops; } else { init.ops = &bcm2835_clock_clk_ops; @@ -48077,7 +65569,7 @@ index 178886823b90..7e74aafddbf8 100644 /* If the clock wasn't actually enabled at boot, it's not * critical. -@@ -1668,16 +1736,12 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { +@@ -1696,16 +1764,12 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { .hold_mask = CM_PLLA_HOLDCORE, .fixed_divider = 1, .flags = CLK_SET_RATE_PARENT), @@ -48100,7 +65592,7 @@ index 178886823b90..7e74aafddbf8 100644 [BCM2835_PLLA_DSI0] = REGISTER_PLL_DIV( SOC_ALL, .name = "plla_dsi0", -@@ -1978,14 +2042,12 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { +@@ -2006,14 +2070,12 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { .int_bits = 6, .frac_bits = 0, .tcnt_mux = 3), @@ -48121,9 +65613,9 @@ index 178886823b90..7e74aafddbf8 100644 /* * VPU clock. This doesn't have an enable bit, since it drives * the bus for everything else, and is special so it doesn't need -@@ -2147,21 +2209,6 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { - .frac_bits = 12, - .tcnt_mux = 28), +@@ -2176,21 +2238,6 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { + .tcnt_mux = 28, + .round_up = true), - /* TV encoder clock. Only operating frequency is 108Mhz. */ - [BCM2835_CLOCK_VEC] = REGISTER_PER_CLK( @@ -48143,7 +65635,7 @@ index 178886823b90..7e74aafddbf8 100644 /* dsi clocks */ [BCM2835_CLOCK_DSI0E] = REGISTER_PER_CLK( SOC_ALL, -@@ -2211,6 +2258,8 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { +@@ -2240,6 +2287,8 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { .ctl_reg = CM_PERIICTL), }; @@ -48152,7 +65644,7 @@ index 178886823b90..7e74aafddbf8 100644 /* * Permanently take a reference on the parent of the SDRAM clock. * -@@ -2230,6 +2279,21 @@ static int bcm2835_mark_sdc_parent_critical(struct clk *sdc) +@@ -2259,6 +2308,21 @@ static int bcm2835_mark_sdc_parent_critical(struct clk *sdc) return clk_prepare_enable(parent); } @@ -48174,7 +65666,7 @@ index 178886823b90..7e74aafddbf8 100644 static int bcm2835_clk_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; -@@ -2238,7 +2302,9 @@ static int bcm2835_clk_probe(struct platform_device *pdev) +@@ -2267,7 +2331,9 @@ static int bcm2835_clk_probe(struct platform_device *pdev) const struct bcm2835_clk_desc *desc; const size_t asize = ARRAY_SIZE(clk_desc_array); const struct cprman_plat_data *pdata; @@ -48184,7 +65676,7 @@ index 178886823b90..7e74aafddbf8 100644 int ret; pdata = of_device_get_match_data(&pdev->dev); -@@ -2257,6 +2323,21 @@ static int bcm2835_clk_probe(struct platform_device *pdev) +@@ -2286,6 +2352,21 @@ static int bcm2835_clk_probe(struct platform_device *pdev) if (IS_ERR(cprman->regs)) return PTR_ERR(cprman->regs); @@ -48206,7 +65698,7 @@ index 178886823b90..7e74aafddbf8 100644 memcpy(cprman->real_parent_names, cprman_parent_names, sizeof(cprman_parent_names)); of_clk_parent_fill(dev->of_node, cprman->real_parent_names, -@@ -2290,8 +2371,15 @@ static int bcm2835_clk_probe(struct platform_device *pdev) +@@ -2319,8 +2400,15 @@ static int bcm2835_clk_probe(struct platform_device *pdev) if (ret) return ret; @@ -48223,7 +65715,7 @@ index 178886823b90..7e74aafddbf8 100644 } static const struct cprman_plat_data cprman_bcm2835_plat_data = { -@@ -2317,7 +2405,11 @@ static struct platform_driver bcm2835_clk_driver = { +@@ -2346,7 +2434,15 @@ static struct platform_driver bcm2835_clk_driver = { .probe = bcm2835_clk_probe, }; @@ -48232,31 +65724,72 @@ index 178886823b90..7e74aafddbf8 100644 +{ + return platform_driver_register(&bcm2835_clk_driver); +} ++#ifdef CONFIG_IMA ++subsys_initcall(__bcm2835_clk_driver_init); ++#else +postcore_initcall(__bcm2835_clk_driver_init); ++#endif MODULE_AUTHOR("Eric Anholt "); MODULE_DESCRIPTION("BCM2835 clock driver"); diff --git a/drivers/clk/bcm/clk-raspberrypi.c b/drivers/clk/bcm/clk-raspberrypi.c -index f89b9cfc4309..c307e054f805 100644 +index 829406dc44a2..9b331f249a98 100644 --- a/drivers/clk/bcm/clk-raspberrypi.c +++ b/drivers/clk/bcm/clk-raspberrypi.c -@@ -33,6 +33,7 @@ enum rpi_firmware_clk_id { - RPI_FIRMWARE_EMMC2_CLK_ID, - RPI_FIRMWARE_M2MC_CLK_ID, - RPI_FIRMWARE_PIXEL_BVB_CLK_ID, -+ RPI_FIRMWARE_VEC_CLK_ID, - RPI_FIRMWARE_NUM_CLK_ID, - }; - -@@ -51,6 +52,7 @@ static char *rpi_firmware_clk_names[] = { - [RPI_FIRMWARE_EMMC2_CLK_ID] = "emmc2", +@@ -34,6 +34,7 @@ static char *rpi_firmware_clk_names[] = { [RPI_FIRMWARE_M2MC_CLK_ID] = "m2mc", [RPI_FIRMWARE_PIXEL_BVB_CLK_ID] = "pixel-bvb", -+ [RPI_FIRMWARE_VEC_CLK_ID] = "vec", + [RPI_FIRMWARE_VEC_CLK_ID] = "vec", ++ [RPI_FIRMWARE_DISP_CLK_ID] = "disp", }; #define RPI_FIRMWARE_STATE_ENABLE_BIT BIT(0) -@@ -97,7 +99,7 @@ static int raspberrypi_clock_property(struct rpi_firmware *firmware, +@@ -56,6 +57,12 @@ struct raspberrypi_clk_data { + struct raspberrypi_clk *rpi; + }; + ++static inline ++const struct raspberrypi_clk_data *clk_hw_to_data(const struct clk_hw *hw) ++{ ++ return container_of(hw, struct raspberrypi_clk_data, hw); ++} ++ + struct raspberrypi_clk_variant { + bool export; + char *clkdev; +@@ -111,18 +118,31 @@ raspberrypi_clk_variants[RPI_FIRMWARE_NUM_CLK_ID] = { + }, + [RPI_FIRMWARE_V3D_CLK_ID] = { + .export = true, ++ .minimize = true, + }, + [RPI_FIRMWARE_PIXEL_CLK_ID] = { + .export = true, ++ .minimize = true, + }, + [RPI_FIRMWARE_HEVC_CLK_ID] = { + .export = true, ++ .minimize = true, ++ }, ++ [RPI_FIRMWARE_ISP_CLK_ID] = { ++ .export = true, ++ .minimize = true, + }, + [RPI_FIRMWARE_PIXEL_BVB_CLK_ID] = { + .export = true, ++ .minimize = true, + }, + [RPI_FIRMWARE_VEC_CLK_ID] = { + .export = true, ++ .minimize = true, ++ }, ++ [RPI_FIRMWARE_DISP_CLK_ID] = { ++ .export = true, ++ .minimize = true, + }, + }; + +@@ -153,7 +173,7 @@ static int raspberrypi_clock_property(struct rpi_firmware *firmware, struct raspberrypi_firmware_prop msg = { .id = cpu_to_le32(data->id), .val = cpu_to_le32(*val), @@ -48265,190 +65798,52 @@ index f89b9cfc4309..c307e054f805 100644 }; int ret; -@@ -271,7 +273,10 @@ static int raspberrypi_discover_clocks(struct raspberrypi_clk *rpi, - case RPI_FIRMWARE_CORE_CLK_ID: - case RPI_FIRMWARE_M2MC_CLK_ID: - case RPI_FIRMWARE_V3D_CLK_ID: -+ case RPI_FIRMWARE_HEVC_CLK_ID: - case RPI_FIRMWARE_PIXEL_BVB_CLK_ID: -+ case RPI_FIRMWARE_VEC_CLK_ID: -+ case RPI_FIRMWARE_PIXEL_CLK_ID: - hw = raspberrypi_clk_register(rpi, clks->parent, - clks->id); - if (IS_ERR(hw)) -diff --git a/drivers/clk/clk-allo-dac.c b/drivers/clk/clk-allo-dac.c -new file mode 100644 -index 000000000000..a9844cb9454b ---- /dev/null -+++ b/drivers/clk/clk-allo-dac.c -@@ -0,0 +1,161 @@ -+/* -+ * Clock Driver for Allo DAC -+ * -+ * Author: Baswaraj K -+ * Copyright 2016 -+ * based on code by Stuart MacLean -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * version 2 as published by the Free Software Foundation. -+ * -+ * This program is distributed in the hope that it will be useful, but -+ * WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -+ * General Public License for more details. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+/* Clock rate of CLK44EN attached to GPIO6 pin */ -+#define CLK_44EN_RATE 45158400UL -+/* Clock rate of CLK48EN attached to GPIO3 pin */ -+#define CLK_48EN_RATE 49152000UL -+ -+/** -+ * struct allo_dac_clk - Common struct to the Allo DAC -+ * @hw: clk_hw for the common clk framework -+ * @mode: 0 => CLK44EN, 1 => CLK48EN -+ */ -+struct clk_allo_hw { -+ struct clk_hw hw; -+ uint8_t mode; -+}; -+ -+#define to_allo_clk(_hw) container_of(_hw, struct clk_allo_hw, hw) -+ -+static const struct of_device_id clk_allo_dac_dt_ids[] = { -+ { .compatible = "allo,dac-clk",}, -+ { } -+}; -+MODULE_DEVICE_TABLE(of, clk_allo_dac_dt_ids); -+ -+static unsigned long clk_allo_dac_recalc_rate(struct clk_hw *hw, -+ unsigned long parent_rate) -+{ -+ return (to_allo_clk(hw)->mode == 0) ? CLK_44EN_RATE : -+ CLK_48EN_RATE; -+} -+ -+static long clk_allo_dac_round_rate(struct clk_hw *hw, -+ unsigned long rate, unsigned long *parent_rate) -+{ -+ long actual_rate; -+ -+ if (rate <= CLK_44EN_RATE) { -+ actual_rate = (long)CLK_44EN_RATE; -+ } else if (rate >= CLK_48EN_RATE) { -+ actual_rate = (long)CLK_48EN_RATE; -+ } else { -+ long diff44Rate = (long)(rate - CLK_44EN_RATE); -+ long diff48Rate = (long)(CLK_48EN_RATE - rate); -+ -+ if (diff44Rate < diff48Rate) -+ actual_rate = (long)CLK_44EN_RATE; -+ else -+ actual_rate = (long)CLK_48EN_RATE; -+ } -+ return actual_rate; -+} -+ -+ -+static int clk_allo_dac_set_rate(struct clk_hw *hw, -+ unsigned long rate, unsigned long parent_rate) -+{ -+ unsigned long actual_rate; -+ struct clk_allo_hw *clk = to_allo_clk(hw); -+ -+ actual_rate = (unsigned long)clk_allo_dac_round_rate(hw, rate, -+ &parent_rate); -+ clk->mode = (actual_rate == CLK_44EN_RATE) ? 0 : 1; -+ return 0; -+} -+ -+ -+const struct clk_ops clk_allo_dac_rate_ops = { -+ .recalc_rate = clk_allo_dac_recalc_rate, -+ .round_rate = clk_allo_dac_round_rate, -+ .set_rate = clk_allo_dac_set_rate, -+}; -+ -+static int clk_allo_dac_probe(struct platform_device *pdev) -+{ -+ int ret; -+ struct clk_allo_hw *proclk; -+ struct clk *clk; -+ struct device *dev; -+ struct clk_init_data init; -+ -+ dev = &pdev->dev; -+ -+ proclk = kzalloc(sizeof(struct clk_allo_hw), GFP_KERNEL); -+ if (!proclk) -+ return -ENOMEM; -+ -+ init.name = "clk-allo-dac"; -+ init.ops = &clk_allo_dac_rate_ops; -+ init.flags = 0; -+ init.parent_names = NULL; -+ init.num_parents = 0; -+ -+ proclk->mode = 0; -+ proclk->hw.init = &init; -+ -+ clk = devm_clk_register(dev, &proclk->hw); -+ if (!IS_ERR(clk)) { -+ ret = of_clk_add_provider(dev->of_node, of_clk_src_simple_get, -+ clk); -+ } else { -+ dev_err(dev, "Fail to register clock driver\n"); -+ kfree(proclk); -+ ret = PTR_ERR(clk); -+ } -+ return ret; -+} -+ -+static int clk_allo_dac_remove(struct platform_device *pdev) -+{ -+ of_clk_del_provider(pdev->dev.of_node); -+ return 0; -+} -+ -+static struct platform_driver clk_allo_dac_driver = { -+ .probe = clk_allo_dac_probe, -+ .remove = clk_allo_dac_remove, -+ .driver = { -+ .name = "clk-allo-dac", -+ .of_match_table = clk_allo_dac_dt_ids, -+ }, -+}; -+ -+static int __init clk_allo_dac_init(void) -+{ -+ return platform_driver_register(&clk_allo_dac_driver); -+} -+core_initcall(clk_allo_dac_init); -+ -+static void __exit clk_allo_dac_exit(void) -+{ -+ platform_driver_unregister(&clk_allo_dac_driver); -+} -+module_exit(clk_allo_dac_exit); -+ -+MODULE_DESCRIPTION("Allo DAC clock driver"); -+MODULE_LICENSE("GPL v2"); -+MODULE_ALIAS("platform:clk-allo-dac"); +@@ -168,8 +188,7 @@ static int raspberrypi_clock_property(struct rpi_firmware *firmware, + + static int raspberrypi_fw_is_prepared(struct clk_hw *hw) + { +- struct raspberrypi_clk_data *data = +- container_of(hw, struct raspberrypi_clk_data, hw); ++ const struct raspberrypi_clk_data *data = clk_hw_to_data(hw); + struct raspberrypi_clk *rpi = data->rpi; + u32 val = 0; + int ret; +@@ -186,8 +205,7 @@ static int raspberrypi_fw_is_prepared(struct clk_hw *hw) + static unsigned long raspberrypi_fw_get_rate(struct clk_hw *hw, + unsigned long parent_rate) + { +- struct raspberrypi_clk_data *data = +- container_of(hw, struct raspberrypi_clk_data, hw); ++ const struct raspberrypi_clk_data *data = clk_hw_to_data(hw); + struct raspberrypi_clk *rpi = data->rpi; + u32 val = 0; + int ret; +@@ -203,8 +221,7 @@ static unsigned long raspberrypi_fw_get_rate(struct clk_hw *hw, + static int raspberrypi_fw_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) + { +- struct raspberrypi_clk_data *data = +- container_of(hw, struct raspberrypi_clk_data, hw); ++ const struct raspberrypi_clk_data *data = clk_hw_to_data(hw); + struct raspberrypi_clk *rpi = data->rpi; + u32 _rate = rate; + int ret; +@@ -221,8 +238,7 @@ static int raspberrypi_fw_set_rate(struct clk_hw *hw, unsigned long rate, + static int raspberrypi_fw_dumb_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) + { +- struct raspberrypi_clk_data *data = +- container_of(hw, struct raspberrypi_clk_data, hw); ++ const struct raspberrypi_clk_data *data = clk_hw_to_data(hw); + struct raspberrypi_clk_variant *variant = data->variant; + + /* diff --git a/drivers/clk/clk-hifiberry-dachd.c b/drivers/clk/clk-hifiberry-dachd.c new file mode 100644 -index 000000000000..ec528a0aef36 +index 000000000000..5280b5100559 --- /dev/null +++ b/drivers/clk/clk-hifiberry-dachd.c -@@ -0,0 +1,333 @@ +@@ -0,0 +1,331 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Clock Driver for HiFiBerry DAC+ HD @@ -48680,8 +66075,7 @@ index 000000000000..ec528a0aef36 +EXPORT_SYMBOL_GPL(hifiberry_pll_regmap); + + -+static int clk_hifiberry_dachd_i2c_probe(struct i2c_client *i2c, -+ const struct i2c_device_id *id) ++static int clk_hifiberry_dachd_i2c_probe(struct i2c_client *i2c) +{ + struct clk_hifiberry_drvdata *hdclk; + int ret = 0; @@ -48747,10 +66141,9 @@ index 000000000000..ec528a0aef36 + return ret; +} + -+static int clk_hifiberry_dachd_i2c_remove(struct i2c_client *i2c) ++static void clk_hifiberry_dachd_i2c_remove(struct i2c_client *i2c) +{ + clk_hifiberry_dachd_remove(&i2c->dev); -+ return 0; +} + +static const struct i2c_device_id clk_hifiberry_dachd_i2c_id[] = { @@ -48784,10 +66177,10 @@ index 000000000000..ec528a0aef36 +MODULE_ALIAS("platform:clk-hifiberry-dachd"); diff --git a/drivers/clk/clk-hifiberry-dacpro.c b/drivers/clk/clk-hifiberry-dacpro.c new file mode 100644 -index 000000000000..9e2634465823 +index 000000000000..25603e75894c --- /dev/null +++ b/drivers/clk/clk-hifiberry-dacpro.c -@@ -0,0 +1,160 @@ +@@ -0,0 +1,181 @@ +/* + * Clock Driver for HiFiBerry DAC Pro + * @@ -48812,10 +66205,12 @@ index 000000000000..9e2634465823 +#include +#include + -+/* Clock rate of CLK44EN attached to GPIO6 pin */ -+#define CLK_44EN_RATE 22579200UL -+/* Clock rate of CLK48EN attached to GPIO3 pin */ -+#define CLK_48EN_RATE 24576000UL ++struct ext_clk_rates { ++ /* Clock rate of CLK44EN attached to GPIO6 pin */ ++ unsigned long clk_44en; ++ /* Clock rate of CLK48EN attached to GPIO3 pin */ ++ unsigned long clk_48en; ++}; + +/** + * struct hifiberry_dacpro_clk - Common struct to the HiFiBerry DAC Pro @@ -48825,12 +66220,24 @@ index 000000000000..9e2634465823 +struct clk_hifiberry_hw { + struct clk_hw hw; + uint8_t mode; ++ struct ext_clk_rates clk_rates; +}; + +#define to_hifiberry_clk(_hw) container_of(_hw, struct clk_hifiberry_hw, hw) + ++static const struct ext_clk_rates hifiberry_dacpro_clks = { ++ .clk_44en = 22579200UL, ++ .clk_48en = 24576000UL, ++}; ++ ++static const struct ext_clk_rates allo_dac_clks = { ++ .clk_44en = 45158400UL, ++ .clk_48en = 49152000UL, ++}; ++ +static const struct of_device_id clk_hifiberry_dacpro_dt_ids[] = { -+ { .compatible = "hifiberry,dacpro-clk",}, ++ { .compatible = "hifiberry,dacpro-clk", &hifiberry_dacpro_clks }, ++ { .compatible = "allo,dac-clk", &allo_dac_clks }, + { } +}; +MODULE_DEVICE_TABLE(of, clk_hifiberry_dacpro_dt_ids); @@ -48838,27 +66245,29 @@ index 000000000000..9e2634465823 +static unsigned long clk_hifiberry_dacpro_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ -+ return (to_hifiberry_clk(hw)->mode == 0) ? CLK_44EN_RATE : -+ CLK_48EN_RATE; ++ struct clk_hifiberry_hw *clk = to_hifiberry_clk(hw); ++ return (clk->mode == 0) ? clk->clk_rates.clk_44en : ++ clk->clk_rates.clk_48en; +} + +static long clk_hifiberry_dacpro_round_rate(struct clk_hw *hw, + unsigned long rate, unsigned long *parent_rate) +{ ++ struct clk_hifiberry_hw *clk = to_hifiberry_clk(hw); + long actual_rate; + -+ if (rate <= CLK_44EN_RATE) { -+ actual_rate = (long)CLK_44EN_RATE; -+ } else if (rate >= CLK_48EN_RATE) { -+ actual_rate = (long)CLK_48EN_RATE; ++ if (rate <= clk->clk_rates.clk_44en) { ++ actual_rate = (long)clk->clk_rates.clk_44en; ++ } else if (rate >= clk->clk_rates.clk_48en) { ++ actual_rate = (long)clk->clk_rates.clk_48en; + } else { -+ long diff44Rate = (long)(rate - CLK_44EN_RATE); -+ long diff48Rate = (long)(CLK_48EN_RATE - rate); ++ long diff44Rate = (long)(rate - clk->clk_rates.clk_44en); ++ long diff48Rate = (long)(clk->clk_rates.clk_48en - rate); + + if (diff44Rate < diff48Rate) -+ actual_rate = (long)CLK_44EN_RATE; ++ actual_rate = (long)clk->clk_rates.clk_44en; + else -+ actual_rate = (long)CLK_48EN_RATE; ++ actual_rate = (long)clk->clk_rates.clk_48en; + } + return actual_rate; +} @@ -48867,12 +66276,12 @@ index 000000000000..9e2634465823 +static int clk_hifiberry_dacpro_set_rate(struct clk_hw *hw, + unsigned long rate, unsigned long parent_rate) +{ -+ unsigned long actual_rate; + struct clk_hifiberry_hw *clk = to_hifiberry_clk(hw); ++ unsigned long actual_rate; + + actual_rate = (unsigned long)clk_hifiberry_dacpro_round_rate(hw, rate, + &parent_rate); -+ clk->mode = (actual_rate == CLK_44EN_RATE) ? 0 : 1; ++ clk->mode = (actual_rate == clk->clk_rates.clk_44en) ? 0 : 1; + return 0; +} + @@ -48885,13 +66294,17 @@ index 000000000000..9e2634465823 + +static int clk_hifiberry_dacpro_probe(struct platform_device *pdev) +{ -+ int ret; ++ const struct of_device_id *of_id; + struct clk_hifiberry_hw *proclk; + struct clk *clk; + struct device *dev; + struct clk_init_data init; ++ int ret; + + dev = &pdev->dev; ++ of_id = of_match_node(clk_hifiberry_dacpro_dt_ids, dev->of_node); ++ if (!of_id) ++ return -EINVAL; + + proclk = kzalloc(sizeof(struct clk_hifiberry_hw), GFP_KERNEL); + if (!proclk) @@ -48905,6 +66318,7 @@ index 000000000000..9e2634465823 + + proclk->mode = 0; + proclk->hw.init = &init; ++ memcpy(&proclk->clk_rates, of_id->data, sizeof(proclk->clk_rates)); + + clk = devm_clk_register(dev, &proclk->hw); + if (!IS_ERR(clk)) { @@ -48948,243 +66362,3045 @@ index 000000000000..9e2634465823 +MODULE_DESCRIPTION("HiFiBerry DAC Pro clock driver"); +MODULE_LICENSE("GPL v2"); +MODULE_ALIAS("platform:clk-hifiberry-dacpro"); -diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c -index b8a0e3d23698..8c10c84098fb 100644 ---- a/drivers/clk/clk.c -+++ b/drivers/clk/clk.c -@@ -77,12 +77,14 @@ struct clk_core { - unsigned int protect_count; - unsigned long min_rate; - unsigned long max_rate; -+ unsigned long default_request_rate; - unsigned long accuracy; - int phase; - struct clk_duty duty; - struct hlist_head children; - struct hlist_node child_node; - struct hlist_head clks; -+ struct list_head pending_requests; - unsigned int notifier_count; - #ifdef CONFIG_DEBUG_FS - struct dentry *dentry; -@@ -105,6 +107,12 @@ struct clk { - struct hlist_node clks_node; - }; - -+struct clk_request { -+ struct list_head list; -+ struct clk *clk; -+ unsigned long rate; +diff --git a/drivers/clk/clk-rp1-sdio.c b/drivers/clk/clk-rp1-sdio.c +new file mode 100644 +index 000000000000..7412e24d34cf +--- /dev/null ++++ b/drivers/clk/clk-rp1-sdio.c +@@ -0,0 +1,600 @@ ++// SPDX-License-Identifier: GPL-2.0-or-later ++/* ++ * SDIO clock driver for RP1 ++ * ++ * Copyright (C) 2023 Raspberry Pi Ltd. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++ ++// Register : MODE ++#define MODE 0x00000000 ++#define MODE_BITS 0x70030000 ++#define MODE_RESET 0x00000000 ++// Field : MODE_STEPS_PER_CYCLE ++#define MODE_STEPS_PER_CYCLE_RESET 0x0 ++#define MODE_STEPS_PER_CYCLE_BITS 0x70000000 ++#define MODE_STEPS_PER_CYCLE_MSB 30 ++#define MODE_STEPS_PER_CYCLE_LSB 28 ++#define MODE_STEPS_PER_CYCLE_VALUE_STEPS_20 0x0 ++#define MODE_STEPS_PER_CYCLE_VALUE_STEPS_10 0x1 ++#define MODE_STEPS_PER_CYCLE_VALUE_STEPS_16 0x2 ++#define MODE_STEPS_PER_CYCLE_VALUE_STEPS_8 0x3 ++#define MODE_STEPS_PER_CYCLE_VALUE_STEPS_12 0x4 ++#define MODE_STEPS_PER_CYCLE_VALUE_STEPS_6 0x5 ++#define MODE_STEPS_PER_CYCLE_VALUE_STEPS_5 0x6 ++#define MODE_STEPS_PER_CYCLE_VALUE_STEPS_4 0x7 ++// Field : MODE_SRC_SEL ++#define MODE_SRC_SEL_RESET 0x0 ++#define MODE_SRC_SEL_BITS 0x00030000 ++#define MODE_SRC_SEL_MSB 17 ++#define MODE_SRC_SEL_LSB 16 ++#define MODE_SRC_SEL_VALUE_STOP 0x0 ++#define MODE_SRC_SEL_VALUE_CLK_ALT_SRC 0x1 ++#define MODE_SRC_SEL_VALUE_PLL_SYS_VCO 0x2 ++#define MODE_SRC_SEL_VALUE_PLL_SYS_VCO_AGAIN 0x3 ++// Register : FROMIP ++#define FROMIP 0x00000004 ++#define FROMIP_BITS 0x0f9713ff ++#define FROMIP_RESET 0x00000000 ++// Field : FROMIP_TUNING_CCLK_SEL ++#define FROMIP_TUNING_CCLK_SEL_RESET 0x0 ++#define FROMIP_TUNING_CCLK_SEL_BITS 0x0f000000 ++#define FROMIP_TUNING_CCLK_SEL_MSB 27 ++#define FROMIP_TUNING_CCLK_SEL_LSB 24 ++// Field : FROMIP_TUNING_CCLK_UPDATE ++#define FROMIP_TUNING_CCLK_UPDATE_RESET 0x0 ++#define FROMIP_TUNING_CCLK_UPDATE_BITS 0x00800000 ++#define FROMIP_TUNING_CCLK_UPDATE_MSB 23 ++#define FROMIP_TUNING_CCLK_UPDATE_LSB 23 ++// Field : FROMIP_SAMPLE_CCLK_SEL ++#define FROMIP_SAMPLE_CCLK_SEL_RESET 0x0 ++#define FROMIP_SAMPLE_CCLK_SEL_BITS 0x00100000 ++#define FROMIP_SAMPLE_CCLK_SEL_MSB 20 ++#define FROMIP_SAMPLE_CCLK_SEL_LSB 20 ++// Field : FROMIP_CLK2CARD_ON ++#define FROMIP_CLK2CARD_ON_RESET 0x0 ++#define FROMIP_CLK2CARD_ON_BITS 0x00040000 ++#define FROMIP_CLK2CARD_ON_MSB 18 ++#define FROMIP_CLK2CARD_ON_LSB 18 ++// Field : FROMIP_CARD_CLK_STABLE ++#define FROMIP_CARD_CLK_STABLE_RESET 0x0 ++#define FROMIP_CARD_CLK_STABLE_BITS 0x00020000 ++#define FROMIP_CARD_CLK_STABLE_MSB 17 ++#define FROMIP_CARD_CLK_STABLE_LSB 17 ++// Field : FROMIP_CARD_CLK_EN ++#define FROMIP_CARD_CLK_EN_RESET 0x0 ++#define FROMIP_CARD_CLK_EN_BITS 0x00010000 ++#define FROMIP_CARD_CLK_EN_MSB 16 ++#define FROMIP_CARD_CLK_EN_LSB 16 ++// Field : FROMIP_CLK_GEN_SEL ++#define FROMIP_CLK_GEN_SEL_RESET 0x0 ++#define FROMIP_CLK_GEN_SEL_BITS 0x00001000 ++#define FROMIP_CLK_GEN_SEL_MSB 12 ++#define FROMIP_CLK_GEN_SEL_LSB 12 ++// Field : FROMIP_FREQ_SEL ++#define FROMIP_FREQ_SEL_RESET 0x000 ++#define FROMIP_FREQ_SEL_BITS 0x000003ff ++#define FROMIP_FREQ_SEL_MSB 9 ++#define FROMIP_FREQ_SEL_LSB 0 ++// Register : LOCAL ++#define LOCAL 0x00000008 ++#define LOCAL_BITS 0x1f9713ff ++#define LOCAL_RESET 0x00000000 ++// Field : LOCAL_TUNING_CCLK_SEL ++#define LOCAL_TUNING_CCLK_SEL_RESET 0x00 ++#define LOCAL_TUNING_CCLK_SEL_BITS 0x1f000000 ++#define LOCAL_TUNING_CCLK_SEL_MSB 28 ++#define LOCAL_TUNING_CCLK_SEL_LSB 24 ++// Field : LOCAL_TUNING_CCLK_UPDATE ++#define LOCAL_TUNING_CCLK_UPDATE_RESET 0x0 ++#define LOCAL_TUNING_CCLK_UPDATE_BITS 0x00800000 ++#define LOCAL_TUNING_CCLK_UPDATE_MSB 23 ++#define LOCAL_TUNING_CCLK_UPDATE_LSB 23 ++// Field : LOCAL_SAMPLE_CCLK_SEL ++#define LOCAL_SAMPLE_CCLK_SEL_RESET 0x0 ++#define LOCAL_SAMPLE_CCLK_SEL_BITS 0x00100000 ++#define LOCAL_SAMPLE_CCLK_SEL_MSB 20 ++#define LOCAL_SAMPLE_CCLK_SEL_LSB 20 ++// Field : LOCAL_CLK2CARD_ON ++#define LOCAL_CLK2CARD_ON_RESET 0x0 ++#define LOCAL_CLK2CARD_ON_BITS 0x00040000 ++#define LOCAL_CLK2CARD_ON_MSB 18 ++#define LOCAL_CLK2CARD_ON_LSB 18 ++// Field : LOCAL_CARD_CLK_STABLE ++#define LOCAL_CARD_CLK_STABLE_RESET 0x0 ++#define LOCAL_CARD_CLK_STABLE_BITS 0x00020000 ++#define LOCAL_CARD_CLK_STABLE_MSB 17 ++#define LOCAL_CARD_CLK_STABLE_LSB 17 ++// Field : LOCAL_CARD_CLK_EN ++#define LOCAL_CARD_CLK_EN_RESET 0x0 ++#define LOCAL_CARD_CLK_EN_BITS 0x00010000 ++#define LOCAL_CARD_CLK_EN_MSB 16 ++#define LOCAL_CARD_CLK_EN_LSB 16 ++// Field : LOCAL_CLK_GEN_SEL ++#define LOCAL_CLK_GEN_SEL_RESET 0x0 ++#define LOCAL_CLK_GEN_SEL_BITS 0x00001000 ++#define LOCAL_CLK_GEN_SEL_MSB 12 ++#define LOCAL_CLK_GEN_SEL_LSB 12 ++#define LOCAL_CLK_GEN_SEL_VALUE_PROGCLOCKMODE 0x0 ++#define LOCAL_CLK_GEN_SEL_VALUE_DIVCLOCKMODE 0x1 ++// Field : LOCAL_FREQ_SEL ++#define LOCAL_FREQ_SEL_RESET 0x000 ++#define LOCAL_FREQ_SEL_BITS 0x000003ff ++#define LOCAL_FREQ_SEL_MSB 9 ++#define LOCAL_FREQ_SEL_LSB 0 ++// Register : USE_LOCAL ++#define USE_LOCAL 0x0000000c ++#define USE_LOCAL_BITS 0x01951001 ++#define USE_LOCAL_RESET 0x00000000 ++// Field : USE_LOCAL_TUNING_CCLK_SEL ++#define USE_LOCAL_TUNING_CCLK_SEL_RESET 0x0 ++#define USE_LOCAL_TUNING_CCLK_SEL_BITS 0x01000000 ++#define USE_LOCAL_TUNING_CCLK_SEL_MSB 24 ++#define USE_LOCAL_TUNING_CCLK_SEL_LSB 24 ++// Field : USE_LOCAL_TUNING_CCLK_UPDATE ++#define USE_LOCAL_TUNING_CCLK_UPDATE_RESET 0x0 ++#define USE_LOCAL_TUNING_CCLK_UPDATE_BITS 0x00800000 ++#define USE_LOCAL_TUNING_CCLK_UPDATE_MSB 23 ++#define USE_LOCAL_TUNING_CCLK_UPDATE_LSB 23 ++// Field : USE_LOCAL_SAMPLE_CCLK_SEL ++#define USE_LOCAL_SAMPLE_CCLK_SEL_RESET 0x0 ++#define USE_LOCAL_SAMPLE_CCLK_SEL_BITS 0x00100000 ++#define USE_LOCAL_SAMPLE_CCLK_SEL_MSB 20 ++#define USE_LOCAL_SAMPLE_CCLK_SEL_LSB 20 ++// Field : USE_LOCAL_CLK2CARD_ON ++#define USE_LOCAL_CLK2CARD_ON_RESET 0x0 ++#define USE_LOCAL_CLK2CARD_ON_BITS 0x00040000 ++#define USE_LOCAL_CLK2CARD_ON_MSB 18 ++#define USE_LOCAL_CLK2CARD_ON_LSB 18 ++// Field : USE_LOCAL_CARD_CLK_EN ++#define USE_LOCAL_CARD_CLK_EN_RESET 0x0 ++#define USE_LOCAL_CARD_CLK_EN_BITS 0x00010000 ++#define USE_LOCAL_CARD_CLK_EN_MSB 16 ++#define USE_LOCAL_CARD_CLK_EN_LSB 16 ++// Field : USE_LOCAL_CLK_GEN_SEL ++#define USE_LOCAL_CLK_GEN_SEL_RESET 0x0 ++#define USE_LOCAL_CLK_GEN_SEL_BITS 0x00001000 ++#define USE_LOCAL_CLK_GEN_SEL_MSB 12 ++#define USE_LOCAL_CLK_GEN_SEL_LSB 12 ++// Field : USE_LOCAL_FREQ_SEL ++#define USE_LOCAL_FREQ_SEL_RESET 0x0 ++#define USE_LOCAL_FREQ_SEL_BITS 0x00000001 ++#define USE_LOCAL_FREQ_SEL_MSB 0 ++#define USE_LOCAL_FREQ_SEL_LSB 0 ++// Register : SD_DELAY ++#define SD_DELAY 0x00000010 ++#define SD_DELAY_BITS 0x0000001f ++#define SD_DELAY_RESET 0x00000000 ++// Field : SD_DELAY_STEPS ++#define SD_DELAY_STEPS_RESET 0x00 ++#define SD_DELAY_STEPS_BITS 0x0000001f ++#define SD_DELAY_STEPS_MSB 4 ++#define SD_DELAY_STEPS_LSB 0 ++// Register : RX_DELAY ++#define RX_DELAY 0x00000014 ++#define RX_DELAY_BITS 0x19f3331f ++#define RX_DELAY_RESET 0x00000000 ++// Field : RX_DELAY_BYPASS ++#define RX_DELAY_BYPASS_RESET 0x0 ++#define RX_DELAY_BYPASS_BITS 0x10000000 ++#define RX_DELAY_BYPASS_MSB 28 ++#define RX_DELAY_BYPASS_LSB 28 ++// Field : RX_DELAY_FAIL_ACTUAL ++#define RX_DELAY_FAIL_ACTUAL_RESET 0x0 ++#define RX_DELAY_FAIL_ACTUAL_BITS 0x08000000 ++#define RX_DELAY_FAIL_ACTUAL_MSB 27 ++#define RX_DELAY_FAIL_ACTUAL_LSB 27 ++// Field : RX_DELAY_ACTUAL ++#define RX_DELAY_ACTUAL_RESET 0x00 ++#define RX_DELAY_ACTUAL_BITS 0x01f00000 ++#define RX_DELAY_ACTUAL_MSB 24 ++#define RX_DELAY_ACTUAL_LSB 20 ++// Field : RX_DELAY_OFFSET ++#define RX_DELAY_OFFSET_RESET 0x0 ++#define RX_DELAY_OFFSET_BITS 0x00030000 ++#define RX_DELAY_OFFSET_MSB 17 ++#define RX_DELAY_OFFSET_LSB 16 ++// Field : RX_DELAY_OVERFLOW ++#define RX_DELAY_OVERFLOW_RESET 0x0 ++#define RX_DELAY_OVERFLOW_BITS 0x00003000 ++#define RX_DELAY_OVERFLOW_MSB 13 ++#define RX_DELAY_OVERFLOW_LSB 12 ++#define RX_DELAY_OVERFLOW_VALUE_ALLOW 0x0 ++#define RX_DELAY_OVERFLOW_VALUE_CLAMP 0x1 ++#define RX_DELAY_OVERFLOW_VALUE_FAIL 0x2 ++// Field : RX_DELAY_MAP ++#define RX_DELAY_MAP_RESET 0x0 ++#define RX_DELAY_MAP_BITS 0x00000300 ++#define RX_DELAY_MAP_MSB 9 ++#define RX_DELAY_MAP_LSB 8 ++#define RX_DELAY_MAP_VALUE_DIRECT 0x0 ++#define RX_DELAY_MAP_VALUE 0x1 ++#define RX_DELAY_MAP_VALUE_STRETCH 0x2 ++// Field : RX_DELAY_FIXED ++#define RX_DELAY_FIXED_RESET 0x00 ++#define RX_DELAY_FIXED_BITS 0x0000001f ++#define RX_DELAY_FIXED_MSB 4 ++#define RX_DELAY_FIXED_LSB 0 ++// Register : NDIV ++#define NDIV 0x00000018 ++#define NDIV_BITS 0x1fff0000 ++#define NDIV_RESET 0x00110000 ++// Field : NDIV_DIVB ++#define NDIV_DIVB_RESET 0x001 ++#define NDIV_DIVB_BITS 0x1ff00000 ++#define NDIV_DIVB_MSB 28 ++#define NDIV_DIVB_LSB 20 ++// Field : NDIV_DIVA ++#define NDIV_DIVA_RESET 0x1 ++#define NDIV_DIVA_BITS 0x000f0000 ++#define NDIV_DIVA_MSB 19 ++#define NDIV_DIVA_LSB 16 ++// Register : CS ++#define CS 0x0000001c ++#define CS_BITS 0x00111101 ++#define CS_RESET 0x00000001 ++// Field : CS_RX_DEL_UPDATED ++#define CS_RX_DEL_UPDATED_RESET 0x0 ++#define CS_RX_DEL_UPDATED_BITS 0x00100000 ++#define CS_RX_DEL_UPDATED_MSB 20 ++#define CS_RX_DEL_UPDATED_LSB 20 ++// Field : CS_RX_CLK_RUNNING ++#define CS_RX_CLK_RUNNING_RESET 0x0 ++#define CS_RX_CLK_RUNNING_BITS 0x00010000 ++#define CS_RX_CLK_RUNNING_MSB 16 ++#define CS_RX_CLK_RUNNING_LSB 16 ++// Field : CS_SD_CLK_RUNNING ++#define CS_SD_CLK_RUNNING_RESET 0x0 ++#define CS_SD_CLK_RUNNING_BITS 0x00001000 ++#define CS_SD_CLK_RUNNING_MSB 12 ++#define CS_SD_CLK_RUNNING_LSB 12 ++// Field : CS_TX_CLK_RUNNING ++#define CS_TX_CLK_RUNNING_RESET 0x0 ++#define CS_TX_CLK_RUNNING_BITS 0x00000100 ++#define CS_TX_CLK_RUNNING_MSB 8 ++#define CS_TX_CLK_RUNNING_LSB 8 ++// Field : CS_RESET ++#define CS_RESET_RESET 0x1 ++#define CS_RESET_BITS 0x00000001 ++#define CS_RESET_MSB 0 ++#define CS_RESET_LSB 0 ++ ++#define FPGA_SRC_RATE 400000000 ++ ++/* Base number of steps to delay in relation to tx clk. ++ * The relationship of the 3 clocks are as follows: ++ * tx_clk: This clock is provided to the controller. Data is sent out ++ * to the pads using this clock. ++ * sd_clk: This clock is sent out to the card. ++ * rx_clk: This clock is used to sample the data coming back from the card. ++ * This may need to be several steps ahead of the tx_clk. The default rx delay ++ * is used as a base delay, and can be further adjusted by the sd host ++ * controller during the tuning process if using a DDR50 or faster SD card ++ */ ++/* ++ * PRJY-1813 - the default SD clock delay needs to be set to ~60% of the total ++ * number of steps to meet tISU (>6ns) and tIH (>2ns) in high-speed mode. ++ * On FPGA this means delay SDCLK by 5, and sample RX with a delay of 6. ++ */ ++#define DEFAULT_RX_DELAY 6 ++#define DEFAULT_SD_DELAY 5 ++ ++struct rp1_sdio_clkgen { ++ struct device *dev; ++ ++ /* Source clock. Either PLL VCO or fixed freq on FPGA */ ++ struct clk *src_clk; ++ /* Desired base frequency. Max freq card can go */ ++ struct clk *base_clk; ++ ++ struct clk_hw hw; ++ void __iomem *regs; ++ ++ /* Starting value of local register before changing freq */ ++ u32 local_base; +}; + - /*** runtime pm ***/ - static int clk_pm_runtime_get(struct clk_core *core) - { -@@ -1308,6 +1316,8 @@ static int clk_core_determine_round_nolock(struct clk_core *core, - if (!core) - return 0; - -+ req->rate = clamp(req->rate, req->min_rate, req->max_rate); -+ - /* - * At this point, core protection will be disabled if - * - if the provider is not protected at all -@@ -1413,10 +1423,14 @@ unsigned long clk_hw_round_rate(struct clk_hw *hw, unsigned long rate) - { - int ret; - struct clk_rate_request req; -+ struct clk_request *clk_req; - - clk_core_get_boundaries(hw->core, &req.min_rate, &req.max_rate); - req.rate = rate; - -+ list_for_each_entry(clk_req, &hw->core->pending_requests, list) -+ req.min_rate = max(clk_req->rate, req.min_rate); -+ - ret = clk_core_round_rate_nolock(hw->core, &req); - if (ret) - return 0; -@@ -1437,6 +1451,7 @@ EXPORT_SYMBOL_GPL(clk_hw_round_rate); - long clk_round_rate(struct clk *clk, unsigned long rate) - { - struct clk_rate_request req; -+ struct clk_request *clk_req; - int ret; - - if (!clk) -@@ -1450,6 +1465,9 @@ long clk_round_rate(struct clk *clk, unsigned long rate) - clk_core_get_boundaries(clk->core, &req.min_rate, &req.max_rate); - req.rate = rate; - -+ list_for_each_entry(clk_req, &clk->core->pending_requests, list) -+ req.min_rate = max(clk_req->rate, req.min_rate); -+ - ret = clk_core_round_rate_nolock(clk->core, &req); - - if (clk->exclusive_count) -@@ -1917,6 +1935,7 @@ static struct clk_core *clk_calc_new_rates(struct clk_core *core, - unsigned long new_rate; - unsigned long min_rate; - unsigned long max_rate; -+ struct clk_request *req; - int p_index = 0; - long ret; - -@@ -1931,6 +1950,9 @@ static struct clk_core *clk_calc_new_rates(struct clk_core *core, - - clk_core_get_boundaries(core, &min_rate, &max_rate); - -+ list_for_each_entry(req, &core->pending_requests, list) -+ min_rate = max(req->rate, min_rate); -+ - /* find the closest rate and parent clk/rate */ - if (clk_core_can_round(core)) { - struct clk_rate_request req; -@@ -2135,6 +2157,7 @@ static unsigned long clk_core_req_round_rate_nolock(struct clk_core *core, - { - int ret, cnt; - struct clk_rate_request req; -+ struct clk_request *clk_req; - - lockdep_assert_held(&prepare_lock); - -@@ -2149,6 +2172,9 @@ static unsigned long clk_core_req_round_rate_nolock(struct clk_core *core, - clk_core_get_boundaries(core, &req.min_rate, &req.max_rate); - req.rate = req_rate; - -+ list_for_each_entry(clk_req, &core->pending_requests, list) -+ req.min_rate = max(clk_req->rate, req.min_rate); -+ - ret = clk_core_round_rate_nolock(core, &req); - - /* restore the protection */ -@@ -2242,6 +2268,9 @@ int clk_set_rate(struct clk *clk, unsigned long rate) - - ret = clk_core_set_rate_nolock(clk->core, rate); - -+ if (!list_empty(&clk->core->pending_requests)) -+ clk->core->default_request_rate = rate; -+ - if (clk->exclusive_count) - clk_core_rate_protect(clk->core); - -@@ -2401,6 +2430,103 @@ int clk_set_max_rate(struct clk *clk, unsigned long rate) - } - EXPORT_SYMBOL_GPL(clk_set_max_rate); - -+/** -+ * clk_request_start - Request a rate to be enforced temporarily -+ * @clk: the clk to act on -+ * @rate: the new rate asked for -+ * -+ * This function will create a request to temporarily increase the rate -+ * of the clock to a given rate to a certain minimum. -+ * -+ * This is meant as a best effort mechanism and while the rate of the -+ * clock will be guaranteed to be equal or higher than the requested -+ * rate, there's none on what the actual rate will be due to other -+ * factors (other requests previously set, clock boundaries, etc.). -+ * -+ * Once the request is marked as done through clk_request_done(), the -+ * rate will be reverted back to what the rate was before the request. -+ * -+ * The reported boundaries of the clock will also be adjusted so that -+ * clk_round_rate() take those requests into account. A call to -+ * clk_set_rate() during a request will affect the rate the clock will -+ * return to after the requests on that clock are done. -+ * -+ * Returns 0 on success, an ERR_PTR otherwise. -+ */ -+struct clk_request *clk_request_start(struct clk *clk, unsigned long rate) ++static inline void clkgen_write(struct rp1_sdio_clkgen *clkgen, u32 reg, u32 val) +{ -+ struct clk_request *req; ++ dev_dbg(clkgen->dev, "%s: write reg 0x%x: 0x%x\n", __func__, reg, val); ++ writel(val, clkgen->regs + reg); ++} ++ ++static inline u32 clkgen_read(struct rp1_sdio_clkgen *clkgen, u32 reg) ++{ ++ u32 val = readl(clkgen->regs + reg); ++ ++ dev_dbg(clkgen->dev, "%s: read reg 0x%x: 0x%x\n", __func__, reg, val); ++ return val; ++} ++ ++static int get_steps(unsigned int steps) ++{ ++ int ret = -1; ++ ++ if (steps == 4) ++ ret = MODE_STEPS_PER_CYCLE_VALUE_STEPS_4; ++ else if (steps == 5) ++ ret = MODE_STEPS_PER_CYCLE_VALUE_STEPS_5; ++ else if (steps == 6) ++ ret = MODE_STEPS_PER_CYCLE_VALUE_STEPS_6; ++ else if (steps == 8) ++ ret = MODE_STEPS_PER_CYCLE_VALUE_STEPS_8; ++ else if (steps == 10) ++ ret = MODE_STEPS_PER_CYCLE_VALUE_STEPS_10; ++ else if (steps == 12) ++ ret = MODE_STEPS_PER_CYCLE_VALUE_STEPS_12; ++ else if (steps == 16) ++ ret = MODE_STEPS_PER_CYCLE_VALUE_STEPS_16; ++ else if (steps == 20) ++ ret = MODE_STEPS_PER_CYCLE_VALUE_STEPS_20; ++ return ret; ++} ++ ++static int rp1_sdio_clk_init(struct rp1_sdio_clkgen *clkgen) ++{ ++ unsigned long src_rate = clk_get_rate(clkgen->src_clk); ++ unsigned long base_rate = clk_get_rate(clkgen->base_clk); ++ unsigned int steps = src_rate / base_rate; ++ u32 reg = 0; ++ int steps_value = 0; ++ ++ dev_dbg(clkgen->dev, "init: src_rate %lu, base_rate %lu, steps %d\n", ++ src_rate, base_rate, steps); ++ ++ /* Assert reset while we set up clkgen */ ++ clkgen_write(clkgen, CS, CS_RESET_BITS); ++ ++ /* Pick clock source */ ++ if (src_rate == FPGA_SRC_RATE) { ++ /* Using ALT SRC */ ++ reg |= MODE_SRC_SEL_VALUE_CLK_ALT_SRC << MODE_SRC_SEL_LSB; ++ } else { ++ /* Assume we are using PLL SYS VCO */ ++ reg |= MODE_SRC_SEL_VALUE_PLL_SYS_VCO << MODE_SRC_SEL_LSB; ++ } ++ ++ /* How many delay steps are available in one cycle for this source */ ++ steps_value = get_steps(steps); ++ if (steps_value < 0) { ++ dev_err(clkgen->dev, "Invalid step value: %d\n", steps); ++ return -EINVAL; ++ } ++ reg |= steps_value << MODE_STEPS_PER_CYCLE_LSB; ++ ++ /* Mode register is done now*/ ++ clkgen_write(clkgen, MODE, reg); ++ ++ /* Now set delay mode */ ++ /* Clamp value if out of range rx delay is used */ ++ reg = RX_DELAY_OVERFLOW_VALUE_CLAMP << RX_DELAY_OVERFLOW_LSB; ++ /* SD tuning bus goes from 0x0 to 0xf but we don't necessarily have that ++ * many steps available depending on the source so map 0x0 -> 0xf to one ++ * cycle of rx delay ++ */ ++ reg |= RX_DELAY_MAP_VALUE_STRETCH << RX_DELAY_MAP_LSB; ++ ++ /* Default RX delay */ ++ dev_dbg(clkgen->dev, "default rx delay %d\n", DEFAULT_RX_DELAY); ++ reg |= (DEFAULT_RX_DELAY & RX_DELAY_FIXED_BITS) << RX_DELAY_FIXED_LSB; ++ clkgen_write(clkgen, RX_DELAY, reg); ++ ++ /* Default SD delay */ ++ dev_dbg(clkgen->dev, "default sd delay %d\n", DEFAULT_SD_DELAY); ++ reg = (DEFAULT_SD_DELAY & SD_DELAY_STEPS_BITS) << SD_DELAY_STEPS_LSB; ++ clkgen_write(clkgen, SD_DELAY, reg); ++ ++ /* We select freq, we turn on tx clock, we turn on sd clk, ++ * we pick clock generator mode ++ */ ++ reg = USE_LOCAL_FREQ_SEL_BITS | USE_LOCAL_CARD_CLK_EN_BITS | ++ USE_LOCAL_CLK2CARD_ON_BITS | USE_LOCAL_CLK_GEN_SEL_BITS; ++ clkgen_write(clkgen, USE_LOCAL, reg); ++ ++ /* Deassert reset. Reset bit is only writable bit of CS ++ * reg so fine to write a 0. ++ */ ++ clkgen_write(clkgen, CS, 0); ++ ++ return 0; ++} ++ ++#define RUNNING \ ++ (CS_TX_CLK_RUNNING_BITS | CS_RX_CLK_RUNNING_BITS | \ ++ CS_SD_CLK_RUNNING_BITS) ++static int rp1_sdio_clk_is_prepared(struct clk_hw *hw) ++{ ++ struct rp1_sdio_clkgen *clkgen = ++ container_of(hw, struct rp1_sdio_clkgen, hw); ++ u32 status; ++ ++ dev_dbg(clkgen->dev, "is_prepared\n"); ++ status = clkgen_read(clkgen, CS); ++ return ((status & RUNNING) == RUNNING); ++} ++ ++/* Can define an additional divider if an sd card isn't working at full speed */ ++/* #define SLOWDOWN 3 */ ++ ++static unsigned long rp1_sdio_clk_get_rate(struct clk_hw *hw, ++ unsigned long parent_rate) ++{ ++ /* Get the current rate */ ++ struct rp1_sdio_clkgen *clkgen = ++ container_of(hw, struct rp1_sdio_clkgen, hw); ++ unsigned long actual_rate = 0; ++ u32 ndiv_diva; ++ u32 ndiv_divb; ++ u32 tmp; ++ u32 div; ++ ++ tmp = clkgen_read(clkgen, LOCAL); ++ if ((tmp & LOCAL_CLK2CARD_ON_BITS) == 0) { ++ dev_dbg(clkgen->dev, "get_rate 0\n"); ++ return 0; ++ } ++ ++ tmp = clkgen_read(clkgen, NDIV); ++ ndiv_diva = (tmp & NDIV_DIVA_BITS) >> NDIV_DIVA_LSB; ++ ndiv_divb = (tmp & NDIV_DIVB_BITS) >> NDIV_DIVB_LSB; ++ div = ndiv_diva * ndiv_divb; ++ actual_rate = (clk_get_rate(clkgen->base_clk) / div); ++ ++#ifdef SLOWDOWN ++ actual_rate *= SLOWDOWN; ++#endif ++ ++ dev_dbg(clkgen->dev, "get_rate. ndiv_diva %d, ndiv_divb %d = %lu\n", ++ ndiv_diva, ndiv_divb, actual_rate); ++ ++ return actual_rate; ++} ++ ++static int rp1_sdio_clk_set_rate(struct clk_hw *hw, unsigned long rate, ++ unsigned long parent_rate) ++{ ++ struct rp1_sdio_clkgen *clkgen = ++ container_of(hw, struct rp1_sdio_clkgen, hw); ++ u32 div; ++ u32 reg; ++ ++ dev_dbg(clkgen->dev, "set_rate %lu\n", rate); ++ ++ if (rate == 0) { ++ /* Keep tx clock running */ ++ clkgen_write(clkgen, LOCAL, LOCAL_CARD_CLK_EN_BITS); ++ return 0; ++ } ++ ++#ifdef SLOWDOWN ++ rate /= SLOWDOWN; ++#endif ++ ++ div = (clk_get_rate(clkgen->base_clk) / rate) - 1; ++ reg = LOCAL_CLK_GEN_SEL_BITS | LOCAL_CARD_CLK_EN_BITS | ++ LOCAL_CLK2CARD_ON_BITS | (div << LOCAL_FREQ_SEL_LSB); ++ clkgen_write(clkgen, LOCAL, reg); ++ ++ return 0; ++} ++ ++#define MAX_NDIV (256 * 8) ++static int rp1_sdio_clk_determine_rate(struct clk_hw *hw, ++ struct clk_rate_request *req) ++{ ++ unsigned long rate; ++ struct rp1_sdio_clkgen *clkgen = ++ container_of(hw, struct rp1_sdio_clkgen, hw); ++ unsigned long base_rate = clk_get_rate(clkgen->base_clk); ++ u32 div; ++ ++ /* What is the actual rate I can get if I request xyz */ ++ if (req->rate) { ++ div = min((u32)(base_rate / req->rate), (u32)MAX_NDIV); ++ rate = base_rate / div; ++ req->rate = rate; ++ dev_dbg(clkgen->dev, "determine_rate %lu: %lu / %d = %lu\n", ++ req->rate, base_rate, div, rate); ++ } else { ++ rate = 0; ++ dev_dbg(clkgen->dev, "determine_rate %lu: %lu\n", req->rate, ++ rate); ++ } ++ ++ return 0; ++} ++ ++static const struct clk_ops rp1_sdio_clk_ops = { ++ .is_prepared = rp1_sdio_clk_is_prepared, ++ .recalc_rate = rp1_sdio_clk_get_rate, ++ .set_rate = rp1_sdio_clk_set_rate, ++ .determine_rate = rp1_sdio_clk_determine_rate, ++}; ++ ++static int rp1_sdio_clk_probe(struct platform_device *pdev) ++{ ++ struct device_node *node = pdev->dev.of_node; ++ struct rp1_sdio_clkgen *clkgen; ++ void __iomem *regs; ++ struct clk_init_data init = {}; + int ret; + -+ if (!clk) -+ return ERR_PTR(-EINVAL); ++ clkgen = devm_kzalloc(&pdev->dev, sizeof(*clkgen), GFP_KERNEL); ++ if (!clkgen) ++ return -ENOMEM; ++ platform_set_drvdata(pdev, clkgen); + -+ req = kzalloc(sizeof(*req), GFP_KERNEL); -+ if (!req) -+ return ERR_PTR(-ENOMEM); ++ clkgen->dev = &pdev->dev; + -+ clk_prepare_lock(); ++ /* Source freq */ ++ clkgen->src_clk = devm_clk_get(&pdev->dev, "src"); ++ if (IS_ERR(clkgen->src_clk)) { ++ int err = PTR_ERR(clkgen->src_clk); + -+ req->clk = clk; -+ req->rate = rate; -+ -+ if (list_empty(&clk->core->pending_requests)) -+ clk->core->default_request_rate = clk_core_get_rate_recalc(clk->core); -+ -+ ret = clk_core_set_rate_nolock(clk->core, rate); -+ if (ret) { -+ clk_prepare_unlock(); -+ kfree(req); -+ return ERR_PTR(ret); ++ dev_err(&pdev->dev, "failed to get src clk: %d\n", err); ++ return err; + } + -+ list_add_tail(&req->list, &clk->core->pending_requests); -+ clk_prepare_unlock(); ++ /* Desired maximum output freq (i.e. base freq) */ ++ clkgen->base_clk = devm_clk_get(&pdev->dev, "base"); ++ if (IS_ERR(clkgen->base_clk)) { ++ int err = PTR_ERR(clkgen->base_clk); + -+ return req; ++ dev_err(&pdev->dev, "failed to get base clk: %d\n", err); ++ return err; ++ } ++ ++ regs = devm_platform_ioremap_resource(pdev, 0); ++ if (IS_ERR(regs)) ++ return PTR_ERR(regs); ++ ++ init.name = node->name; ++ init.ops = &rp1_sdio_clk_ops; ++ init.flags = CLK_GET_RATE_NOCACHE; ++ ++ clkgen->hw.init = &init; ++ clkgen->regs = regs; ++ ++ dev_info(&pdev->dev, "loaded %s\n", init.name); ++ ++ ret = devm_clk_hw_register(&pdev->dev, &clkgen->hw); ++ if (ret) ++ return ret; ++ ++ ret = of_clk_add_hw_provider(node, of_clk_hw_simple_get, &clkgen->hw); ++ if (ret) ++ return ret; ++ ++ ret = rp1_sdio_clk_init(clkgen); ++ return ret; +} -+EXPORT_SYMBOL_GPL(clk_request_start); + -+/** -+ * clk_request_done - Mark a clk_request as done -+ * @req: the request to mark done -+ * -+ * This function will remove the rate request from the clock and adjust -+ * the clock rate back to either to what it was before the request -+ * started, or if there's any other request on that clock to a proper -+ * rate for them. -+ */ -+void clk_request_done(struct clk_request *req) ++static int rp1_sdio_clk_remove(struct platform_device *pdev) +{ -+ struct clk_core *core; ++ return 0; ++} + -+ if (!req) ++static const struct of_device_id rp1_sdio_clk_dt_ids[] = { ++ { .compatible = "raspberrypi,rp1-sdio-clk", }, ++ { /* sentinel */ } ++}; ++MODULE_DEVICE_TABLE(of, rp1_sdio_clk_dt_ids); ++ ++static struct platform_driver rp1_sdio_clk_driver = { ++ .probe = rp1_sdio_clk_probe, ++ .remove = rp1_sdio_clk_remove, ++ .driver = { ++ .name = "rp1-sdio-clk", ++ .of_match_table = rp1_sdio_clk_dt_ids, ++ }, ++}; ++module_platform_driver(rp1_sdio_clk_driver); ++ ++MODULE_AUTHOR("Liam Fraser "); ++MODULE_DESCRIPTION("RP1 SDIO clock driver"); ++MODULE_LICENSE("GPL"); +diff --git a/drivers/clk/clk-rp1.c b/drivers/clk/clk-rp1.c +new file mode 100644 +index 000000000000..b4964babf84a +--- /dev/null ++++ b/drivers/clk/clk-rp1.c +@@ -0,0 +1,2422 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * Copyright (C) 2023 Raspberry Pi Ltd. ++ * ++ * Clock driver for RP1 PCIe multifunction chip. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#include ++ ++#define PLL_SYS_CS 0x08000 ++#define PLL_SYS_PWR 0x08004 ++#define PLL_SYS_FBDIV_INT 0x08008 ++#define PLL_SYS_FBDIV_FRAC 0x0800c ++#define PLL_SYS_PRIM 0x08010 ++#define PLL_SYS_SEC 0x08014 ++ ++#define PLL_AUDIO_CS 0x0c000 ++#define PLL_AUDIO_PWR 0x0c004 ++#define PLL_AUDIO_FBDIV_INT 0x0c008 ++#define PLL_AUDIO_FBDIV_FRAC 0x0c00c ++#define PLL_AUDIO_PRIM 0x0c010 ++#define PLL_AUDIO_SEC 0x0c014 ++#define PLL_AUDIO_TERN 0x0c018 ++ ++#define PLL_VIDEO_CS 0x10000 ++#define PLL_VIDEO_PWR 0x10004 ++#define PLL_VIDEO_FBDIV_INT 0x10008 ++#define PLL_VIDEO_FBDIV_FRAC 0x1000c ++#define PLL_VIDEO_PRIM 0x10010 ++#define PLL_VIDEO_SEC 0x10014 ++ ++#define GPCLK_OE_CTRL 0x00000 ++ ++#define CLK_SYS_CTRL 0x00014 ++#define CLK_SYS_DIV_INT 0x00018 ++#define CLK_SYS_SEL 0x00020 ++ ++#define CLK_SLOW_SYS_CTRL 0x00024 ++#define CLK_SLOW_SYS_DIV_INT 0x00028 ++#define CLK_SLOW_SYS_SEL 0x00030 ++ ++#define CLK_DMA_CTRL 0x00044 ++#define CLK_DMA_DIV_INT 0x00048 ++#define CLK_DMA_SEL 0x00050 ++ ++#define CLK_UART_CTRL 0x00054 ++#define CLK_UART_DIV_INT 0x00058 ++#define CLK_UART_SEL 0x00060 ++ ++#define CLK_ETH_CTRL 0x00064 ++#define CLK_ETH_DIV_INT 0x00068 ++#define CLK_ETH_SEL 0x00070 ++ ++#define CLK_PWM0_CTRL 0x00074 ++#define CLK_PWM0_DIV_INT 0x00078 ++#define CLK_PWM0_DIV_FRAC 0x0007c ++#define CLK_PWM0_SEL 0x00080 ++ ++#define CLK_PWM1_CTRL 0x00084 ++#define CLK_PWM1_DIV_INT 0x00088 ++#define CLK_PWM1_DIV_FRAC 0x0008c ++#define CLK_PWM1_SEL 0x00090 ++ ++#define CLK_AUDIO_IN_CTRL 0x00094 ++#define CLK_AUDIO_IN_DIV_INT 0x00098 ++#define CLK_AUDIO_IN_SEL 0x000a0 ++ ++#define CLK_AUDIO_OUT_CTRL 0x000a4 ++#define CLK_AUDIO_OUT_DIV_INT 0x000a8 ++#define CLK_AUDIO_OUT_SEL 0x000b0 ++ ++#define CLK_I2S_CTRL 0x000b4 ++#define CLK_I2S_DIV_INT 0x000b8 ++#define CLK_I2S_SEL 0x000c0 ++ ++#define CLK_MIPI0_CFG_CTRL 0x000c4 ++#define CLK_MIPI0_CFG_DIV_INT 0x000c8 ++#define CLK_MIPI0_CFG_SEL 0x000d0 ++ ++#define CLK_MIPI1_CFG_CTRL 0x000d4 ++#define CLK_MIPI1_CFG_DIV_INT 0x000d8 ++#define CLK_MIPI1_CFG_SEL 0x000e0 ++ ++#define CLK_PCIE_AUX_CTRL 0x000e4 ++#define CLK_PCIE_AUX_DIV_INT 0x000e8 ++#define CLK_PCIE_AUX_SEL 0x000f0 ++ ++#define CLK_USBH0_MICROFRAME_CTRL 0x000f4 ++#define CLK_USBH0_MICROFRAME_DIV_INT 0x000f8 ++#define CLK_USBH0_MICROFRAME_SEL 0x00100 ++ ++#define CLK_USBH1_MICROFRAME_CTRL 0x00104 ++#define CLK_USBH1_MICROFRAME_DIV_INT 0x00108 ++#define CLK_USBH1_MICROFRAME_SEL 0x00110 ++ ++#define CLK_USBH0_SUSPEND_CTRL 0x00114 ++#define CLK_USBH0_SUSPEND_DIV_INT 0x00118 ++#define CLK_USBH0_SUSPEND_SEL 0x00120 ++ ++#define CLK_USBH1_SUSPEND_CTRL 0x00124 ++#define CLK_USBH1_SUSPEND_DIV_INT 0x00128 ++#define CLK_USBH1_SUSPEND_SEL 0x00130 ++ ++#define CLK_ETH_TSU_CTRL 0x00134 ++#define CLK_ETH_TSU_DIV_INT 0x00138 ++#define CLK_ETH_TSU_SEL 0x00140 ++ ++#define CLK_ADC_CTRL 0x00144 ++#define CLK_ADC_DIV_INT 0x00148 ++#define CLK_ADC_SEL 0x00150 ++ ++#define CLK_SDIO_TIMER_CTRL 0x00154 ++#define CLK_SDIO_TIMER_DIV_INT 0x00158 ++#define CLK_SDIO_TIMER_SEL 0x00160 ++ ++#define CLK_SDIO_ALT_SRC_CTRL 0x00164 ++#define CLK_SDIO_ALT_SRC_DIV_INT 0x00168 ++#define CLK_SDIO_ALT_SRC_SEL 0x00170 ++ ++#define CLK_GP0_CTRL 0x00174 ++#define CLK_GP0_DIV_INT 0x00178 ++#define CLK_GP0_DIV_FRAC 0x0017c ++#define CLK_GP0_SEL 0x00180 ++ ++#define CLK_GP1_CTRL 0x00184 ++#define CLK_GP1_DIV_INT 0x00188 ++#define CLK_GP1_DIV_FRAC 0x0018c ++#define CLK_GP1_SEL 0x00190 ++ ++#define CLK_GP2_CTRL 0x00194 ++#define CLK_GP2_DIV_INT 0x00198 ++#define CLK_GP2_DIV_FRAC 0x0019c ++#define CLK_GP2_SEL 0x001a0 ++ ++#define CLK_GP3_CTRL 0x001a4 ++#define CLK_GP3_DIV_INT 0x001a8 ++#define CLK_GP3_DIV_FRAC 0x001ac ++#define CLK_GP3_SEL 0x001b0 ++ ++#define CLK_GP4_CTRL 0x001b4 ++#define CLK_GP4_DIV_INT 0x001b8 ++#define CLK_GP4_DIV_FRAC 0x001bc ++#define CLK_GP4_SEL 0x001c0 ++ ++#define CLK_GP5_CTRL 0x001c4 ++#define CLK_GP5_DIV_INT 0x001c8 ++#define CLK_GP5_DIV_FRAC 0x001cc ++#define CLK_GP5_SEL 0x001d0 ++ ++#define CLK_SYS_RESUS_CTRL 0x0020c ++ ++#define CLK_SLOW_SYS_RESUS_CTRL 0x00214 ++ ++#define FC0_REF_KHZ 0x0021c ++#define FC0_MIN_KHZ 0x00220 ++#define FC0_MAX_KHZ 0x00224 ++#define FC0_DELAY 0x00228 ++#define FC0_INTERVAL 0x0022c ++#define FC0_SRC 0x00230 ++#define FC0_STATUS 0x00234 ++#define FC0_RESULT 0x00238 ++#define FC_SIZE 0x20 ++#define FC_COUNT 8 ++#define FC_NUM(idx, off) ((idx) * 32 + (off)) ++ ++#define AUX_SEL 1 ++ ++#define VIDEO_CLOCKS_OFFSET 0x4000 ++#define VIDEO_CLK_VEC_CTRL (VIDEO_CLOCKS_OFFSET + 0x0000) ++#define VIDEO_CLK_VEC_DIV_INT (VIDEO_CLOCKS_OFFSET + 0x0004) ++#define VIDEO_CLK_VEC_SEL (VIDEO_CLOCKS_OFFSET + 0x000c) ++#define VIDEO_CLK_DPI_CTRL (VIDEO_CLOCKS_OFFSET + 0x0010) ++#define VIDEO_CLK_DPI_DIV_INT (VIDEO_CLOCKS_OFFSET + 0x0014) ++#define VIDEO_CLK_DPI_SEL (VIDEO_CLOCKS_OFFSET + 0x001c) ++#define VIDEO_CLK_MIPI0_DPI_CTRL (VIDEO_CLOCKS_OFFSET + 0x0020) ++#define VIDEO_CLK_MIPI0_DPI_DIV_INT (VIDEO_CLOCKS_OFFSET + 0x0024) ++#define VIDEO_CLK_MIPI0_DPI_DIV_FRAC (VIDEO_CLOCKS_OFFSET + 0x0028) ++#define VIDEO_CLK_MIPI0_DPI_SEL (VIDEO_CLOCKS_OFFSET + 0x002c) ++#define VIDEO_CLK_MIPI1_DPI_CTRL (VIDEO_CLOCKS_OFFSET + 0x0030) ++#define VIDEO_CLK_MIPI1_DPI_DIV_INT (VIDEO_CLOCKS_OFFSET + 0x0034) ++#define VIDEO_CLK_MIPI1_DPI_DIV_FRAC (VIDEO_CLOCKS_OFFSET + 0x0038) ++#define VIDEO_CLK_MIPI1_DPI_SEL (VIDEO_CLOCKS_OFFSET + 0x003c) ++ ++#define DIV_INT_8BIT_MAX 0x000000ffu /* max divide for most clocks */ ++#define DIV_INT_16BIT_MAX 0x0000ffffu /* max divide for GPx, PWM */ ++#define DIV_INT_24BIT_MAX 0x00ffffffu /* max divide for CLK_SYS */ ++ ++#define FC0_STATUS_DONE BIT(4) ++#define FC0_STATUS_RUNNING BIT(8) ++#define FC0_RESULT_FRAC_SHIFT 5 ++ ++#define PLL_PRIM_DIV1_SHIFT 16 ++#define PLL_PRIM_DIV1_MASK 0x00070000 ++#define PLL_PRIM_DIV2_SHIFT 12 ++#define PLL_PRIM_DIV2_MASK 0x00007000 ++ ++#define PLL_SEC_DIV_SHIFT 8 ++#define PLL_SEC_DIV_WIDTH 5 ++#define PLL_SEC_DIV_MASK 0x00001f00 ++ ++#define PLL_CS_LOCK BIT(31) ++#define PLL_CS_REFDIV_SHIFT 0 ++ ++#define PLL_PWR_PD BIT(0) ++#define PLL_PWR_DACPD BIT(1) ++#define PLL_PWR_DSMPD BIT(2) ++#define PLL_PWR_POSTDIVPD BIT(3) ++#define PLL_PWR_4PHASEPD BIT(4) ++#define PLL_PWR_VCOPD BIT(5) ++#define PLL_PWR_MASK 0x0000003f ++ ++#define PLL_SEC_RST BIT(16) ++#define PLL_SEC_IMPL BIT(31) ++ ++/* PLL phase output for both PRI and SEC */ ++#define PLL_PH_EN BIT(4) ++#define PLL_PH_PHASE_SHIFT 0 ++ ++#define RP1_PLL_PHASE_0 0 ++#define RP1_PLL_PHASE_90 1 ++#define RP1_PLL_PHASE_180 2 ++#define RP1_PLL_PHASE_270 3 ++ ++/* Clock fields for all clocks */ ++#define CLK_CTRL_ENABLE BIT(11) ++#define CLK_CTRL_AUXSRC_MASK 0x000003e0 ++#define CLK_CTRL_AUXSRC_SHIFT 5 ++#define CLK_CTRL_SRC_SHIFT 0 ++#define CLK_DIV_FRAC_BITS 16 ++ ++#define KHz 1000 ++#define MHz (KHz * KHz) ++#define LOCK_TIMEOUT_NS 100000000 ++#define FC_TIMEOUT_NS 100000000 ++ ++#define MAX_CLK_PARENTS 16 ++ ++#define MEASURE_CLOCK_RATE ++const char * const fc0_ref_clk_name = "clk_slow_sys"; ++ ++#define ABS_DIFF(a, b) ((a) > (b) ? (a) - (b) : (b) - (a)) ++#define DIV_NEAREST(a, b) (((a) + ((b) >> 1)) / (b)) ++#define DIV_U64_NEAREST(a, b) div_u64(((a) + ((b) >> 1)), (b)) ++ ++/* ++ * Names of the reference clock for the pll cores. This name must match ++ * the DT reference clock-output-name. ++ */ ++static const char *const ref_clock = "xosc"; ++ ++/* ++ * Secondary PLL channel output divider table. ++ * Divider values range from 8 to 19. ++ * Invalid values default to 19 ++ */ ++static const struct clk_div_table pll_sec_div_table[] = { ++ { 0x00, 19 }, ++ { 0x01, 19 }, ++ { 0x02, 19 }, ++ { 0x03, 19 }, ++ { 0x04, 19 }, ++ { 0x05, 19 }, ++ { 0x06, 19 }, ++ { 0x07, 19 }, ++ { 0x08, 8 }, ++ { 0x09, 9 }, ++ { 0x0a, 10 }, ++ { 0x0b, 11 }, ++ { 0x0c, 12 }, ++ { 0x0d, 13 }, ++ { 0x0e, 14 }, ++ { 0x0f, 15 }, ++ { 0x10, 16 }, ++ { 0x11, 17 }, ++ { 0x12, 18 }, ++ { 0x13, 19 }, ++ { 0x14, 19 }, ++ { 0x15, 19 }, ++ { 0x16, 19 }, ++ { 0x17, 19 }, ++ { 0x18, 19 }, ++ { 0x19, 19 }, ++ { 0x1a, 19 }, ++ { 0x1b, 19 }, ++ { 0x1c, 19 }, ++ { 0x1d, 19 }, ++ { 0x1e, 19 }, ++ { 0x1f, 19 }, ++ { 0 } ++}; ++ ++struct rp1_clockman { ++ struct device *dev; ++ void __iomem *regs; ++ spinlock_t regs_lock; /* spinlock for all clocks */ ++ ++ /* Must be last */ ++ struct clk_hw_onecell_data onecell; ++}; ++ ++struct rp1_pll_core_data { ++ const char *name; ++ u32 cs_reg; ++ u32 pwr_reg; ++ u32 fbdiv_int_reg; ++ u32 fbdiv_frac_reg; ++ unsigned long flags; ++ u32 fc0_src; ++}; ++ ++struct rp1_pll_data { ++ const char *name; ++ const char *source_pll; ++ u32 ctrl_reg; ++ unsigned long flags; ++ u32 fc0_src; ++}; ++ ++struct rp1_pll_ph_data { ++ const char *name; ++ const char *source_pll; ++ unsigned int phase; ++ unsigned int fixed_divider; ++ u32 ph_reg; ++ unsigned long flags; ++ u32 fc0_src; ++}; ++ ++struct rp1_pll_divider_data { ++ const char *name; ++ const char *source_pll; ++ u32 sec_reg; ++ unsigned long flags; ++ u32 fc0_src; ++}; ++ ++struct rp1_clock_data { ++ const char *name; ++ const char *const parents[MAX_CLK_PARENTS]; ++ int num_std_parents; ++ int num_aux_parents; ++ unsigned long flags; ++ u32 oe_mask; ++ u32 clk_src_mask; ++ u32 ctrl_reg; ++ u32 div_int_reg; ++ u32 div_frac_reg; ++ u32 sel_reg; ++ u32 div_int_max; ++ unsigned long max_freq; ++ u32 fc0_src; ++}; ++ ++struct rp1_pll_core { ++ struct clk_hw hw; ++ struct rp1_clockman *clockman; ++ const struct rp1_pll_core_data *data; ++ unsigned long cached_rate; ++}; ++ ++struct rp1_pll { ++ struct clk_hw hw; ++ struct clk_divider div; ++ struct rp1_clockman *clockman; ++ const struct rp1_pll_data *data; ++ unsigned long cached_rate; ++}; ++ ++struct rp1_pll_ph { ++ struct clk_hw hw; ++ struct rp1_clockman *clockman; ++ const struct rp1_pll_ph_data *data; ++}; ++ ++struct rp1_clock { ++ struct clk_hw hw; ++ struct rp1_clockman *clockman; ++ const struct rp1_clock_data *data; ++ unsigned long cached_rate; ++}; ++ ++ ++struct rp1_clk_change { ++ struct clk_hw *hw; ++ unsigned long new_rate; ++}; ++ ++struct rp1_clk_change rp1_clk_chg_tree[3]; ++ ++static struct clk_hw *clk_xosc; ++static struct clk_hw *clk_audio; ++static struct clk_hw *clk_i2s; ++ ++static void rp1_debugfs_regset(struct rp1_clockman *clockman, u32 base, ++ const struct debugfs_reg32 *regs, ++ size_t nregs, struct dentry *dentry) ++{ ++ struct debugfs_regset32 *regset; ++ ++ regset = devm_kzalloc(clockman->dev, sizeof(*regset), GFP_KERNEL); ++ if (!regset) + return; -+ core = req->clk->core; + -+ clk_prepare_lock(); ++ regset->regs = regs; ++ regset->nregs = nregs; ++ regset->base = clockman->regs + base; + -+ list_del(&req->list); ++ debugfs_create_regset32("regdump", 0444, dentry, regset); ++} + -+ if (list_empty(&core->pending_requests)) { -+ clk_core_set_rate_nolock(core, core->default_request_rate); -+ core->default_request_rate = 0; -+ } else { -+ struct clk_request *cur_req; -+ unsigned long new_rate = 0; ++static inline u32 set_register_field(u32 reg, u32 val, u32 mask, u32 shift) ++{ ++ reg &= ~mask; ++ reg |= (val << shift) & mask; ++ return reg; ++} + -+ list_for_each_entry(cur_req, &core->pending_requests, list) -+ new_rate = max(new_rate, cur_req->rate); ++static inline ++void clockman_write(struct rp1_clockman *clockman, u32 reg, u32 val) ++{ ++ writel(val, clockman->regs + reg); ++} + -+ clk_core_set_rate_nolock(core, new_rate); ++static inline u32 clockman_read(struct rp1_clockman *clockman, u32 reg) ++{ ++ return readl(clockman->regs + reg); ++} ++ ++#ifdef MEASURE_CLOCK_RATE ++static unsigned long clockman_measure_clock(struct rp1_clockman *clockman, ++ const char *clk_name, ++ unsigned int fc0_src) ++{ ++ struct clk *ref_clk = __clk_lookup(fc0_ref_clk_name); ++ unsigned long result; ++ ktime_t timeout; ++ unsigned int fc_idx, fc_offset, fc_src; ++ ++ fc_idx = fc0_src / 32; ++ fc_src = fc0_src % 32; ++ ++ /* fc_src == 0 is invalid. */ ++ if (!fc_src || fc_idx >= FC_COUNT) ++ return 0; ++ ++ fc_offset = fc_idx * FC_SIZE; ++ ++ /* Ensure the frequency counter is idle. */ ++ timeout = ktime_add_ns(ktime_get(), FC_TIMEOUT_NS); ++ while (clockman_read(clockman, fc_offset + FC0_STATUS) & FC0_STATUS_RUNNING) { ++ if (ktime_after(ktime_get(), timeout)) { ++ dev_err(clockman->dev, "%s: FC0 busy timeout\n", ++ clk_name); ++ return 0; ++ } ++ cpu_relax(); + } + -+ clk_prepare_unlock(); ++ spin_lock(&clockman->regs_lock); ++ clockman_write(clockman, fc_offset + FC0_REF_KHZ, ++ clk_get_rate(ref_clk) / KHz); ++ clockman_write(clockman, fc_offset + FC0_MIN_KHZ, 0); ++ clockman_write(clockman, fc_offset + FC0_MAX_KHZ, 0x1ffffff); ++ clockman_write(clockman, fc_offset + FC0_INTERVAL, 8); ++ clockman_write(clockman, fc_offset + FC0_DELAY, 7); ++ clockman_write(clockman, fc_offset + FC0_SRC, fc_src); ++ spin_unlock(&clockman->regs_lock); + -+ kfree(req); ++ /* Ensure the frequency counter is idle. */ ++ timeout = ktime_add_ns(ktime_get(), FC_TIMEOUT_NS); ++ while (!(clockman_read(clockman, fc_offset + FC0_STATUS) & FC0_STATUS_DONE)) { ++ if (ktime_after(ktime_get(), timeout)) { ++ dev_err(clockman->dev, "%s: FC0 wait timeout\n", ++ clk_name); ++ return 0; ++ } ++ cpu_relax(); ++ } ++ ++ result = clockman_read(clockman, fc_offset + FC0_RESULT); ++ ++ /* Disable FC0 */ ++ spin_lock(&clockman->regs_lock); ++ clockman_write(clockman, fc_offset + FC0_SRC, 0); ++ spin_unlock(&clockman->regs_lock); ++ ++ return result; +} -+EXPORT_SYMBOL_GPL(clk_request_done); ++#endif + - /** - * clk_get_parent - return the parent of a clk - * @clk: the clk whose parent gets returned -@@ -3838,6 +3964,7 @@ __clk_register(struct device *dev, struct device_node *np, struct clk_hw *hw) - goto fail_parents; - - INIT_HLIST_HEAD(&core->clks); -+ INIT_LIST_HEAD(&core->pending_requests); - - /* - * Don't call clk_hw_create_clk() here because that would pin the ++static int rp1_pll_core_is_on(struct clk_hw *hw) ++{ ++ struct rp1_pll_core *pll_core = container_of(hw, struct rp1_pll_core, hw); ++ struct rp1_clockman *clockman = pll_core->clockman; ++ const struct rp1_pll_core_data *data = pll_core->data; ++ u32 pwr = clockman_read(clockman, data->pwr_reg); ++ ++ return (pwr & PLL_PWR_PD) || (pwr & PLL_PWR_POSTDIVPD); ++} ++ ++static int rp1_pll_core_on(struct clk_hw *hw) ++{ ++ struct rp1_pll_core *pll_core = container_of(hw, struct rp1_pll_core, hw); ++ struct rp1_clockman *clockman = pll_core->clockman; ++ const struct rp1_pll_core_data *data = pll_core->data; ++ u32 fbdiv_frac; ++ ktime_t timeout; ++ ++ spin_lock(&clockman->regs_lock); ++ ++ if (!(clockman_read(clockman, data->cs_reg) & PLL_CS_LOCK)) { ++ /* Reset to a known state. */ ++ clockman_write(clockman, data->pwr_reg, PLL_PWR_MASK); ++ clockman_write(clockman, data->fbdiv_int_reg, 20); ++ clockman_write(clockman, data->fbdiv_frac_reg, 0); ++ clockman_write(clockman, data->cs_reg, 1 << PLL_CS_REFDIV_SHIFT); ++ } ++ ++ /* Come out of reset. */ ++ fbdiv_frac = clockman_read(clockman, data->fbdiv_frac_reg); ++ clockman_write(clockman, data->pwr_reg, fbdiv_frac ? 0 : PLL_PWR_DSMPD); ++ spin_unlock(&clockman->regs_lock); ++ ++ /* Wait for the PLL to lock. */ ++ timeout = ktime_add_ns(ktime_get(), LOCK_TIMEOUT_NS); ++ while (!(clockman_read(clockman, data->cs_reg) & PLL_CS_LOCK)) { ++ if (ktime_after(ktime_get(), timeout)) { ++ dev_err(clockman->dev, "%s: can't lock PLL\n", ++ clk_hw_get_name(hw)); ++ return -ETIMEDOUT; ++ } ++ cpu_relax(); ++ } ++ ++ return 0; ++} ++ ++static void rp1_pll_core_off(struct clk_hw *hw) ++{ ++ struct rp1_pll_core *pll_core = container_of(hw, struct rp1_pll_core, hw); ++ struct rp1_clockman *clockman = pll_core->clockman; ++ const struct rp1_pll_core_data *data = pll_core->data; ++ ++ spin_lock(&clockman->regs_lock); ++ clockman_write(clockman, data->pwr_reg, 0); ++ spin_unlock(&clockman->regs_lock); ++} ++ ++static inline unsigned long get_pll_core_divider(struct clk_hw *hw, ++ unsigned long rate, ++ unsigned long parent_rate, ++ u32 *div_int, u32 *div_frac) ++{ ++ unsigned long calc_rate; ++ u32 fbdiv_int, fbdiv_frac; ++ u64 div_fp64; /* 32.32 fixed point fraction. */ ++ ++ /* Factor of reference clock to VCO frequency. */ ++ div_fp64 = (u64)(rate) << 32; ++ div_fp64 = DIV_U64_NEAREST(div_fp64, parent_rate); ++ ++ /* Round the fractional component at 24 bits. */ ++ div_fp64 += 1 << (32 - 24 - 1); ++ ++ fbdiv_int = div_fp64 >> 32; ++ fbdiv_frac = (div_fp64 >> (32 - 24)) & 0xffffff; ++ ++ calc_rate = ++ ((u64)parent_rate * (((u64)fbdiv_int << 24) + fbdiv_frac) + (1 << 23)) >> 24; ++ ++ *div_int = fbdiv_int; ++ *div_frac = fbdiv_frac; ++ ++ return calc_rate; ++} ++ ++static int rp1_pll_core_set_rate(struct clk_hw *hw, ++ unsigned long rate, unsigned long parent_rate) ++{ ++ struct rp1_pll_core *pll_core = container_of(hw, struct rp1_pll_core, hw); ++ struct rp1_clockman *clockman = pll_core->clockman; ++ const struct rp1_pll_core_data *data = pll_core->data; ++ unsigned long calc_rate; ++ u32 fbdiv_int, fbdiv_frac; ++ ++ // todo: is this needed?? ++ //rp1_pll_off(hw); ++ ++ /* Disable dividers to start with. */ ++ spin_lock(&clockman->regs_lock); ++ clockman_write(clockman, data->fbdiv_int_reg, 0); ++ clockman_write(clockman, data->fbdiv_frac_reg, 0); ++ spin_unlock(&clockman->regs_lock); ++ ++ calc_rate = get_pll_core_divider(hw, rate, parent_rate, ++ &fbdiv_int, &fbdiv_frac); ++ ++ spin_lock(&clockman->regs_lock); ++ clockman_write(clockman, data->pwr_reg, fbdiv_frac ? 0 : PLL_PWR_DSMPD); ++ clockman_write(clockman, data->fbdiv_int_reg, fbdiv_int); ++ clockman_write(clockman, data->fbdiv_frac_reg, fbdiv_frac); ++ spin_unlock(&clockman->regs_lock); ++ ++ /* Check that reference frequency is no greater than VCO / 16. */ ++ BUG_ON(parent_rate > (rate / 16)); ++ ++ pll_core->cached_rate = calc_rate; ++ ++ spin_lock(&clockman->regs_lock); ++ /* Don't need to divide ref unless parent_rate > (output freq / 16) */ ++ clockman_write(clockman, data->cs_reg, ++ clockman_read(clockman, data->cs_reg) | ++ (1 << PLL_CS_REFDIV_SHIFT)); ++ spin_unlock(&clockman->regs_lock); ++ ++ return 0; ++} ++ ++static unsigned long rp1_pll_core_recalc_rate(struct clk_hw *hw, ++ unsigned long parent_rate) ++{ ++ struct rp1_pll_core *pll_core = container_of(hw, struct rp1_pll_core, hw); ++ struct rp1_clockman *clockman = pll_core->clockman; ++ const struct rp1_pll_core_data *data = pll_core->data; ++ u32 fbdiv_int, fbdiv_frac; ++ unsigned long calc_rate; ++ ++ fbdiv_int = clockman_read(clockman, data->fbdiv_int_reg); ++ fbdiv_frac = clockman_read(clockman, data->fbdiv_frac_reg); ++ calc_rate = ++ ((u64)parent_rate * (((u64)fbdiv_int << 24) + fbdiv_frac) + (1 << 23)) >> 24; ++ ++ return calc_rate; ++} ++ ++static long rp1_pll_core_round_rate(struct clk_hw *hw, unsigned long rate, ++ unsigned long *parent_rate) ++{ ++ u32 fbdiv_int, fbdiv_frac; ++ long calc_rate; ++ ++ calc_rate = get_pll_core_divider(hw, rate, *parent_rate, ++ &fbdiv_int, &fbdiv_frac); ++ return calc_rate; ++} ++ ++static void rp1_pll_core_debug_init(struct clk_hw *hw, struct dentry *dentry) ++{ ++ struct rp1_pll_core *pll_core = container_of(hw, struct rp1_pll_core, hw); ++ struct rp1_clockman *clockman = pll_core->clockman; ++ const struct rp1_pll_core_data *data = pll_core->data; ++ struct debugfs_reg32 *regs; ++ ++ regs = devm_kcalloc(clockman->dev, 4, sizeof(*regs), GFP_KERNEL); ++ if (!regs) ++ return; ++ ++ regs[0].name = "cs"; ++ regs[0].offset = data->cs_reg; ++ regs[1].name = "pwr"; ++ regs[1].offset = data->pwr_reg; ++ regs[2].name = "fbdiv_int"; ++ regs[2].offset = data->fbdiv_int_reg; ++ regs[3].name = "fbdiv_frac"; ++ regs[3].offset = data->fbdiv_frac_reg; ++ ++ rp1_debugfs_regset(clockman, 0, regs, 4, dentry); ++} ++ ++static void get_pll_prim_dividers(unsigned long rate, unsigned long parent_rate, ++ u32 *divider1, u32 *divider2) ++{ ++ unsigned int div1, div2; ++ unsigned int best_div1 = 7, best_div2 = 7; ++ unsigned long best_rate_diff = ++ ABS_DIFF(DIV_ROUND_CLOSEST(parent_rate, best_div1 * best_div2), rate); ++ long rate_diff, calc_rate; ++ ++ for (div1 = 1; div1 <= 7; div1++) { ++ for (div2 = 1; div2 <= div1; div2++) { ++ calc_rate = DIV_ROUND_CLOSEST(parent_rate, div1 * div2); ++ rate_diff = ABS_DIFF(calc_rate, rate); ++ ++ if (calc_rate == rate) { ++ best_div1 = div1; ++ best_div2 = div2; ++ goto done; ++ } else if (rate_diff < best_rate_diff) { ++ best_div1 = div1; ++ best_div2 = div2; ++ best_rate_diff = rate_diff; ++ } ++ } ++ } ++ ++done: ++ *divider1 = best_div1; ++ *divider2 = best_div2; ++} ++ ++static int rp1_pll_set_rate(struct clk_hw *hw, ++ unsigned long rate, unsigned long parent_rate) ++{ ++ struct rp1_pll *pll = container_of(hw, struct rp1_pll, hw); ++ struct rp1_clockman *clockman = pll->clockman; ++ const struct rp1_pll_data *data = pll->data; ++ u32 prim, prim_div1, prim_div2; ++ ++ get_pll_prim_dividers(rate, parent_rate, &prim_div1, &prim_div2); ++ ++ spin_lock(&clockman->regs_lock); ++ prim = clockman_read(clockman, data->ctrl_reg); ++ prim = set_register_field(prim, prim_div1, PLL_PRIM_DIV1_MASK, ++ PLL_PRIM_DIV1_SHIFT); ++ prim = set_register_field(prim, prim_div2, PLL_PRIM_DIV2_MASK, ++ PLL_PRIM_DIV2_SHIFT); ++ clockman_write(clockman, data->ctrl_reg, prim); ++ spin_unlock(&clockman->regs_lock); ++ ++#ifdef MEASURE_CLOCK_RATE ++ clockman_measure_clock(clockman, data->name, data->fc0_src); ++#endif ++ return 0; ++} ++ ++static unsigned long rp1_pll_recalc_rate(struct clk_hw *hw, ++ unsigned long parent_rate) ++{ ++ struct rp1_pll *pll = container_of(hw, struct rp1_pll, hw); ++ struct rp1_clockman *clockman = pll->clockman; ++ const struct rp1_pll_data *data = pll->data; ++ u32 prim, prim_div1, prim_div2; ++ ++ prim = clockman_read(clockman, data->ctrl_reg); ++ prim_div1 = (prim & PLL_PRIM_DIV1_MASK) >> PLL_PRIM_DIV1_SHIFT; ++ prim_div2 = (prim & PLL_PRIM_DIV2_MASK) >> PLL_PRIM_DIV2_SHIFT; ++ ++ if (!prim_div1 || !prim_div2) { ++ dev_err(clockman->dev, "%s: (%s) zero divider value\n", ++ __func__, data->name); ++ return 0; ++ } ++ ++ return DIV_ROUND_CLOSEST(parent_rate, prim_div1 * prim_div2); ++} ++ ++static long rp1_pll_round_rate(struct clk_hw *hw, unsigned long rate, ++ unsigned long *parent_rate) ++{ ++ const struct rp1_clk_change *chg = &rp1_clk_chg_tree[1]; ++ u32 div1, div2; ++ ++ if (chg->hw == hw && chg->new_rate == rate) ++ *parent_rate = chg[1].new_rate; ++ ++ get_pll_prim_dividers(rate, *parent_rate, &div1, &div2); ++ ++ return DIV_ROUND_CLOSEST(*parent_rate, div1 * div2); ++} ++ ++static void rp1_pll_debug_init(struct clk_hw *hw, ++ struct dentry *dentry) ++{ ++ struct rp1_pll *pll = container_of(hw, struct rp1_pll, hw); ++ struct rp1_clockman *clockman = pll->clockman; ++ const struct rp1_pll_data *data = pll->data; ++ struct debugfs_reg32 *regs; ++ ++ regs = devm_kcalloc(clockman->dev, 1, sizeof(*regs), GFP_KERNEL); ++ if (!regs) ++ return; ++ ++ regs[0].name = "prim"; ++ regs[0].offset = data->ctrl_reg; ++ ++ rp1_debugfs_regset(clockman, 0, regs, 1, dentry); ++} ++ ++static int rp1_pll_ph_is_on(struct clk_hw *hw) ++{ ++ struct rp1_pll_ph *pll = container_of(hw, struct rp1_pll_ph, hw); ++ struct rp1_clockman *clockman = pll->clockman; ++ const struct rp1_pll_ph_data *data = pll->data; ++ ++ return !!(clockman_read(clockman, data->ph_reg) & PLL_PH_EN); ++} ++ ++static int rp1_pll_ph_on(struct clk_hw *hw) ++{ ++ struct rp1_pll_ph *pll_ph = container_of(hw, struct rp1_pll_ph, hw); ++ struct rp1_clockman *clockman = pll_ph->clockman; ++ const struct rp1_pll_ph_data *data = pll_ph->data; ++ u32 ph_reg; ++ ++ /* todo: ensure pri/sec is enabled! */ ++ spin_lock(&clockman->regs_lock); ++ ph_reg = clockman_read(clockman, data->ph_reg); ++ ph_reg |= data->phase << PLL_PH_PHASE_SHIFT; ++ ph_reg |= PLL_PH_EN; ++ clockman_write(clockman, data->ph_reg, ph_reg); ++ spin_unlock(&clockman->regs_lock); ++ ++#ifdef MEASURE_CLOCK_RATE ++ clockman_measure_clock(clockman, data->name, data->fc0_src); ++#endif ++ return 0; ++} ++ ++static void rp1_pll_ph_off(struct clk_hw *hw) ++{ ++ struct rp1_pll_ph *pll_ph = container_of(hw, struct rp1_pll_ph, hw); ++ struct rp1_clockman *clockman = pll_ph->clockman; ++ const struct rp1_pll_ph_data *data = pll_ph->data; ++ ++ spin_lock(&clockman->regs_lock); ++ clockman_write(clockman, data->ph_reg, ++ clockman_read(clockman, data->ph_reg) & ~PLL_PH_EN); ++ spin_unlock(&clockman->regs_lock); ++} ++ ++static int rp1_pll_ph_set_rate(struct clk_hw *hw, ++ unsigned long rate, unsigned long parent_rate) ++{ ++ struct rp1_pll_ph *pll_ph = container_of(hw, struct rp1_pll_ph, hw); ++ const struct rp1_pll_ph_data *data = pll_ph->data; ++ struct rp1_clockman *clockman = pll_ph->clockman; ++ ++ /* Nothing really to do here! */ ++ WARN_ON(data->fixed_divider != 1 && data->fixed_divider != 2); ++ WARN_ON(rate != parent_rate / data->fixed_divider); ++ ++#ifdef MEASURE_CLOCK_RATE ++ if (rp1_pll_ph_is_on(hw)) ++ clockman_measure_clock(clockman, data->name, data->fc0_src); ++#endif ++ return 0; ++} ++ ++static unsigned long rp1_pll_ph_recalc_rate(struct clk_hw *hw, ++ unsigned long parent_rate) ++{ ++ struct rp1_pll_ph *pll_ph = container_of(hw, struct rp1_pll_ph, hw); ++ const struct rp1_pll_ph_data *data = pll_ph->data; ++ ++ return parent_rate / data->fixed_divider; ++} ++ ++static long rp1_pll_ph_round_rate(struct clk_hw *hw, unsigned long rate, ++ unsigned long *parent_rate) ++{ ++ struct rp1_pll_ph *pll_ph = container_of(hw, struct rp1_pll_ph, hw); ++ const struct rp1_pll_ph_data *data = pll_ph->data; ++ ++ return *parent_rate / data->fixed_divider; ++} ++ ++static void rp1_pll_ph_debug_init(struct clk_hw *hw, ++ struct dentry *dentry) ++{ ++ struct rp1_pll_ph *pll_ph = container_of(hw, struct rp1_pll_ph, hw); ++ const struct rp1_pll_ph_data *data = pll_ph->data; ++ struct rp1_clockman *clockman = pll_ph->clockman; ++ struct debugfs_reg32 *regs; ++ ++ regs = devm_kcalloc(clockman->dev, 1, sizeof(*regs), GFP_KERNEL); ++ if (!regs) ++ return; ++ ++ regs[0].name = "ph_reg"; ++ regs[0].offset = data->ph_reg; ++ ++ rp1_debugfs_regset(clockman, 0, regs, 1, dentry); ++} ++ ++static int rp1_pll_divider_is_on(struct clk_hw *hw) ++{ ++ struct rp1_pll *divider = container_of(hw, struct rp1_pll, div.hw); ++ struct rp1_clockman *clockman = divider->clockman; ++ const struct rp1_pll_data *data = divider->data; ++ ++ return !(clockman_read(clockman, data->ctrl_reg) & PLL_SEC_RST); ++} ++ ++static int rp1_pll_divider_on(struct clk_hw *hw) ++{ ++ struct rp1_pll *divider = container_of(hw, struct rp1_pll, div.hw); ++ struct rp1_clockman *clockman = divider->clockman; ++ const struct rp1_pll_data *data = divider->data; ++ ++ spin_lock(&clockman->regs_lock); ++ /* Check the implementation bit is set! */ ++ WARN_ON(!(clockman_read(clockman, data->ctrl_reg) & PLL_SEC_IMPL)); ++ clockman_write(clockman, data->ctrl_reg, ++ clockman_read(clockman, data->ctrl_reg) & ~PLL_SEC_RST); ++ spin_unlock(&clockman->regs_lock); ++ ++#ifdef MEASURE_CLOCK_RATE ++ clockman_measure_clock(clockman, data->name, data->fc0_src); ++#endif ++ return 0; ++} ++ ++static void rp1_pll_divider_off(struct clk_hw *hw) ++{ ++ struct rp1_pll *divider = container_of(hw, struct rp1_pll, div.hw); ++ struct rp1_clockman *clockman = divider->clockman; ++ const struct rp1_pll_data *data = divider->data; ++ ++ spin_lock(&clockman->regs_lock); ++ clockman_write(clockman, data->ctrl_reg, PLL_SEC_RST); ++ spin_unlock(&clockman->regs_lock); ++} ++ ++static int rp1_pll_divider_set_rate(struct clk_hw *hw, ++ unsigned long rate, ++ unsigned long parent_rate) ++{ ++ struct rp1_pll *divider = container_of(hw, struct rp1_pll, div.hw); ++ struct rp1_clockman *clockman = divider->clockman; ++ const struct rp1_pll_data *data = divider->data; ++ u32 div, sec; ++ ++ div = DIV_ROUND_UP_ULL(parent_rate, rate); ++ div = clamp(div, 8u, 19u); ++ ++ spin_lock(&clockman->regs_lock); ++ sec = clockman_read(clockman, data->ctrl_reg); ++ sec = set_register_field(sec, div, PLL_SEC_DIV_MASK, PLL_SEC_DIV_SHIFT); ++ ++ /* Must keep the divider in reset to change the value. */ ++ sec |= PLL_SEC_RST; ++ clockman_write(clockman, data->ctrl_reg, sec); ++ ++ // todo: must sleep 10 pll vco cycles ++ sec &= ~PLL_SEC_RST; ++ clockman_write(clockman, data->ctrl_reg, sec); ++ spin_unlock(&clockman->regs_lock); ++ ++#ifdef MEASURE_CLOCK_RATE ++ if (rp1_pll_divider_is_on(hw)) ++ clockman_measure_clock(clockman, data->name, data->fc0_src); ++#endif ++ return 0; ++} ++ ++static unsigned long rp1_pll_divider_recalc_rate(struct clk_hw *hw, ++ unsigned long parent_rate) ++{ ++ return clk_divider_ops.recalc_rate(hw, parent_rate); ++} ++ ++static long rp1_pll_divider_round_rate(struct clk_hw *hw, ++ unsigned long rate, ++ unsigned long *parent_rate) ++{ ++ return clk_divider_ops.round_rate(hw, rate, parent_rate); ++} ++ ++static void rp1_pll_divider_debug_init(struct clk_hw *hw, struct dentry *dentry) ++{ ++ struct rp1_pll *divider = container_of(hw, struct rp1_pll, div.hw); ++ struct rp1_clockman *clockman = divider->clockman; ++ const struct rp1_pll_data *data = divider->data; ++ struct debugfs_reg32 *regs; ++ ++ regs = devm_kcalloc(clockman->dev, 1, sizeof(*regs), GFP_KERNEL); ++ if (!regs) ++ return; ++ ++ regs[0].name = "sec"; ++ regs[0].offset = data->ctrl_reg; ++ ++ rp1_debugfs_regset(clockman, 0, regs, 1, dentry); ++} ++ ++static int rp1_clock_is_on(struct clk_hw *hw) ++{ ++ struct rp1_clock *clock = container_of(hw, struct rp1_clock, hw); ++ struct rp1_clockman *clockman = clock->clockman; ++ const struct rp1_clock_data *data = clock->data; ++ ++ return !!(clockman_read(clockman, data->ctrl_reg) & CLK_CTRL_ENABLE); ++} ++ ++static unsigned long rp1_clock_recalc_rate(struct clk_hw *hw, ++ unsigned long parent_rate) ++{ ++ struct rp1_clock *clock = container_of(hw, struct rp1_clock, hw); ++ struct rp1_clockman *clockman = clock->clockman; ++ const struct rp1_clock_data *data = clock->data; ++ u64 calc_rate; ++ u64 div; ++ ++ u32 frac; ++ ++ div = clockman_read(clockman, data->div_int_reg); ++ frac = (data->div_frac_reg != 0) ? ++ clockman_read(clockman, data->div_frac_reg) : 0; ++ ++ /* If the integer portion of the divider is 0, treat it as 2^16 */ ++ if (!div) ++ div = 1 << 16; ++ ++ div = (div << CLK_DIV_FRAC_BITS) | (frac >> (32 - CLK_DIV_FRAC_BITS)); ++ ++ calc_rate = (u64)parent_rate << CLK_DIV_FRAC_BITS; ++ calc_rate = div64_u64(calc_rate, div); ++ ++ return calc_rate; ++} ++ ++static int rp1_clock_on(struct clk_hw *hw) ++{ ++ struct rp1_clock *clock = container_of(hw, struct rp1_clock, hw); ++ struct rp1_clockman *clockman = clock->clockman; ++ const struct rp1_clock_data *data = clock->data; ++ ++ spin_lock(&clockman->regs_lock); ++ clockman_write(clockman, data->ctrl_reg, ++ clockman_read(clockman, data->ctrl_reg) | CLK_CTRL_ENABLE); ++ /* If this is a GPCLK, turn on the output-enable */ ++ if (data->oe_mask) ++ clockman_write(clockman, GPCLK_OE_CTRL, ++ clockman_read(clockman, GPCLK_OE_CTRL) | data->oe_mask); ++ spin_unlock(&clockman->regs_lock); ++ ++#ifdef MEASURE_CLOCK_RATE ++ clockman_measure_clock(clockman, data->name, data->fc0_src); ++#endif ++ return 0; ++} ++ ++static void rp1_clock_off(struct clk_hw *hw) ++{ ++ struct rp1_clock *clock = container_of(hw, struct rp1_clock, hw); ++ struct rp1_clockman *clockman = clock->clockman; ++ const struct rp1_clock_data *data = clock->data; ++ ++ spin_lock(&clockman->regs_lock); ++ clockman_write(clockman, data->ctrl_reg, ++ clockman_read(clockman, data->ctrl_reg) & ~CLK_CTRL_ENABLE); ++ /* If this is a GPCLK, turn off the output-enable */ ++ if (data->oe_mask) ++ clockman_write(clockman, GPCLK_OE_CTRL, ++ clockman_read(clockman, GPCLK_OE_CTRL) & ~data->oe_mask); ++ spin_unlock(&clockman->regs_lock); ++} ++ ++static u32 rp1_clock_choose_div(unsigned long rate, unsigned long parent_rate, ++ const struct rp1_clock_data *data) ++{ ++ u64 div; ++ ++ /* ++ * Due to earlier rounding, calculated parent_rate may differ from ++ * expected value. Don't fail on a small discrepancy near unity divide. ++ */ ++ if (!rate || rate > parent_rate + (parent_rate >> CLK_DIV_FRAC_BITS)) ++ return 0; ++ ++ /* ++ * Always express div in fixed-point format for fractional division; ++ * If no fractional divider is present, the fraction part will be zero. ++ */ ++ if (data->div_frac_reg) { ++ div = (u64)parent_rate << CLK_DIV_FRAC_BITS; ++ div = DIV_U64_NEAREST(div, rate); ++ } else { ++ div = DIV_U64_NEAREST(parent_rate, rate); ++ div <<= CLK_DIV_FRAC_BITS; ++ } ++ ++ div = clamp(div, ++ 1ull << CLK_DIV_FRAC_BITS, ++ (u64)data->div_int_max << CLK_DIV_FRAC_BITS); ++ ++ return div; ++} ++ ++static u8 rp1_clock_get_parent(struct clk_hw *hw) ++{ ++ struct rp1_clock *clock = container_of(hw, struct rp1_clock, hw); ++ struct rp1_clockman *clockman = clock->clockman; ++ const struct rp1_clock_data *data = clock->data; ++ u32 sel, ctrl; ++ u8 parent; ++ ++ /* Sel is one-hot, so find the first bit set */ ++ sel = clockman_read(clockman, data->sel_reg); ++ parent = ffs(sel) - 1; ++ ++ /* sel == 0 implies the parent clock is not enabled yet. */ ++ if (!sel) { ++ /* Read the clock src from the CTRL register instead */ ++ ctrl = clockman_read(clockman, data->ctrl_reg); ++ parent = (ctrl & data->clk_src_mask) >> CLK_CTRL_SRC_SHIFT; ++ } ++ ++ if (parent >= data->num_std_parents) ++ parent = AUX_SEL; ++ ++ if (parent == AUX_SEL) { ++ /* ++ * Clock parent is an auxiliary source, so get the parent from ++ * the AUXSRC register field. ++ */ ++ ctrl = clockman_read(clockman, data->ctrl_reg); ++ parent = (ctrl & CLK_CTRL_AUXSRC_MASK) >> CLK_CTRL_AUXSRC_SHIFT; ++ parent += data->num_std_parents; ++ } ++ ++ return parent; ++} ++ ++static int rp1_clock_set_parent(struct clk_hw *hw, u8 index) ++{ ++ struct rp1_clock *clock = container_of(hw, struct rp1_clock, hw); ++ struct rp1_clockman *clockman = clock->clockman; ++ const struct rp1_clock_data *data = clock->data; ++ u32 ctrl, sel; ++ ++ spin_lock(&clockman->regs_lock); ++ ctrl = clockman_read(clockman, data->ctrl_reg); ++ ++ if (index >= data->num_std_parents) { ++ /* This is an aux source request */ ++ if (index >= data->num_std_parents + data->num_aux_parents) ++ return -EINVAL; ++ ++ /* Select parent from aux list */ ++ ctrl = set_register_field(ctrl, index - data->num_std_parents, ++ CLK_CTRL_AUXSRC_MASK, ++ CLK_CTRL_AUXSRC_SHIFT); ++ /* Set src to aux list */ ++ ctrl = set_register_field(ctrl, AUX_SEL, data->clk_src_mask, ++ CLK_CTRL_SRC_SHIFT); ++ } else { ++ ctrl = set_register_field(ctrl, index, data->clk_src_mask, ++ CLK_CTRL_SRC_SHIFT); ++ } ++ ++ clockman_write(clockman, data->ctrl_reg, ctrl); ++ spin_unlock(&clockman->regs_lock); ++ ++ sel = rp1_clock_get_parent(hw); ++ WARN(sel != index, "(%s): Parent index req %u returned back %u\n", ++ data->name, index, sel); ++ ++ return 0; ++} ++ ++static int rp1_clock_set_rate_and_parent(struct clk_hw *hw, ++ unsigned long rate, ++ unsigned long parent_rate, ++ u8 parent) ++{ ++ struct rp1_clock *clock = container_of(hw, struct rp1_clock, hw); ++ struct rp1_clockman *clockman = clock->clockman; ++ const struct rp1_clock_data *data = clock->data; ++ u32 div = rp1_clock_choose_div(rate, parent_rate, data); ++ ++ WARN(rate > 4000000000ll, "rate is -ve (%d)\n", (int)rate); ++ ++ if (WARN(!div, ++ "clk divider calculated as 0! (%s, rate %ld, parent rate %ld)\n", ++ data->name, rate, parent_rate)) ++ div = 1 << CLK_DIV_FRAC_BITS; ++ ++ spin_lock(&clockman->regs_lock); ++ ++ clockman_write(clockman, data->div_int_reg, div >> CLK_DIV_FRAC_BITS); ++ if (data->div_frac_reg) ++ clockman_write(clockman, data->div_frac_reg, div << (32 - CLK_DIV_FRAC_BITS)); ++ ++ spin_unlock(&clockman->regs_lock); ++ ++ if (parent != 0xff) ++ rp1_clock_set_parent(hw, parent); ++ ++#ifdef MEASURE_CLOCK_RATE ++ if (rp1_clock_is_on(hw)) ++ clockman_measure_clock(clockman, data->name, data->fc0_src); ++#endif ++ return 0; ++} ++ ++static int rp1_clock_set_rate(struct clk_hw *hw, unsigned long rate, ++ unsigned long parent_rate) ++{ ++ return rp1_clock_set_rate_and_parent(hw, rate, parent_rate, 0xff); ++} ++ ++static unsigned long calc_core_pll_rate(struct clk_hw *pll_hw, ++ unsigned long target_rate, ++ int *pdiv_prim, int *pdiv_clk) ++{ ++ static const int prim_divs[] = { ++ 2, 3, 4, 5, 6, 7, 8, 9, 10, 12, 14, 15, 16, ++ 18, 20, 21, 24, 25, 28, 30, 35, 36, 42, 49, ++ }; ++ const unsigned long xosc_rate = clk_hw_get_rate(clk_xosc); ++ const unsigned long core_max = 2400000000; ++ const unsigned long core_min = xosc_rate * 16; ++ unsigned long best_rate = core_max + 1; ++ int best_div_prim = 1, best_div_clk = 1; ++ unsigned long core_rate = 0; ++ int div_int, div_frac; ++ u64 div; ++ int i; ++ ++ /* Given the target rate, choose a set of divisors/multipliers */ ++ for (i = 0; i < ARRAY_SIZE(prim_divs); i++) { ++ int div_prim = prim_divs[i]; ++ int div_clk; ++ ++ for (div_clk = 1; div_clk <= 256; div_clk++) { ++ core_rate = target_rate * div_clk * div_prim; ++ if (core_rate >= core_min) { ++ if (core_rate < best_rate) { ++ best_rate = core_rate; ++ best_div_prim = div_prim; ++ best_div_clk = div_clk; ++ } ++ break; ++ } ++ } ++ } ++ ++ if (best_rate < core_max) { ++ div = ((best_rate << 24) + xosc_rate / 2) / xosc_rate; ++ div_int = div >> 24; ++ div_frac = div % (1 << 24); ++ core_rate = (xosc_rate * ((div_int << 24) + div_frac) + (1 << 23)) >> 24; ++ } else { ++ core_rate = 0; ++ } ++ ++ if (pdiv_prim) ++ *pdiv_prim = best_div_prim; ++ if (pdiv_clk) ++ *pdiv_clk = best_div_clk; ++ ++ return core_rate; ++} ++ ++static void rp1_clock_choose_div_and_prate(struct clk_hw *hw, ++ int parent_idx, ++ unsigned long rate, ++ unsigned long *prate, ++ unsigned long *calc_rate) ++{ ++ struct rp1_clock *clock = container_of(hw, struct rp1_clock, hw); ++ const struct rp1_clock_data *data = clock->data; ++ struct clk_hw *parent; ++ u32 div; ++ u64 tmp; ++ int i; ++ ++ parent = clk_hw_get_parent_by_index(hw, parent_idx); ++ ++ for (i = 0; i < ARRAY_SIZE(rp1_clk_chg_tree); i++) { ++ const struct rp1_clk_change *chg = &rp1_clk_chg_tree[i]; ++ ++ if (chg->hw == hw && chg->new_rate == rate) { ++ if (i == 2) ++ *prate = clk_hw_get_rate(clk_xosc); ++ else if (parent == rp1_clk_chg_tree[i + 1].hw) ++ *prate = rp1_clk_chg_tree[i + 1].new_rate; ++ else ++ continue; ++ *calc_rate = chg->new_rate; ++ return; ++ } ++ } ++ ++ if (hw == clk_i2s && parent == clk_audio) { ++ unsigned long core_rate, audio_rate, i2s_rate; ++ int div_prim, div_clk; ++ ++ core_rate = calc_core_pll_rate(parent, rate, &div_prim, &div_clk); ++ audio_rate = DIV_NEAREST(core_rate, div_prim); ++ i2s_rate = DIV_NEAREST(audio_rate, div_clk); ++ rp1_clk_chg_tree[2].hw = clk_hw_get_parent(parent); ++ rp1_clk_chg_tree[2].new_rate = core_rate; ++ rp1_clk_chg_tree[1].hw = clk_audio; ++ rp1_clk_chg_tree[1].new_rate = audio_rate; ++ rp1_clk_chg_tree[0].hw = clk_i2s; ++ rp1_clk_chg_tree[0].new_rate = i2s_rate; ++ *prate = audio_rate; ++ *calc_rate = i2s_rate; ++ return; ++ } ++ ++ *prate = clk_hw_get_rate(parent); ++ div = rp1_clock_choose_div(rate, *prate, data); ++ ++ if (!div) { ++ *calc_rate = 0; ++ return; ++ } ++ ++ /* Recalculate to account for rounding errors */ ++ tmp = (u64)*prate << CLK_DIV_FRAC_BITS; ++ tmp = div_u64(tmp, div); ++ /* ++ * Prevent overclocks - if all parent choices result in ++ * a downstream clock in excess of the maximum, then the ++ * call to set the clock will fail. ++ */ ++ if (tmp > clock->data->max_freq) ++ *calc_rate = 0; ++ else ++ *calc_rate = tmp; ++} ++ ++static int rp1_clock_determine_rate(struct clk_hw *hw, ++ struct clk_rate_request *req) ++{ ++ struct clk_hw *parent, *best_parent = NULL; ++ unsigned long best_rate = 0; ++ unsigned long best_prate = 0; ++ unsigned long best_rate_diff = ULONG_MAX; ++ unsigned long prate, calc_rate; ++ size_t i; ++ ++ /* ++ * If the NO_REPARENT flag is set, try to use existing parent. ++ */ ++ if ((clk_hw_get_flags(hw) & CLK_SET_RATE_NO_REPARENT)) { ++ i = rp1_clock_get_parent(hw); ++ parent = clk_hw_get_parent_by_index(hw, i); ++ if (parent) { ++ rp1_clock_choose_div_and_prate(hw, i, req->rate, &prate, ++ &calc_rate); ++ if (calc_rate > 0) { ++ req->best_parent_hw = parent; ++ req->best_parent_rate = prate; ++ req->rate = calc_rate; ++ return 0; ++ } ++ } ++ } ++ ++ /* ++ * Select parent clock that results in the closest rate (lower or ++ * higher) ++ */ ++ for (i = 0; i < clk_hw_get_num_parents(hw); i++) { ++ parent = clk_hw_get_parent_by_index(hw, i); ++ if (!parent) ++ continue; ++ ++ rp1_clock_choose_div_and_prate(hw, i, req->rate, &prate, ++ &calc_rate); ++ ++ if (ABS_DIFF(calc_rate, req->rate) < best_rate_diff) { ++ best_parent = parent; ++ best_prate = prate; ++ best_rate = calc_rate; ++ best_rate_diff = ABS_DIFF(calc_rate, req->rate); ++ ++ if (best_rate_diff == 0) ++ break; ++ } ++ } ++ ++ if (best_rate == 0) ++ return -EINVAL; ++ ++ req->best_parent_hw = best_parent; ++ req->best_parent_rate = best_prate; ++ req->rate = best_rate; ++ ++ return 0; ++} ++ ++static void rp1_clk_debug_init(struct clk_hw *hw, struct dentry *dentry) ++{ ++ struct rp1_clock *clock = container_of(hw, struct rp1_clock, hw); ++ struct rp1_clockman *clockman = clock->clockman; ++ const struct rp1_clock_data *data = clock->data; ++ struct debugfs_reg32 *regs; ++ int i; ++ ++ regs = devm_kcalloc(clockman->dev, 4, sizeof(*regs), GFP_KERNEL); ++ if (!regs) ++ return; ++ ++ i = 0; ++ regs[i].name = "ctrl"; ++ regs[i++].offset = data->ctrl_reg; ++ regs[i].name = "div_int"; ++ regs[i++].offset = data->div_int_reg; ++ regs[i].name = "div_frac"; ++ regs[i++].offset = data->div_frac_reg; ++ regs[i].name = "sel"; ++ regs[i++].offset = data->sel_reg; ++ ++ rp1_debugfs_regset(clockman, 0, regs, i, dentry); ++} ++ ++static const struct clk_ops rp1_pll_core_ops = { ++ .is_prepared = rp1_pll_core_is_on, ++ .prepare = rp1_pll_core_on, ++ .unprepare = rp1_pll_core_off, ++ .set_rate = rp1_pll_core_set_rate, ++ .recalc_rate = rp1_pll_core_recalc_rate, ++ .round_rate = rp1_pll_core_round_rate, ++ .debug_init = rp1_pll_core_debug_init, ++}; ++ ++static const struct clk_ops rp1_pll_ops = { ++ .set_rate = rp1_pll_set_rate, ++ .recalc_rate = rp1_pll_recalc_rate, ++ .round_rate = rp1_pll_round_rate, ++ .debug_init = rp1_pll_debug_init, ++}; ++ ++static const struct clk_ops rp1_pll_ph_ops = { ++ .is_prepared = rp1_pll_ph_is_on, ++ .prepare = rp1_pll_ph_on, ++ .unprepare = rp1_pll_ph_off, ++ .set_rate = rp1_pll_ph_set_rate, ++ .recalc_rate = rp1_pll_ph_recalc_rate, ++ .round_rate = rp1_pll_ph_round_rate, ++ .debug_init = rp1_pll_ph_debug_init, ++}; ++ ++static const struct clk_ops rp1_pll_divider_ops = { ++ .is_prepared = rp1_pll_divider_is_on, ++ .prepare = rp1_pll_divider_on, ++ .unprepare = rp1_pll_divider_off, ++ .set_rate = rp1_pll_divider_set_rate, ++ .recalc_rate = rp1_pll_divider_recalc_rate, ++ .round_rate = rp1_pll_divider_round_rate, ++ .debug_init = rp1_pll_divider_debug_init, ++}; ++ ++static const struct clk_ops rp1_clk_ops = { ++ .is_prepared = rp1_clock_is_on, ++ .prepare = rp1_clock_on, ++ .unprepare = rp1_clock_off, ++ .recalc_rate = rp1_clock_recalc_rate, ++ .get_parent = rp1_clock_get_parent, ++ .set_parent = rp1_clock_set_parent, ++ .set_rate_and_parent = rp1_clock_set_rate_and_parent, ++ .set_rate = rp1_clock_set_rate, ++ .determine_rate = rp1_clock_determine_rate, ++ .debug_init = rp1_clk_debug_init, ++}; ++ ++static bool rp1_clk_is_claimed(const char *name); ++ ++static struct clk_hw *rp1_register_pll_core(struct rp1_clockman *clockman, ++ const void *data) ++{ ++ const struct rp1_pll_core_data *pll_core_data = data; ++ struct rp1_pll_core *pll_core; ++ struct clk_init_data init; ++ int ret; ++ ++ memset(&init, 0, sizeof(init)); ++ ++ /* All of the PLL cores derive from the external oscillator. */ ++ init.parent_names = &ref_clock; ++ init.num_parents = 1; ++ init.name = pll_core_data->name; ++ init.ops = &rp1_pll_core_ops; ++ init.flags = pll_core_data->flags | CLK_IGNORE_UNUSED | CLK_IS_CRITICAL; ++ ++ pll_core = kzalloc(sizeof(*pll_core), GFP_KERNEL); ++ if (!pll_core) ++ return NULL; ++ ++ pll_core->clockman = clockman; ++ pll_core->data = pll_core_data; ++ pll_core->hw.init = &init; ++ ++ ret = devm_clk_hw_register(clockman->dev, &pll_core->hw); ++ if (ret) { ++ kfree(pll_core); ++ return NULL; ++ } ++ ++ return &pll_core->hw; ++} ++ ++static struct clk_hw *rp1_register_pll(struct rp1_clockman *clockman, ++ const void *data) ++{ ++ const struct rp1_pll_data *pll_data = data; ++ struct rp1_pll *pll; ++ struct clk_init_data init; ++ int ret; ++ ++ memset(&init, 0, sizeof(init)); ++ ++ init.parent_names = &pll_data->source_pll; ++ init.num_parents = 1; ++ init.name = pll_data->name; ++ init.ops = &rp1_pll_ops; ++ init.flags = pll_data->flags | CLK_IGNORE_UNUSED | CLK_IS_CRITICAL; ++ ++ pll = kzalloc(sizeof(*pll), GFP_KERNEL); ++ if (!pll) ++ return NULL; ++ ++ pll->clockman = clockman; ++ pll->data = pll_data; ++ pll->hw.init = &init; ++ ++ ret = devm_clk_hw_register(clockman->dev, &pll->hw); ++ if (ret) { ++ kfree(pll); ++ return NULL; ++ } ++ ++ return &pll->hw; ++} ++ ++static struct clk_hw *rp1_register_pll_ph(struct rp1_clockman *clockman, ++ const void *data) ++{ ++ const struct rp1_pll_ph_data *ph_data = data; ++ struct rp1_pll_ph *ph; ++ struct clk_init_data init; ++ int ret; ++ ++ memset(&init, 0, sizeof(init)); ++ ++ /* All of the PLLs derive from the external oscillator. */ ++ init.parent_names = &ph_data->source_pll; ++ init.num_parents = 1; ++ init.name = ph_data->name; ++ init.ops = &rp1_pll_ph_ops; ++ init.flags = ph_data->flags | CLK_IGNORE_UNUSED; ++ ++ ph = kzalloc(sizeof(*ph), GFP_KERNEL); ++ if (!ph) ++ return NULL; ++ ++ ph->clockman = clockman; ++ ph->data = ph_data; ++ ph->hw.init = &init; ++ ++ ret = devm_clk_hw_register(clockman->dev, &ph->hw); ++ if (ret) { ++ kfree(ph); ++ return NULL; ++ } ++ ++ return &ph->hw; ++} ++ ++static struct clk_hw *rp1_register_pll_divider(struct rp1_clockman *clockman, ++ const void *data) ++{ ++ const struct rp1_pll_data *divider_data = data; ++ struct rp1_pll *divider; ++ struct clk_init_data init; ++ int ret; ++ ++ memset(&init, 0, sizeof(init)); ++ ++ init.parent_names = ÷r_data->source_pll; ++ init.num_parents = 1; ++ init.name = divider_data->name; ++ init.ops = &rp1_pll_divider_ops; ++ init.flags = divider_data->flags | CLK_IGNORE_UNUSED; ++ ++ divider = devm_kzalloc(clockman->dev, sizeof(*divider), GFP_KERNEL); ++ if (!divider) ++ return NULL; ++ ++ divider->div.reg = clockman->regs + divider_data->ctrl_reg; ++ divider->div.shift = PLL_SEC_DIV_SHIFT; ++ divider->div.width = PLL_SEC_DIV_WIDTH; ++ divider->div.flags = CLK_DIVIDER_ROUND_CLOSEST; ++ divider->div.lock = &clockman->regs_lock; ++ divider->div.hw.init = &init; ++ divider->div.table = pll_sec_div_table; ++ ++ if (!rp1_clk_is_claimed(divider_data->source_pll)) ++ init.flags |= CLK_IS_CRITICAL; ++ if (!rp1_clk_is_claimed(divider_data->name)) ++ divider->div.flags |= CLK_IS_CRITICAL; ++ ++ divider->clockman = clockman; ++ divider->data = divider_data; ++ ++ ret = devm_clk_hw_register(clockman->dev, ÷r->div.hw); ++ if (ret) ++ return ERR_PTR(ret); ++ ++ return ÷r->div.hw; ++} ++ ++static struct clk_hw *rp1_register_clock(struct rp1_clockman *clockman, ++ const void *data) ++{ ++ const struct rp1_clock_data *clock_data = data; ++ struct rp1_clock *clock; ++ struct clk_init_data init; ++ int ret; ++ ++ BUG_ON(MAX_CLK_PARENTS < ++ clock_data->num_std_parents + clock_data->num_aux_parents); ++ /* There must be a gap for the AUX selector */ ++ BUG_ON((clock_data->num_std_parents > AUX_SEL) && ++ strcmp("-", clock_data->parents[AUX_SEL])); ++ ++ memset(&init, 0, sizeof(init)); ++ init.parent_names = clock_data->parents; ++ init.num_parents = ++ clock_data->num_std_parents + clock_data->num_aux_parents; ++ init.name = clock_data->name; ++ init.flags = clock_data->flags | CLK_IGNORE_UNUSED; ++ init.ops = &rp1_clk_ops; ++ ++ clock = devm_kzalloc(clockman->dev, sizeof(*clock), GFP_KERNEL); ++ if (!clock) ++ return NULL; ++ ++ clock->clockman = clockman; ++ clock->data = clock_data; ++ clock->hw.init = &init; ++ ++ ret = devm_clk_hw_register(clockman->dev, &clock->hw); ++ if (ret) ++ return ERR_PTR(ret); ++ ++ return &clock->hw; ++} ++ ++struct rp1_clk_desc { ++ struct clk_hw *(*clk_register)(struct rp1_clockman *clockman, ++ const void *data); ++ const void *data; ++}; ++ ++/* Assignment helper macros for different clock types. */ ++#define _REGISTER(f, ...) { .clk_register = f, .data = __VA_ARGS__ } ++ ++#define REGISTER_PLL_CORE(...) _REGISTER(&rp1_register_pll_core, \ ++ &(struct rp1_pll_core_data) \ ++ {__VA_ARGS__}) ++ ++#define REGISTER_PLL(...) _REGISTER(&rp1_register_pll, \ ++ &(struct rp1_pll_data) \ ++ {__VA_ARGS__}) ++ ++#define REGISTER_PLL_PH(...) _REGISTER(&rp1_register_pll_ph, \ ++ &(struct rp1_pll_ph_data) \ ++ {__VA_ARGS__}) ++ ++#define REGISTER_PLL_DIV(...) _REGISTER(&rp1_register_pll_divider, \ ++ &(struct rp1_pll_data) \ ++ {__VA_ARGS__}) ++ ++#define REGISTER_CLK(...) _REGISTER(&rp1_register_clock, \ ++ &(struct rp1_clock_data) \ ++ {__VA_ARGS__}) ++ ++static const struct rp1_clk_desc clk_desc_array[] = { ++ [RP1_PLL_SYS_CORE] = REGISTER_PLL_CORE( ++ .name = "pll_sys_core", ++ .cs_reg = PLL_SYS_CS, ++ .pwr_reg = PLL_SYS_PWR, ++ .fbdiv_int_reg = PLL_SYS_FBDIV_INT, ++ .fbdiv_frac_reg = PLL_SYS_FBDIV_FRAC, ++ ), ++ ++ [RP1_PLL_AUDIO_CORE] = REGISTER_PLL_CORE( ++ .name = "pll_audio_core", ++ .cs_reg = PLL_AUDIO_CS, ++ .pwr_reg = PLL_AUDIO_PWR, ++ .fbdiv_int_reg = PLL_AUDIO_FBDIV_INT, ++ .fbdiv_frac_reg = PLL_AUDIO_FBDIV_FRAC, ++ ), ++ ++ [RP1_PLL_VIDEO_CORE] = REGISTER_PLL_CORE( ++ .name = "pll_video_core", ++ .cs_reg = PLL_VIDEO_CS, ++ .pwr_reg = PLL_VIDEO_PWR, ++ .fbdiv_int_reg = PLL_VIDEO_FBDIV_INT, ++ .fbdiv_frac_reg = PLL_VIDEO_FBDIV_FRAC, ++ ), ++ ++ [RP1_PLL_SYS] = REGISTER_PLL( ++ .name = "pll_sys", ++ .source_pll = "pll_sys_core", ++ .ctrl_reg = PLL_SYS_PRIM, ++ .fc0_src = FC_NUM(0, 2), ++ ), ++ ++ [RP1_PLL_AUDIO] = REGISTER_PLL( ++ .name = "pll_audio", ++ .source_pll = "pll_audio_core", ++ .ctrl_reg = PLL_AUDIO_PRIM, ++ .fc0_src = FC_NUM(4, 2), ++ .flags = CLK_SET_RATE_PARENT, ++ ), ++ ++ [RP1_PLL_VIDEO] = REGISTER_PLL( ++ .name = "pll_video", ++ .source_pll = "pll_video_core", ++ .ctrl_reg = PLL_VIDEO_PRIM, ++ .fc0_src = FC_NUM(3, 2), ++ ), ++ ++ [RP1_PLL_SYS_PRI_PH] = REGISTER_PLL_PH( ++ .name = "pll_sys_pri_ph", ++ .source_pll = "pll_sys", ++ .ph_reg = PLL_SYS_PRIM, ++ .fixed_divider = 2, ++ .phase = RP1_PLL_PHASE_0, ++ .fc0_src = FC_NUM(1, 2), ++ ), ++ ++ [RP1_PLL_AUDIO_PRI_PH] = REGISTER_PLL_PH( ++ .name = "pll_audio_pri_ph", ++ .source_pll = "pll_audio", ++ .ph_reg = PLL_AUDIO_PRIM, ++ .fixed_divider = 2, ++ .phase = RP1_PLL_PHASE_0, ++ .fc0_src = FC_NUM(5, 1), ++ ), ++ ++ [RP1_PLL_VIDEO_PRI_PH] = REGISTER_PLL_PH( ++ .name = "pll_video_pri_ph", ++ .source_pll = "pll_video", ++ .ph_reg = PLL_VIDEO_PRIM, ++ .fixed_divider = 2, ++ .phase = RP1_PLL_PHASE_0, ++ .fc0_src = FC_NUM(4, 3), ++ ), ++ ++ [RP1_PLL_SYS_SEC] = REGISTER_PLL_DIV( ++ .name = "pll_sys_sec", ++ .source_pll = "pll_sys_core", ++ .ctrl_reg = PLL_SYS_SEC, ++ .fc0_src = FC_NUM(2, 2), ++ ), ++ ++ [RP1_PLL_AUDIO_SEC] = REGISTER_PLL_DIV( ++ .name = "pll_audio_sec", ++ .source_pll = "pll_audio_core", ++ .ctrl_reg = PLL_AUDIO_SEC, ++ .fc0_src = FC_NUM(6, 2), ++ ), ++ ++ [RP1_PLL_VIDEO_SEC] = REGISTER_PLL_DIV( ++ .name = "pll_video_sec", ++ .source_pll = "pll_video_core", ++ .ctrl_reg = PLL_VIDEO_SEC, ++ .fc0_src = FC_NUM(5, 3), ++ ), ++ ++ [RP1_PLL_AUDIO_TERN] = REGISTER_PLL_DIV( ++ .name = "pll_audio_tern", ++ .source_pll = "pll_audio_core", ++ .ctrl_reg = PLL_AUDIO_TERN, ++ .fc0_src = FC_NUM(6, 2), ++ ), ++ ++ [RP1_CLK_SYS] = REGISTER_CLK( ++ .name = "clk_sys", ++ .parents = {"xosc", "-", "pll_sys"}, ++ .num_std_parents = 3, ++ .num_aux_parents = 0, ++ .ctrl_reg = CLK_SYS_CTRL, ++ .div_int_reg = CLK_SYS_DIV_INT, ++ .sel_reg = CLK_SYS_SEL, ++ .div_int_max = DIV_INT_24BIT_MAX, ++ .max_freq = 200 * MHz, ++ .fc0_src = FC_NUM(0, 4), ++ .clk_src_mask = 0x3, ++ ), ++ ++ [RP1_CLK_SLOW_SYS] = REGISTER_CLK( ++ .name = "clk_slow_sys", ++ .parents = {"xosc"}, ++ .num_std_parents = 1, ++ .num_aux_parents = 0, ++ .ctrl_reg = CLK_SLOW_SYS_CTRL, ++ .div_int_reg = CLK_SLOW_SYS_DIV_INT, ++ .sel_reg = CLK_SLOW_SYS_SEL, ++ .div_int_max = DIV_INT_8BIT_MAX, ++ .max_freq = 50 * MHz, ++ .fc0_src = FC_NUM(1, 4), ++ .clk_src_mask = 0x1, ++ ), ++ ++ [RP1_CLK_UART] = REGISTER_CLK( ++ .name = "clk_uart", ++ .parents = {"pll_sys_pri_ph", ++ "pll_video", ++ "xosc", ++ "clksrc_gp0", ++ "clksrc_gp1", ++ "clksrc_gp2", ++ "clksrc_gp3", ++ "clksrc_gp4", ++ "clksrc_gp5"}, ++ .num_std_parents = 0, ++ .num_aux_parents = 9, ++ .ctrl_reg = CLK_UART_CTRL, ++ .div_int_reg = CLK_UART_DIV_INT, ++ .sel_reg = CLK_UART_SEL, ++ .div_int_max = DIV_INT_8BIT_MAX, ++ .max_freq = 100 * MHz, ++ .fc0_src = FC_NUM(6, 7), ++ ), ++ ++ [RP1_CLK_ETH] = REGISTER_CLK( ++ .name = "clk_eth", ++ .parents = {"pll_sys_sec", ++ "pll_sys", ++ "pll_video_sec", ++ "clksrc_gp0", ++ "clksrc_gp1", ++ "clksrc_gp2", ++ "clksrc_gp3", ++ "clksrc_gp4", ++ "clksrc_gp5"}, ++ .num_std_parents = 0, ++ .num_aux_parents = 9, ++ .ctrl_reg = CLK_ETH_CTRL, ++ .div_int_reg = CLK_ETH_DIV_INT, ++ .sel_reg = CLK_ETH_SEL, ++ .div_int_max = DIV_INT_8BIT_MAX, ++ .max_freq = 125 * MHz, ++ .fc0_src = FC_NUM(4, 6), ++ ), ++ ++ [RP1_CLK_PWM0] = REGISTER_CLK( ++ .name = "clk_pwm0", ++ .parents = {"", // "pll_audio_pri_ph", ++ "pll_video_sec", ++ "xosc", ++ "clksrc_gp0", ++ "clksrc_gp1", ++ "clksrc_gp2", ++ "clksrc_gp3", ++ "clksrc_gp4", ++ "clksrc_gp5"}, ++ .num_std_parents = 0, ++ .num_aux_parents = 9, ++ .ctrl_reg = CLK_PWM0_CTRL, ++ .div_int_reg = CLK_PWM0_DIV_INT, ++ .div_frac_reg = CLK_PWM0_DIV_FRAC, ++ .sel_reg = CLK_PWM0_SEL, ++ .div_int_max = DIV_INT_16BIT_MAX, ++ .max_freq = 76800 * KHz, ++ .fc0_src = FC_NUM(0, 5), ++ ), ++ ++ [RP1_CLK_PWM1] = REGISTER_CLK( ++ .name = "clk_pwm1", ++ .parents = {"", // "pll_audio_pri_ph", ++ "pll_video_sec", ++ "xosc", ++ "clksrc_gp0", ++ "clksrc_gp1", ++ "clksrc_gp2", ++ "clksrc_gp3", ++ "clksrc_gp4", ++ "clksrc_gp5"}, ++ .num_std_parents = 0, ++ .num_aux_parents = 9, ++ .ctrl_reg = CLK_PWM1_CTRL, ++ .div_int_reg = CLK_PWM1_DIV_INT, ++ .div_frac_reg = CLK_PWM1_DIV_FRAC, ++ .sel_reg = CLK_PWM1_SEL, ++ .div_int_max = DIV_INT_16BIT_MAX, ++ .max_freq = 76800 * KHz, ++ .fc0_src = FC_NUM(1, 5), ++ ), ++ ++ [RP1_CLK_AUDIO_IN] = REGISTER_CLK( ++ .name = "clk_audio_in", ++ .parents = {"", //"pll_audio", ++ "", //"pll_audio_pri_ph", ++ "", //"pll_audio_sec", ++ "pll_video_sec", ++ "xosc", ++ "clksrc_gp0", ++ "clksrc_gp1", ++ "clksrc_gp2", ++ "clksrc_gp3", ++ "clksrc_gp4", ++ "clksrc_gp5"}, ++ .num_std_parents = 0, ++ .num_aux_parents = 11, ++ .ctrl_reg = CLK_AUDIO_IN_CTRL, ++ .div_int_reg = CLK_AUDIO_IN_DIV_INT, ++ .sel_reg = CLK_AUDIO_IN_SEL, ++ .div_int_max = DIV_INT_8BIT_MAX, ++ .max_freq = 76800 * KHz, ++ .fc0_src = FC_NUM(2, 5), ++ ), ++ ++ [RP1_CLK_AUDIO_OUT] = REGISTER_CLK( ++ .name = "clk_audio_out", ++ .parents = {"", //"pll_audio", ++ "", //"pll_audio_sec", ++ "pll_video_sec", ++ "xosc", ++ "clksrc_gp0", ++ "clksrc_gp1", ++ "clksrc_gp2", ++ "clksrc_gp3", ++ "clksrc_gp4", ++ "clksrc_gp5"}, ++ .num_std_parents = 0, ++ .num_aux_parents = 10, ++ .ctrl_reg = CLK_AUDIO_OUT_CTRL, ++ .div_int_reg = CLK_AUDIO_OUT_DIV_INT, ++ .sel_reg = CLK_AUDIO_OUT_SEL, ++ .div_int_max = DIV_INT_8BIT_MAX, ++ .max_freq = 153600 * KHz, ++ .fc0_src = FC_NUM(3, 5), ++ ), ++ ++ [RP1_CLK_I2S] = REGISTER_CLK( ++ .name = "clk_i2s", ++ .parents = {"xosc", ++ "pll_audio", ++ "pll_audio_sec", ++ "clksrc_gp0", ++ "clksrc_gp1", ++ "clksrc_gp2", ++ "clksrc_gp3", ++ "clksrc_gp4", ++ "clksrc_gp5"}, ++ .num_std_parents = 0, ++ .num_aux_parents = 9, ++ .ctrl_reg = CLK_I2S_CTRL, ++ .div_int_reg = CLK_I2S_DIV_INT, ++ .sel_reg = CLK_I2S_SEL, ++ .div_int_max = DIV_INT_8BIT_MAX, ++ .max_freq = 50 * MHz, ++ .fc0_src = FC_NUM(4, 4), ++ .flags = CLK_SET_RATE_PARENT, ++ ), ++ ++ [RP1_CLK_MIPI0_CFG] = REGISTER_CLK( ++ .name = "clk_mipi0_cfg", ++ .parents = {"xosc"}, ++ .num_std_parents = 0, ++ .num_aux_parents = 1, ++ .ctrl_reg = CLK_MIPI0_CFG_CTRL, ++ .div_int_reg = CLK_MIPI0_CFG_DIV_INT, ++ .sel_reg = CLK_MIPI0_CFG_SEL, ++ .div_int_max = DIV_INT_8BIT_MAX, ++ .max_freq = 50 * MHz, ++ .fc0_src = FC_NUM(4, 5), ++ ), ++ ++ [RP1_CLK_MIPI1_CFG] = REGISTER_CLK( ++ .name = "clk_mipi1_cfg", ++ .parents = {"xosc"}, ++ .num_std_parents = 0, ++ .num_aux_parents = 1, ++ .ctrl_reg = CLK_MIPI1_CFG_CTRL, ++ .div_int_reg = CLK_MIPI1_CFG_DIV_INT, ++ .sel_reg = CLK_MIPI1_CFG_SEL, ++ .clk_src_mask = 1, ++ .div_int_max = DIV_INT_8BIT_MAX, ++ .max_freq = 50 * MHz, ++ .fc0_src = FC_NUM(5, 6), ++ ), ++ ++ [RP1_CLK_ETH_TSU] = REGISTER_CLK( ++ .name = "clk_eth_tsu", ++ .parents = {"xosc", ++ "pll_video_sec", ++ "clksrc_gp0", ++ "clksrc_gp1", ++ "clksrc_gp2", ++ "clksrc_gp3", ++ "clksrc_gp4", ++ "clksrc_gp5"}, ++ .num_std_parents = 0, ++ .num_aux_parents = 8, ++ .ctrl_reg = CLK_ETH_TSU_CTRL, ++ .div_int_reg = CLK_ETH_TSU_DIV_INT, ++ .sel_reg = CLK_ETH_TSU_SEL, ++ .div_int_max = DIV_INT_8BIT_MAX, ++ .max_freq = 50 * MHz, ++ .fc0_src = FC_NUM(5, 7), ++ ), ++ ++ [RP1_CLK_ADC] = REGISTER_CLK( ++ .name = "clk_adc", ++ .parents = {"xosc", ++ "", //"pll_audio_tern", ++ "clksrc_gp0", ++ "clksrc_gp1", ++ "clksrc_gp2", ++ "clksrc_gp3", ++ "clksrc_gp4", ++ "clksrc_gp5"}, ++ .num_std_parents = 0, ++ .num_aux_parents = 8, ++ .ctrl_reg = CLK_ADC_CTRL, ++ .div_int_reg = CLK_ADC_DIV_INT, ++ .sel_reg = CLK_ADC_SEL, ++ .div_int_max = DIV_INT_8BIT_MAX, ++ .max_freq = 50 * MHz, ++ .fc0_src = FC_NUM(5, 5), ++ ), ++ ++ [RP1_CLK_SDIO_TIMER] = REGISTER_CLK( ++ .name = "clk_sdio_timer", ++ .parents = {"xosc"}, ++ .num_std_parents = 0, ++ .num_aux_parents = 1, ++ .ctrl_reg = CLK_SDIO_TIMER_CTRL, ++ .div_int_reg = CLK_SDIO_TIMER_DIV_INT, ++ .sel_reg = CLK_SDIO_TIMER_SEL, ++ .div_int_max = DIV_INT_8BIT_MAX, ++ .max_freq = 50 * MHz, ++ .fc0_src = FC_NUM(3, 4), ++ ), ++ ++ [RP1_CLK_SDIO_ALT_SRC] = REGISTER_CLK( ++ .name = "clk_sdio_alt_src", ++ .parents = {"pll_sys"}, ++ .num_std_parents = 0, ++ .num_aux_parents = 1, ++ .ctrl_reg = CLK_SDIO_ALT_SRC_CTRL, ++ .div_int_reg = CLK_SDIO_ALT_SRC_DIV_INT, ++ .sel_reg = CLK_SDIO_ALT_SRC_SEL, ++ .div_int_max = DIV_INT_8BIT_MAX, ++ .max_freq = 200 * MHz, ++ .fc0_src = FC_NUM(5, 4), ++ ), ++ ++ [RP1_CLK_GP0] = REGISTER_CLK( ++ .name = "clk_gp0", ++ .parents = {"xosc", ++ "clksrc_gp1", ++ "clksrc_gp2", ++ "clksrc_gp3", ++ "clksrc_gp4", ++ "clksrc_gp5", ++ "pll_sys", ++ "", //"pll_audio", ++ "", ++ "", ++ "clk_i2s", ++ "clk_adc", ++ "", ++ "", ++ "", ++ "clk_sys"}, ++ .num_std_parents = 0, ++ .num_aux_parents = 16, ++ .oe_mask = BIT(0), ++ .ctrl_reg = CLK_GP0_CTRL, ++ .div_int_reg = CLK_GP0_DIV_INT, ++ .div_frac_reg = CLK_GP0_DIV_FRAC, ++ .sel_reg = CLK_GP0_SEL, ++ .div_int_max = DIV_INT_16BIT_MAX, ++ .max_freq = 100 * MHz, ++ .fc0_src = FC_NUM(0, 1), ++ ), ++ ++ [RP1_CLK_GP1] = REGISTER_CLK( ++ .name = "clk_gp1", ++ .parents = {"clk_sdio_timer", ++ "clksrc_gp0", ++ "clksrc_gp2", ++ "clksrc_gp3", ++ "clksrc_gp4", ++ "clksrc_gp5", ++ "pll_sys_pri_ph", ++ "", //"pll_audio_pri_ph", ++ "", ++ "", ++ "clk_adc", ++ "clk_dpi", ++ "clk_pwm0", ++ "", ++ "", ++ ""}, ++ .num_std_parents = 0, ++ .num_aux_parents = 16, ++ .oe_mask = BIT(1), ++ .ctrl_reg = CLK_GP1_CTRL, ++ .div_int_reg = CLK_GP1_DIV_INT, ++ .div_frac_reg = CLK_GP1_DIV_FRAC, ++ .sel_reg = CLK_GP1_SEL, ++ .div_int_max = DIV_INT_16BIT_MAX, ++ .max_freq = 100 * MHz, ++ .fc0_src = FC_NUM(1, 1), ++ ), ++ ++ [RP1_CLK_GP2] = REGISTER_CLK( ++ .name = "clk_gp2", ++ .parents = {"clk_sdio_alt_src", ++ "clksrc_gp0", ++ "clksrc_gp1", ++ "clksrc_gp3", ++ "clksrc_gp4", ++ "clksrc_gp5", ++ "pll_sys_sec", ++ "", //"pll_audio_sec", ++ "pll_video", ++ "clk_audio_in", ++ "clk_dpi", ++ "clk_pwm0", ++ "clk_pwm1", ++ "clk_mipi0_dpi", ++ "clk_mipi1_cfg", ++ "clk_sys"}, ++ .num_std_parents = 0, ++ .num_aux_parents = 16, ++ .oe_mask = BIT(2), ++ .ctrl_reg = CLK_GP2_CTRL, ++ .div_int_reg = CLK_GP2_DIV_INT, ++ .div_frac_reg = CLK_GP2_DIV_FRAC, ++ .sel_reg = CLK_GP2_SEL, ++ .div_int_max = DIV_INT_16BIT_MAX, ++ .max_freq = 100 * MHz, ++ .fc0_src = FC_NUM(2, 1), ++ ), ++ ++ [RP1_CLK_GP3] = REGISTER_CLK( ++ .name = "clk_gp3", ++ .parents = {"xosc", ++ "clksrc_gp0", ++ "clksrc_gp1", ++ "clksrc_gp2", ++ "clksrc_gp4", ++ "clksrc_gp5", ++ "", ++ "", ++ "pll_video_pri_ph", ++ "clk_audio_out", ++ "", ++ "", ++ "clk_mipi1_dpi", ++ "", ++ "", ++ ""}, ++ .num_std_parents = 0, ++ .num_aux_parents = 16, ++ .oe_mask = BIT(3), ++ .ctrl_reg = CLK_GP3_CTRL, ++ .div_int_reg = CLK_GP3_DIV_INT, ++ .div_frac_reg = CLK_GP3_DIV_FRAC, ++ .sel_reg = CLK_GP3_SEL, ++ .div_int_max = DIV_INT_16BIT_MAX, ++ .max_freq = 100 * MHz, ++ .fc0_src = FC_NUM(3, 1), ++ ), ++ ++ [RP1_CLK_GP4] = REGISTER_CLK( ++ .name = "clk_gp4", ++ .parents = {"xosc", ++ "clksrc_gp0", ++ "clksrc_gp1", ++ "clksrc_gp2", ++ "clksrc_gp3", ++ "clksrc_gp5", ++ "", //"pll_audio_tern", ++ "pll_video_sec", ++ "", ++ "", ++ "", ++ "clk_mipi0_cfg", ++ "clk_uart", ++ "", ++ "", ++ "clk_sys", ++ }, ++ .num_std_parents = 0, ++ .num_aux_parents = 16, ++ .oe_mask = BIT(4), ++ .ctrl_reg = CLK_GP4_CTRL, ++ .div_int_reg = CLK_GP4_DIV_INT, ++ .div_frac_reg = CLK_GP4_DIV_FRAC, ++ .sel_reg = CLK_GP4_SEL, ++ .div_int_max = DIV_INT_16BIT_MAX, ++ .max_freq = 100 * MHz, ++ .fc0_src = FC_NUM(4, 1), ++ ), ++ ++ [RP1_CLK_GP5] = REGISTER_CLK( ++ .name = "clk_gp5", ++ .parents = {"xosc", ++ "clksrc_gp0", ++ "clksrc_gp1", ++ "clksrc_gp2", ++ "clksrc_gp3", ++ "clksrc_gp4", ++ "", //"pll_audio_tern", ++ "pll_video_sec", ++ "clk_eth_tsu", ++ "", ++ "clk_vec", ++ "", ++ "", ++ "", ++ "", ++ ""}, ++ .num_std_parents = 0, ++ .num_aux_parents = 16, ++ .oe_mask = BIT(5), ++ .ctrl_reg = CLK_GP5_CTRL, ++ .div_int_reg = CLK_GP5_DIV_INT, ++ .div_frac_reg = CLK_GP5_DIV_FRAC, ++ .sel_reg = CLK_GP5_SEL, ++ .div_int_max = DIV_INT_16BIT_MAX, ++ .max_freq = 100 * MHz, ++ .fc0_src = FC_NUM(5, 1), ++ ), ++ ++ [RP1_CLK_VEC] = REGISTER_CLK( ++ .name = "clk_vec", ++ .parents = {"pll_sys_pri_ph", ++ "pll_video_sec", ++ "pll_video", ++ "clksrc_gp0", ++ "clksrc_gp1", ++ "clksrc_gp2", ++ "clksrc_gp3", ++ "clksrc_gp4"}, ++ .num_std_parents = 0, ++ .num_aux_parents = 8, /* XXX in fact there are more than 8 */ ++ .ctrl_reg = VIDEO_CLK_VEC_CTRL, ++ .div_int_reg = VIDEO_CLK_VEC_DIV_INT, ++ .sel_reg = VIDEO_CLK_VEC_SEL, ++ .flags = CLK_SET_RATE_NO_REPARENT, /* Let VEC driver set parent */ ++ .div_int_max = DIV_INT_8BIT_MAX, ++ .max_freq = 108 * MHz, ++ .fc0_src = FC_NUM(0, 6), ++ ), ++ ++ [RP1_CLK_DPI] = REGISTER_CLK( ++ .name = "clk_dpi", ++ .parents = {"pll_sys", ++ "pll_video_sec", ++ "pll_video", ++ "clksrc_gp0", ++ "clksrc_gp1", ++ "clksrc_gp2", ++ "clksrc_gp3", ++ "clksrc_gp4"}, ++ .num_std_parents = 0, ++ .num_aux_parents = 8, /* XXX in fact there are more than 8 */ ++ .ctrl_reg = VIDEO_CLK_DPI_CTRL, ++ .div_int_reg = VIDEO_CLK_DPI_DIV_INT, ++ .sel_reg = VIDEO_CLK_DPI_SEL, ++ .flags = CLK_SET_RATE_NO_REPARENT, /* Let DPI driver set parent */ ++ .div_int_max = DIV_INT_8BIT_MAX, ++ .max_freq = 200 * MHz, ++ .fc0_src = FC_NUM(1, 6), ++ ), ++ ++ [RP1_CLK_MIPI0_DPI] = REGISTER_CLK( ++ .name = "clk_mipi0_dpi", ++ .parents = {"pll_sys", ++ "pll_video_sec", ++ "pll_video", ++ "clksrc_mipi0_dsi_byteclk", ++ "clksrc_gp0", ++ "clksrc_gp1", ++ "clksrc_gp2", ++ "clksrc_gp3"}, ++ .num_std_parents = 0, ++ .num_aux_parents = 8, /* XXX in fact there are more than 8 */ ++ .ctrl_reg = VIDEO_CLK_MIPI0_DPI_CTRL, ++ .div_int_reg = VIDEO_CLK_MIPI0_DPI_DIV_INT, ++ .div_frac_reg = VIDEO_CLK_MIPI0_DPI_DIV_FRAC, ++ .sel_reg = VIDEO_CLK_MIPI0_DPI_SEL, ++ .flags = CLK_SET_RATE_NO_REPARENT, /* Let DSI driver set parent */ ++ .div_int_max = DIV_INT_8BIT_MAX, ++ .max_freq = 200 * MHz, ++ .fc0_src = FC_NUM(2, 6), ++ ), ++ ++ [RP1_CLK_MIPI1_DPI] = REGISTER_CLK( ++ .name = "clk_mipi1_dpi", ++ .parents = {"pll_sys", ++ "pll_video_sec", ++ "pll_video", ++ "clksrc_mipi1_dsi_byteclk", ++ "clksrc_gp0", ++ "clksrc_gp1", ++ "clksrc_gp2", ++ "clksrc_gp3"}, ++ .num_std_parents = 0, ++ .num_aux_parents = 8, /* XXX in fact there are more than 8 */ ++ .ctrl_reg = VIDEO_CLK_MIPI1_DPI_CTRL, ++ .div_int_reg = VIDEO_CLK_MIPI1_DPI_DIV_INT, ++ .div_frac_reg = VIDEO_CLK_MIPI1_DPI_DIV_FRAC, ++ .sel_reg = VIDEO_CLK_MIPI1_DPI_SEL, ++ .flags = CLK_SET_RATE_NO_REPARENT, /* Let DSI driver set parent */ ++ .div_int_max = DIV_INT_8BIT_MAX, ++ .max_freq = 200 * MHz, ++ .fc0_src = FC_NUM(3, 6), ++ ), ++}; ++ ++static bool rp1_clk_claimed[ARRAY_SIZE(clk_desc_array)]; ++ ++static bool rp1_clk_is_claimed(const char *name) ++{ ++ unsigned int i; ++ ++ for (i = 0; i < ARRAY_SIZE(clk_desc_array); i++) { ++ if (clk_desc_array[i].data) { ++ const char *clk_name = *(const char **)(clk_desc_array[i].data); ++ ++ if (!strcmp(name, clk_name)) ++ return rp1_clk_claimed[i]; ++ } ++ } ++ ++ return false; ++} ++ ++static int rp1_clk_probe(struct platform_device *pdev) ++{ ++ const struct rp1_clk_desc *desc; ++ struct device *dev = &pdev->dev; ++ struct rp1_clockman *clockman; ++ struct resource *res; ++ struct clk_hw **hws; ++ const size_t asize = ARRAY_SIZE(clk_desc_array); ++ u32 chip_id, platform; ++ unsigned int i; ++ u32 clk_id; ++ int ret; ++ ++ clockman = devm_kzalloc(dev, struct_size(clockman, onecell.hws, asize), ++ GFP_KERNEL); ++ if (!clockman) ++ return -ENOMEM; ++ ++ rp1_get_platform(&chip_id, &platform); ++ ++ spin_lock_init(&clockman->regs_lock); ++ clockman->dev = dev; ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ clockman->regs = devm_ioremap_resource(&pdev->dev, res); ++ if (IS_ERR(clockman->regs)) ++ return PTR_ERR(clockman->regs); ++ ++ memset(rp1_clk_claimed, 0, sizeof(rp1_clk_claimed)); ++ for (i = 0; ++ !of_property_read_u32_index(pdev->dev.of_node, "claim-clocks", ++ i, &clk_id); ++ i++) ++ rp1_clk_claimed[clk_id] = true; ++ ++ platform_set_drvdata(pdev, clockman); ++ ++ clockman->onecell.num = asize; ++ hws = clockman->onecell.hws; ++ ++ for (i = 0; i < asize; i++) { ++ desc = &clk_desc_array[i]; ++ if (desc->clk_register && desc->data) { ++ hws[i] = desc->clk_register(clockman, desc->data); ++ if (!strcmp(clk_hw_get_name(hws[i]), "clk_i2s")) { ++ clk_i2s = hws[i]; ++ clk_xosc = clk_hw_get_parent_by_index(clk_i2s, 0); ++ clk_audio = clk_hw_get_parent_by_index(clk_i2s, 1); ++ } ++ } ++ } ++ ++ ret = of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get, ++ &clockman->onecell); ++ if (ret) ++ return ret; ++ ++ return 0; ++} ++ ++static const struct of_device_id rp1_clk_of_match[] = { ++ { .compatible = "raspberrypi,rp1-clocks" }, ++ {} ++}; ++MODULE_DEVICE_TABLE(of, rp1_clk_of_match); ++ ++static struct platform_driver rp1_clk_driver = { ++ .driver = { ++ .name = "rp1-clk", ++ .of_match_table = rp1_clk_of_match, ++ }, ++ .probe = rp1_clk_probe, ++}; ++ ++static int __init __rp1_clk_driver_init(void) ++{ ++ return platform_driver_register(&rp1_clk_driver); ++} ++postcore_initcall(__rp1_clk_driver_init); ++ ++MODULE_AUTHOR("Naushir Patuck "); ++MODULE_DESCRIPTION("RP1 clock driver"); ++MODULE_LICENSE("GPL"); diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig -index 08013345d1f2..cdfb63c723f6 100644 +index 4ccae1a3b884..7d3435a7df41 100644 --- a/drivers/dma/Kconfig +++ b/drivers/dma/Kconfig -@@ -652,6 +652,10 @@ config UNIPHIER_XDMAC +@@ -669,6 +669,10 @@ config UNIPHIER_XDMAC UniPhier platform. This DMA controller can transfer data from memory to memory, memory to peripheral and peripheral to memory. @@ -49196,20 +69412,20 @@ index 08013345d1f2..cdfb63c723f6 100644 tristate "APM X-Gene DMA support" depends on ARCH_XGENE || COMPILE_TEST diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile -index 948a8da05f8b..e543c69fa6b5 100644 +index 83553a97a010..b4a8e3585400 100644 --- a/drivers/dma/Makefile +++ b/drivers/dma/Makefile -@@ -21,6 +21,7 @@ obj-$(CONFIG_AT_XDMAC) += at_xdmac.o +@@ -22,6 +22,7 @@ obj-$(CONFIG_AT_HDMAC) += at_hdmac.o + obj-$(CONFIG_AT_XDMAC) += at_xdmac.o obj-$(CONFIG_AXI_DMAC) += dma-axi-dmac.o obj-$(CONFIG_BCM_SBA_RAID) += bcm-sba-raid.o - obj-$(CONFIG_COH901318) += coh901318.o coh901318_lli.o +obj-$(CONFIG_DMA_BCM2708) += bcm2708-dmaengine.o obj-$(CONFIG_DMA_BCM2835) += bcm2835-dma.o obj-$(CONFIG_DMA_JZ4780) += dma-jz4780.o obj-$(CONFIG_DMA_SA11X0) += sa11x0-dma.o diff --git a/drivers/dma/bcm2708-dmaengine.c b/drivers/dma/bcm2708-dmaengine.c new file mode 100644 -index 000000000000..075da9aadf6d +index 000000000000..a9a7f92584c8 --- /dev/null +++ b/drivers/dma/bcm2708-dmaengine.c @@ -0,0 +1,281 @@ @@ -49414,8 +69630,8 @@ index 000000000000..075da9aadf6d +{ + struct vc_dmaman *dmaman = g_dmaman; + struct platform_device *pdev = to_platform_device(dmaman_dev); -+ struct resource *r; + int chan; ++ int irq; + + if (!dmaman_dev) + return -ENODEV; @@ -49425,8 +69641,8 @@ index 000000000000..075da9aadf6d + if (chan < 0) + goto out; + -+ r = platform_get_resource(pdev, IORESOURCE_IRQ, (unsigned int)chan); -+ if (!r) { ++ irq = platform_get_irq(pdev, (unsigned int)chan); ++ if (irq < 0) { + dev_err(dmaman_dev, "failed to get irq for DMA channel %d\n", + chan); + vc_dmaman_chan_free(dmaman, chan); @@ -49435,7 +69651,7 @@ index 000000000000..075da9aadf6d + } + + *out_dma_base = BCM2708_DMA_CHANIO(dmaman->dma_base, chan); -+ *out_dma_irq = r->start; ++ *out_dma_irq = irq; + dev_dbg(dmaman_dev, + "Legacy API allocated channel=%d, base=%p, irq=%i\n", + chan, *out_dma_base, *out_dma_irq); @@ -49495,10 +69711,18 @@ index 000000000000..075da9aadf6d + +MODULE_LICENSE("GPL"); diff --git a/drivers/dma/bcm2835-dma.c b/drivers/dma/bcm2835-dma.c -index 630dfbb01a40..94a1b40b1645 100644 +index 0807fb9eb262..e159f976a6b1 100644 --- a/drivers/dma/bcm2835-dma.c +++ b/drivers/dma/bcm2835-dma.c -@@ -25,6 +25,7 @@ +@@ -18,6 +18,7 @@ + * Copyright 2012 Marvell International Ltd. + */ + #include ++#include + #include + #include + #include +@@ -25,6 +26,7 @@ #include #include #include @@ -49506,7 +69730,7 @@ index 630dfbb01a40..94a1b40b1645 100644 #include #include #include -@@ -36,6 +37,13 @@ +@@ -36,6 +38,13 @@ #define BCM2835_DMA_MAX_DMA_CHAN_SUPPORTED 14 #define BCM2835_DMA_CHAN_NAME_SIZE 8 @@ -49520,7 +69744,7 @@ index 630dfbb01a40..94a1b40b1645 100644 /** * struct bcm2835_dmadev - BCM2835 DMA controller -@@ -48,6 +56,7 @@ struct bcm2835_dmadev { +@@ -48,6 +57,7 @@ struct bcm2835_dmadev { struct dma_device ddev; void __iomem *base; dma_addr_t zero_page; @@ -49528,7 +69752,7 @@ index 630dfbb01a40..94a1b40b1645 100644 }; struct bcm2835_dma_cb { -@@ -60,6 +69,17 @@ struct bcm2835_dma_cb { +@@ -60,6 +70,17 @@ struct bcm2835_dma_cb { uint32_t pad[2]; }; @@ -49546,18 +69770,22 @@ index 630dfbb01a40..94a1b40b1645 100644 struct bcm2835_cb_entry { struct bcm2835_dma_cb *cb; dma_addr_t paddr; -@@ -80,6 +100,7 @@ struct bcm2835_chan { +@@ -80,6 +101,8 @@ struct bcm2835_chan { unsigned int irq_flags; bool is_lite_channel; + bool is_40bit_channel; ++ bool is_2712; }; struct bcm2835_desc { -@@ -137,10 +158,30 @@ struct bcm2835_desc { +@@ -136,11 +159,37 @@ struct bcm2835_desc { + #define BCM2835_DMA_S_WIDTH BIT(9) /* 128bit writes if set */ #define BCM2835_DMA_S_DREQ BIT(10) /* enable SREQ for source */ #define BCM2835_DMA_S_IGNORE BIT(11) /* ignore source reads - read 0 */ - #define BCM2835_DMA_BURST_LENGTH(x) ((x & 15) << 12) +-#define BCM2835_DMA_BURST_LENGTH(x) ((x & 15) << 12) ++#define BCM2835_DMA_BURST_LENGTH(x) (((x) & 15) << 12) ++#define BCM2835_DMA_GET_BURST_LENGTH(x) (((x) >> 12) & 15) +#define BCM2835_DMA_CS_FLAGS(x) (x & (BCM2835_DMA_PRIORITY(15) | \ + BCM2835_DMA_PANIC_PRIORITY(15) | \ + BCM2835_DMA_WAIT_FOR_WRITES | \ @@ -49581,11 +69809,16 @@ index 630dfbb01a40..94a1b40b1645 100644 +#define WIDE_DEST(x) ((x & BCM2835_DMA_WIDE_DEST) ? \ + BCM2835_DMA_D_WIDTH : 0) + ++/* A fake bit to request that the driver requires multi-beat burst */ ++#define BCM2835_DMA_BURST BIT(30) ++#define BURST_LENGTH(x) ((x & BCM2835_DMA_BURST) ? \ ++ BCM2835_DMA_BURST_LENGTH(3) : 0) ++ + /* debug register bits */ #define BCM2835_DMA_DEBUG_LAST_NOT_SET_ERR BIT(0) #define BCM2835_DMA_DEBUG_FIFO_ERR BIT(1) -@@ -165,13 +206,120 @@ struct bcm2835_desc { +@@ -165,13 +214,130 @@ struct bcm2835_desc { #define BCM2835_DMA_DATA_TYPE_S128 16 /* Valid only for channels 0 - 14, 15 has its own base address */ @@ -49619,13 +69852,17 @@ index 630dfbb01a40..94a1b40b1645 100644 +#define BCM2711_DMA40_WR_PAUSED BIT(5) /* Writing is paused */ +#define BCM2711_DMA40_DREQ_PAUSED BIT(6) /* Is paused by DREQ flow control */ +#define BCM2711_DMA40_WAITING_FOR_WRITES BIT(7) /* Waiting for last write */ ++// we always want to run in supervisor mode ++#define BCM2711_DMA40_PROT (BIT(8)|BIT(9)) +#define BCM2711_DMA40_ERR BIT(10) +#define BCM2711_DMA40_QOS(x) (((x) & 0x1f) << 16) +#define BCM2711_DMA40_PANIC_QOS(x) (((x) & 0x1f) << 20) ++#define BCM2711_DMA40_TRANSACTIONS BIT(25) +#define BCM2711_DMA40_WAIT_FOR_WRITES BIT(28) +#define BCM2711_DMA40_DISDEBUG BIT(29) +#define BCM2711_DMA40_ABORT BIT(30) +#define BCM2711_DMA40_HALT BIT(31) ++ +#define BCM2711_DMA40_CS_FLAGS(x) (x & (BCM2711_DMA40_QOS(15) | \ + BCM2711_DMA40_PANIC_QOS(15) | \ + BCM2711_DMA40_WAIT_FOR_WRITES | \ @@ -49668,7 +69905,7 @@ index 630dfbb01a40..94a1b40b1645 100644 +/* the max dma length for different channels */ +#define MAX_DMA40_LEN SZ_1G + -+#define BCM2711_DMA40_BURST_LEN(x) ((min(x,16) - 1) << 8) ++#define BCM2711_DMA40_BURST_LEN(x) (((x) & 15) << 8) +#define BCM2711_DMA40_INC BIT(12) +#define BCM2711_DMA40_SIZE_32 (0 << 13) +#define BCM2711_DMA40_SIZE_64 (1 << 13) @@ -49703,11 +69940,17 @@ index 630dfbb01a40..94a1b40b1645 100644 + .chan_40bit_mask = BIT(11) | BIT(12) | BIT(13) | BIT(14), + .dma_mask = DMA_BIT_MASK(36), +}; ++ ++static const struct bcm2835_dma_cfg_data bcm2712_dma_cfg = { ++ .chan_40bit_mask = BIT(6) | BIT(7) | BIT(8) | BIT(9) | ++ BIT(10) | BIT(11), ++ .dma_mask = DMA_BIT_MASK(40), ++}; + static inline size_t bcm2835_dma_max_frame_length(struct bcm2835_chan *c) { /* lite and normal channels have different max frame length */ -@@ -201,6 +349,32 @@ static inline struct bcm2835_desc *to_bcm2835_dma_desc( +@@ -201,6 +367,36 @@ static inline struct bcm2835_desc *to_bcm2835_dma_desc( return container_of(t, struct bcm2835_desc, vd.tx); } @@ -49723,15 +69966,19 @@ index 630dfbb01a40..94a1b40b1645 100644 + +static inline uint32_t to_bcm2711_srci(uint32_t info) +{ -+ return ((info & BCM2835_DMA_S_INC) ? BCM2711_DMA40_INC : 0); ++ return ((info & BCM2835_DMA_S_INC) ? BCM2711_DMA40_INC : 0) | ++ ((info & BCM2835_DMA_S_WIDTH) ? BCM2711_DMA40_SIZE_128 : 0) | ++ BCM2711_DMA40_BURST_LEN(BCM2835_DMA_GET_BURST_LENGTH(info)); +} + +static inline uint32_t to_bcm2711_dsti(uint32_t info) +{ -+ return ((info & BCM2835_DMA_D_INC) ? BCM2711_DMA40_INC : 0); ++ return ((info & BCM2835_DMA_D_INC) ? BCM2711_DMA40_INC : 0) | ++ ((info & BCM2835_DMA_D_WIDTH) ? BCM2711_DMA40_SIZE_128 : 0) | ++ BCM2711_DMA40_BURST_LEN(BCM2835_DMA_GET_BURST_LENGTH(info)); +} + -+static inline uint32_t to_bcm2711_cbaddr(dma_addr_t addr) ++static inline uint32_t to_40bit_cbaddr(dma_addr_t addr) +{ + BUG_ON(addr & 0x1f); + return (addr >> 5); @@ -49740,7 +69987,7 @@ index 630dfbb01a40..94a1b40b1645 100644 static void bcm2835_dma_free_cb_chain(struct bcm2835_desc *desc) { size_t i; -@@ -219,45 +393,53 @@ static void bcm2835_dma_desc_free(struct virt_dma_desc *vd) +@@ -219,45 +415,53 @@ static void bcm2835_dma_desc_free(struct virt_dma_desc *vd) } static void bcm2835_dma_create_cb_set_length( @@ -49799,13 +70046,13 @@ index 630dfbb01a40..94a1b40b1645 100644 - /* calculate the length that remains to reach period_length */ - control_block->length = period_len - *total_len; -- -- /* reset total_length for next period */ -- *total_len = 0; + if (c->is_40bit_channel) { + struct bcm2711_dma40_scb *scb = + (struct bcm2711_dma40_scb *)control_block; +- /* reset total_length for next period */ +- *total_len = 0; +- - /* add extrainfo bits in info */ - control_block->info |= finalextrainfo; + scb->len = cb_len; @@ -49819,7 +70066,7 @@ index 630dfbb01a40..94a1b40b1645 100644 } static inline size_t bcm2835_dma_count_frames_for_sg( -@@ -280,7 +462,7 @@ static inline size_t bcm2835_dma_count_frames_for_sg( +@@ -280,7 +484,7 @@ static inline size_t bcm2835_dma_count_frames_for_sg( /** * bcm2835_dma_create_cb_chain - create a control block and fills data in * @@ -49828,7 +70075,7 @@ index 630dfbb01a40..94a1b40b1645 100644 * @direction: the direction in which we transfer * @cyclic: it is a cyclic transfer * @info: the default info bits to apply per controlblock -@@ -298,12 +480,11 @@ static inline size_t bcm2835_dma_count_frames_for_sg( +@@ -298,12 +502,11 @@ static inline size_t bcm2835_dma_count_frames_for_sg( * @gfp: the GFP flag to use for allocation */ static struct bcm2835_desc *bcm2835_dma_create_cb_chain( @@ -49842,7 +70089,7 @@ index 630dfbb01a40..94a1b40b1645 100644 size_t len = buf_len, total_len; size_t frame; struct bcm2835_desc *d; -@@ -335,11 +516,23 @@ static struct bcm2835_desc *bcm2835_dma_create_cb_chain( +@@ -335,11 +538,27 @@ static struct bcm2835_desc *bcm2835_dma_create_cb_chain( /* fill in the control block */ control_block = cb_entry->cb; @@ -49864,28 +70111,57 @@ index 630dfbb01a40..94a1b40b1645 100644 + control_block->info = info; + control_block->src = src; + control_block->dst = dst; -+ control_block->stride = 0; ++ if (c->is_2712) ++ control_block->stride = (upper_32_bits(dst) << 8) | ++ upper_32_bits(src); ++ else ++ control_block->stride = 0; + control_block->next = 0; + } + /* set up length in control_block if requested */ if (buf_len) { /* calculate length honoring period_length */ -@@ -353,7 +546,11 @@ static struct bcm2835_desc *bcm2835_dma_create_cb_chain( +@@ -349,25 +568,52 @@ static struct bcm2835_desc *bcm2835_dma_create_cb_chain( + cyclic ? finalextrainfo : 0); + + /* calculate new remaining length */ +- len -= control_block->length; ++ if (c->is_40bit_channel) ++ len -= ((struct bcm2711_dma40_scb *)control_block)->len; ++ else ++ len -= control_block->length; } /* link this the last controlblock */ - if (frame) +- d->cb_list[frame - 1].cb->next = cb_entry->paddr; + if (frame && c->is_40bit_channel) + ((struct bcm2711_dma40_scb *) + d->cb_list[frame - 1].cb)->next_cb = -+ to_bcm2711_cbaddr(cb_entry->paddr); ++ to_40bit_cbaddr(cb_entry->paddr); + if (frame && !c->is_40bit_channel) - d->cb_list[frame - 1].cb->next = cb_entry->paddr; ++ d->cb_list[frame - 1].cb->next = c->is_2712 ? ++ to_40bit_cbaddr(cb_entry->paddr) : cb_entry->paddr; /* update src and dst and length */ -@@ -363,11 +560,21 @@ static struct bcm2835_desc *bcm2835_dma_create_cb_chain( - dst += control_block->length; +- if (src && (info & BCM2835_DMA_S_INC)) +- src += control_block->length; +- if (dst && (info & BCM2835_DMA_D_INC)) +- dst += control_block->length; ++ if (src && (info & BCM2835_DMA_S_INC)) { ++ if (c->is_40bit_channel) ++ src += ((struct bcm2711_dma40_scb *)control_block)->len; ++ else ++ src += control_block->length; ++ } ++ ++ if (dst && (info & BCM2835_DMA_D_INC)) { ++ if (c->is_40bit_channel) ++ dst += ((struct bcm2711_dma40_scb *)control_block)->len; ++ else ++ dst += control_block->length; ++ } /* Length of total transfer */ - d->size += control_block->length; @@ -49908,7 +70184,7 @@ index 630dfbb01a40..94a1b40b1645 100644 /* detect a size missmatch */ if (buf_len && (d->size != buf_len)) -@@ -381,13 +588,12 @@ static struct bcm2835_desc *bcm2835_dma_create_cb_chain( +@@ -381,13 +627,12 @@ static struct bcm2835_desc *bcm2835_dma_create_cb_chain( } static void bcm2835_dma_fill_cb_chain_with_sg( @@ -49923,7 +70199,7 @@ index 630dfbb01a40..94a1b40b1645 100644 size_t len, max_len; unsigned int i; dma_addr_t addr; -@@ -395,14 +601,35 @@ static void bcm2835_dma_fill_cb_chain_with_sg( +@@ -395,14 +640,35 @@ static void bcm2835_dma_fill_cb_chain_with_sg( max_len = bcm2835_dma_max_frame_length(c); for_each_sg(sgl, sgent, sg_len, i) { @@ -49967,88 +70243,232 @@ index 630dfbb01a40..94a1b40b1645 100644 } } } -@@ -411,6 +638,10 @@ static void bcm2835_dma_abort(struct bcm2835_chan *c) +@@ -410,29 +676,74 @@ static void bcm2835_dma_fill_cb_chain_with_sg( + static void bcm2835_dma_abort(struct bcm2835_chan *c) { void __iomem *chan_base = c->chan_base; - long int timeout = 10000; -+ u32 wait_mask = BCM2835_DMA_WAITING_FOR_WRITES; +- long int timeout = 10000; ++ long timeout = 100; + +- /* +- * A zero control block address means the channel is idle. +- * (The ACTIVE flag in the CS register is not a reliable indicator.) +- */ +- if (!readl(chan_base + BCM2835_DMA_ADDR)) +- return; ++ if (c->is_40bit_channel) { ++ /* ++ * A zero control block address means the channel is idle. ++ * (The ACTIVE flag in the CS register is not a reliable indicator.) ++ */ ++ if (!readl(chan_base + BCM2711_DMA40_CB)) ++ return; + -+ if (c->is_40bit_channel) -+ wait_mask = BCM2711_DMA40_WAITING_FOR_WRITES; ++ /* Pause the current DMA */ ++ writel(readl(chan_base + BCM2711_DMA40_CS) & ~BCM2711_DMA40_ACTIVE, ++ chan_base + BCM2711_DMA40_CS); ++ ++ /* wait for outstanding transactions to complete */ ++ while ((readl(chan_base + BCM2711_DMA40_CS) & BCM2711_DMA40_TRANSACTIONS) && ++ --timeout) ++ cpu_relax(); ++ ++ /* Peripheral might be stuck and fail to complete */ ++ if (!timeout) ++ dev_err(c->vc.chan.device->dev, ++ "failed to complete pause on dma %d (CS:%08x)\n", c->ch, ++ readl(chan_base + BCM2711_DMA40_CS)); ++ ++ /* Set CS back to default state */ ++ writel(BCM2711_DMA40_PROT, chan_base + BCM2711_DMA40_CS); ++ ++ /* Reset the DMA */ ++ writel(readl(chan_base + BCM2711_DMA40_DEBUG) | BCM2711_DMA40_DEBUG_RESET, ++ chan_base + BCM2711_DMA40_DEBUG); ++ } else { ++ /* ++ * A zero control block address means the channel is idle. ++ * (The ACTIVE flag in the CS register is not a reliable indicator.) ++ */ ++ if (!readl(chan_base + BCM2835_DMA_ADDR)) ++ return; - /* - * A zero control block address means the channel is idle. -@@ -423,8 +654,7 @@ static void bcm2835_dma_abort(struct bcm2835_chan *c) - writel(0, chan_base + BCM2835_DMA_CS); +- /* Write 0 to the active bit - Pause the DMA */ +- writel(0, chan_base + BCM2835_DMA_CS); ++ /* We need to clear the next DMA block pending */ ++ writel(0, chan_base + BCM2835_DMA_NEXTCB); - /* Wait for any current AXI transfer to complete */ +- /* Wait for any current AXI transfer to complete */ - while ((readl(chan_base + BCM2835_DMA_CS) & - BCM2835_DMA_WAITING_FOR_WRITES) && --timeout) -+ while ((readl(chan_base + BCM2835_DMA_CS) & wait_mask) && --timeout) - cpu_relax(); +- cpu_relax(); ++ /* Abort the DMA, which needs to be enabled to complete */ ++ writel(readl(chan_base + BCM2835_DMA_CS) | BCM2835_DMA_ABORT | BCM2835_DMA_ACTIVE, ++ chan_base + BCM2835_DMA_CS); ++ ++ /* wait for DMA to be aborted */ ++ while ((readl(chan_base + BCM2835_DMA_CS) & BCM2835_DMA_ABORT) && --timeout) ++ cpu_relax(); - /* Peripheral might be stuck and fail to signal AXI write responses */ -@@ -449,8 +679,16 @@ static void bcm2835_dma_start_desc(struct bcm2835_chan *c) +- /* Peripheral might be stuck and fail to signal AXI write responses */ +- if (!timeout) +- dev_err(c->vc.chan.device->dev, +- "failed to complete outstanding writes\n"); ++ /* Write 0 to the active bit - Pause the DMA */ ++ writel(readl(chan_base + BCM2835_DMA_CS) & ~BCM2835_DMA_ACTIVE, ++ chan_base + BCM2835_DMA_CS); + +- writel(BCM2835_DMA_RESET, chan_base + BCM2835_DMA_CS); ++ /* ++ * Peripheral might be stuck and fail to complete ++ * This is expected when dreqs are enabled but not asserted ++ * so only report error in non dreq case ++ */ ++ if (!timeout && !(readl(chan_base + BCM2835_DMA_TI) & ++ (BCM2835_DMA_S_DREQ | BCM2835_DMA_D_DREQ))) ++ dev_err(c->vc.chan.device->dev, ++ "failed to complete pause on dma %d (CS:%08x)\n", c->ch, ++ readl(chan_base + BCM2835_DMA_CS)); ++ ++ /* Set CS back to default state and reset the DMA */ ++ writel(BCM2835_DMA_RESET, chan_base + BCM2835_DMA_CS); ++ } + } + + static void bcm2835_dma_start_desc(struct bcm2835_chan *c) +@@ -449,8 +760,19 @@ static void bcm2835_dma_start_desc(struct bcm2835_chan *c) c->desc = d = to_bcm2835_dma_desc(&vd->tx); - writel(d->cb_list[0].paddr, c->chan_base + BCM2835_DMA_ADDR); - writel(BCM2835_DMA_ACTIVE, c->chan_base + BCM2835_DMA_CS); + if (c->is_40bit_channel) { -+ writel(to_bcm2711_cbaddr(d->cb_list[0].paddr), ++ writel(to_40bit_cbaddr(d->cb_list[0].paddr), + c->chan_base + BCM2711_DMA40_CB); -+ writel(BCM2711_DMA40_ACTIVE | BCM2711_DMA40_CS_FLAGS(c->dreq), ++ writel(BCM2711_DMA40_ACTIVE | BCM2711_DMA40_PROT | BCM2711_DMA40_CS_FLAGS(c->dreq), + c->chan_base + BCM2711_DMA40_CS); + } else { -+ writel(d->cb_list[0].paddr, c->chan_base + BCM2835_DMA_ADDR); ++ writel(BIT(31), c->chan_base + BCM2835_DMA_CS); ++ ++ writel(c->is_2712 ? to_40bit_cbaddr(d->cb_list[0].paddr) : d->cb_list[0].paddr, ++ c->chan_base + BCM2835_DMA_ADDR); + writel(BCM2835_DMA_ACTIVE | BCM2835_DMA_CS_FLAGS(c->dreq), + c->chan_base + BCM2835_DMA_CS); + } } static irqreturn_t bcm2835_dma_callback(int irq, void *data) -@@ -477,7 +715,7 @@ static irqreturn_t bcm2835_dma_callback(int irq, void *data) +@@ -477,8 +799,13 @@ static irqreturn_t bcm2835_dma_callback(int irq, void *data) * if this IRQ handler is threaded.) If the channel is finished, it * will remain idle despite the ACTIVE flag being set. */ - writel(BCM2835_DMA_INT | BCM2835_DMA_ACTIVE, -+ writel(BCM2835_DMA_INT | BCM2835_DMA_ACTIVE | BCM2835_DMA_CS_FLAGS(c->dreq), - c->chan_base + BCM2835_DMA_CS); +- c->chan_base + BCM2835_DMA_CS); ++ if (c->is_40bit_channel) ++ writel(BCM2835_DMA_INT | BCM2711_DMA40_ACTIVE | BCM2711_DMA40_PROT | ++ BCM2711_DMA40_CS_FLAGS(c->dreq), ++ c->chan_base + BCM2711_DMA40_CS); ++ else ++ writel(BCM2835_DMA_INT | BCM2835_DMA_ACTIVE | BCM2835_DMA_CS_FLAGS(c->dreq), ++ c->chan_base + BCM2835_DMA_CS); d = c->desc; -@@ -580,9 +818,17 @@ static enum dma_status bcm2835_dma_tx_status(struct dma_chan *chan, + +@@ -540,20 +867,39 @@ static size_t bcm2835_dma_desc_size_pos(struct bcm2835_desc *d, dma_addr_t addr) + unsigned int i; + size_t size; + +- for (size = i = 0; i < d->frames; i++) { +- struct bcm2835_dma_cb *control_block = d->cb_list[i].cb; +- size_t this_size = control_block->length; +- dma_addr_t dma; ++ if (d->c->is_40bit_channel) { ++ for (size = i = 0; i < d->frames; i++) { ++ struct bcm2711_dma40_scb *control_block = ++ (struct bcm2711_dma40_scb *)d->cb_list[i].cb; ++ size_t this_size = control_block->len; ++ dma_addr_t dma; + +- if (d->dir == DMA_DEV_TO_MEM) +- dma = control_block->dst; +- else +- dma = control_block->src; ++ if (d->dir == DMA_DEV_TO_MEM) ++ dma = control_block->dst; ++ else ++ dma = control_block->src; + +- if (size) +- size += this_size; +- else if (addr >= dma && addr < dma + this_size) +- size += dma + this_size - addr; ++ if (size) ++ size += this_size; ++ else if (addr >= dma && addr < dma + this_size) ++ size += dma + this_size - addr; ++ } ++ } else { ++ for (size = i = 0; i < d->frames; i++) { ++ struct bcm2835_dma_cb *control_block = d->cb_list[i].cb; ++ size_t this_size = control_block->length; ++ dma_addr_t dma; ++ ++ if (d->dir == DMA_DEV_TO_MEM) ++ dma = control_block->dst; ++ else ++ dma = control_block->src; ++ ++ if (size) ++ size += this_size; ++ else if (addr >= dma && addr < dma + this_size) ++ size += dma + this_size - addr; ++ } + } + + return size; +@@ -580,12 +926,25 @@ static enum dma_status bcm2835_dma_tx_status(struct dma_chan *chan, struct bcm2835_desc *d = c->desc; dma_addr_t pos; - if (d->dir == DMA_MEM_TO_DEV) -+ if (d->dir == DMA_MEM_TO_DEV && c->is_40bit_channel) -+ pos = readl(c->chan_base + BCM2711_DMA40_SRC) + -+ ((readl(c->chan_base + BCM2711_DMA40_SRCI) & -+ 0xff) << 8); -+ else if (d->dir == DMA_MEM_TO_DEV && !c->is_40bit_channel) ++ if (d->dir == DMA_MEM_TO_DEV && c->is_40bit_channel) { ++ u64 lo_bits, hi_bits; ++ ++ lo_bits = readl(c->chan_base + BCM2711_DMA40_SRC); ++ hi_bits = readl(c->chan_base + BCM2711_DMA40_SRCI) & 0xff; ++ pos = (hi_bits << 32) | lo_bits; ++ } else if (d->dir == DMA_MEM_TO_DEV && !c->is_40bit_channel) { pos = readl(c->chan_base + BCM2835_DMA_SOURCE_AD); - else if (d->dir == DMA_DEV_TO_MEM) -+ else if (d->dir == DMA_DEV_TO_MEM && c->is_40bit_channel) -+ pos = readl(c->chan_base + BCM2711_DMA40_DEST) + -+ ((readl(c->chan_base + BCM2711_DMA40_DESTI) & -+ 0xff) << 8); -+ else if (d->dir == DMA_DEV_TO_MEM && !c->is_40bit_channel) ++ } else if (d->dir == DMA_DEV_TO_MEM && c->is_40bit_channel) { ++ u64 lo_bits, hi_bits; ++ ++ lo_bits = readl(c->chan_base + BCM2711_DMA40_DEST); ++ hi_bits = readl(c->chan_base + BCM2711_DMA40_DESTI) & 0xff; ++ pos = (hi_bits << 32) | lo_bits; ++ } else if (d->dir == DMA_DEV_TO_MEM && !c->is_40bit_channel) { pos = readl(c->chan_base + BCM2835_DMA_DEST_AD); - else +- else ++ } else { pos = 0; -@@ -615,8 +861,9 @@ static struct dma_async_tx_descriptor *bcm2835_dma_prep_dma_memcpy( ++ } + + txstate->residue = bcm2835_dma_desc_size_pos(d, pos); + } else { +@@ -615,8 +974,10 @@ static struct dma_async_tx_descriptor *bcm2835_dma_prep_dma_memcpy( { struct bcm2835_chan *c = to_bcm2835_dma_chan(chan); struct bcm2835_desc *d; - u32 info = BCM2835_DMA_D_INC | BCM2835_DMA_S_INC; - u32 extra = BCM2835_DMA_INT_EN | BCM2835_DMA_WAIT_RESP; -+ u32 info = BCM2835_DMA_D_INC | BCM2835_DMA_S_INC | WAIT_RESP(c->dreq) | -+ WIDE_SOURCE(c->dreq) | WIDE_DEST(c->dreq); ++ u32 info = BCM2835_DMA_D_INC | BCM2835_DMA_S_INC | ++ WAIT_RESP(c->dreq) | WIDE_SOURCE(c->dreq) | ++ WIDE_DEST(c->dreq) | BURST_LENGTH(c->dreq); + u32 extra = BCM2835_DMA_INT_EN; size_t max_len = bcm2835_dma_max_frame_length(c); size_t frames; -@@ -628,7 +875,7 @@ static struct dma_async_tx_descriptor *bcm2835_dma_prep_dma_memcpy( +@@ -628,7 +989,7 @@ static struct dma_async_tx_descriptor *bcm2835_dma_prep_dma_memcpy( frames = bcm2835_dma_frames_for_length(len, max_len); /* allocate the CB chain - this also fills in the pointers */ @@ -50057,39 +70477,32 @@ index 630dfbb01a40..94a1b40b1645 100644 info, extra, frames, src, dst, len, 0, GFP_KERNEL); if (!d) -@@ -646,7 +893,8 @@ static struct dma_async_tx_descriptor *bcm2835_dma_prep_slave_sg( +@@ -646,7 +1007,8 @@ static struct dma_async_tx_descriptor *bcm2835_dma_prep_slave_sg( struct bcm2835_chan *c = to_bcm2835_dma_chan(chan); struct bcm2835_desc *d; dma_addr_t src = 0, dst = 0; - u32 info = BCM2835_DMA_WAIT_RESP; -+ u32 info = WAIT_RESP(c->dreq) | -+ WIDE_SOURCE(c->dreq) | WIDE_DEST(c->dreq); ++ u32 info = WAIT_RESP(c->dreq) | WIDE_SOURCE(c->dreq) | ++ WIDE_DEST(c->dreq) | BURST_LENGTH(c->dreq); u32 extra = BCM2835_DMA_INT_EN; size_t frames; -@@ -663,11 +911,21 @@ static struct dma_async_tx_descriptor *bcm2835_dma_prep_slave_sg( +@@ -662,12 +1024,12 @@ static struct dma_async_tx_descriptor *bcm2835_dma_prep_slave_sg( + if (direction == DMA_DEV_TO_MEM) { if (c->cfg.src_addr_width != DMA_SLAVE_BUSWIDTH_4_BYTES) return NULL; - src = c->cfg.src_addr; -+ /* -+ * One would think it ought to be possible to get the physical -+ * to dma address mapping information from the dma-ranges DT -+ * property, but I've not found a way yet that doesn't involve -+ * open-coding the whole thing. -+ */ -+ if (c->is_40bit_channel) -+ src |= 0x400000000ull; +- src = c->cfg.src_addr; ++ src = phys_to_dma(chan->device->dev, c->cfg.src_addr); info |= BCM2835_DMA_S_DREQ | BCM2835_DMA_D_INC; } else { if (c->cfg.dst_addr_width != DMA_SLAVE_BUSWIDTH_4_BYTES) return NULL; - dst = c->cfg.dst_addr; -+ if (c->is_40bit_channel) -+ dst |= 0x400000000ull; +- dst = c->cfg.dst_addr; ++ dst = phys_to_dma(chan->device->dev, c->cfg.dst_addr); info |= BCM2835_DMA_D_DREQ | BCM2835_DMA_S_INC; } -@@ -675,7 +933,7 @@ static struct dma_async_tx_descriptor *bcm2835_dma_prep_slave_sg( +@@ -675,7 +1037,7 @@ static struct dma_async_tx_descriptor *bcm2835_dma_prep_slave_sg( frames = bcm2835_dma_count_frames_for_sg(c, sgl, sg_len); /* allocate the CB chain */ @@ -50098,7 +70511,7 @@ index 630dfbb01a40..94a1b40b1645 100644 info, extra, frames, src, dst, 0, 0, GFP_NOWAIT); -@@ -683,7 +941,7 @@ static struct dma_async_tx_descriptor *bcm2835_dma_prep_slave_sg( +@@ -683,7 +1045,7 @@ static struct dma_async_tx_descriptor *bcm2835_dma_prep_slave_sg( return NULL; /* fill in frames with scatterlist pointers */ @@ -50107,33 +70520,33 @@ index 630dfbb01a40..94a1b40b1645 100644 sgl, sg_len); return vchan_tx_prep(&c->vc, &d->vd, flags); -@@ -698,7 +956,7 @@ static struct dma_async_tx_descriptor *bcm2835_dma_prep_dma_cyclic( +@@ -698,7 +1060,8 @@ static struct dma_async_tx_descriptor *bcm2835_dma_prep_dma_cyclic( struct bcm2835_chan *c = to_bcm2835_dma_chan(chan); struct bcm2835_desc *d; dma_addr_t src, dst; - u32 info = BCM2835_DMA_WAIT_RESP; -+ u32 info = WAIT_RESP(c->dreq) | WIDE_SOURCE(c->dreq) | WIDE_DEST(c->dreq); ++ u32 info = WAIT_RESP(c->dreq) | WIDE_SOURCE(c->dreq) | ++ WIDE_DEST(c->dreq) | BURST_LENGTH(c->dreq); u32 extra = 0; size_t max_len = bcm2835_dma_max_frame_length(c); size_t frames; -@@ -737,12 +995,16 @@ static struct dma_async_tx_descriptor *bcm2835_dma_prep_dma_cyclic( +@@ -736,13 +1099,13 @@ static struct dma_async_tx_descriptor *bcm2835_dma_prep_dma_cyclic( + if (direction == DMA_DEV_TO_MEM) { if (c->cfg.src_addr_width != DMA_SLAVE_BUSWIDTH_4_BYTES) return NULL; - src = c->cfg.src_addr; -+ if (c->is_40bit_channel) -+ src |= 0x400000000ull; +- src = c->cfg.src_addr; ++ src = phys_to_dma(chan->device->dev, c->cfg.src_addr); dst = buf_addr; info |= BCM2835_DMA_S_DREQ | BCM2835_DMA_D_INC; } else { if (c->cfg.dst_addr_width != DMA_SLAVE_BUSWIDTH_4_BYTES) return NULL; - dst = c->cfg.dst_addr; -+ if (c->is_40bit_channel) -+ dst |= 0x400000000ull; +- dst = c->cfg.dst_addr; ++ dst = phys_to_dma(chan->device->dev, c->cfg.dst_addr); src = buf_addr; info |= BCM2835_DMA_D_DREQ | BCM2835_DMA_S_INC; -@@ -762,7 +1024,7 @@ static struct dma_async_tx_descriptor *bcm2835_dma_prep_dma_cyclic( +@@ -762,7 +1125,7 @@ static struct dma_async_tx_descriptor *bcm2835_dma_prep_dma_cyclic( * note that we need to use GFP_NOWAIT, as the ALSA i2s dmaengine * implementation calls prep_dma_cyclic with interrupts disabled. */ @@ -50142,7 +70555,7 @@ index 630dfbb01a40..94a1b40b1645 100644 info, extra, frames, src, dst, buf_len, period_len, GFP_NOWAIT); -@@ -770,7 +1032,12 @@ static struct dma_async_tx_descriptor *bcm2835_dma_prep_dma_cyclic( +@@ -770,7 +1133,13 @@ static struct dma_async_tx_descriptor *bcm2835_dma_prep_dma_cyclic( return NULL; /* wrap around into a loop */ @@ -50150,13 +70563,14 @@ index 630dfbb01a40..94a1b40b1645 100644 + if (c->is_40bit_channel) + ((struct bcm2711_dma40_scb *) + d->cb_list[frames - 1].cb)->next_cb = -+ to_bcm2711_cbaddr(d->cb_list[0].paddr); ++ to_40bit_cbaddr(d->cb_list[0].paddr); + else -+ d->cb_list[d->frames - 1].cb->next = d->cb_list[0].paddr; ++ d->cb_list[d->frames - 1].cb->next = c->is_2712 ? ++ to_40bit_cbaddr(d->cb_list[0].paddr) : d->cb_list[0].paddr; return vchan_tx_prep(&c->vc, &d->vd, flags); } -@@ -831,9 +1098,11 @@ static int bcm2835_dma_chan_init(struct bcm2835_dmadev *d, int chan_id, +@@ -831,10 +1200,14 @@ static int bcm2835_dma_chan_init(struct bcm2835_dmadev *d, int chan_id, c->irq_number = irq; c->irq_flags = irq_flags; @@ -50169,9 +70583,12 @@ index 630dfbb01a40..94a1b40b1645 100644 + else if (readl(c->chan_base + BCM2835_DMA_DEBUG) & + BCM2835_DMA_DEBUG_LITE) c->is_lite_channel = true; ++ if (d->cfg_data->dma_mask == DMA_BIT_MASK(40)) ++ c->is_2712 = true; return 0; -@@ -853,8 +1122,58 @@ static void bcm2835_dma_free(struct bcm2835_dmadev *od) + } +@@ -853,8 +1226,59 @@ static void bcm2835_dma_free(struct bcm2835_dmadev *od) DMA_TO_DEVICE, DMA_ATTR_SKIP_CPU_SYNC); } @@ -50210,15 +70627,15 @@ index 630dfbb01a40..94a1b40b1645 100644 + scb->len = size; + scb->next_cb = 0; + -+ writel((u32)(memcpy_scb_dma >> 5), memcpy_chan + BCM2711_DMA40_CB); -+ writel(BCM2711_DMA40_MEMCPY_FLAGS + BCM2711_DMA40_ACTIVE, ++ writel(to_40bit_cbaddr(memcpy_scb_dma), memcpy_chan + BCM2711_DMA40_CB); ++ writel(BCM2711_DMA40_MEMCPY_FLAGS | BCM2711_DMA40_ACTIVE | BCM2711_DMA40_PROT, + memcpy_chan + BCM2711_DMA40_CS); + + /* Poll for completion */ + while (!(readl(memcpy_chan + BCM2711_DMA40_CS) & BCM2711_DMA40_END)) + cpu_relax(); + -+ writel(BCM2711_DMA40_END, memcpy_chan + BCM2711_DMA40_CS); ++ writel(BCM2711_DMA40_END | BCM2711_DMA40_PROT, memcpy_chan + BCM2711_DMA40_CS); + + spin_unlock_irqrestore(&memcpy_lock, flags); +} @@ -50228,19 +70645,22 @@ index 630dfbb01a40..94a1b40b1645 100644 - { .compatible = "brcm,bcm2835-dma", }, + { .compatible = "brcm,bcm2835-dma", .data = &bcm2835_dma_cfg }, + { .compatible = "brcm,bcm2711-dma", .data = &bcm2711_dma_cfg }, ++ { .compatible = "brcm,bcm2712-dma", .data = &bcm2712_dma_cfg }, {}, }; MODULE_DEVICE_TABLE(of, bcm2835_dma_of_match); -@@ -877,6 +1196,8 @@ static struct dma_chan *bcm2835_dma_xlate(struct of_phandle_args *spec, +@@ -877,7 +1301,10 @@ static struct dma_chan *bcm2835_dma_xlate(struct of_phandle_args *spec, static int bcm2835_dma_probe(struct platform_device *pdev) { + const struct bcm2835_dma_cfg_data *cfg_data; + const struct of_device_id *of_id; struct bcm2835_dmadev *od; - struct resource *res; ++ struct resource *res; void __iomem *base; -@@ -886,11 +1207,20 @@ static int bcm2835_dma_probe(struct platform_device *pdev) + int rc; + int i, j; +@@ -885,11 +1312,20 @@ static int bcm2835_dma_probe(struct platform_device *pdev) int irq_flags; uint32_t chans_available; char chan_name[BCM2835_DMA_CHAN_NAME_SIZE]; @@ -50262,7 +70682,12 @@ index 630dfbb01a40..94a1b40b1645 100644 if (rc) { dev_err(&pdev->dev, "Unable to set DMA mask\n"); return rc; -@@ -907,6 +1237,13 @@ static int bcm2835_dma_probe(struct platform_device *pdev) +@@ -901,10 +1337,17 @@ static int bcm2835_dma_probe(struct platform_device *pdev) + + dma_set_max_seg_size(&pdev->dev, 0x3FFFFFFF); + +- base = devm_platform_ioremap_resource(pdev, 0); ++ base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); if (IS_ERR(base)) return PTR_ERR(base); @@ -50276,7 +70701,7 @@ index 630dfbb01a40..94a1b40b1645 100644 od->base = base; dma_cap_set(DMA_SLAVE, od->ddev.cap_mask); -@@ -942,6 +1279,14 @@ static int bcm2835_dma_probe(struct platform_device *pdev) +@@ -940,6 +1383,14 @@ static int bcm2835_dma_probe(struct platform_device *pdev) return -ENOMEM; } @@ -50291,7 +70716,7 @@ index 630dfbb01a40..94a1b40b1645 100644 /* Request DMA channel mask from device tree */ if (of_property_read_u32(pdev->dev.of_node, "brcm,dma-channel-mask", -@@ -951,8 +1296,36 @@ static int bcm2835_dma_probe(struct platform_device *pdev) +@@ -949,8 +1400,36 @@ static int bcm2835_dma_probe(struct platform_device *pdev) goto err_no_dma; } @@ -50329,7 +70754,7 @@ index 630dfbb01a40..94a1b40b1645 100644 /* skip masked out channels */ if (!(chans_available & (1 << i))) { irq[i] = -1; -@@ -975,13 +1348,17 @@ static int bcm2835_dma_probe(struct platform_device *pdev) +@@ -973,13 +1452,17 @@ static int bcm2835_dma_probe(struct platform_device *pdev) irq[i] = platform_get_irq(pdev, i < 11 ? i : 11); } @@ -50348,7 +70773,7 @@ index 630dfbb01a40..94a1b40b1645 100644 irq_flags = 0; for (j = 0; j <= BCM2835_DMA_MAX_DMA_CHAN_SUPPORTED; j++) if ((i != j) && (irq[j] == irq[i])) { -@@ -993,9 +1370,10 @@ static int bcm2835_dma_probe(struct platform_device *pdev) +@@ -991,9 +1474,10 @@ static int bcm2835_dma_probe(struct platform_device *pdev) rc = bcm2835_dma_chan_init(od, i, irq[i], irq_flags); if (rc) goto err_no_dma; @@ -50360,7 +70785,7 @@ index 630dfbb01a40..94a1b40b1645 100644 /* Device-tree DMA controller registration */ rc = of_dma_controller_register(pdev->dev.of_node, -@@ -1025,7 +1403,15 @@ static int bcm2835_dma_remove(struct platform_device *pdev) +@@ -1023,7 +1507,15 @@ static int bcm2835_dma_remove(struct platform_device *pdev) { struct bcm2835_dmadev *od = platform_get_drvdata(pdev); @@ -50376,7 +70801,7 @@ index 630dfbb01a40..94a1b40b1645 100644 bcm2835_dma_free(od); return 0; -@@ -1040,7 +1426,22 @@ static struct platform_driver bcm2835_dma_driver = { +@@ -1038,7 +1530,22 @@ static struct platform_driver bcm2835_dma_driver = { }, }; @@ -50400,25 +70825,337 @@ index 630dfbb01a40..94a1b40b1645 100644 MODULE_ALIAS("platform:bcm2835-dma"); MODULE_DESCRIPTION("BCM2835 DMA engine driver"); +diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c +index dd02f84e404d..5874620bf7ed 100644 +--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c ++++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c +@@ -12,6 +12,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -84,6 +85,17 @@ axi_chan_iowrite64(struct axi_dma_chan *chan, u32 reg, u64 val) + iowrite32(upper_32_bits(val), chan->chan_regs + reg + 4); + } + ++static inline u64 ++axi_chan_ioread64(struct axi_dma_chan *chan, u32 reg) ++{ ++ /* ++ * We split one 64 bit read into two 32 bit reads as some HW doesn't ++ * support 64 bit access. ++ */ ++ return ((u64)ioread32(chan->chan_regs + reg + 4) << 32) + ++ ioread32(chan->chan_regs + reg); ++} ++ + static inline void axi_chan_config_write(struct axi_dma_chan *chan, + struct axi_dma_chan_config *config) + { +@@ -220,7 +232,18 @@ static void axi_dma_hw_init(struct axi_dma_chip *chip) + { + int ret; + u32 i; +- ++ int retries = 1000; ++ ++ axi_dma_iowrite32(chip, DMAC_RESET, 1); ++ while (axi_dma_ioread32(chip, DMAC_RESET)) { ++ retries--; ++ if (!retries) { ++ dev_err(chip->dev, "%s: DMAC failed to reset\n", ++ __func__); ++ return; ++ } ++ cpu_relax(); ++ } + for (i = 0; i < chip->dw->hdata->nr_channels; i++) { + axi_chan_irq_disable(&chip->dw->chan[i], DWAXIDMAC_IRQ_ALL); + axi_chan_disable(&chip->dw->chan[i]); +@@ -282,7 +305,7 @@ static struct axi_dma_lli *axi_desc_get(struct axi_dma_chan *chan, + static void axi_desc_put(struct axi_dma_desc *desc) + { + struct axi_dma_chan *chan = desc->chan; +- int count = atomic_read(&chan->descs_allocated); ++ u32 count = desc->hw_desc_count; + struct axi_dma_hw_desc *hw_desc; + int descs_put; + +@@ -304,6 +327,48 @@ static void vchan_desc_put(struct virt_dma_desc *vdesc) + axi_desc_put(vd_to_axi_desc(vdesc)); + } + ++static u32 axi_dma_desc_src_pos(struct axi_dma_desc *desc, dma_addr_t addr) ++{ ++ unsigned int idx = 0; ++ u32 pos = 0; ++ ++ while (pos < desc->length) { ++ struct axi_dma_hw_desc *hw_desc = &desc->hw_desc[idx++]; ++ u32 len = hw_desc->len; ++ dma_addr_t start = le64_to_cpu(hw_desc->lli->sar); ++ ++ if (addr >= start && addr <= (start + len)) { ++ pos += addr - start; ++ break; ++ } ++ ++ pos += len; ++ } ++ ++ return pos; ++} ++ ++static u32 axi_dma_desc_dst_pos(struct axi_dma_desc *desc, dma_addr_t addr) ++{ ++ unsigned int idx = 0; ++ u32 pos = 0; ++ ++ while (pos < desc->length) { ++ struct axi_dma_hw_desc *hw_desc = &desc->hw_desc[idx++]; ++ u32 len = hw_desc->len; ++ dma_addr_t start = le64_to_cpu(hw_desc->lli->dar); ++ ++ if (addr >= start && addr <= (start + len)) { ++ pos += addr - start; ++ break; ++ } ++ ++ pos += len; ++ } ++ ++ return pos; ++} ++ + static enum dma_status + dma_chan_tx_status(struct dma_chan *dchan, dma_cookie_t cookie, + struct dma_tx_state *txstate) +@@ -313,10 +378,7 @@ dma_chan_tx_status(struct dma_chan *dchan, dma_cookie_t cookie, + enum dma_status status; + u32 completed_length; + unsigned long flags; +- u32 completed_blocks; + size_t bytes = 0; +- u32 length; +- u32 len; + + status = dma_cookie_status(dchan, cookie, txstate); + if (status == DMA_COMPLETE || !txstate) +@@ -325,16 +387,31 @@ dma_chan_tx_status(struct dma_chan *dchan, dma_cookie_t cookie, + spin_lock_irqsave(&chan->vc.lock, flags); + + vdesc = vchan_find_desc(&chan->vc, cookie); +- if (vdesc) { +- length = vd_to_axi_desc(vdesc)->length; +- completed_blocks = vd_to_axi_desc(vdesc)->completed_blocks; +- len = vd_to_axi_desc(vdesc)->hw_desc[0].len; +- completed_length = completed_blocks * len; +- bytes = length - completed_length; ++ if (vdesc && vdesc == vchan_next_desc(&chan->vc)) { ++ /* This descriptor is in-progress */ ++ struct axi_dma_desc *desc = vd_to_axi_desc(vdesc); ++ dma_addr_t addr; ++ ++ if (chan->direction == DMA_MEM_TO_DEV) { ++ addr = axi_chan_ioread64(chan, CH_SAR); ++ completed_length = axi_dma_desc_src_pos(desc, addr); ++ } else if (chan->direction == DMA_DEV_TO_MEM) { ++ addr = axi_chan_ioread64(chan, CH_DAR); ++ completed_length = axi_dma_desc_dst_pos(desc, addr); ++ } else { ++ completed_length = 0; ++ } ++ bytes = desc->length - completed_length; ++ } else if (vdesc) { ++ /* Still in the queue so not started */ ++ bytes = vd_to_axi_desc(vdesc)->length; + } + +- spin_unlock_irqrestore(&chan->vc.lock, flags); ++ if (chan->is_paused && status == DMA_IN_PROGRESS) ++ status = DMA_PAUSED; ++ + dma_set_residue(txstate, bytes); ++ spin_unlock_irqrestore(&chan->vc.lock, flags); + + return status; + } +@@ -388,8 +465,6 @@ static void axi_chan_block_xfer_start(struct axi_dma_chan *chan, + return; + } + +- axi_dma_enable(chan->chip); +- + config.dst_multblk_type = DWAXIDMAC_MBLK_TYPE_LL; + config.src_multblk_type = DWAXIDMAC_MBLK_TYPE_LL; + config.tt_fc = DWAXIDMAC_TT_FC_MEM_TO_MEM_DMAC; +@@ -522,7 +597,7 @@ static void dw_axi_dma_set_hw_channel(struct axi_dma_chan *chan, bool set) + unsigned long reg_value, val; + + if (!chip->apb_regs) { +- dev_err(chip->dev, "apb_regs not initialized\n"); ++ dev_dbg(chip->dev, "apb_regs not initialized\n"); + return; + } + +@@ -626,18 +701,25 @@ static int dw_axi_dma_set_hw_desc(struct axi_dma_chan *chan, + switch (chan->direction) { + case DMA_MEM_TO_DEV: + reg_width = __ffs(chan->config.dst_addr_width); +- device_addr = chan->config.dst_addr; ++ device_addr = phys_to_dma(chan->chip->dev, chan->config.dst_addr); + ctllo = reg_width << CH_CTL_L_DST_WIDTH_POS | + mem_width << CH_CTL_L_SRC_WIDTH_POS | ++ DWAXIDMAC_BURST_TRANS_LEN_1 << CH_CTL_L_DST_MSIZE_POS | ++ DWAXIDMAC_BURST_TRANS_LEN_4 << CH_CTL_L_SRC_MSIZE_POS | + DWAXIDMAC_CH_CTL_L_NOINC << CH_CTL_L_DST_INC_POS | + DWAXIDMAC_CH_CTL_L_INC << CH_CTL_L_SRC_INC_POS; + block_ts = len >> mem_width; + break; + case DMA_DEV_TO_MEM: + reg_width = __ffs(chan->config.src_addr_width); +- device_addr = chan->config.src_addr; ++ /* Prevent partial access units getting lost */ ++ if (mem_width > reg_width) ++ mem_width = reg_width; ++ device_addr = phys_to_dma(chan->chip->dev, chan->config.src_addr); + ctllo = reg_width << CH_CTL_L_SRC_WIDTH_POS | + mem_width << CH_CTL_L_DST_WIDTH_POS | ++ DWAXIDMAC_BURST_TRANS_LEN_4 << CH_CTL_L_DST_MSIZE_POS | ++ DWAXIDMAC_BURST_TRANS_LEN_1 << CH_CTL_L_SRC_MSIZE_POS | + DWAXIDMAC_CH_CTL_L_INC << CH_CTL_L_DST_INC_POS | + DWAXIDMAC_CH_CTL_L_NOINC << CH_CTL_L_SRC_INC_POS; + block_ts = len >> reg_width; +@@ -673,9 +755,6 @@ static int dw_axi_dma_set_hw_desc(struct axi_dma_chan *chan, + } + + hw_desc->lli->block_ts_lo = cpu_to_le32(block_ts - 1); +- +- ctllo |= DWAXIDMAC_BURST_TRANS_LEN_4 << CH_CTL_L_DST_MSIZE_POS | +- DWAXIDMAC_BURST_TRANS_LEN_4 << CH_CTL_L_SRC_MSIZE_POS; + hw_desc->lli->ctl_lo = cpu_to_le32(ctllo); + + set_desc_src_master(hw_desc); +@@ -770,6 +849,8 @@ dw_axi_dma_chan_prep_cyclic(struct dma_chan *dchan, dma_addr_t dma_addr, + src_addr += segment_len; + } + ++ desc->hw_desc_count = total_segments; ++ + llp = desc->hw_desc[0].llp; + + /* Managed transfer list */ +@@ -849,6 +930,8 @@ dw_axi_dma_chan_prep_slave_sg(struct dma_chan *dchan, struct scatterlist *sgl, + } while (len >= segment_len); + } + ++ desc->hw_desc_count = loop; ++ + /* Set end-of-link to the last link descriptor of list */ + set_desc_last(&desc->hw_desc[num_sgs - 1]); + +@@ -956,6 +1039,8 @@ dma_chan_prep_dma_memcpy(struct dma_chan *dchan, dma_addr_t dst_adr, + num++; + } + ++ desc->hw_desc_count = num; ++ + /* Set end-of-link to the last link descriptor of list */ + set_desc_last(&desc->hw_desc[num - 1]); + /* Managed transfer list */ +@@ -1004,7 +1089,7 @@ static void axi_chan_dump_lli(struct axi_dma_chan *chan, + static void axi_chan_list_dump_lli(struct axi_dma_chan *chan, + struct axi_dma_desc *desc_head) + { +- int count = atomic_read(&chan->descs_allocated); ++ u32 count = desc_head->hw_desc_count; + int i; + + for (i = 0; i < count; i++) +@@ -1047,11 +1132,11 @@ static noinline void axi_chan_handle_err(struct axi_dma_chan *chan, u32 status) + + static void axi_chan_block_xfer_complete(struct axi_dma_chan *chan) + { +- int count = atomic_read(&chan->descs_allocated); + struct axi_dma_hw_desc *hw_desc; + struct axi_dma_desc *desc; + struct virt_dma_desc *vd; + unsigned long flags; ++ u32 count; + u64 llp; + int i; + +@@ -1073,6 +1158,7 @@ static void axi_chan_block_xfer_complete(struct axi_dma_chan *chan) + if (chan->cyclic) { + desc = vd_to_axi_desc(vd); + if (desc) { ++ count = desc->hw_desc_count; + llp = lo_hi_readq(chan->chan_regs + CH_LLP); + for (i = 0; i < count; i++) { + hw_desc = &desc->hw_desc[i]; +@@ -1325,6 +1411,10 @@ static int parse_device_properties(struct axi_dma_chip *chip) + + chip->dw->hdata->nr_masters = tmp; + ++ ret = device_property_read_u32(dev, "snps,dma-targets", &tmp); ++ if (!ret && tmp > 16) ++ chip->dw->hdata->use_cfg2 = true; ++ + ret = device_property_read_u32(dev, "snps,data-width", &tmp); + if (ret) + return ret; +diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h +index eb267cb24f67..47c3a4f0dac3 100644 +--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h ++++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h +@@ -101,6 +101,7 @@ struct axi_dma_desc { + + struct virt_dma_desc vd; + struct axi_dma_chan *chan; ++ u32 hw_desc_count; + u32 completed_blocks; + u32 length; + u32 period_len; +diff --git a/drivers/firmware/psci/psci.c b/drivers/firmware/psci/psci.c +index d9629ff87861..e2ffd734d5e8 100644 +--- a/drivers/firmware/psci/psci.c ++++ b/drivers/firmware/psci/psci.c +@@ -315,7 +315,14 @@ static int psci_sys_reset(struct notifier_block *nb, unsigned long action, + * reset_type[30:0] = 0 (SYSTEM_WARM_RESET) + * cookie = 0 (ignored by the implementation) + */ +- invoke_psci_fn(PSCI_FN_NATIVE(1_1, SYSTEM_RESET2), 0, 0, 0); ++ // Allow extra arguments separated by spaces after ++ // the partition number. ++ unsigned long val; ++ u8 partition = 0; ++ ++ if (data && sscanf(data, "%lu", &val) == 1 && val < 63) ++ partition = val; ++ invoke_psci_fn(PSCI_FN_NATIVE(1_1, SYSTEM_RESET2), 0, partition, 0); + } else { + invoke_psci_fn(PSCI_0_2_FN_SYSTEM_RESET, 0, 0, 0); + } diff --git a/drivers/firmware/raspberrypi.c b/drivers/firmware/raspberrypi.c -index 1d965c1252ca..849e63bb426d 100644 +index f66efaa5196d..17abde1e7d55 100644 --- a/drivers/firmware/raspberrypi.c +++ b/drivers/firmware/raspberrypi.c -@@ -12,6 +12,7 @@ - #include +@@ -13,6 +13,7 @@ + #include #include #include +#include #include #include -@@ -28,10 +29,13 @@ struct rpi_firmware { - struct mbox_chan *chan; /* The property channel. */ - struct completion c; +@@ -31,8 +32,11 @@ struct rpi_firmware { u32 enabled; -+ u32 get_throttled; struct kref consumers; ++ u32 get_throttled; }; +static struct platform_device *g_pdev; @@ -50426,7 +71163,7 @@ index 1d965c1252ca..849e63bb426d 100644 static DEFINE_MUTEX(transaction_lock); static void response_callback(struct mbox_client *cl, void *msg) -@@ -173,15 +177,92 @@ int rpi_firmware_property(struct rpi_firmware *fw, +@@ -174,15 +178,92 @@ int rpi_firmware_property(struct rpi_firmware *fw, kfree(data); @@ -50519,7 +71256,7 @@ index 1d965c1252ca..849e63bb426d 100644 int ret = rpi_firmware_property(fw, RPI_FIRMWARE_GET_FIRMWARE_REVISION, &packet, sizeof(packet)); -@@ -191,7 +272,35 @@ rpi_firmware_print_firmware_revision(struct rpi_firmware *fw) +@@ -192,7 +273,35 @@ rpi_firmware_print_firmware_revision(struct rpi_firmware *fw) /* This is not compatible with y2038 */ date_and_time = packet; @@ -50556,7 +71293,7 @@ index 1d965c1252ca..849e63bb426d 100644 } static void -@@ -206,6 +315,11 @@ rpi_register_hwmon_driver(struct device *dev, struct rpi_firmware *fw) +@@ -207,6 +316,11 @@ rpi_register_hwmon_driver(struct device *dev, struct rpi_firmware *fw) rpi_hwmon = platform_device_register_data(dev, "raspberrypi-hwmon", -1, NULL, 0); @@ -50568,7 +71305,7 @@ index 1d965c1252ca..849e63bb426d 100644 } static void rpi_register_clk_driver(struct device *dev) -@@ -272,8 +386,10 @@ static int rpi_firmware_probe(struct platform_device *pdev) +@@ -299,8 +413,10 @@ static int rpi_firmware_probe(struct platform_device *pdev) kref_init(&fw->consumers); platform_set_drvdata(pdev, fw); @@ -50579,15 +71316,15 @@ index 1d965c1252ca..849e63bb426d 100644 rpi_register_hwmon_driver(dev, fw); rpi_register_clk_driver(dev); -@@ -298,6 +414,7 @@ static int rpi_firmware_remove(struct platform_device *pdev) - rpi_hwmon = NULL; - platform_device_unregister(rpi_clk); +@@ -327,6 +443,7 @@ static int rpi_firmware_remove(struct platform_device *pdev) rpi_clk = NULL; -+ g_pdev = NULL; rpi_firmware_put(fw); ++ g_pdev = NULL; -@@ -352,7 +469,35 @@ static struct platform_driver rpi_firmware_driver = { + return 0; + } +@@ -407,7 +524,35 @@ static struct platform_driver rpi_firmware_driver = { .shutdown = rpi_firmware_shutdown, .remove = rpi_firmware_remove, }; @@ -50625,10 +71362,10 @@ index 1d965c1252ca..849e63bb426d 100644 MODULE_AUTHOR("Eric Anholt "); MODULE_DESCRIPTION("Raspberry Pi firmware driver"); diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig -index c91355c89ec6..344405baf78e 100644 +index 3d186a39dd71..7d651afd4c20 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig -@@ -193,6 +193,12 @@ config GPIO_BCM_XGS_IPROC +@@ -207,10 +207,16 @@ config GPIO_BCM_XGS_IPROC help Say yes here to enable GPIO support for Broadcom XGS iProc SoCs. @@ -50641,9 +71378,14 @@ index c91355c89ec6..344405baf78e 100644 config GPIO_BRCMSTB tristate "BRCMSTB GPIO support" default y if (ARCH_BRCMSTB || BMIPS_GENERIC) -@@ -487,6 +493,14 @@ config GPIO_PMIC_EIC_SPRD +- depends on OF_GPIO && (ARCH_BRCMSTB || BMIPS_GENERIC || COMPILE_TEST) ++ depends on OF_GPIO && (ARCH_BRCMSTB || BMIPS_GENERIC || ARCH_BCM2835 || COMPILE_TEST) + select GPIO_GENERIC + select IRQ_DOMAIN help - Say yes here to support Spreadtrum PMIC EIC device. +@@ -512,6 +518,14 @@ config GPIO_PL061 + help + Say yes here to support the PrimeCell PL061 GPIO device. +config GPIO_PWM + tristate "PWM chip GPIO" @@ -50656,9 +71398,9 @@ index c91355c89ec6..344405baf78e 100644 config GPIO_PXA bool "PXA GPIO support" depends on ARCH_PXA || ARCH_MMP || COMPILE_TEST -@@ -1178,6 +1192,15 @@ config HTC_EGPIO - several HTC phones. It provides basic support for input - pins, output pins, and irqs. +@@ -1301,6 +1315,15 @@ config GPIO_ELKHARTLAKE + To compile this driver as a module, choose M here: the module will + be called gpio-elkhartlake. +config GPIO_FSM + tristate "GPIO FSM support" @@ -50673,7 +71415,7 @@ index c91355c89ec6..344405baf78e 100644 tristate "Janz VMOD-TTL Digital IO Module" depends on MFD_JANZ_CMODIO diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile -index 1af147d8ad71..cb5a275692d5 100644 +index e44a700ec7d3..b24942a691bb 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -38,6 +38,7 @@ obj-$(CONFIG_GPIO_ASPEED_SGPIO) += gpio-aspeed-sgpio.o @@ -50681,18 +71423,18 @@ index 1af147d8ad71..cb5a275692d5 100644 obj-$(CONFIG_GPIO_BCM_KONA) += gpio-bcm-kona.o obj-$(CONFIG_GPIO_BCM_XGS_IPROC) += gpio-xgs-iproc.o +obj-$(CONFIG_GPIO_BCM_VIRT) += gpio-bcm-virt.o - obj-$(CONFIG_GPIO_BD70528) += gpio-bd70528.o + obj-$(CONFIG_GPIO_BD71815) += gpio-bd71815.o obj-$(CONFIG_GPIO_BD71828) += gpio-bd71828.o obj-$(CONFIG_GPIO_BD9571MWV) += gpio-bd9571mwv.o -@@ -59,6 +60,7 @@ obj-$(CONFIG_GPIO_EP93XX) += gpio-ep93xx.o +@@ -61,6 +62,7 @@ obj-$(CONFIG_GPIO_EN7523) += gpio-en7523.o + obj-$(CONFIG_GPIO_EP93XX) += gpio-ep93xx.o obj-$(CONFIG_GPIO_EXAR) += gpio-exar.o obj-$(CONFIG_GPIO_F7188X) += gpio-f7188x.o - obj-$(CONFIG_GPIO_FTGPIO010) += gpio-ftgpio010.o +obj-$(CONFIG_GPIO_FSM) += gpio-fsm.o + obj-$(CONFIG_GPIO_FTGPIO010) += gpio-ftgpio010.o + obj-$(CONFIG_GPIO_FXL6408) += gpio-fxl6408.o obj-$(CONFIG_GPIO_GE_FPGA) += gpio-ge.o - obj-$(CONFIG_GPIO_GPIO_MM) += gpio-gpio-mm.o - obj-$(CONFIG_GPIO_GRGPIO) += gpio-grgpio.o -@@ -119,6 +121,7 @@ obj-$(CONFIG_GPIO_PCI_IDIO_16) += gpio-pci-idio-16.o +@@ -128,6 +130,7 @@ obj-$(CONFIG_GPIO_PCI_IDIO_16) += gpio-pci-idio-16.o obj-$(CONFIG_GPIO_PISOSR) += gpio-pisosr.o obj-$(CONFIG_GPIO_PL061) += gpio-pl061.o obj-$(CONFIG_GPIO_PMIC_EIC_SPRD) += gpio-pmic-eic-sprd.o @@ -50702,7 +71444,7 @@ index 1af147d8ad71..cb5a275692d5 100644 obj-$(CONFIG_GPIO_RC5T583) += gpio-rc5t583.o diff --git a/drivers/gpio/gpio-bcm-virt.c b/drivers/gpio/gpio-bcm-virt.c new file mode 100644 -index 000000000000..55c40190e88a +index 000000000000..3b1ae097cd7b --- /dev/null +++ b/drivers/gpio/gpio-bcm-virt.c @@ -0,0 +1,214 @@ @@ -50719,7 +71461,7 @@ index 000000000000..55c40190e88a + */ + +#include -+#include ++#include +#include +#include +#include @@ -50787,19 +71529,20 @@ index 000000000000..55c40190e88a +{ + int err = 0; + struct device *dev = &pdev->dev; -+ struct device_node *np = dev->of_node; ++ struct device_node *np = dev_of_node(dev); + struct device_node *fw_node; + struct rpi_firmware *fw; + struct brcmvirt_gpio *ucb; + u32 gpiovirtbuf; + -+ fw_node = of_parse_phandle(np, "firmware", 0); ++ fw_node = of_get_parent(np); + if (!fw_node) { + dev_err(dev, "Missing firmware node\n"); + return -ENOENT; + } + -+ fw = rpi_firmware_get(fw_node); ++ fw = devm_rpi_firmware_get(&pdev->dev, fw_node); ++ of_node_put(fw_node); + if (!fw) + return -EPROBE_DEFER; + @@ -50853,11 +71596,10 @@ index 000000000000..55c40190e88a + } + ucb->bus_addr = 0; + } ++ ucb->gc.parent = dev; + ucb->gc.label = MODULE_NAME; + ucb->gc.owner = THIS_MODULE; -+ //ucb->gc.dev = dev; -+ ucb->gc.of_node = np; -+ ucb->gc.base = 100; ++ ucb->gc.base = -1; + ucb->gc.ngpio = NUM_GPIO; + + ucb->gc.direction_input = brcmvirt_gpio_dir_in; @@ -50920,12 +71662,151 @@ index 000000000000..55c40190e88a +MODULE_AUTHOR("Dom Cobley "); +MODULE_DESCRIPTION("brcmvirt GPIO driver"); +MODULE_ALIAS("platform:brcmvirt-gpio"); +diff --git a/drivers/gpio/gpio-brcmstb.c b/drivers/gpio/gpio-brcmstb.c +index bccdbfd5ec80..5f7e93335dcb 100644 +--- a/drivers/gpio/gpio-brcmstb.c ++++ b/drivers/gpio/gpio-brcmstb.c +@@ -50,7 +50,6 @@ struct brcmstb_gpio_priv { + struct irq_domain *irq_domain; + struct irq_chip irq_chip; + int parent_irq; +- int gpio_base; + int num_gpios; + int parent_wake_irq; + }; +@@ -92,7 +91,7 @@ brcmstb_gpio_get_active_irqs(struct brcmstb_gpio_bank *bank) + static int brcmstb_gpio_hwirq_to_offset(irq_hw_number_t hwirq, + struct brcmstb_gpio_bank *bank) + { +- return hwirq - (bank->gc.base - bank->parent_priv->gpio_base); ++ return hwirq - bank->id * 32; + } + + static void brcmstb_gpio_set_imask(struct brcmstb_gpio_bank *bank, +@@ -117,8 +116,9 @@ static void brcmstb_gpio_set_imask(struct brcmstb_gpio_bank *bank, + static int brcmstb_gpio_to_irq(struct gpio_chip *gc, unsigned offset) + { + struct brcmstb_gpio_priv *priv = brcmstb_gpio_gc_to_priv(gc); ++ struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc); + /* gc_offset is relative to this gpio_chip; want real offset */ +- int hwirq = offset + (gc->base - priv->gpio_base); ++ int hwirq = offset + bank->id * 32; + + if (hwirq >= priv->num_gpios) + return -ENXIO; +@@ -263,7 +263,7 @@ static void brcmstb_gpio_irq_bank_handler(struct brcmstb_gpio_bank *bank) + { + struct brcmstb_gpio_priv *priv = bank->parent_priv; + struct irq_domain *domain = priv->irq_domain; +- int hwbase = bank->gc.base - priv->gpio_base; ++ int hwbase = bank->id * 32; + unsigned long status; + + while ((status = brcmstb_gpio_get_active_irqs(bank))) { +@@ -414,7 +414,7 @@ static int brcmstb_gpio_of_xlate(struct gpio_chip *gc, + if (WARN_ON(gpiospec->args_count < gc->of_gpio_n_cells)) + return -EINVAL; + +- offset = gpiospec->args[0] - (gc->base - priv->gpio_base); ++ offset = gpiospec->args[0] - bank->id * 32; + if (offset >= gc->ngpio || offset < 0) + return -EINVAL; + +@@ -598,8 +598,8 @@ static int brcmstb_gpio_probe(struct platform_device *pdev) + const __be32 *p; + u32 bank_width; + int num_banks = 0; ++ int num_gpios = 0; + int err; +- static int gpio_base; + unsigned long flags = 0; + bool need_wakeup_event = false; + +@@ -613,7 +613,6 @@ static int brcmstb_gpio_probe(struct platform_device *pdev) + if (IS_ERR(reg_base)) + return PTR_ERR(reg_base); + +- priv->gpio_base = gpio_base; + priv->reg_base = reg_base; + priv->pdev = pdev; + +@@ -639,6 +638,8 @@ static int brcmstb_gpio_probe(struct platform_device *pdev) + #if defined(CONFIG_MIPS) && defined(__BIG_ENDIAN) + flags = BGPIOF_BIG_ENDIAN_BYTE_ORDER; + #endif ++ if (of_property_read_bool(np, "brcm,gpio-direct")) ++ flags |= BGPIOF_REG_DIRECT; + + of_property_for_each_u32(np, "brcm,gpio-bank-widths", prop, p, + bank_width) { +@@ -653,7 +654,7 @@ static int brcmstb_gpio_probe(struct platform_device *pdev) + dev_dbg(dev, "Width 0 found: Empty bank @ %d\n", + num_banks); + num_banks++; +- gpio_base += MAX_GPIO_PER_BANK; ++ num_gpios += MAX_GPIO_PER_BANK; + continue; + } + +@@ -688,16 +689,18 @@ static int brcmstb_gpio_probe(struct platform_device *pdev) + } + + gc->owner = THIS_MODULE; +- gc->label = devm_kasprintf(dev, GFP_KERNEL, "%pOF", np); ++ gc->label = devm_kasprintf(dev, GFP_KERNEL, "gpio-brcmstb@%zx", ++ (size_t)res->start + ++ GIO_BANK_OFF(bank->id, 0)); + if (!gc->label) { + err = -ENOMEM; + goto fail; + } +- gc->base = gpio_base; ++ gc->base = -1; + gc->of_gpio_n_cells = 2; + gc->of_xlate = brcmstb_gpio_of_xlate; + /* not all ngpio lines are valid, will use bank width later */ +- gc->ngpio = MAX_GPIO_PER_BANK; ++ gc->ngpio = bank_width; + gc->offset = bank->id * MAX_GPIO_PER_BANK; + if (priv->parent_irq > 0) + gc->to_irq = brcmstb_gpio_to_irq; +@@ -706,8 +709,10 @@ static int brcmstb_gpio_probe(struct platform_device *pdev) + * Mask all interrupts by default, since wakeup interrupts may + * be retained from S5 cold boot + */ +- need_wakeup_event |= !!__brcmstb_gpio_get_active_irqs(bank); +- gc->write_reg(reg_base + GIO_MASK(bank->id), 0); ++ if (priv->parent_irq > 0) { ++ need_wakeup_event |= !!__brcmstb_gpio_get_active_irqs(bank); ++ gc->write_reg(reg_base + GIO_MASK(bank->id), 0); ++ } + + err = gpiochip_add_data(gc, bank); + if (err) { +@@ -715,7 +720,7 @@ static int brcmstb_gpio_probe(struct platform_device *pdev) + bank->id); + goto fail; + } +- gpio_base += gc->ngpio; ++ num_gpios += gc->ngpio; + + dev_dbg(dev, "bank=%d, base=%d, ngpio=%d, width=%d\n", bank->id, + gc->base, gc->ngpio, bank->width); +@@ -726,7 +731,7 @@ static int brcmstb_gpio_probe(struct platform_device *pdev) + num_banks++; + } + +- priv->num_gpios = gpio_base - priv->gpio_base; ++ priv->num_gpios = num_gpios; + if (priv->parent_irq > 0) { + err = brcmstb_gpio_irq_setup(pdev, priv); + if (err) diff --git a/drivers/gpio/gpio-fsm.c b/drivers/gpio/gpio-fsm.c new file mode 100644 -index 000000000000..3a348f1c6514 +index 000000000000..ad8cbd894ca6 --- /dev/null +++ b/drivers/gpio/gpio-fsm.c -@@ -0,0 +1,1210 @@ +@@ -0,0 +1,1212 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * GPIO FSM driver @@ -50946,6 +71827,7 @@ index 000000000000..3a348f1c6514 +#include +#include +#include ++#include +#include +#include +#include @@ -51049,7 +71931,7 @@ index 000000000000..3a348f1c6514 + struct fsm_state *current_state; + struct fsm_state *next_state; + struct fsm_state *delay_target_state; -+ unsigned int delay_jiffies; ++ unsigned long delay_jiffies; + int delay_ms; + unsigned int debug; + bool shutting_down; @@ -51121,131 +72003,11 @@ index 000000000000..3a348f1c6514 + } +} + -+static int gpio_fsm_get_direction(struct gpio_chip *gc, unsigned int off) -+{ -+ struct gpio_fsm *gf = gpiochip_get_data(gc); -+ struct soft_gpio *sg; -+ -+ if (off >= gf->num_soft_gpios) -+ return -EINVAL; -+ sg = &gf->soft_gpios[off]; -+ -+ return sg->dir; -+} -+ -+static int gpio_fsm_get(struct gpio_chip *gc, unsigned int off) -+{ -+ struct gpio_fsm *gf = gpiochip_get_data(gc); -+ struct soft_gpio *sg; -+ -+ if (off >= gf->num_soft_gpios) -+ return -EINVAL; -+ sg = &gf->soft_gpios[off]; -+ -+ return sg->value; -+} -+ -+static void gpio_fsm_go_to_state(struct gpio_fsm *gf, -+ struct fsm_state *new_state) -+{ -+ struct input_gpio_state *inp_state; -+ struct gpio_event *gp_ev; -+ struct fsm_state *state; -+ int i; -+ -+ dev_dbg(gf->dev, "go_to_state(%s)\n", -+ new_state ? new_state->name : ""); -+ -+ spin_lock(&gf->spinlock); -+ -+ if (gf->next_state) { -+ /* Something else has already requested a transition */ -+ spin_unlock(&gf->spinlock); -+ return; -+ } -+ -+ gf->next_state = new_state; -+ state = gf->current_state; -+ gf->delay_target_state = NULL; -+ -+ if (state) { -+ /* Disarm any GPIO IRQs */ -+ for (i = 0; i < state->num_gpio_events; i++) { -+ gp_ev = &state->gpio_events[i]; -+ inp_state = &gf->input_gpio_states[gp_ev->index]; -+ inp_state->target = NULL; -+ } -+ } -+ -+ spin_unlock(&gf->spinlock); -+ -+ if (new_state) -+ schedule_work(&gf->work); -+} -+ +static void gpio_fsm_set_soft(struct gpio_fsm *gf, -+ unsigned int off, int val) -+{ -+ struct soft_gpio *sg = &gf->soft_gpios[off]; -+ struct gpio_event *gp_ev; -+ struct fsm_state *state; -+ int i; -+ -+ dev_dbg(gf->dev, "set(%d,%d)\n", off, val); -+ state = gf->current_state; -+ sg->value = val; -+ for (i = 0; i < state->num_soft_events; i++) { -+ gp_ev = &state->soft_events[i]; -+ if (gp_ev->index == off && gp_ev->value == val) { -+ if (gf->debug) -+ dev_info(gf->dev, -+ "GF_SOFT %d->%d -> %s\n", gp_ev->index, -+ gp_ev->value, gp_ev->target->name); -+ gpio_fsm_go_to_state(gf, gp_ev->target); -+ break; -+ } -+ } -+} -+ -+static int gpio_fsm_direction_input(struct gpio_chip *gc, unsigned int off) -+{ -+ struct gpio_fsm *gf = gpiochip_get_data(gc); -+ struct soft_gpio *sg; -+ -+ if (off >= gf->num_soft_gpios) -+ return -EINVAL; -+ sg = &gf->soft_gpios[off]; -+ sg->dir = GPIOF_DIR_IN; -+ -+ return 0; -+} -+ -+static int gpio_fsm_direction_output(struct gpio_chip *gc, unsigned int off, -+ int value) -+{ -+ struct gpio_fsm *gf = gpiochip_get_data(gc); -+ struct soft_gpio *sg; -+ -+ if (off >= gf->num_soft_gpios) -+ return -EINVAL; -+ sg = &gf->soft_gpios[off]; -+ sg->dir = GPIOF_DIR_OUT; -+ gpio_fsm_set_soft(gf, off, value); -+ -+ return 0; -+} -+ -+static void gpio_fsm_set(struct gpio_chip *gc, unsigned int off, int val) -+{ -+ struct gpio_fsm *gf; -+ -+ gf = gpiochip_get_data(gc); -+ if (off < gf->num_soft_gpios) -+ gpio_fsm_set_soft(gf, off, val); -+} ++ unsigned int off, int val); + +static void gpio_fsm_enter_state(struct gpio_fsm *gf, -+ struct fsm_state *state) ++ struct fsm_state *state) +{ + struct input_gpio_state *inp_state; + struct output_signal *signal; @@ -51258,6 +72020,7 @@ index 000000000000..3a348f1c6514 + dev_dbg(gf->dev, "enter_state(%s)\n", state->name); + + gf->current_state = state; ++ gf->delay_target_state = NULL; + + // 1. Apply any listed signals + for (i = 0; i < state->num_signals; i++) { @@ -51316,7 +72079,7 @@ index 000000000000..3a348f1c6514 + dev_info(gf->dev, + "GF_SOFT %d=%d -> %s\n", event->index, + event->value, event->target->name); -+ gpio_fsm_go_to_state(gf, event->target); ++ gpio_fsm_enter_state(gf, event->target); + return; + } + } @@ -51329,7 +72092,7 @@ index 000000000000..3a348f1c6514 + inp_state->value = event->value; + inp_state->enabled = true; + -+ value = gpiod_get_value(gf->input_gpios->desc[event->index]); ++ value = gpiod_get_value_cansleep(gf->input_gpios->desc[event->index]); + + // Clear stale event state + disable_irq(inp_state->irq); @@ -51344,7 +72107,7 @@ index 000000000000..3a348f1c6514 + dev_info(gf->dev, + "GF_IN %d=%d -> %s\n", event->index, + event->value, event->target->name); -+ gpio_fsm_go_to_state(gf, event->target); ++ gpio_fsm_enter_state(gf, event->target); + return; + } + } @@ -51359,40 +72122,79 @@ index 000000000000..3a348f1c6514 + } +} + -+static void gpio_fsm_work(struct work_struct *work) ++static void gpio_fsm_go_to_state(struct gpio_fsm *gf, ++ struct fsm_state *new_state) +{ + struct input_gpio_state *inp_state; -+ struct fsm_state *new_state; -+ struct fsm_state *state; + struct gpio_event *gp_ev; -+ struct gpio_fsm *gf; ++ struct fsm_state *state; + int i; + -+ gf = container_of(work, struct gpio_fsm, work); -+ spin_lock(&gf->spinlock); -+ state = gf->current_state; -+ new_state = gf->next_state; -+ if (!new_state) -+ new_state = gf->delay_target_state; -+ gf->next_state = NULL; -+ gf->delay_target_state = NULL; -+ spin_unlock(&gf->spinlock); ++ dev_dbg(gf->dev, "go_to_state(%s)\n", ++ new_state ? new_state->name : ""); + -+ if (state) { -+ /* Disable any enabled GPIO IRQs */ -+ for (i = 0; i < state->num_gpio_events; i++) { -+ gp_ev = &state->gpio_events[i]; -+ inp_state = &gf->input_gpio_states[gp_ev->index]; -+ if (inp_state->enabled) { -+ inp_state->enabled = false; -+ irq_set_irq_type(inp_state->irq, -+ IRQF_TRIGGER_NONE); -+ } ++ state = gf->current_state; ++ ++ /* Disable any enabled GPIO IRQs */ ++ for (i = 0; i < state->num_gpio_events; i++) { ++ gp_ev = &state->gpio_events[i]; ++ inp_state = &gf->input_gpio_states[gp_ev->index]; ++ if (inp_state->enabled) { ++ inp_state->enabled = false; ++ irq_set_irq_type(inp_state->irq, ++ IRQF_TRIGGER_NONE); + } + } + -+ if (new_state) -+ gpio_fsm_enter_state(gf, new_state); ++ gpio_fsm_enter_state(gf, new_state); ++} ++ ++static void gpio_fsm_go_to_state_deferred(struct gpio_fsm *gf, ++ struct fsm_state *new_state) ++{ ++ struct input_gpio_state *inp_state; ++ struct gpio_event *gp_ev; ++ struct fsm_state *state; ++ int i; ++ ++ dev_dbg(gf->dev, "go_to_state_deferred(%s)\n", ++ new_state ? new_state->name : ""); ++ ++ spin_lock(&gf->spinlock); ++ ++ if (gf->next_state) { ++ /* Something else has already requested a transition */ ++ spin_unlock(&gf->spinlock); ++ return; ++ } ++ ++ gf->next_state = new_state; ++ state = gf->current_state; ++ ++ /* Disarm any GPIO IRQs */ ++ for (i = 0; i < state->num_gpio_events; i++) { ++ gp_ev = &state->gpio_events[i]; ++ inp_state = &gf->input_gpio_states[gp_ev->index]; ++ inp_state->target = NULL; ++ } ++ ++ spin_unlock(&gf->spinlock); ++ ++ schedule_work(&gf->work); ++} ++ ++static void gpio_fsm_work(struct work_struct *work) ++{ ++ struct fsm_state *new_state; ++ struct gpio_fsm *gf; ++ ++ gf = container_of(work, struct gpio_fsm, work); ++ spin_lock(&gf->spinlock); ++ new_state = gf->next_state; ++ gf->next_state = NULL; ++ spin_unlock(&gf->spinlock); ++ ++ gpio_fsm_go_to_state(gf, new_state); +} + +static irqreturn_t gpio_fsm_gpio_irq_handler(int irq, void *dev_id) @@ -51411,7 +72213,7 @@ index 000000000000..3a348f1c6514 + if (gf->debug) + dev_info(gf->dev, "GF_IN %d->%d -> %s\n", + inp_state->index, inp_state->value, target->name); -+ gpio_fsm_go_to_state(gf, target); ++ gpio_fsm_go_to_state_deferred(gf, target); + return IRQ_HANDLED; +} + @@ -51423,12 +72225,11 @@ index 000000000000..3a348f1c6514 + target = gf->delay_target_state; + if (!target) + return; -+ + if (gf->debug) + dev_info(gf->dev, "GF_DELAY %d -> %s\n", gf->delay_ms, + target->name); + -+ gpio_fsm_go_to_state(gf, target); ++ gpio_fsm_go_to_state_deferred(gf, target); +} + +int gpio_fsm_parse_signals(struct gpio_fsm *gf, struct fsm_state *state, @@ -51779,6 +72580,90 @@ index 000000000000..3a348f1c6514 + return 0; +} + ++static void gpio_fsm_set_soft(struct gpio_fsm *gf, ++ unsigned int off, int val) ++{ ++ struct soft_gpio *sg = &gf->soft_gpios[off]; ++ struct gpio_event *gp_ev; ++ struct fsm_state *state; ++ int i; ++ ++ dev_dbg(gf->dev, "set(%d,%d)\n", off, val); ++ state = gf->current_state; ++ sg->value = val; ++ for (i = 0; i < state->num_soft_events; i++) { ++ gp_ev = &state->soft_events[i]; ++ if (gp_ev->index == off && gp_ev->value == val) { ++ if (gf->debug) ++ dev_info(gf->dev, ++ "GF_SOFT %d->%d -> %s\n", gp_ev->index, ++ gp_ev->value, gp_ev->target->name); ++ gpio_fsm_go_to_state(gf, gp_ev->target); ++ break; ++ } ++ } ++} ++ ++static int gpio_fsm_get(struct gpio_chip *gc, unsigned int off) ++{ ++ struct gpio_fsm *gf = gpiochip_get_data(gc); ++ struct soft_gpio *sg; ++ ++ if (off >= gf->num_soft_gpios) ++ return -EINVAL; ++ sg = &gf->soft_gpios[off]; ++ ++ return sg->value; ++} ++ ++static void gpio_fsm_set(struct gpio_chip *gc, unsigned int off, int val) ++{ ++ struct gpio_fsm *gf; ++ ++ gf = gpiochip_get_data(gc); ++ if (off < gf->num_soft_gpios) ++ gpio_fsm_set_soft(gf, off, val); ++} ++ ++static int gpio_fsm_get_direction(struct gpio_chip *gc, unsigned int off) ++{ ++ struct gpio_fsm *gf = gpiochip_get_data(gc); ++ struct soft_gpio *sg; ++ ++ if (off >= gf->num_soft_gpios) ++ return -EINVAL; ++ sg = &gf->soft_gpios[off]; ++ ++ return sg->dir; ++} ++ ++static int gpio_fsm_direction_input(struct gpio_chip *gc, unsigned int off) ++{ ++ struct gpio_fsm *gf = gpiochip_get_data(gc); ++ struct soft_gpio *sg; ++ ++ if (off >= gf->num_soft_gpios) ++ return -EINVAL; ++ sg = &gf->soft_gpios[off]; ++ sg->dir = GPIOF_DIR_IN; ++ ++ return 0; ++} ++ ++static int gpio_fsm_direction_output(struct gpio_chip *gc, unsigned int off, ++ int value) ++{ ++ struct gpio_fsm *gf = gpiochip_get_data(gc); ++ struct soft_gpio *sg; ++ ++ if (off >= gf->num_soft_gpios) ++ return -EINVAL; ++ sg = &gf->soft_gpios[off]; ++ sg->dir = GPIOF_DIR_OUT; ++ gpio_fsm_set_soft(gf, off, value); ++ ++ return 0; ++} + +/* + * /sys/class/gpio-fsm// @@ -51844,7 +72729,6 @@ index 000000000000..3a348f1c6514 + +static struct class gpio_fsm_class = { + .name = MODULE_NAME, -+ .owner = THIS_MODULE, + + .class_groups = gpio_fsm_class_groups, +}; @@ -51854,7 +72738,7 @@ index 000000000000..3a348f1c6514 + struct input_gpio_state *inp_state; + struct device *dev = &pdev->dev; + struct device *sysfs_dev; -+ struct device_node *np = dev->of_node; ++ struct device_node *np = dev_of_node(dev); + struct device_node *cp; + struct gpio_fsm *gf; + u32 debug = 0; @@ -52015,7 +72899,6 @@ index 000000000000..3a348f1c6514 + gf->gc.parent = dev; + gf->gc.label = np->name; + gf->gc.owner = THIS_MODULE; -+ gf->gc.of_node = np; + gf->gc.base = -1; + gf->gc.ngpio = num_soft_gpios; + @@ -52042,7 +72925,7 @@ index 000000000000..3a348f1c6514 + if (gf->debug) + dev_info(gf->dev, "Start -> %s\n", gf->start_state->name); + -+ gpio_fsm_go_to_state(gf, gf->start_state); ++ gpio_fsm_enter_state(gf, gf->start_state); + + return devm_gpiochip_add_data(dev, &gf->gc, gf); +} @@ -52136,9 +73019,198 @@ index 000000000000..3a348f1c6514 +MODULE_AUTHOR("Phil Elwell "); +MODULE_DESCRIPTION("GPIO FSM driver"); +MODULE_ALIAS("platform:gpio-fsm"); +diff --git a/drivers/gpio/gpio-mmio.c b/drivers/gpio/gpio-mmio.c +index 74fdf0d87b2c..7e26fa957d5e 100644 +--- a/drivers/gpio/gpio-mmio.c ++++ b/drivers/gpio/gpio-mmio.c +@@ -234,6 +234,25 @@ static void bgpio_set(struct gpio_chip *gc, unsigned int gpio, int val) + raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); + } + ++static void bgpio_set_direct(struct gpio_chip *gc, unsigned int gpio, int val) ++{ ++ unsigned long mask = bgpio_line2mask(gc, gpio); ++ unsigned long flags; ++ ++ raw_spin_lock_irqsave(&gc->bgpio_lock, flags); ++ ++ gc->bgpio_data = gc->read_reg(gc->reg_dat); ++ ++ if (val) ++ gc->bgpio_data |= mask; ++ else ++ gc->bgpio_data &= ~mask; ++ ++ gc->write_reg(gc->reg_dat, gc->bgpio_data); ++ ++ raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); ++} ++ + static void bgpio_set_with_clear(struct gpio_chip *gc, unsigned int gpio, + int val) + { +@@ -326,6 +345,27 @@ static void bgpio_set_multiple_with_clear(struct gpio_chip *gc, + gc->write_reg(gc->reg_clr, clear_mask); + } + ++static void bgpio_set_multiple_direct(struct gpio_chip *gc, ++ unsigned long *mask, ++ unsigned long *bits) ++{ ++ unsigned long flags; ++ unsigned long set_mask, clear_mask; ++ ++ raw_spin_lock_irqsave(&gc->bgpio_lock, flags); ++ ++ bgpio_multiple_get_masks(gc, mask, bits, &set_mask, &clear_mask); ++ ++ gc->bgpio_data = gc->read_reg(gc->reg_dat); ++ ++ gc->bgpio_data |= set_mask; ++ gc->bgpio_data &= ~clear_mask; ++ ++ gc->write_reg(gc->reg_dat, gc->bgpio_data); ++ ++ raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); ++} ++ + static int bgpio_simple_dir_in(struct gpio_chip *gc, unsigned int gpio) + { + return 0; +@@ -363,6 +403,29 @@ static int bgpio_dir_in(struct gpio_chip *gc, unsigned int gpio) + return 0; + } + ++static int bgpio_dir_in_direct(struct gpio_chip *gc, unsigned int gpio) ++{ ++ unsigned long flags; ++ ++ raw_spin_lock_irqsave(&gc->bgpio_lock, flags); ++ ++ if (gc->reg_dir_in) ++ gc->bgpio_dir = ~gc->read_reg(gc->reg_dir_in); ++ if (gc->reg_dir_out) ++ gc->bgpio_dir = gc->read_reg(gc->reg_dir_out); ++ ++ gc->bgpio_dir &= ~bgpio_line2mask(gc, gpio); ++ ++ if (gc->reg_dir_in) ++ gc->write_reg(gc->reg_dir_in, ~gc->bgpio_dir); ++ if (gc->reg_dir_out) ++ gc->write_reg(gc->reg_dir_out, gc->bgpio_dir); ++ ++ raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); ++ ++ return 0; ++} ++ + static int bgpio_get_dir(struct gpio_chip *gc, unsigned int gpio) + { + /* Return 0 if output, 1 if input */ +@@ -401,6 +464,28 @@ static void bgpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val) + raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); + } + ++static void bgpio_dir_out_direct(struct gpio_chip *gc, unsigned int gpio, ++ int val) ++{ ++ unsigned long flags; ++ ++ raw_spin_lock_irqsave(&gc->bgpio_lock, flags); ++ ++ if (gc->reg_dir_in) ++ gc->bgpio_dir = ~gc->read_reg(gc->reg_dir_in); ++ if (gc->reg_dir_out) ++ gc->bgpio_dir = gc->read_reg(gc->reg_dir_out); ++ ++ gc->bgpio_dir |= bgpio_line2mask(gc, gpio); ++ ++ if (gc->reg_dir_in) ++ gc->write_reg(gc->reg_dir_in, ~gc->bgpio_dir); ++ if (gc->reg_dir_out) ++ gc->write_reg(gc->reg_dir_out, gc->bgpio_dir); ++ ++ raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); ++} ++ + static int bgpio_dir_out_dir_first(struct gpio_chip *gc, unsigned int gpio, + int val) + { +@@ -417,6 +502,22 @@ static int bgpio_dir_out_val_first(struct gpio_chip *gc, unsigned int gpio, + return 0; + } + ++static int bgpio_dir_out_dir_first_direct(struct gpio_chip *gc, ++ unsigned int gpio, int val) ++{ ++ bgpio_dir_out_direct(gc, gpio, val); ++ gc->set(gc, gpio, val); ++ return 0; ++} ++ ++static int bgpio_dir_out_val_first_direct(struct gpio_chip *gc, ++ unsigned int gpio, int val) ++{ ++ gc->set(gc, gpio, val); ++ bgpio_dir_out_direct(gc, gpio, val); ++ return 0; ++} ++ + static int bgpio_setup_accessors(struct device *dev, + struct gpio_chip *gc, + bool byte_be) +@@ -510,6 +611,9 @@ static int bgpio_setup_io(struct gpio_chip *gc, + } else if (flags & BGPIOF_NO_OUTPUT) { + gc->set = bgpio_set_none; + gc->set_multiple = NULL; ++ } else if (flags & BGPIOF_REG_DIRECT) { ++ gc->set = bgpio_set_direct; ++ gc->set_multiple = bgpio_set_multiple_direct; + } else { + gc->set = bgpio_set; + gc->set_multiple = bgpio_set_multiple; +@@ -546,11 +650,21 @@ static int bgpio_setup_direction(struct gpio_chip *gc, + if (dirout || dirin) { + gc->reg_dir_out = dirout; + gc->reg_dir_in = dirin; +- if (flags & BGPIOF_NO_SET_ON_INPUT) +- gc->direction_output = bgpio_dir_out_dir_first; +- else +- gc->direction_output = bgpio_dir_out_val_first; +- gc->direction_input = bgpio_dir_in; ++ if (flags & BGPIOF_REG_DIRECT) { ++ if (flags & BGPIOF_NO_SET_ON_INPUT) ++ gc->direction_output = ++ bgpio_dir_out_dir_first_direct; ++ else ++ gc->direction_output = ++ bgpio_dir_out_val_first_direct; ++ gc->direction_input = bgpio_dir_in_direct; ++ } else { ++ if (flags & BGPIOF_NO_SET_ON_INPUT) ++ gc->direction_output = bgpio_dir_out_dir_first; ++ else ++ gc->direction_output = bgpio_dir_out_val_first; ++ gc->direction_input = bgpio_dir_in; ++ } + gc->get_direction = bgpio_get_dir; + } else { + if (flags & BGPIOF_NO_OUTPUT) +diff --git a/drivers/gpio/gpio-pca953x.c b/drivers/gpio/gpio-pca953x.c +index bdd50a78e414..52923f616222 100644 +--- a/drivers/gpio/gpio-pca953x.c ++++ b/drivers/gpio/gpio-pca953x.c +@@ -1345,6 +1345,7 @@ static const struct of_device_id pca953x_dt_ids[] = { + { .compatible = "ti,tca6424", .data = OF_953X(24, PCA_INT), }, + { .compatible = "ti,tca9538", .data = OF_953X( 8, PCA_INT), }, + { .compatible = "ti,tca9539", .data = OF_953X(16, PCA_INT), }, ++ { .compatible = "ti,tca9554", .data = OF_953X( 8, PCA_INT), }, + + { .compatible = "onnn,cat9554", .data = OF_953X( 8, PCA_INT), }, + { .compatible = "onnn,pca9654", .data = OF_953X( 8, PCA_INT), }, diff --git a/drivers/gpio/gpio-pwm.c b/drivers/gpio/gpio-pwm.c new file mode 100644 -index 000000000000..89f5d6b353ab +index 000000000000..4a718b365a6f --- /dev/null +++ b/drivers/gpio/gpio-pwm.c @@ -0,0 +1,144 @@ @@ -52245,7 +73317,7 @@ index 000000000000..89f5d6b353ab + pwm_gpio->gc.parent = dev; + pwm_gpio->gc.label = "pwm-gpio"; + pwm_gpio->gc.owner = THIS_MODULE; -+ pwm_gpio->gc.of_node = dev->of_node; ++ pwm_gpio->gc.fwnode = dev->fwnode; + pwm_gpio->gc.base = -1; + + pwm_gpio->gc.get_direction = pwm_gpio_get_direction; @@ -52287,10 +73359,10 @@ index 000000000000..89f5d6b353ab +MODULE_AUTHOR("Dave Stevenson "); +MODULE_DESCRIPTION("PWM GPIO driver"); diff --git a/drivers/gpio/gpiolib.c b/drivers/gpio/gpiolib.c -index af5bb8fedfea..2bd26c985246 100644 +index deca1d43de9c..48acc58cdf2d 100644 --- a/drivers/gpio/gpiolib.c +++ b/drivers/gpio/gpiolib.c -@@ -51,6 +51,8 @@ +@@ -57,6 +57,8 @@ #define extra_checks 0 #endif @@ -52299,7 +73371,7 @@ index af5bb8fedfea..2bd26c985246 100644 /* Device and char device-related information */ static DEFINE_IDA(gpio_ida); static dev_t gpio_devt; -@@ -2444,8 +2446,8 @@ int gpiod_direction_output(struct gpio_desc *desc, int value) +@@ -2591,8 +2593,8 @@ int gpiod_direction_output(struct gpio_desc *desc, int value) value = !!value; /* GPIOs used for enabled IRQs shall not be set as output */ @@ -52310,7 +73382,7 @@ index af5bb8fedfea..2bd26c985246 100644 gpiod_err(desc, "%s: tried to set a GPIO tied to an IRQ as output\n", __func__); -@@ -3250,8 +3252,8 @@ int gpiochip_lock_as_irq(struct gpio_chip *gc, unsigned int offset) +@@ -3470,8 +3472,8 @@ int gpiochip_lock_as_irq(struct gpio_chip *gc, unsigned int offset) } /* To be valid for IRQ the line needs to be input or open drain */ @@ -52322,648 +73394,57 @@ index af5bb8fedfea..2bd26c985246 100644 "%s: tried to flag a GPIO set as output for IRQ\n", __func__); diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig -index ca868271f4c4..74872b157233 100644 +index c4a0e10b9704..a67248eb854e 100644 --- a/drivers/gpu/drm/Kconfig +++ b/drivers/gpu/drm/Kconfig -@@ -392,6 +392,8 @@ source "drivers/gpu/drm/tidss/Kconfig" +@@ -345,6 +345,8 @@ source "drivers/gpu/drm/v3d/Kconfig" - source "drivers/gpu/drm/xlnx/Kconfig" + source "drivers/gpu/drm/vc4/Kconfig" -+source "drivers/gpu/drm/gud/Kconfig" ++source "drivers/gpu/drm/rp1/Kconfig" + - # Keep legacy drivers last + source "drivers/gpu/drm/loongson/Kconfig" - menuconfig DRM_LEGACY + source "drivers/gpu/drm/etnaviv/Kconfig" diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile -index 81569009f884..78dd8e12525d 100644 +index a670c0d95023..0df4a7d4f8e2 100644 --- a/drivers/gpu/drm/Makefile +++ b/drivers/gpu/drm/Makefile -@@ -124,3 +124,4 @@ obj-$(CONFIG_DRM_ASPEED_GFX) += aspeed/ - obj-$(CONFIG_DRM_MCDE) += mcde/ - obj-$(CONFIG_DRM_TIDSS) += tidss/ - obj-y += xlnx/ -+obj-y += gud/ -diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c -index 6c8f141103da..374f2bf06c3a 100644 ---- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c -+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c -@@ -4992,7 +4992,6 @@ static void dm_disable_vblank(struct drm_crtc *crtc) - static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = { - .reset = dm_crtc_reset_state, - .destroy = amdgpu_dm_crtc_destroy, -- .gamma_set = drm_atomic_helper_legacy_gamma_set, - .set_config = drm_atomic_helper_set_config, - .page_flip = drm_atomic_helper_page_flip, - .atomic_duplicate_state = dm_crtc_duplicate_state, -@@ -5476,25 +5475,6 @@ static int fill_hdr_info_packet(const struct drm_connector_state *state, - return 0; - } - --static bool --is_hdr_metadata_different(const struct drm_connector_state *old_state, -- const struct drm_connector_state *new_state) --{ -- struct drm_property_blob *old_blob = old_state->hdr_output_metadata; -- struct drm_property_blob *new_blob = new_state->hdr_output_metadata; -- -- if (old_blob != new_blob) { -- if (old_blob && new_blob && -- old_blob->length == new_blob->length) -- return memcmp(old_blob->data, new_blob->data, -- old_blob->length); -- -- return true; -- } -- -- return false; --} -- - static int - amdgpu_dm_connector_atomic_check(struct drm_connector *conn, - struct drm_atomic_state *state) -@@ -5510,7 +5490,7 @@ amdgpu_dm_connector_atomic_check(struct drm_connector *conn, - if (!crtc) - return 0; - -- if (is_hdr_metadata_different(old_con_state, new_con_state)) { -+ if (!drm_connector_atomic_hdr_metadata_equal(old_con_state, new_con_state)) { - struct dc_info_packet hdr_infopacket; - - ret = fill_hdr_info_packet(new_con_state, &hdr_infopacket); -@@ -5605,17 +5585,19 @@ static void dm_update_crtc_active_planes(struct drm_crtc *crtc, - } - - static int dm_crtc_helper_atomic_check(struct drm_crtc *crtc, -- struct drm_crtc_state *state) -+ struct drm_atomic_state *state) - { -+ struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, -+ crtc); - struct amdgpu_device *adev = drm_to_adev(crtc->dev); - struct dc *dc = adev->dm.dc; -- struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(state); -+ struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state); - int ret = -EINVAL; - -- dm_update_crtc_active_planes(crtc, state); -+ dm_update_crtc_active_planes(crtc, crtc_state); - - if (unlikely(!dm_crtc_state->stream && -- modeset_required(state, NULL, dm_crtc_state->stream))) { -+ modeset_required(crtc_state, NULL, dm_crtc_state->stream))) { - WARN_ON(1); - return ret; +@@ -199,3 +199,4 @@ obj-y += solomon/ + obj-$(CONFIG_DRM_SPRD) += sprd/ + obj-$(CONFIG_DRM_LOONGSON) += loongson/ + obj-$(CONFIG_DRM_PHYTIUM) += phytium/ ++obj-y += rp1/ +diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig +index 3e6a4e2044c0..b1c5ef817598 100644 +--- a/drivers/gpu/drm/bridge/Kconfig ++++ b/drivers/gpu/drm/bridge/Kconfig +@@ -56,6 +56,7 @@ config DRM_CROS_EC_ANX7688 + config DRM_DISPLAY_CONNECTOR + tristate "Display connector support" + depends on OF ++ select DRM_KMS_HELPER + help + Driver for display connectors with support for DDC and hot-plug + detection. Most display controllers handle display connectors +diff --git a/drivers/gpu/drm/bridge/tc358762.c b/drivers/gpu/drm/bridge/tc358762.c +index 46198af9eebb..8b856bc2ed5b 100644 +--- a/drivers/gpu/drm/bridge/tc358762.c ++++ b/drivers/gpu/drm/bridge/tc358762.c +@@ -294,7 +294,7 @@ static int tc358762_probe(struct mipi_dsi_device *dsi) + ret = mipi_dsi_attach(dsi); + if (ret < 0) { + drm_bridge_remove(&ctx->bridge); +- dev_err(dev, "failed to attach dsi\n"); ++ dev_err_probe(dev, ret, "failed to attach dsi\n"); } -@@ -5626,8 +5608,8 @@ static int dm_crtc_helper_atomic_check(struct drm_crtc *crtc, - * planes are disabled, which is not supported by the hardware. And there is legacy - * userspace which stops using the HW cursor altogether in response to the resulting EINVAL. - */ -- if (state->enable && -- !(state->plane_mask & drm_plane_mask(crtc->primary))) -+ if (crtc_state->enable && -+ !(crtc_state->plane_mask & drm_plane_mask(crtc->primary))) - return -EINVAL; - - /* In some use cases, like reset, no stream is attached */ -@@ -6526,9 +6508,7 @@ void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm, - if (connector_type == DRM_MODE_CONNECTOR_HDMIA || - connector_type == DRM_MODE_CONNECTOR_DisplayPort || - connector_type == DRM_MODE_CONNECTOR_eDP) { -- drm_object_attach_property( -- &aconnector->base.base, -- dm->ddev->mode_config.hdr_output_metadata_property, 0); -+ drm_connector_attach_hdr_output_metadata_property(&aconnector->base); - - if (!aconnector->mst_port) - drm_connector_attach_vrr_capable_property(&aconnector->base); -@@ -7778,7 +7758,7 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) - dm_old_crtc_state->abm_level; - - hdr_changed = -- is_hdr_metadata_different(old_con_state, new_con_state); -+ !drm_connector_atomic_hdr_metadata_equal(old_con_state, new_con_state); - - if (!scaling_changed && !abm_changed && !hdr_changed) - continue; -diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c -index d617e98afb76..935e351e8ec4 100644 ---- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c -+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c -@@ -24,6 +24,7 @@ - */ - - #include -+#include - #include - #include - #include -@@ -264,8 +265,10 @@ static int dm_dp_mst_get_modes(struct drm_connector *connector) - - static struct drm_encoder * - dm_mst_atomic_best_encoder(struct drm_connector *connector, -- struct drm_connector_state *connector_state) -+ struct drm_atomic_state *state) - { -+ struct drm_connector_state *connector_state = drm_atomic_get_new_connector_state(state, -+ connector); - struct drm_device *dev = connector->dev; - struct amdgpu_device *adev = drm_to_adev(dev); - struct amdgpu_crtc *acrtc = to_amdgpu_crtc(connector_state->crtc); -diff --git a/drivers/gpu/drm/arc/arcpgu_crtc.c b/drivers/gpu/drm/arc/arcpgu_crtc.c -index be7c29cec318..042d7b54a6de 100644 ---- a/drivers/gpu/drm/arc/arcpgu_crtc.c -+++ b/drivers/gpu/drm/arc/arcpgu_crtc.c -@@ -116,7 +116,7 @@ static void arc_pgu_crtc_mode_set_nofb(struct drm_crtc *crtc) - } - - static void arc_pgu_crtc_atomic_enable(struct drm_crtc *crtc, -- struct drm_crtc_state *old_state) -+ struct drm_atomic_state *state) - { - struct arcpgu_drm_private *arcpgu = crtc_to_arcpgu_priv(crtc); - -@@ -127,7 +127,7 @@ static void arc_pgu_crtc_atomic_enable(struct drm_crtc *crtc, - } - - static void arc_pgu_crtc_atomic_disable(struct drm_crtc *crtc, -- struct drm_crtc_state *old_state) -+ struct drm_atomic_state *state) - { - struct arcpgu_drm_private *arcpgu = crtc_to_arcpgu_priv(crtc); - -diff --git a/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c b/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c -index f33418d6e1a0..00472e15ba0b 100644 ---- a/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c -+++ b/drivers/gpu/drm/arm/display/komeda/komeda_crtc.c -@@ -74,16 +74,18 @@ static void komeda_crtc_update_clock_ratio(struct komeda_crtc_state *kcrtc_st) - */ - static int - komeda_crtc_atomic_check(struct drm_crtc *crtc, -- struct drm_crtc_state *state) -+ struct drm_atomic_state *state) - { -+ struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, -+ crtc); - struct komeda_crtc *kcrtc = to_kcrtc(crtc); -- struct komeda_crtc_state *kcrtc_st = to_kcrtc_st(state); -+ struct komeda_crtc_state *kcrtc_st = to_kcrtc_st(crtc_state); - int err; - -- if (drm_atomic_crtc_needs_modeset(state)) -+ if (drm_atomic_crtc_needs_modeset(crtc_state)) - komeda_crtc_update_clock_ratio(kcrtc_st); - -- if (state->active) { -+ if (crtc_state->active) { - err = komeda_build_display_data_flow(kcrtc, kcrtc_st); - if (err) - return err; -@@ -273,8 +275,10 @@ komeda_crtc_do_flush(struct drm_crtc *crtc, - - static void - komeda_crtc_atomic_enable(struct drm_crtc *crtc, -- struct drm_crtc_state *old) -+ struct drm_atomic_state *state) - { -+ struct drm_crtc_state *old = drm_atomic_get_old_crtc_state(state, -+ crtc); - pm_runtime_get_sync(crtc->dev->dev); - komeda_crtc_prepare(to_kcrtc(crtc)); - drm_crtc_vblank_on(crtc); -@@ -319,8 +323,10 @@ komeda_crtc_flush_and_wait_for_flip_done(struct komeda_crtc *kcrtc, - - static void - komeda_crtc_atomic_disable(struct drm_crtc *crtc, -- struct drm_crtc_state *old) -+ struct drm_atomic_state *state) - { -+ struct drm_crtc_state *old = drm_atomic_get_old_crtc_state(state, -+ crtc); - struct komeda_crtc *kcrtc = to_kcrtc(crtc); - struct komeda_crtc_state *old_st = to_kcrtc_st(old); - struct komeda_pipeline *master = kcrtc->master; -@@ -379,8 +385,10 @@ komeda_crtc_atomic_disable(struct drm_crtc *crtc, - - static void - komeda_crtc_atomic_flush(struct drm_crtc *crtc, -- struct drm_crtc_state *old) -+ struct drm_atomic_state *state) - { -+ struct drm_crtc_state *old = drm_atomic_get_old_crtc_state(state, -+ crtc); - /* commit with modeset will be handled in enable/disable */ - if (drm_atomic_crtc_needs_modeset(crtc->state)) - return; -@@ -540,7 +548,6 @@ static void komeda_crtc_vblank_disable(struct drm_crtc *crtc) - } - - static const struct drm_crtc_funcs komeda_crtc_funcs = { -- .gamma_set = drm_atomic_helper_legacy_gamma_set, - .destroy = drm_crtc_cleanup, - .set_config = drm_atomic_helper_set_config, - .page_flip = drm_atomic_helper_page_flip, -diff --git a/drivers/gpu/drm/arm/hdlcd_crtc.c b/drivers/gpu/drm/arm/hdlcd_crtc.c -index af67fefed38d..a3234bfb0917 100644 ---- a/drivers/gpu/drm/arm/hdlcd_crtc.c -+++ b/drivers/gpu/drm/arm/hdlcd_crtc.c -@@ -168,7 +168,7 @@ static void hdlcd_crtc_mode_set_nofb(struct drm_crtc *crtc) - } - - static void hdlcd_crtc_atomic_enable(struct drm_crtc *crtc, -- struct drm_crtc_state *old_state) -+ struct drm_atomic_state *state) - { - struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc); - -@@ -179,7 +179,7 @@ static void hdlcd_crtc_atomic_enable(struct drm_crtc *crtc, - } - - static void hdlcd_crtc_atomic_disable(struct drm_crtc *crtc, -- struct drm_crtc_state *old_state) -+ struct drm_atomic_state *state) - { - struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc); - -@@ -205,7 +205,7 @@ static enum drm_mode_status hdlcd_crtc_mode_valid(struct drm_crtc *crtc, - } - - static void hdlcd_crtc_atomic_begin(struct drm_crtc *crtc, -- struct drm_crtc_state *state) -+ struct drm_atomic_state *state) - { - struct drm_pending_vblank_event *event = crtc->state->event; - -diff --git a/drivers/gpu/drm/arm/malidp_crtc.c b/drivers/gpu/drm/arm/malidp_crtc.c -index 587d94798f5c..494075ddbef6 100644 ---- a/drivers/gpu/drm/arm/malidp_crtc.c -+++ b/drivers/gpu/drm/arm/malidp_crtc.c -@@ -46,7 +46,7 @@ static enum drm_mode_status malidp_crtc_mode_valid(struct drm_crtc *crtc, - } - - static void malidp_crtc_atomic_enable(struct drm_crtc *crtc, -- struct drm_crtc_state *old_state) -+ struct drm_atomic_state *state) - { - struct malidp_drm *malidp = crtc_to_malidp_device(crtc); - struct malidp_hw_device *hwdev = malidp->dev; -@@ -70,8 +70,10 @@ static void malidp_crtc_atomic_enable(struct drm_crtc *crtc, - } - - static void malidp_crtc_atomic_disable(struct drm_crtc *crtc, -- struct drm_crtc_state *old_state) -+ struct drm_atomic_state *state) - { -+ struct drm_crtc_state *old_state = drm_atomic_get_old_crtc_state(state, -+ crtc); - struct malidp_drm *malidp = crtc_to_malidp_device(crtc); - struct malidp_hw_device *hwdev = malidp->dev; - int err; -@@ -335,8 +337,10 @@ static int malidp_crtc_atomic_check_scaling(struct drm_crtc *crtc, - } - - static int malidp_crtc_atomic_check(struct drm_crtc *crtc, -- struct drm_crtc_state *state) -+ struct drm_atomic_state *state) - { -+ struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, -+ crtc); - struct malidp_drm *malidp = crtc_to_malidp_device(crtc); - struct malidp_hw_device *hwdev = malidp->dev; - struct drm_plane *plane; -@@ -371,7 +375,7 @@ static int malidp_crtc_atomic_check(struct drm_crtc *crtc, - */ - - /* first count the number of rotated planes */ -- drm_atomic_crtc_state_for_each_plane_state(plane, pstate, state) { -+ drm_atomic_crtc_state_for_each_plane_state(plane, pstate, crtc_state) { - struct drm_framebuffer *fb = pstate->fb; - - if ((pstate->rotation & MALIDP_ROTATED_MASK) || fb->modifier) -@@ -387,7 +391,7 @@ static int malidp_crtc_atomic_check(struct drm_crtc *crtc, - rot_mem_free += hwdev->rotation_memory[1]; - - /* now validate the rotation memory requirements */ -- drm_atomic_crtc_state_for_each_plane_state(plane, pstate, state) { -+ drm_atomic_crtc_state_for_each_plane_state(plane, pstate, crtc_state) { - struct malidp_plane *mp = to_malidp_plane(plane); - struct malidp_plane_state *ms = to_malidp_plane_state(pstate); - struct drm_framebuffer *fb = pstate->fb; -@@ -415,18 +419,18 @@ static int malidp_crtc_atomic_check(struct drm_crtc *crtc, - } - - /* If only the writeback routing has changed, we don't need a modeset */ -- if (state->connectors_changed) { -+ if (crtc_state->connectors_changed) { - u32 old_mask = crtc->state->connector_mask; -- u32 new_mask = state->connector_mask; -+ u32 new_mask = crtc_state->connector_mask; - - if ((old_mask ^ new_mask) == - (1 << drm_connector_index(&malidp->mw_connector.base))) -- state->connectors_changed = false; -+ crtc_state->connectors_changed = false; - } - -- ret = malidp_crtc_atomic_check_gamma(crtc, state); -- ret = ret ? ret : malidp_crtc_atomic_check_ctm(crtc, state); -- ret = ret ? ret : malidp_crtc_atomic_check_scaling(crtc, state); -+ ret = malidp_crtc_atomic_check_gamma(crtc, crtc_state); -+ ret = ret ? ret : malidp_crtc_atomic_check_ctm(crtc, crtc_state); -+ ret = ret ? ret : malidp_crtc_atomic_check_scaling(crtc, crtc_state); return ret; - } -@@ -506,7 +510,6 @@ static void malidp_crtc_disable_vblank(struct drm_crtc *crtc) - } - - static const struct drm_crtc_funcs malidp_crtc_funcs = { -- .gamma_set = drm_atomic_helper_legacy_gamma_set, - .destroy = drm_crtc_cleanup, - .set_config = drm_atomic_helper_set_config, - .page_flip = drm_atomic_helper_page_flip, -diff --git a/drivers/gpu/drm/armada/armada_crtc.c b/drivers/gpu/drm/armada/armada_crtc.c -index a887b6a5f8bd..f10a063b338c 100644 ---- a/drivers/gpu/drm/armada/armada_crtc.c -+++ b/drivers/gpu/drm/armada/armada_crtc.c -@@ -413,21 +413,23 @@ static void armada_drm_crtc_mode_set_nofb(struct drm_crtc *crtc) - } - - static int armada_drm_crtc_atomic_check(struct drm_crtc *crtc, -- struct drm_crtc_state *state) -+ struct drm_atomic_state *state) - { -+ struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, -+ crtc); - DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.id, crtc->name); - -- if (state->gamma_lut && drm_color_lut_size(state->gamma_lut) != 256) -+ if (crtc_state->gamma_lut && drm_color_lut_size(crtc_state->gamma_lut) != 256) - return -EINVAL; - -- if (state->color_mgmt_changed) -- state->planes_changed = true; -+ if (crtc_state->color_mgmt_changed) -+ crtc_state->planes_changed = true; - - return 0; - } - - static void armada_drm_crtc_atomic_begin(struct drm_crtc *crtc, -- struct drm_crtc_state *old_crtc_state) -+ struct drm_atomic_state *state) - { - struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc); - -@@ -441,7 +443,7 @@ static void armada_drm_crtc_atomic_begin(struct drm_crtc *crtc, - } - - static void armada_drm_crtc_atomic_flush(struct drm_crtc *crtc, -- struct drm_crtc_state *old_crtc_state) -+ struct drm_atomic_state *state) - { - struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc); - -@@ -467,8 +469,10 @@ static void armada_drm_crtc_atomic_flush(struct drm_crtc *crtc, - } - - static void armada_drm_crtc_atomic_disable(struct drm_crtc *crtc, -- struct drm_crtc_state *old_state) -+ struct drm_atomic_state *state) - { -+ struct drm_crtc_state *old_state = drm_atomic_get_old_crtc_state(state, -+ crtc); - struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc); - struct drm_pending_vblank_event *event; - -@@ -503,8 +507,10 @@ static void armada_drm_crtc_atomic_disable(struct drm_crtc *crtc, - } - - static void armada_drm_crtc_atomic_enable(struct drm_crtc *crtc, -- struct drm_crtc_state *old_state) -+ struct drm_atomic_state *state) - { -+ struct drm_crtc_state *old_state = drm_atomic_get_old_crtc_state(state, -+ crtc); - struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc); - - DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.id, crtc->name); -@@ -810,7 +816,6 @@ static const struct drm_crtc_funcs armada_crtc_funcs = { - .cursor_set = armada_drm_crtc_cursor_set, - .cursor_move = armada_drm_crtc_cursor_move, - .destroy = armada_drm_crtc_destroy, -- .gamma_set = drm_atomic_helper_legacy_gamma_set, - .set_config = drm_atomic_helper_set_config, - .page_flip = drm_atomic_helper_page_flip, - .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state, -diff --git a/drivers/gpu/drm/ast/ast_mode.c b/drivers/gpu/drm/ast/ast_mode.c -index d27f2840b955..9f3b8152becd 100644 ---- a/drivers/gpu/drm/ast/ast_mode.c -+++ b/drivers/gpu/drm/ast/ast_mode.c -@@ -751,24 +751,26 @@ static void ast_crtc_dpms(struct drm_crtc *crtc, int mode) - } - - static int ast_crtc_helper_atomic_check(struct drm_crtc *crtc, -- struct drm_crtc_state *state) -+ struct drm_atomic_state *state) - { -+ struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, -+ crtc); - struct drm_device *dev = crtc->dev; - struct ast_crtc_state *ast_state; - const struct drm_format_info *format; - bool succ; - -- if (!state->enable) -+ if (!crtc_state->enable) - return 0; /* no mode checks if CRTC is being disabled */ - -- ast_state = to_ast_crtc_state(state); -+ ast_state = to_ast_crtc_state(crtc_state); - - format = ast_state->format; - if (drm_WARN_ON_ONCE(dev, !format)) - return -EINVAL; /* BUG: We didn't set format in primary check(). */ - -- succ = ast_get_vbios_mode_info(format, &state->mode, -- &state->adjusted_mode, -+ succ = ast_get_vbios_mode_info(format, &crtc_state->mode, -+ &crtc_state->adjusted_mode, - &ast_state->vbios_mode_info); - if (!succ) - return -EINVAL; -@@ -793,7 +795,7 @@ ast_crtc_helper_atomic_flush(struct drm_crtc *crtc, struct drm_crtc_state *old_c - - static void - ast_crtc_helper_atomic_enable(struct drm_crtc *crtc, -- struct drm_crtc_state *old_crtc_state) -+ struct drm_atomic_state *state) - { - struct drm_device *dev = crtc->dev; - struct ast_private *ast = to_ast_private(dev); -@@ -816,8 +818,10 @@ ast_crtc_helper_atomic_enable(struct drm_crtc *crtc, - - static void - ast_crtc_helper_atomic_disable(struct drm_crtc *crtc, -- struct drm_crtc_state *old_crtc_state) -+ struct drm_atomic_state *state) - { -+ struct drm_crtc_state *old_crtc_state = drm_atomic_get_old_crtc_state(state, -+ crtc); - struct drm_device *dev = crtc->dev; - struct ast_private *ast = to_ast_private(dev); - -@@ -897,7 +901,6 @@ static void ast_crtc_atomic_destroy_state(struct drm_crtc *crtc, - - static const struct drm_crtc_funcs ast_crtc_funcs = { - .reset = ast_crtc_reset, -- .gamma_set = drm_atomic_helper_legacy_gamma_set, - .destroy = drm_crtc_cleanup, - .set_config = drm_atomic_helper_set_config, - .page_flip = drm_atomic_helper_page_flip, -diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c -index ce246b96330b..c8471bd4abbb 100644 ---- a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c -+++ b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c -@@ -165,7 +165,7 @@ atmel_hlcdc_crtc_mode_valid(struct drm_crtc *c, - } - - static void atmel_hlcdc_crtc_atomic_disable(struct drm_crtc *c, -- struct drm_crtc_state *old_state) -+ struct drm_atomic_state *state) - { - struct drm_device *dev = c->dev; - struct atmel_hlcdc_crtc *crtc = drm_crtc_to_atmel_hlcdc_crtc(c); -@@ -200,7 +200,7 @@ static void atmel_hlcdc_crtc_atomic_disable(struct drm_crtc *c, - } - - static void atmel_hlcdc_crtc_atomic_enable(struct drm_crtc *c, -- struct drm_crtc_state *old_state) -+ struct drm_atomic_state *state) - { - struct drm_device *dev = c->dev; - struct atmel_hlcdc_crtc *crtc = drm_crtc_to_atmel_hlcdc_crtc(c); -@@ -325,8 +325,9 @@ static int atmel_hlcdc_crtc_select_output_mode(struct drm_crtc_state *state) - } - - static int atmel_hlcdc_crtc_atomic_check(struct drm_crtc *c, -- struct drm_crtc_state *s) -+ struct drm_atomic_state *state) - { -+ struct drm_crtc_state *s = drm_atomic_get_new_crtc_state(state, c); - int ret; - - ret = atmel_hlcdc_crtc_select_output_mode(s); -@@ -341,7 +342,7 @@ static int atmel_hlcdc_crtc_atomic_check(struct drm_crtc *c, - } - - static void atmel_hlcdc_crtc_atomic_begin(struct drm_crtc *c, -- struct drm_crtc_state *old_s) -+ struct drm_atomic_state *state) - { - struct atmel_hlcdc_crtc *crtc = drm_crtc_to_atmel_hlcdc_crtc(c); - -@@ -356,7 +357,7 @@ static void atmel_hlcdc_crtc_atomic_begin(struct drm_crtc *c, - } - - static void atmel_hlcdc_crtc_atomic_flush(struct drm_crtc *crtc, -- struct drm_crtc_state *old_s) -+ struct drm_atomic_state *state) - { - /* TODO: write common plane control register if available */ - } -@@ -472,7 +473,6 @@ static const struct drm_crtc_funcs atmel_hlcdc_crtc_funcs = { - .atomic_destroy_state = atmel_hlcdc_crtc_destroy_state, - .enable_vblank = atmel_hlcdc_crtc_enable_vblank, - .disable_vblank = atmel_hlcdc_crtc_disable_vblank, -- .gamma_set = drm_atomic_helper_legacy_gamma_set, - }; - - int atmel_hlcdc_crtc_create(struct drm_device *dev) -diff --git a/drivers/gpu/drm/bridge/panel.c b/drivers/gpu/drm/bridge/panel.c -index c916f4b8907e..a63d6d238e3c 100644 ---- a/drivers/gpu/drm/bridge/panel.c -+++ b/drivers/gpu/drm/bridge/panel.c -@@ -79,6 +79,10 @@ static int panel_bridge_attach(struct drm_bridge *bridge, - return ret; - } - -+ /* set up connector's "panel orientation" property */ -+ drm_connector_set_panel_orientation(&panel_bridge->connector, -+ panel_bridge->panel->orientation); -+ - drm_connector_attach_encoder(&panel_bridge->connector, - bridge->encoder); - -diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c -index 29c0eb4bd754..f7830acb45ea 100644 ---- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c -+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c -@@ -2403,21 +2403,6 @@ static int dw_hdmi_connector_get_modes(struct drm_connector *connector) - return ret; - } - --static bool hdr_metadata_equal(const struct drm_connector_state *old_state, -- const struct drm_connector_state *new_state) --{ -- struct drm_property_blob *old_blob = old_state->hdr_output_metadata; -- struct drm_property_blob *new_blob = new_state->hdr_output_metadata; -- -- if (!old_blob || !new_blob) -- return old_blob == new_blob; -- -- if (old_blob->length != new_blob->length) -- return false; -- -- return !memcmp(old_blob->data, new_blob->data, old_blob->length); --} -- - static int dw_hdmi_connector_atomic_check(struct drm_connector *connector, - struct drm_atomic_state *state) - { -@@ -2431,7 +2416,7 @@ static int dw_hdmi_connector_atomic_check(struct drm_connector *connector, - if (!crtc) - return 0; - -- if (!hdr_metadata_equal(old_state, new_state)) { -+ if (!drm_connector_atomic_hdr_metadata_equal(old_state, new_state)) { - crtc_state = drm_atomic_get_crtc_state(state, crtc); - if (IS_ERR(crtc_state)) - return PTR_ERR(crtc_state); -@@ -2500,8 +2485,7 @@ static int dw_hdmi_connector_create(struct dw_hdmi *hdmi) - drm_connector_attach_max_bpc_property(connector, 8, 16); - - if (hdmi->version >= 0x200a && hdmi->plat_data->use_drm_infoframe) -- drm_object_attach_property(&connector->base, -- connector->dev->mode_config.hdr_output_metadata_property, 0); -+ drm_connector_attach_hdr_output_metadata_property(connector); - - drm_connector_attach_encoder(connector, hdmi->bridge.encoder); - diff --git a/drivers/gpu/drm/drm_atomic_helper.c b/drivers/gpu/drm/drm_atomic_helper.c -index 8a871e5c3e26..95addc0070ac 100644 +index 554d4468aa7c..d759c5ebd410 100644 --- a/drivers/gpu/drm/drm_atomic_helper.c +++ b/drivers/gpu/drm/drm_atomic_helper.c -@@ -122,7 +122,8 @@ static int handle_conflicting_encoders(struct drm_atomic_state *state, - continue; - - if (funcs->atomic_best_encoder) -- new_encoder = funcs->atomic_best_encoder(connector, new_conn_state); -+ new_encoder = funcs->atomic_best_encoder(connector, -+ state); - else if (funcs->best_encoder) - new_encoder = funcs->best_encoder(connector); - else -@@ -345,8 +346,7 @@ update_connector_routing(struct drm_atomic_state *state, - funcs = connector->helper_private; - - if (funcs->atomic_best_encoder) -- new_encoder = funcs->atomic_best_encoder(connector, -- new_connector_state); -+ new_encoder = funcs->atomic_best_encoder(connector, state); - else if (funcs->best_encoder) - new_encoder = funcs->best_encoder(connector); - else -@@ -430,6 +430,11 @@ mode_fixup(struct drm_atomic_state *state) +@@ -443,6 +443,11 @@ mode_fixup(struct drm_atomic_state *state) new_crtc_state = drm_atomic_get_new_crtc_state(state, new_conn_state->crtc); @@ -52975,4057 +73456,1039 @@ index 8a871e5c3e26..95addc0070ac 100644 /* * Each encoder has at most one connector (since we always steal * it away), so we won't call ->mode_fixup twice. -@@ -918,7 +923,7 @@ drm_atomic_helper_check_planes(struct drm_device *dev, - if (!funcs || !funcs->atomic_check) - continue; - -- ret = funcs->atomic_check(crtc, new_crtc_state); -+ ret = funcs->atomic_check(crtc, state); - if (ret) { - DRM_DEBUG_ATOMIC("[CRTC:%d:%s] atomic driver check failed\n", - crtc->base.id, crtc->name); -@@ -1093,7 +1098,7 @@ disable_outputs(struct drm_device *dev, struct drm_atomic_state *old_state) - if (new_crtc_state->enable && funcs->prepare) - funcs->prepare(crtc); - else if (funcs->atomic_disable) -- funcs->atomic_disable(crtc, old_crtc_state); -+ funcs->atomic_disable(crtc, old_state); - else if (funcs->disable) - funcs->disable(crtc); - else if (funcs->dpms) -@@ -1313,7 +1318,7 @@ static void drm_atomic_helper_commit_writebacks(struct drm_device *dev, - - if (new_conn_state->writeback_job && new_conn_state->writeback_job->fb) { - WARN_ON(connector->connector_type != DRM_MODE_CONNECTOR_WRITEBACK); -- funcs->atomic_commit(connector, new_conn_state); -+ funcs->atomic_commit(connector, old_state); - } - } - } -@@ -1358,7 +1363,7 @@ void drm_atomic_helper_commit_modeset_enables(struct drm_device *dev, - DRM_DEBUG_ATOMIC("enabling [CRTC:%d:%s]\n", - crtc->base.id, crtc->name); - if (funcs->atomic_enable) -- funcs->atomic_enable(crtc, old_crtc_state); -+ funcs->atomic_enable(crtc, old_state); - else if (funcs->commit) - funcs->commit(crtc); - } -@@ -2034,6 +2039,9 @@ crtc_or_fake_commit(struct drm_atomic_state *state, struct drm_crtc *crtc) - * should always call this function from their - * &drm_mode_config_funcs.atomic_commit hook. - * -+ * Drivers that need to extend the commit setup to private objects can use the -+ * &drm_mode_config_helper_funcs.atomic_commit_setup hook. -+ * - * To be able to use this support drivers need to use a few more helper - * functions. drm_atomic_helper_wait_for_dependencies() must be called before - * actually committing the hardware state, and for nonblocking commits this call -@@ -2077,8 +2085,11 @@ int drm_atomic_helper_setup_commit(struct drm_atomic_state *state, - struct drm_plane *plane; - struct drm_plane_state *old_plane_state, *new_plane_state; - struct drm_crtc_commit *commit; -+ const struct drm_mode_config_helper_funcs *funcs; +@@ -1648,13 +1653,6 @@ drm_atomic_helper_wait_for_vblanks(struct drm_device *dev, int i, ret; + unsigned int crtc_mask = 0; -+ funcs = state->dev->mode_config.helper_private; -+ - for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { - commit = kzalloc(sizeof(*commit), GFP_KERNEL); - if (!commit) -@@ -2155,6 +2166,9 @@ int drm_atomic_helper_setup_commit(struct drm_atomic_state *state, - new_plane_state->commit = drm_crtc_commit_get(commit); +- /* +- * Legacy cursor ioctls are completely unsynced, and userspace +- * relies on that (by doing tons of cursor updates). +- */ +- if (old_state->legacy_cursor_update) +- return; +- + for_each_oldnew_crtc_in_state(old_state, crtc, old_crtc_state, new_crtc_state, i) { + if (!new_crtc_state->active) + continue; +@@ -2305,12 +2303,6 @@ int drm_atomic_helper_setup_commit(struct drm_atomic_state *state, + continue; + } + +- /* Legacy cursor updates are fully unsynced. */ +- if (state->legacy_cursor_update) { +- complete_all(&commit->flip_done); +- continue; +- } +- + if (!new_crtc_state->event) { + commit->event = kzalloc(sizeof(*commit->event), + GFP_KERNEL); +diff --git a/drivers/gpu/drm/drm_atomic_state_helper.c b/drivers/gpu/drm/drm_atomic_state_helper.c +index 784e63d70a42..d7c761d9fb72 100644 +--- a/drivers/gpu/drm/drm_atomic_state_helper.c ++++ b/drivers/gpu/drm/drm_atomic_state_helper.c +@@ -267,6 +267,20 @@ void __drm_atomic_helper_plane_state_reset(struct drm_plane_state *plane_state, + plane_state->color_range = val; } -+ if (funcs && funcs->atomic_commit_setup) -+ return funcs->atomic_commit_setup(state); ++ if (plane->chroma_siting_h_property) { ++ if (!drm_object_property_get_default_value(&plane->base, ++ plane->chroma_siting_h_property, ++ &val)) ++ plane_state->chroma_siting_h = val; ++ } ++ ++ if (plane->chroma_siting_v_property) { ++ if (!drm_object_property_get_default_value(&plane->base, ++ plane->chroma_siting_v_property, ++ &val)) ++ plane_state->chroma_siting_v = val; ++ } ++ + if (plane->zpos_property) { + if (!drm_object_property_get_default_value(&plane->base, + plane->zpos_property, +diff --git a/drivers/gpu/drm/drm_atomic_uapi.c b/drivers/gpu/drm/drm_atomic_uapi.c +index 98d3b10c08ae..1e7c35b36a39 100644 +--- a/drivers/gpu/drm/drm_atomic_uapi.c ++++ b/drivers/gpu/drm/drm_atomic_uapi.c +@@ -580,6 +580,10 @@ static int drm_atomic_plane_set_property(struct drm_plane *plane, + state->color_encoding = val; + } else if (property == plane->color_range_property) { + state->color_range = val; ++ } else if (property == plane->chroma_siting_h_property) { ++ state->chroma_siting_h = val; ++ } else if (property == plane->chroma_siting_v_property) { ++ state->chroma_siting_v = val; + } else if (property == config->prop_fb_damage_clips) { + ret = drm_atomic_replace_property_blob_from_id(dev, + &state->fb_damage_clips, +@@ -646,6 +650,10 @@ drm_atomic_plane_get_property(struct drm_plane *plane, + *val = state->color_encoding; + } else if (property == plane->color_range_property) { + *val = state->color_range; ++ } else if (property == plane->chroma_siting_h_property) { ++ *val = state->chroma_siting_h; ++ } else if (property == plane->chroma_siting_v_property) { ++ *val = state->chroma_siting_v; + } else if (property == config->prop_fb_damage_clips) { + *val = (state->fb_damage_clips) ? + state->fb_damage_clips->base.id : 0; +@@ -693,6 +701,7 @@ static int drm_atomic_connector_set_property(struct drm_connector *connector, + { + struct drm_device *dev = connector->dev; + struct drm_mode_config *config = &dev->mode_config; ++ bool margins_updated = false; + bool replaced = false; + int ret; + +@@ -721,12 +730,16 @@ static int drm_atomic_connector_set_property(struct drm_connector *connector, + state->tv.subconnector = val; + } else if (property == config->tv_left_margin_property) { + state->tv.margins.left = val; ++ margins_updated = true; + } else if (property == config->tv_right_margin_property) { + state->tv.margins.right = val; ++ margins_updated = true; + } else if (property == config->tv_top_margin_property) { + state->tv.margins.top = val; ++ margins_updated = true; + } else if (property == config->tv_bottom_margin_property) { + state->tv.margins.bottom = val; ++ margins_updated = true; + } else if (property == config->legacy_tv_mode_property) { + state->tv.legacy_mode = val; + } else if (property == config->tv_mode_property) { +@@ -809,6 +822,12 @@ static int drm_atomic_connector_set_property(struct drm_connector *connector, + return -EINVAL; + } + ++ if (margins_updated && state->crtc) { ++ ret = drm_atomic_add_affected_planes(state->state, state->crtc); ++ ++ return ret; ++ } + return 0; } - EXPORT_SYMBOL(drm_atomic_helper_setup_commit); -@@ -2507,7 +2521,7 @@ void drm_atomic_helper_commit_planes(struct drm_device *dev, - if (active_only && !new_crtc_state->active) - continue; -- funcs->atomic_begin(crtc, old_crtc_state); -+ funcs->atomic_begin(crtc, old_state); - } - - for_each_oldnew_plane_in_state(old_state, plane, old_plane_state, new_plane_state, i) { -@@ -2565,7 +2579,7 @@ void drm_atomic_helper_commit_planes(struct drm_device *dev, - if (active_only && !new_crtc_state->active) - continue; - -- funcs->atomic_flush(crtc, old_crtc_state); -+ funcs->atomic_flush(crtc, old_state); - } - } - EXPORT_SYMBOL(drm_atomic_helper_commit_planes); -@@ -2603,7 +2617,7 @@ drm_atomic_helper_commit_planes_on_crtc(struct drm_crtc_state *old_crtc_state) - - crtc_funcs = crtc->helper_private; - if (crtc_funcs && crtc_funcs->atomic_begin) -- crtc_funcs->atomic_begin(crtc, old_crtc_state); -+ crtc_funcs->atomic_begin(crtc, old_state); - - drm_for_each_plane_mask(plane, crtc->dev, plane_mask) { - struct drm_plane_state *old_plane_state = -@@ -2629,7 +2643,7 @@ drm_atomic_helper_commit_planes_on_crtc(struct drm_crtc_state *old_crtc_state) - } - - if (crtc_funcs && crtc_funcs->atomic_flush) -- crtc_funcs->atomic_flush(crtc, old_crtc_state); -+ crtc_funcs->atomic_flush(crtc, old_state); - } - EXPORT_SYMBOL(drm_atomic_helper_commit_planes_on_crtc); - -@@ -3485,76 +3499,6 @@ int drm_atomic_helper_page_flip_target(struct drm_crtc *crtc, - } - EXPORT_SYMBOL(drm_atomic_helper_page_flip_target); - --/** -- * drm_atomic_helper_legacy_gamma_set - set the legacy gamma correction table -- * @crtc: CRTC object -- * @red: red correction table -- * @green: green correction table -- * @blue: green correction table -- * @size: size of the tables -- * @ctx: lock acquire context -- * -- * Implements support for legacy gamma correction table for drivers -- * that support color management through the DEGAMMA_LUT/GAMMA_LUT -- * properties. See drm_crtc_enable_color_mgmt() and the containing chapter for -- * how the atomic color management and gamma tables work. -- */ --int drm_atomic_helper_legacy_gamma_set(struct drm_crtc *crtc, -- u16 *red, u16 *green, u16 *blue, -- uint32_t size, -- struct drm_modeset_acquire_ctx *ctx) --{ -- struct drm_device *dev = crtc->dev; -- struct drm_atomic_state *state; -- struct drm_crtc_state *crtc_state; -- struct drm_property_blob *blob = NULL; -- struct drm_color_lut *blob_data; -- int i, ret = 0; -- bool replaced; -- -- state = drm_atomic_state_alloc(crtc->dev); -- if (!state) -- return -ENOMEM; -- -- blob = drm_property_create_blob(dev, -- sizeof(struct drm_color_lut) * size, -- NULL); -- if (IS_ERR(blob)) { -- ret = PTR_ERR(blob); -- blob = NULL; -- goto fail; -- } -- -- /* Prepare GAMMA_LUT with the legacy values. */ -- blob_data = blob->data; -- for (i = 0; i < size; i++) { -- blob_data[i].red = red[i]; -- blob_data[i].green = green[i]; -- blob_data[i].blue = blue[i]; -- } -- -- state->acquire_ctx = ctx; -- crtc_state = drm_atomic_get_crtc_state(state, crtc); -- if (IS_ERR(crtc_state)) { -- ret = PTR_ERR(crtc_state); -- goto fail; -- } -- -- /* Reset DEGAMMA_LUT and CTM properties. */ -- replaced = drm_property_replace_blob(&crtc_state->degamma_lut, NULL); -- replaced |= drm_property_replace_blob(&crtc_state->ctm, NULL); -- replaced |= drm_property_replace_blob(&crtc_state->gamma_lut, blob); -- crtc_state->color_mgmt_changed |= replaced; -- -- ret = drm_atomic_commit(state); -- --fail: -- drm_atomic_state_put(state); -- drm_property_blob_put(blob); -- return ret; --} --EXPORT_SYMBOL(drm_atomic_helper_legacy_gamma_set); -- - /** - * drm_atomic_helper_bridge_propagate_bus_fmt() - Propagate output format to - * the input end of a bridge diff --git a/drivers/gpu/drm/drm_color_mgmt.c b/drivers/gpu/drm/drm_color_mgmt.c -index 138ff34b31db..78933e2a5f44 100644 +index d021497841b8..973c6aeff8a1 100644 --- a/drivers/gpu/drm/drm_color_mgmt.c +++ b/drivers/gpu/drm/drm_color_mgmt.c -@@ -22,6 +22,7 @@ - - #include - -+#include - #include - #include - #include -@@ -89,9 +90,8 @@ - * modes) appropriately. - * - * There is also support for a legacy gamma table, which is set up by calling -- * drm_mode_crtc_set_gamma_size(). Drivers which support both should use -- * drm_atomic_helper_legacy_gamma_set() to alias the legacy gamma ramp with the -- * "GAMMA_LUT" property above. -+ * drm_mode_crtc_set_gamma_size(). The DRM core will then alias the legacy gamma -+ * ramp with "GAMMA_LUT". - * - * Support for different non RGB color encodings is controlled through - * &drm_plane specific COLOR_ENCODING and COLOR_RANGE properties. They -@@ -156,9 +156,6 @@ EXPORT_SYMBOL(drm_color_ctm_s31_32_to_qm_n); - * optional. The gamma and degamma properties are only attached if - * their size is not 0 and ctm_property is only attached if has_ctm is - * true. -- * -- * Drivers should use drm_atomic_helper_legacy_gamma_set() to implement the -- * legacy &drm_crtc_funcs.gamma_set callback. - */ - void drm_crtc_enable_color_mgmt(struct drm_crtc *crtc, - uint degamma_lut_size, -@@ -231,6 +228,105 @@ int drm_mode_crtc_set_gamma_size(struct drm_crtc *crtc, - } - EXPORT_SYMBOL(drm_mode_crtc_set_gamma_size); - -+/** -+ * drm_crtc_supports_legacy_gamma - does the crtc support legacy gamma correction table -+ * @crtc: CRTC object -+ * -+ * Returns true/false if the given crtc supports setting the legacy gamma -+ * correction table. -+ */ -+static bool drm_crtc_supports_legacy_gamma(struct drm_crtc *crtc) -+{ -+ u32 gamma_id = crtc->dev->mode_config.gamma_lut_property->base.id; -+ -+ if (!crtc->gamma_size) -+ return false; -+ -+ if (crtc->funcs->gamma_set) -+ return true; -+ -+ return !!drm_mode_obj_find_prop_id(&crtc->base, gamma_id); -+} -+ -+/** -+ * drm_crtc_legacy_gamma_set - set the legacy gamma correction table -+ * @crtc: CRTC object -+ * @red: red correction table -+ * @green: green correction table -+ * @blue: green correction table -+ * @size: size of the tables -+ * @ctx: lock acquire context -+ * -+ * Implements support for legacy gamma correction table for drivers -+ * that have set drm_crtc_funcs.gamma_set or that support color management -+ * through the DEGAMMA_LUT/GAMMA_LUT properties. See -+ * drm_crtc_enable_color_mgmt() and the containing chapter for -+ * how the atomic color management and gamma tables work. -+ * -+ * This function sets the gamma using drm_crtc_funcs.gamma_set if set, or -+ * alternatively using crtc color management properties. -+ */ -+static int drm_crtc_legacy_gamma_set(struct drm_crtc *crtc, -+ u16 *red, u16 *green, u16 *blue, -+ u32 size, -+ struct drm_modeset_acquire_ctx *ctx) -+{ -+ struct drm_device *dev = crtc->dev; -+ struct drm_atomic_state *state; -+ struct drm_crtc_state *crtc_state; -+ struct drm_property_blob *blob; -+ struct drm_color_lut *blob_data; -+ int i, ret = 0; -+ bool replaced; -+ -+ if (crtc->funcs->gamma_set) -+ return crtc->funcs->gamma_set(crtc, red, green, blue, size, ctx); -+ -+ state = drm_atomic_state_alloc(crtc->dev); -+ if (!state) -+ return -ENOMEM; -+ -+ blob = drm_property_create_blob(dev, -+ sizeof(struct drm_color_lut) * size, -+ NULL); -+ if (IS_ERR(blob)) { -+ ret = PTR_ERR(blob); -+ blob = NULL; -+ goto fail; -+ } -+ -+ /* Prepare GAMMA_LUT with the legacy values. */ -+ blob_data = blob->data; -+ for (i = 0; i < size; i++) { -+ blob_data[i].red = red[i]; -+ blob_data[i].green = green[i]; -+ blob_data[i].blue = blue[i]; -+ } -+ -+ state->acquire_ctx = ctx; -+ crtc_state = drm_atomic_get_crtc_state(state, crtc); -+ if (IS_ERR(crtc_state)) { -+ ret = PTR_ERR(crtc_state); -+ goto fail; -+ } -+ -+ /* Set GAMMA_LUT and reset DEGAMMA_LUT and CTM */ -+ replaced = drm_property_replace_blob(&crtc_state->degamma_lut, NULL); -+ replaced |= drm_property_replace_blob(&crtc_state->ctm, NULL); +@@ -330,7 +330,9 @@ static int drm_crtc_legacy_gamma_set(struct drm_crtc *crtc, + replaced = drm_property_replace_blob(&crtc_state->degamma_lut, + use_gamma_lut ? NULL : blob); + replaced |= drm_property_replace_blob(&crtc_state->ctm, NULL); +- replaced |= drm_property_replace_blob(&crtc_state->gamma_lut, + if (!crtc_state->gamma_lut || !crtc_state->gamma_lut->data || + memcmp(crtc_state->gamma_lut->data, blob_data, blob->length)) -+ replaced |= drm_property_replace_blob(&crtc_state->gamma_lut, blob); ++ replaced |= drm_property_replace_blob(&crtc_state->gamma_lut, + use_gamma_lut ? blob : NULL); + crtc_state->color_mgmt_changed |= replaced; + +@@ -588,6 +590,42 @@ int drm_plane_create_color_properties(struct drm_plane *plane, + } + EXPORT_SYMBOL(drm_plane_create_color_properties); + ++/** ++ * drm_plane_create_chroma_siting_properties - chroma siting related plane properties ++ * @plane: plane object ++ * ++ * Create and attach plane specific CHROMA_SITING ++ * properties to @plane. ++ */ ++int drm_plane_create_chroma_siting_properties(struct drm_plane *plane, ++ int32_t default_chroma_siting_h, ++ int32_t default_chroma_siting_v) ++{ ++ struct drm_device *dev = plane->dev; ++ struct drm_property *prop; + -+ crtc_state->color_mgmt_changed |= replaced; ++ prop = drm_property_create_range(dev, 0, "CHROMA_SITING_H", ++ 0, 1<<16); ++ if (!prop) ++ return -ENOMEM; ++ plane->chroma_siting_h_property = prop; ++ drm_object_attach_property(&plane->base, prop, default_chroma_siting_h); + -+ ret = drm_atomic_commit(state); ++ prop = drm_property_create_range(dev, 0, "CHROMA_SITING_V", ++ 0, 1<<16); ++ if (!prop) ++ return -ENOMEM; ++ plane->chroma_siting_v_property = prop; ++ drm_object_attach_property(&plane->base, prop, default_chroma_siting_v); + -+fail: -+ drm_atomic_state_put(state); -+ drm_property_blob_put(blob); -+ return ret; ++ if (plane->state) { ++ plane->state->chroma_siting_h = default_chroma_siting_h; ++ plane->state->chroma_siting_v = default_chroma_siting_v; ++ } ++ return 0; +} ++EXPORT_SYMBOL(drm_plane_create_chroma_siting_properties); + /** - * drm_mode_gamma_set_ioctl - set the gamma table - * @dev: DRM device -@@ -262,7 +358,7 @@ int drm_mode_gamma_set_ioctl(struct drm_device *dev, - if (!crtc) - return -ENOENT; - -- if (crtc->funcs->gamma_set == NULL) -+ if (!drm_crtc_supports_legacy_gamma(crtc)) - return -ENOSYS; - - /* memcpy into gamma store */ -@@ -290,8 +386,8 @@ int drm_mode_gamma_set_ioctl(struct drm_device *dev, - goto out; - } - -- ret = crtc->funcs->gamma_set(crtc, r_base, g_base, b_base, -- crtc->gamma_size, &ctx); -+ ret = drm_crtc_legacy_gamma_set(crtc, r_base, g_base, b_base, -+ crtc->gamma_size, &ctx); - - out: - DRM_MODESET_LOCK_ALL_END(dev, ctx, ret); + * drm_color_lut_check - check validity of lookup table + * @lut: property blob containing LUT to check diff --git a/drivers/gpu/drm/drm_connector.c b/drivers/gpu/drm/drm_connector.c -index 717c4e7271b0..c0beaa2ea6ee 100644 +index c44d5bcf1284..75ce5af3502b 100644 --- a/drivers/gpu/drm/drm_connector.c +++ b/drivers/gpu/drm/drm_connector.c -@@ -94,6 +94,7 @@ static struct drm_conn_prop_enum_list drm_connector_enum_list[] = { - { DRM_MODE_CONNECTOR_DPI, "DPI" }, - { DRM_MODE_CONNECTOR_WRITEBACK, "Writeback" }, - { DRM_MODE_CONNECTOR_SPI, "SPI" }, -+ { DRM_MODE_CONNECTOR_USB, "USB" }, +@@ -33,6 +33,7 @@ + #include + #include + ++#include + #include + #include + +@@ -83,6 +84,7 @@ struct drm_conn_prop_enum_list { + int type; + const char *name; + struct ida ida; ++ int first_dyn_num; }; + /* +@@ -112,12 +114,41 @@ static struct drm_conn_prop_enum_list drm_connector_enum_list[] = { + { DRM_MODE_CONNECTOR_USB, "USB" }, + }; + ++#define MAX_DT_NODE_NAME_LEN 20 ++#define DT_DRM_NODE_PREFIX "drm-" ++ ++static void drm_connector_get_of_name(int type, char *node_name, int length) ++{ ++ int i = 0; ++ ++ strcpy(node_name, DT_DRM_NODE_PREFIX); ++ ++ do { ++ node_name[i + strlen(DT_DRM_NODE_PREFIX)] = ++ tolower(drm_connector_enum_list[type].name[i]); ++ ++ } while (drm_connector_enum_list[type].name[i++] && ++ i < length); ++ ++ node_name[length - 1] = '\0'; ++} ++ void drm_connector_ida_init(void) -@@ -2143,6 +2144,75 @@ int drm_connector_attach_max_bpc_property(struct drm_connector *connector, - } - EXPORT_SYMBOL(drm_connector_attach_max_bpc_property); - -+/** -+ * drm_connector_attach_hdr_output_metadata_property - attach "HDR_OUTPUT_METADA" property -+ * @connector: connector to attach the property on. -+ * -+ * This is used to allow the userspace to send HDR Metadata to the -+ * driver. -+ * -+ * Returns: -+ * Zero on success, negative errno on failure. -+ */ -+int drm_connector_attach_hdr_output_metadata_property(struct drm_connector *connector) -+{ -+ struct drm_device *dev = connector->dev; -+ struct drm_property *prop = dev->mode_config.hdr_output_metadata_property; -+ -+ drm_object_attach_property(&connector->base, prop, 0); -+ -+ return 0; -+} -+EXPORT_SYMBOL(drm_connector_attach_hdr_output_metadata_property); -+ -+/** -+ * drm_connector_attach_colorspace_property - attach "Colorspace" property -+ * @connector: connector to attach the property on. -+ * -+ * This is used to allow the userspace to signal the output colorspace -+ * to the driver. -+ * -+ * Returns: -+ * Zero on success, negative errno on failure. -+ */ -+int drm_connector_attach_colorspace_property(struct drm_connector *connector) -+{ -+ struct drm_property *prop = connector->colorspace_property; -+ -+ drm_object_attach_property(&connector->base, prop, DRM_MODE_COLORIMETRY_DEFAULT); -+ -+ return 0; -+} -+EXPORT_SYMBOL(drm_connector_attach_colorspace_property); -+ -+/** -+ * drm_connector_atomic_hdr_metadata_equal - checks if the hdr metadata changed -+ * @old_state: old connector state to compare -+ * @new_state: new connector state to compare -+ * -+ * This is used by HDR-enabled drivers to test whether the HDR metadata -+ * have changed between two different connector state (and thus probably -+ * requires a full blown mode change). -+ * -+ * Returns: -+ * True if the metadata are equal, False otherwise -+ */ -+bool drm_connector_atomic_hdr_metadata_equal(struct drm_connector_state *old_state, -+ struct drm_connector_state *new_state) -+{ -+ struct drm_property_blob *old_blob = old_state->hdr_output_metadata; -+ struct drm_property_blob *new_blob = new_state->hdr_output_metadata; -+ -+ if (!old_blob || !new_blob) -+ return old_blob == new_blob; -+ -+ if (old_blob->length != new_blob->length) -+ return false; -+ -+ return !memcmp(old_blob->data, new_blob->data, old_blob->length); -+} -+EXPORT_SYMBOL(drm_connector_atomic_hdr_metadata_equal); -+ - /** - * drm_connector_set_vrr_capable_property - sets the variable refresh rate - * capable property for a connector -diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c -index add317bd8d55..46e41ad5e44f 100644 ---- a/drivers/gpu/drm/drm_edid.c -+++ b/drivers/gpu/drm/drm_edid.c -@@ -4961,10 +4961,9 @@ static void drm_parse_hdmi_deep_color_info(struct drm_connector *connector, - - /* - * Deep color support mandates RGB444 support for all video -- * modes and forbids YCRCB422 support for all video modes per -- * HDMI 1.3 spec. -+ * modes. - */ -- info->color_formats = DRM_COLOR_FORMAT_RGB444; -+ info->color_formats |= DRM_COLOR_FORMAT_RGB444; - - /* YCRCB444 is optional according to spec. */ - if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) { -@@ -5712,13 +5711,13 @@ static const u32 hdmi_colorimetry_val[] = { - #undef ACE - - /** -- * drm_hdmi_avi_infoframe_colorspace() - fill the HDMI AVI infoframe -- * colorspace information -+ * drm_hdmi_avi_infoframe_colorimetry() - fill the HDMI AVI infoframe -+ * colorimetry information - * @frame: HDMI AVI infoframe - * @conn_state: connector state - */ - void --drm_hdmi_avi_infoframe_colorspace(struct hdmi_avi_infoframe *frame, -+drm_hdmi_avi_infoframe_colorimetry(struct hdmi_avi_infoframe *frame, - const struct drm_connector_state *conn_state) { - u32 colorimetry_val; -@@ -5737,7 +5736,7 @@ drm_hdmi_avi_infoframe_colorspace(struct hdmi_avi_infoframe *frame, - frame->extended_colorimetry = (colorimetry_val >> 2) & - EXTENDED_COLORIMETRY_MASK; - } --EXPORT_SYMBOL(drm_hdmi_avi_infoframe_colorspace); -+EXPORT_SYMBOL(drm_hdmi_avi_infoframe_colorimetry); +- int i; ++ int i, id; ++ char node_name[MAX_DT_NODE_NAME_LEN]; - /** - * drm_hdmi_avi_infoframe_quant_range() - fill the HDMI AVI infoframe -diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c -index 722c7ebe4e88..bdc7c605f43e 100644 ---- a/drivers/gpu/drm/drm_fourcc.c -+++ b/drivers/gpu/drm/drm_fourcc.c -@@ -286,6 +286,9 @@ const struct drm_format_info *__drm_format_info(u32 format) - .num_planes = 3, .char_per_block = { 2, 2, 2 }, - .block_w = { 1, 1, 1 }, .block_h = { 1, 1, 1 }, .hsub = 0, - .vsub = 0, .is_yuv = true }, -+ { .format = DRM_FORMAT_P030, .depth = 0, .num_planes = 2, -+ .char_per_block = { 4, 4, 0 }, .block_w = { 3, 0, 0 }, .block_h = { 1, 0, 0 }, -+ .hsub = 2, .vsub = 2, .is_yuv = true}, - }; - - unsigned int i; -diff --git a/drivers/gpu/drm/drm_framebuffer.c b/drivers/gpu/drm/drm_framebuffer.c -index 2f5b0c2bb0fe..89ced6af9c5c 100644 ---- a/drivers/gpu/drm/drm_framebuffer.c -+++ b/drivers/gpu/drm/drm_framebuffer.c -@@ -217,12 +217,16 @@ static int framebuffer_check(struct drm_device *dev, - if (min_pitch > UINT_MAX) - return -ERANGE; - -- if ((uint64_t) height * r->pitches[i] + r->offsets[i] > UINT_MAX) -- return -ERANGE; -- -- if (block_size && r->pitches[i] < min_pitch) { -- DRM_DEBUG_KMS("bad pitch %u for plane %d\n", r->pitches[i], i); -- return -EINVAL; -+ if (r->modifier[i] == DRM_FORMAT_MOD_LINEAR) { -+ if ((uint64_t)height * r->pitches[i] + r->offsets[i] > -+ UINT_MAX) -+ return -ERANGE; +- for (i = 0; i < ARRAY_SIZE(drm_connector_enum_list); i++) ++ for (i = 0; i < ARRAY_SIZE(drm_connector_enum_list); i++) { + ida_init(&drm_connector_enum_list[i].ida); + -+ if (block_size && r->pitches[i] < min_pitch) { -+ DRM_DEBUG_KMS("bad pitch %u for plane %d\n", -+ r->pitches[i], i); -+ return -EINVAL; -+ } - } - - if (r->modifier[i] && !(r->flags & DRM_MODE_FB_MODIFIERS)) { -diff --git a/drivers/gpu/drm/drm_panel.c b/drivers/gpu/drm/drm_panel.c -index f634371c717a..bee5066e9227 100644 ---- a/drivers/gpu/drm/drm_panel.c -+++ b/drivers/gpu/drm/drm_panel.c -@@ -61,6 +61,9 @@ void drm_panel_init(struct drm_panel *panel, struct device *dev, - panel->dev = dev; - panel->funcs = funcs; - panel->connector_type = connector_type; ++ drm_connector_get_of_name(i, node_name, MAX_DT_NODE_NAME_LEN); + -+ panel->orientation = DRM_MODE_PANEL_ORIENTATION_UNKNOWN; -+ of_drm_get_panel_orientation(dev->of_node, &panel->orientation); ++ id = of_alias_get_highest_id(node_name); ++ if (id > 0) ++ drm_connector_enum_list[i].first_dyn_num = id + 1; ++ else ++ drm_connector_enum_list[i].first_dyn_num = 1; ++ } } - EXPORT_SYMBOL(drm_panel_init); -@@ -289,16 +292,18 @@ int of_drm_get_panel_orientation(const struct device_node *np, + void drm_connector_ida_destroy(void) +@@ -225,7 +256,9 @@ static int __drm_connector_init(struct drm_device *dev, + struct i2c_adapter *ddc) + { + struct drm_mode_config *config = &dev->mode_config; ++ char node_name[MAX_DT_NODE_NAME_LEN]; + int ret; ++ int id; + struct ida *connector_ida = + &drm_connector_enum_list[connector_type].ida; + +@@ -255,8 +288,28 @@ static int __drm_connector_init(struct drm_device *dev, + ret = 0; + + connector->connector_type = connector_type; +- connector->connector_type_id = +- ida_alloc_min(connector_ida, 1, GFP_KERNEL); ++ connector->connector_type_id = 0; ++ ++ drm_connector_get_of_name(connector_type, node_name, MAX_DT_NODE_NAME_LEN); ++ id = of_alias_get_id(dev->dev->of_node, node_name); ++ if (id > 0) { ++ /* Try and allocate the requested ID ++ * Valid range is 1 to 31, hence ignoring 0 as an error ++ */ ++ int type_id = ida_alloc_range(connector_ida, id, id, GFP_KERNEL); ++ ++ if (type_id > 0) ++ connector->connector_type_id = type_id; ++ else ++ drm_err(dev, "Failed to acquire type ID %d for interface type %s, ret %d\n", ++ id, drm_connector_enum_list[connector_type].name, ++ type_id); ++ } ++ if (!connector->connector_type_id) ++ connector->connector_type_id = ++ ida_alloc_min(connector_ida, ++ drm_connector_enum_list[connector_type].first_dyn_num, ++ GFP_KERNEL); + if (connector->connector_type_id < 0) { + ret = connector->connector_type_id; + goto out_put_id; +@@ -996,6 +1049,7 @@ static const struct drm_prop_enum_list drm_tv_mode_enum_list[] = { + { DRM_MODE_TV_MODE_PAL_M, "PAL-M" }, + { DRM_MODE_TV_MODE_PAL_N, "PAL-N" }, + { DRM_MODE_TV_MODE_SECAM, "SECAM" }, ++ { DRM_MODE_TV_MODE_MONOCHROME, "Mono" }, + }; + DRM_ENUM_NAME_FN(drm_get_tv_mode_name, drm_tv_mode_enum_list) + +@@ -1682,6 +1736,12 @@ EXPORT_SYMBOL(drm_connector_attach_dp_subconnector_property); + * TV Mode is CCIR System B (aka 625-lines) together with + * the SECAM Color Encoding. + * ++ * Mono: ++ * ++ * Use timings appropriate to the DRM mode, including ++ * equalizing pulses for a 525-line or 625-line mode, ++ * with no pedestal or color encoding. ++ * + * Drivers can set up this property by calling + * drm_mode_create_tv_properties(). + */ +diff --git a/drivers/gpu/drm/drm_fb_helper.c b/drivers/gpu/drm/drm_fb_helper.c +index d612133e2cf7..7d4ed1530ac2 100644 +--- a/drivers/gpu/drm/drm_fb_helper.c ++++ b/drivers/gpu/drm/drm_fb_helper.c +@@ -1837,7 +1837,7 @@ __drm_fb_helper_initial_config_and_unlock(struct drm_fb_helper *fb_helper) + struct drm_device *dev = fb_helper->dev; + struct fb_info *info; + unsigned int width, height; +- int ret; ++ int ret, id; + + width = dev->mode_config.max_width; + height = dev->mode_config.max_height; +@@ -1868,6 +1868,15 @@ __drm_fb_helper_initial_config_and_unlock(struct drm_fb_helper *fb_helper) + * register the fbdev emulation instance in kernel_fb_helper_list. */ + mutex_unlock(&fb_helper->lock); + ++ id = of_alias_get_highest_id("drm-fb"); ++ if (id >= 0) ++ fb_set_lowest_dynamic_fb(id + 1); ++ ++ id = of_alias_get_id(dev->dev->of_node, "drm-fb"); ++ if (id >= 0) { ++ info->node = id; ++ info->custom_fb_num = true; ++ } + ret = register_framebuffer(info); if (ret < 0) return ret; +diff --git a/drivers/gpu/drm/drm_modes.c b/drivers/gpu/drm/drm_modes.c +index ac9a406250c5..5a6d966f7ada 100644 +--- a/drivers/gpu/drm/drm_modes.c ++++ b/drivers/gpu/drm/drm_modes.c +@@ -530,7 +530,8 @@ static int fill_analog_mode(struct drm_device *dev, + * @interlace: whether to compute an interlaced mode + * + * This function creates a struct drm_display_mode instance suited for +- * an analog TV output, for one of the usual analog TV mode. ++ * an analog TV output, for one of the usual analog TV modes. Where ++ * this is DRM_MODE_TV_MODE_MONOCHROME, a 625-line mode will be created. + * + * Note that @hdisplay is larger than the usual constraints for the PAL + * and NTSC timings, and we'll choose to ignore most timings constraints +@@ -568,6 +569,8 @@ struct drm_display_mode *drm_analog_tv_mode(struct drm_device *dev, + case DRM_MODE_TV_MODE_PAL_N: + fallthrough; + case DRM_MODE_TV_MODE_SECAM: ++ fallthrough; ++ case DRM_MODE_TV_MODE_MONOCHROME: + analog = DRM_MODE_ANALOG_PAL; + break; -- if (rotation == 0) -+ if (rotation == 0) { - *orientation = DRM_MODE_PANEL_ORIENTATION_NORMAL; -- else if (rotation == 90) -+ } else if (rotation == 90) { - *orientation = DRM_MODE_PANEL_ORIENTATION_RIGHT_UP; -- else if (rotation == 180) -+ } else if (rotation == 180) { - *orientation = DRM_MODE_PANEL_ORIENTATION_BOTTOM_UP; -- else if (rotation == 270) -+ } else if (rotation == 270) { - *orientation = DRM_MODE_PANEL_ORIENTATION_LEFT_UP; -- else -+ } else { -+ DRM_ERROR("%pOF: invalid orientation %d\n", np, ret); - return -EINVAL; -+ } - - return 0; - } diff --git a/drivers/gpu/drm/drm_probe_helper.c b/drivers/gpu/drm/drm_probe_helper.c -index e5432dcf6999..f8eb1061a55f 100644 +index 3f479483d7d8..cb9c201250d5 100644 --- a/drivers/gpu/drm/drm_probe_helper.c +++ b/drivers/gpu/drm/drm_probe_helper.c -@@ -794,6 +794,84 @@ void drm_kms_helper_poll_fini(struct drm_device *dev) - } - EXPORT_SYMBOL(drm_kms_helper_poll_fini); +@@ -1247,8 +1247,9 @@ int drm_connector_helper_tv_get_modes(struct drm_connector *connector) + for (i = 0; i < tv_mode_property->num_values; i++) + supported_tv_modes |= BIT(tv_mode_property->values[i]); -+static bool -+_drm_connector_helper_hpd_irq_event(struct drm_connector *connector) -+{ -+ struct drm_device *dev = connector->dev; -+ enum drm_connector_status old_status; -+ u64 old_epoch_counter; -+ bool changed = false; -+ -+ /* Only handle HPD capable connectors. */ -+ drm_WARN_ON(dev, !(connector->polled & DRM_CONNECTOR_POLL_HPD)); -+ -+ drm_WARN_ON(dev, !mutex_is_locked(&dev->mode_config.mutex)); -+ -+ old_status = connector->status; -+ old_epoch_counter = connector->epoch_counter; -+ -+ DRM_DEBUG_KMS("[CONNECTOR:%d:%s] Old epoch counter %llu\n", -+ connector->base.id, -+ connector->name, -+ old_epoch_counter); -+ -+ connector->status = drm_helper_probe_detect(connector, NULL, -+ false); -+ DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %s to %s\n", -+ connector->base.id, -+ connector->name, -+ drm_get_connector_status_name(old_status), -+ drm_get_connector_status_name(connector->status)); -+ -+ DRM_DEBUG_KMS("[CONNECTOR:%d:%s] New epoch counter %llu\n", -+ connector->base.id, -+ connector->name, -+ connector->epoch_counter); -+ -+ /* -+ * Check if epoch counter had changed, meaning that we need -+ * to send a uevent. -+ */ -+ if (old_epoch_counter != connector->epoch_counter) -+ changed = true; -+ -+ return changed; -+} -+ -+/** -+ * drm_connector_helper_hpd_irq_event - hotplug processing -+ * @connector: drm_connector -+ * -+ * Drivers can use this helper function to run a detect cycle on a connector -+ * which has the DRM_CONNECTOR_POLL_HPD flag set in its &polled member. -+ * -+ * This helper function is useful for drivers which can track hotplug -+ * interrupts for a single connector. -+ * -+ * This function must be called from process context with no mode -+ * setting locks held. -+ * -+ * Note that a connector can be both polled and probed from the hotplug -+ * handler, in case the hotplug interrupt is known to be unreliable. -+ */ -+bool drm_connector_helper_hpd_irq_event(struct drm_connector *connector) -+{ -+ struct drm_device *dev = connector->dev; -+ bool changed; -+ -+ mutex_lock(&dev->mode_config.mutex); -+ changed = _drm_connector_helper_hpd_irq_event(connector); -+ mutex_unlock(&dev->mode_config.mutex); -+ -+ if (changed) { -+ drm_kms_helper_hotplug_event(dev); -+ DRM_DEBUG_KMS("Sent hotplug event\n"); -+ } -+ -+ return changed; -+} -+EXPORT_SYMBOL(drm_connector_helper_hpd_irq_event); -+ - /** - * drm_helper_hpd_irq_event - hotplug processing - * @dev: drm_device -@@ -821,9 +899,7 @@ bool drm_helper_hpd_irq_event(struct drm_device *dev) - { - struct drm_connector *connector; - struct drm_connector_list_iter conn_iter; -- enum drm_connector_status old_status; - bool changed = false; -- u64 old_epoch_counter; +- if ((supported_tv_modes & ntsc_modes) && +- (supported_tv_modes & pal_modes)) { ++ if (((supported_tv_modes & ntsc_modes) && ++ (supported_tv_modes & pal_modes)) || ++ (supported_tv_modes & BIT(DRM_MODE_TV_MODE_MONOCHROME))) { + uint64_t default_mode; - if (!dev->mode_config.poll_enabled) - return false; -@@ -831,37 +907,8 @@ bool drm_helper_hpd_irq_event(struct drm_device *dev) - mutex_lock(&dev->mode_config.mutex); - drm_connector_list_iter_begin(dev, &conn_iter); - drm_for_each_connector_iter(connector, &conn_iter) { -- /* Only handle HPD capable connectors. */ -- if (!(connector->polled & DRM_CONNECTOR_POLL_HPD)) -- continue; -- -- old_status = connector->status; -- -- old_epoch_counter = connector->epoch_counter; -- -- DRM_DEBUG_KMS("[CONNECTOR:%d:%s] Old epoch counter %llu\n", connector->base.id, -- connector->name, -- old_epoch_counter); -- -- connector->status = drm_helper_probe_detect(connector, NULL, false); -- DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %s to %s\n", -- connector->base.id, -- connector->name, -- drm_get_connector_status_name(old_status), -- drm_get_connector_status_name(connector->status)); -- -- DRM_DEBUG_KMS("[CONNECTOR:%d:%s] New epoch counter %llu\n", -- connector->base.id, -- connector->name, -- connector->epoch_counter); -- -- /* -- * Check if epoch counter had changed, meaning that we need -- * to send a uevent. -- */ -- if (old_epoch_counter != connector->epoch_counter) -+ if (_drm_connector_helper_hpd_irq_event(connector)) - changed = true; -- - } - drm_connector_list_iter_end(&conn_iter); - mutex_unlock(&dev->mode_config.mutex); -diff --git a/drivers/gpu/drm/drm_simple_kms_helper.c b/drivers/gpu/drm/drm_simple_kms_helper.c -index 74946690aba4..743e57c1b44f 100644 ---- a/drivers/gpu/drm/drm_simple_kms_helper.c -+++ b/drivers/gpu/drm/drm_simple_kms_helper.c -@@ -86,20 +86,22 @@ drm_simple_kms_crtc_mode_valid(struct drm_crtc *crtc, + if (drm_object_property_get_default_value(&connector->base, +diff --git a/drivers/gpu/drm/i915/display/intel_backlight.c b/drivers/gpu/drm/i915/display/intel_backlight.c +index 2e8f17c04522..ff9b9918b0a1 100644 +--- a/drivers/gpu/drm/i915/display/intel_backlight.c ++++ b/drivers/gpu/drm/i915/display/intel_backlight.c +@@ -274,7 +274,7 @@ static void ext_pwm_set_backlight(const struct drm_connector_state *conn_state, + struct intel_panel *panel = &to_intel_connector(conn_state->connector)->panel; + + pwm_set_relative_duty_cycle(&panel->backlight.pwm_state, level, 100); +- pwm_apply_state(panel->backlight.pwm, &panel->backlight.pwm_state); ++ pwm_apply_might_sleep(panel->backlight.pwm, &panel->backlight.pwm_state); } - static int drm_simple_kms_crtc_check(struct drm_crtc *crtc, -- struct drm_crtc_state *state) -+ struct drm_atomic_state *state) - { -- bool has_primary = state->plane_mask & -+ struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, -+ crtc); -+ bool has_primary = crtc_state->plane_mask & - drm_plane_mask(crtc->primary); + static void +@@ -427,7 +427,7 @@ static void ext_pwm_disable_backlight(const struct drm_connector_state *old_conn + intel_backlight_set_pwm_level(old_conn_state, level); - /* We always want to have an active plane with an active CRTC */ -- if (has_primary != state->enable) -+ if (has_primary != crtc_state->enable) - return -EINVAL; - -- return drm_atomic_add_affected_planes(state->state, crtc); -+ return drm_atomic_add_affected_planes(state, crtc); + panel->backlight.pwm_state.enabled = false; +- pwm_apply_state(panel->backlight.pwm, &panel->backlight.pwm_state); ++ pwm_apply_might_sleep(panel->backlight.pwm, &panel->backlight.pwm_state); } - static void drm_simple_kms_crtc_enable(struct drm_crtc *crtc, -- struct drm_crtc_state *old_state) -+ struct drm_atomic_state *state) - { - struct drm_plane *plane; - struct drm_simple_display_pipe *pipe; -@@ -113,7 +115,7 @@ static void drm_simple_kms_crtc_enable(struct drm_crtc *crtc, + void intel_backlight_disable(const struct drm_connector_state *old_conn_state) +@@ -749,7 +749,7 @@ static void ext_pwm_enable_backlight(const struct intel_crtc_state *crtc_state, + + pwm_set_relative_duty_cycle(&panel->backlight.pwm_state, level, 100); + panel->backlight.pwm_state.enabled = true; +- pwm_apply_state(panel->backlight.pwm, &panel->backlight.pwm_state); ++ pwm_apply_might_sleep(panel->backlight.pwm, &panel->backlight.pwm_state); } - static void drm_simple_kms_crtc_disable(struct drm_crtc *crtc, -- struct drm_crtc_state *old_state) -+ struct drm_atomic_state *state) - { - struct drm_simple_display_pipe *pipe; - -diff --git a/drivers/gpu/drm/exynos/exynos_drm_crtc.c b/drivers/gpu/drm/exynos/exynos_drm_crtc.c -index 1c03485676ef..4153f302de7c 100644 ---- a/drivers/gpu/drm/exynos/exynos_drm_crtc.c -+++ b/drivers/gpu/drm/exynos/exynos_drm_crtc.c -@@ -19,7 +19,7 @@ - #include "exynos_drm_plane.h" - - static void exynos_drm_crtc_atomic_enable(struct drm_crtc *crtc, -- struct drm_crtc_state *old_state) -+ struct drm_atomic_state *state) - { - struct exynos_drm_crtc *exynos_crtc = to_exynos_crtc(crtc); - -@@ -30,7 +30,7 @@ static void exynos_drm_crtc_atomic_enable(struct drm_crtc *crtc, - } - - static void exynos_drm_crtc_atomic_disable(struct drm_crtc *crtc, -- struct drm_crtc_state *old_state) -+ struct drm_atomic_state *state) - { - struct exynos_drm_crtc *exynos_crtc = to_exynos_crtc(crtc); - -@@ -49,21 +49,23 @@ static void exynos_drm_crtc_atomic_disable(struct drm_crtc *crtc, - } - - static int exynos_crtc_atomic_check(struct drm_crtc *crtc, -- struct drm_crtc_state *state) -+ struct drm_atomic_state *state) - { -+ struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, -+ crtc); - struct exynos_drm_crtc *exynos_crtc = to_exynos_crtc(crtc); - -- if (!state->enable) -+ if (!crtc_state->enable) - return 0; - - if (exynos_crtc->ops->atomic_check) -- return exynos_crtc->ops->atomic_check(exynos_crtc, state); -+ return exynos_crtc->ops->atomic_check(exynos_crtc, crtc_state); - - return 0; - } - - static void exynos_crtc_atomic_begin(struct drm_crtc *crtc, -- struct drm_crtc_state *old_crtc_state) -+ struct drm_atomic_state *state) - { - struct exynos_drm_crtc *exynos_crtc = to_exynos_crtc(crtc); - -@@ -72,7 +74,7 @@ static void exynos_crtc_atomic_begin(struct drm_crtc *crtc, - } - - static void exynos_crtc_atomic_flush(struct drm_crtc *crtc, -- struct drm_crtc_state *old_crtc_state) -+ struct drm_atomic_state *state) - { - struct exynos_drm_crtc *exynos_crtc = to_exynos_crtc(crtc); - -diff --git a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c -index b9ca81a6f80f..2af60d98f48f 100644 ---- a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c -+++ b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c -@@ -21,7 +21,7 @@ - #include "fsl_dcu_drm_plane.h" - - static void fsl_dcu_drm_crtc_atomic_flush(struct drm_crtc *crtc, -- struct drm_crtc_state *old_crtc_state) -+ struct drm_atomic_state *state) - { - struct drm_device *dev = crtc->dev; - struct fsl_dcu_drm_device *fsl_dev = dev->dev_private; -@@ -43,8 +43,10 @@ static void fsl_dcu_drm_crtc_atomic_flush(struct drm_crtc *crtc, - } - - static void fsl_dcu_drm_crtc_atomic_disable(struct drm_crtc *crtc, -- struct drm_crtc_state *old_crtc_state) -+ struct drm_atomic_state *state) - { -+ struct drm_crtc_state *old_crtc_state = drm_atomic_get_old_crtc_state(state, -+ crtc); - struct drm_device *dev = crtc->dev; - struct fsl_dcu_drm_device *fsl_dev = dev->dev_private; - -@@ -62,7 +64,7 @@ static void fsl_dcu_drm_crtc_atomic_disable(struct drm_crtc *crtc, - } - - static void fsl_dcu_drm_crtc_atomic_enable(struct drm_crtc *crtc, -- struct drm_crtc_state *old_state) -+ struct drm_atomic_state *state) - { - struct drm_device *dev = crtc->dev; - struct fsl_dcu_drm_device *fsl_dev = dev->dev_private; -diff --git a/drivers/gpu/drm/gud/Kconfig b/drivers/gpu/drm/gud/Kconfig -new file mode 100644 -index 000000000000..1c8601bf4d91 ---- /dev/null -+++ b/drivers/gpu/drm/gud/Kconfig -@@ -0,0 +1,14 @@ -+# SPDX-License-Identifier: GPL-2.0 -+ -+config DRM_GUD -+ tristate "GUD USB Display" -+ depends on DRM && USB -+ select LZ4_COMPRESS -+ select DRM_KMS_HELPER -+ select DRM_GEM_SHMEM_HELPER -+ select BACKLIGHT_CLASS_DEVICE -+ help -+ This is a DRM display driver for GUD USB Displays or display -+ adapters. -+ -+ If M is selected the module will be called gud. -diff --git a/drivers/gpu/drm/gud/Makefile b/drivers/gpu/drm/gud/Makefile -new file mode 100644 -index 000000000000..68a1c622cf33 ---- /dev/null -+++ b/drivers/gpu/drm/gud/Makefile -@@ -0,0 +1,4 @@ -+# SPDX-License-Identifier: GPL-2.0 -+ -+gud-y := gud_drv.o gud_pipe.o gud_connector.o -+obj-$(CONFIG_DRM_GUD) += gud.o -diff --git a/drivers/gpu/drm/gud/gud_connector.c b/drivers/gpu/drm/gud/gud_connector.c -new file mode 100644 -index 000000000000..ae051133e050 ---- /dev/null -+++ b/drivers/gpu/drm/gud/gud_connector.c -@@ -0,0 +1,729 @@ -+// SPDX-License-Identifier: MIT -+/* -+ * Copyright 2020 Noralf Trønnes -+ */ -+ -+#include -+#include -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "gud_internal.h" -+ -+struct gud_connector { -+ struct drm_connector connector; -+ struct drm_encoder encoder; -+ struct backlight_device *backlight; -+ struct work_struct backlight_work; -+ -+ /* Supported properties */ -+ u16 *properties; -+ unsigned int num_properties; -+ -+ /* Initial gadget tv state if applicable, applied on state reset */ -+ struct drm_tv_connector_state initial_tv_state; -+ -+ /* -+ * Initial gadget backlight brightness if applicable, applied on state reset. -+ * The value -ENODEV is used to signal no backlight. -+ */ -+ int initial_brightness; -+}; -+ -+static inline struct gud_connector *to_gud_connector(struct drm_connector *connector) -+{ -+ return container_of(connector, struct gud_connector, connector); -+} -+ -+static void gud_conn_err(struct drm_connector *connector, const char *msg, int ret) -+{ -+ dev_err(connector->dev->dev, "%s: %s (ret=%d)\n", connector->name, msg, ret); -+} -+ -+/* -+ * Use a worker to avoid taking kms locks inside the backlight lock. -+ * Other display drivers use backlight within their kms locks. -+ * This avoids inconsistent locking rules, which would upset lockdep. -+ */ -+static void gud_connector_backlight_update_status_work(struct work_struct *work) -+{ -+ struct gud_connector *gconn = container_of(work, struct gud_connector, backlight_work); -+ struct drm_connector *connector = &gconn->connector; -+ struct drm_connector_state *connector_state; -+ struct drm_device *drm = connector->dev; -+ struct drm_modeset_acquire_ctx ctx; -+ struct drm_atomic_state *state; -+ int idx, ret; -+ -+ if (!drm_dev_enter(drm, &idx)) -+ return; -+ -+ state = drm_atomic_state_alloc(drm); -+ if (!state) { -+ ret = -ENOMEM; -+ goto exit; -+ } -+ -+ drm_modeset_acquire_init(&ctx, 0); -+ state->acquire_ctx = &ctx; -+retry: -+ connector_state = drm_atomic_get_connector_state(state, connector); -+ if (IS_ERR(connector_state)) { -+ ret = PTR_ERR(connector_state); -+ goto out; -+ } -+ -+ /* Reuse tv.brightness to avoid having to subclass */ -+ connector_state->tv.brightness = gconn->backlight->props.brightness; -+ -+ ret = drm_atomic_commit(state); -+out: -+ if (ret == -EDEADLK) { -+ drm_atomic_state_clear(state); -+ drm_modeset_backoff(&ctx); -+ goto retry; -+ } -+ -+ drm_atomic_state_put(state); -+ -+ drm_modeset_drop_locks(&ctx); -+ drm_modeset_acquire_fini(&ctx); -+exit: -+ drm_dev_exit(idx); -+ -+ if (ret) -+ dev_err(drm->dev, "Failed to update backlight, err=%d\n", ret); -+} -+ -+static int gud_connector_backlight_update_status(struct backlight_device *bd) -+{ -+ struct drm_connector *connector = bl_get_data(bd); -+ struct gud_connector *gconn = to_gud_connector(connector); -+ -+ /* The USB timeout is 5 seconds so use system_long_wq for worst case scenario */ -+ queue_work(system_long_wq, &gconn->backlight_work); -+ -+ return 0; -+} -+ -+static const struct backlight_ops gud_connector_backlight_ops = { -+ .update_status = gud_connector_backlight_update_status, -+}; -+ -+static int gud_connector_backlight_register(struct gud_connector *gconn) -+{ -+ struct drm_connector *connector = &gconn->connector; -+ struct backlight_device *bd; -+ const char *name; -+ const struct backlight_properties props = { -+ .type = BACKLIGHT_RAW, -+ .scale = BACKLIGHT_SCALE_NON_LINEAR, -+ .max_brightness = 100, -+ .brightness = gconn->initial_brightness, -+ }; -+ -+ name = kasprintf(GFP_KERNEL, "card%d-%s-backlight", -+ connector->dev->primary->index, connector->name); -+ if (!name) -+ return -ENOMEM; -+ -+ bd = backlight_device_register(name, connector->kdev, connector, -+ &gud_connector_backlight_ops, &props); -+ kfree(name); -+ if (IS_ERR(bd)) -+ return PTR_ERR(bd); -+ -+ gconn->backlight = bd; -+ -+ return 0; -+} -+ -+static int gud_connector_detect(struct drm_connector *connector, -+ struct drm_modeset_acquire_ctx *ctx, bool force) -+{ -+ struct gud_device *gdrm = to_gud_device(connector->dev); -+ int idx, ret; -+ u8 status; -+ -+ if (!drm_dev_enter(connector->dev, &idx)) -+ return connector_status_disconnected; -+ -+ if (force) { -+ ret = gud_usb_set(gdrm, GUD_REQ_SET_CONNECTOR_FORCE_DETECT, -+ connector->index, NULL, 0); -+ if (ret) { -+ ret = connector_status_unknown; -+ goto exit; -+ } -+ } -+ -+ ret = gud_usb_get_u8(gdrm, GUD_REQ_GET_CONNECTOR_STATUS, connector->index, &status); -+ if (ret) { -+ ret = connector_status_unknown; -+ goto exit; -+ } -+ -+ switch (status & GUD_CONNECTOR_STATUS_CONNECTED_MASK) { -+ case GUD_CONNECTOR_STATUS_DISCONNECTED: -+ ret = connector_status_disconnected; -+ break; -+ case GUD_CONNECTOR_STATUS_CONNECTED: -+ ret = connector_status_connected; -+ break; -+ default: -+ ret = connector_status_unknown; -+ break; -+ } -+ -+ if (status & GUD_CONNECTOR_STATUS_CHANGED) -+ connector->epoch_counter += 1; -+exit: -+ drm_dev_exit(idx); -+ -+ return ret; -+} -+ -+struct gud_connector_get_edid_ctx { -+ void *buf; -+ size_t len; -+ bool edid_override; -+}; -+ -+static int gud_connector_get_edid_block(void *data, u8 *buf, unsigned int block, size_t len) -+{ -+ struct gud_connector_get_edid_ctx *ctx = data; -+ size_t start = block * EDID_LENGTH; -+ -+ ctx->edid_override = false; -+ -+ if (start + len > ctx->len) -+ return -1; -+ -+ memcpy(buf, ctx->buf + start, len); -+ -+ return 0; -+} -+ -+static int gud_connector_get_modes(struct drm_connector *connector) -+{ -+ struct gud_device *gdrm = to_gud_device(connector->dev); -+ struct gud_display_mode_req *reqmodes = NULL; -+ struct gud_connector_get_edid_ctx edid_ctx; -+ unsigned int i, num_modes = 0; -+ struct edid *edid = NULL; -+ int idx, ret; -+ -+ if (!drm_dev_enter(connector->dev, &idx)) -+ return 0; -+ -+ edid_ctx.edid_override = true; -+ edid_ctx.buf = kmalloc(GUD_CONNECTOR_MAX_EDID_LEN, GFP_KERNEL); -+ if (!edid_ctx.buf) -+ goto out; -+ -+ ret = gud_usb_get(gdrm, GUD_REQ_GET_CONNECTOR_EDID, connector->index, -+ edid_ctx.buf, GUD_CONNECTOR_MAX_EDID_LEN); -+ if (ret > 0 && ret % EDID_LENGTH) { -+ gud_conn_err(connector, "Invalid EDID size", ret); -+ } else if (ret > 0) { -+ edid_ctx.len = ret; -+ edid = drm_do_get_edid(connector, gud_connector_get_edid_block, &edid_ctx); -+ } -+ -+ kfree(edid_ctx.buf); -+ drm_connector_update_edid_property(connector, edid); -+ -+ if (edid && edid_ctx.edid_override) -+ goto out; -+ -+ reqmodes = kmalloc_array(GUD_CONNECTOR_MAX_NUM_MODES, sizeof(*reqmodes), GFP_KERNEL); -+ if (!reqmodes) -+ goto out; -+ -+ ret = gud_usb_get(gdrm, GUD_REQ_GET_CONNECTOR_MODES, connector->index, -+ reqmodes, GUD_CONNECTOR_MAX_NUM_MODES * sizeof(*reqmodes)); -+ if (ret <= 0) -+ goto out; -+ if (ret % sizeof(*reqmodes)) { -+ gud_conn_err(connector, "Invalid display mode array size", ret); -+ goto out; -+ } -+ -+ num_modes = ret / sizeof(*reqmodes); -+ -+ for (i = 0; i < num_modes; i++) { -+ struct drm_display_mode *mode; -+ -+ mode = drm_mode_create(connector->dev); -+ if (!mode) { -+ num_modes = i; -+ goto out; -+ } -+ -+ gud_to_display_mode(mode, &reqmodes[i]); -+ drm_mode_probed_add(connector, mode); -+ } -+out: -+ if (!num_modes) -+ num_modes = drm_add_edid_modes(connector, edid); -+ -+ kfree(reqmodes); -+ kfree(edid); -+ drm_dev_exit(idx); -+ -+ return num_modes; -+} -+ -+static int gud_connector_atomic_check(struct drm_connector *connector, -+ struct drm_atomic_state *state) -+{ -+ struct drm_connector_state *new_state; -+ struct drm_crtc_state *new_crtc_state; -+ struct drm_connector_state *old_state; -+ -+ new_state = drm_atomic_get_new_connector_state(state, connector); -+ if (!new_state->crtc) -+ return 0; -+ -+ old_state = drm_atomic_get_old_connector_state(state, connector); -+ new_crtc_state = drm_atomic_get_new_crtc_state(state, new_state->crtc); -+ -+ if (old_state->tv.margins.left != new_state->tv.margins.left || -+ old_state->tv.margins.right != new_state->tv.margins.right || -+ old_state->tv.margins.top != new_state->tv.margins.top || -+ old_state->tv.margins.bottom != new_state->tv.margins.bottom || -+ old_state->tv.mode != new_state->tv.mode || -+ old_state->tv.brightness != new_state->tv.brightness || -+ old_state->tv.contrast != new_state->tv.contrast || -+ old_state->tv.flicker_reduction != new_state->tv.flicker_reduction || -+ old_state->tv.overscan != new_state->tv.overscan || -+ old_state->tv.saturation != new_state->tv.saturation || -+ old_state->tv.hue != new_state->tv.hue) -+ new_crtc_state->connectors_changed = true; -+ -+ return 0; -+} -+ -+static const struct drm_connector_helper_funcs gud_connector_helper_funcs = { -+ .detect_ctx = gud_connector_detect, -+ .get_modes = gud_connector_get_modes, -+ .atomic_check = gud_connector_atomic_check, -+}; -+ -+static int gud_connector_late_register(struct drm_connector *connector) -+{ -+ struct gud_connector *gconn = to_gud_connector(connector); -+ -+ if (gconn->initial_brightness < 0) -+ return 0; -+ -+ return gud_connector_backlight_register(gconn); -+} -+ -+static void gud_connector_early_unregister(struct drm_connector *connector) -+{ -+ struct gud_connector *gconn = to_gud_connector(connector); -+ -+ backlight_device_unregister(gconn->backlight); -+ cancel_work_sync(&gconn->backlight_work); -+} -+ -+static void gud_connector_destroy(struct drm_connector *connector) -+{ -+ struct gud_connector *gconn = to_gud_connector(connector); -+ -+ drm_connector_cleanup(connector); -+ kfree(gconn->properties); -+ kfree(gconn); -+} -+ -+static void gud_connector_reset(struct drm_connector *connector) -+{ -+ struct gud_connector *gconn = to_gud_connector(connector); -+ -+ drm_atomic_helper_connector_reset(connector); -+ connector->state->tv = gconn->initial_tv_state; -+ /* Set margins from command line */ -+ drm_atomic_helper_connector_tv_reset(connector); -+ if (gconn->initial_brightness >= 0) -+ connector->state->tv.brightness = gconn->initial_brightness; -+} -+ -+static const struct drm_connector_funcs gud_connector_funcs = { -+ .fill_modes = drm_helper_probe_single_connector_modes, -+ .late_register = gud_connector_late_register, -+ .early_unregister = gud_connector_early_unregister, -+ .destroy = gud_connector_destroy, -+ .reset = gud_connector_reset, -+ .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, -+ .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, -+}; -+ -+/* -+ * The tv.mode property is shared among the connectors and its enum names are -+ * driver specific. This means that if more than one connector uses tv.mode, -+ * the enum names has to be the same. -+ */ -+static int gud_connector_add_tv_mode(struct gud_device *gdrm, struct drm_connector *connector) -+{ -+ size_t buf_len = GUD_CONNECTOR_TV_MODE_MAX_NUM * GUD_CONNECTOR_TV_MODE_NAME_LEN; -+ const char *modes[GUD_CONNECTOR_TV_MODE_MAX_NUM]; -+ unsigned int i, num_modes; -+ char *buf; -+ int ret; -+ -+ buf = kmalloc(buf_len, GFP_KERNEL); -+ if (!buf) -+ return -ENOMEM; -+ -+ ret = gud_usb_get(gdrm, GUD_REQ_GET_CONNECTOR_TV_MODE_VALUES, -+ connector->index, buf, buf_len); -+ if (ret < 0) -+ goto free; -+ if (!ret || ret % GUD_CONNECTOR_TV_MODE_NAME_LEN) { -+ ret = -EIO; -+ goto free; -+ } -+ -+ num_modes = ret / GUD_CONNECTOR_TV_MODE_NAME_LEN; -+ for (i = 0; i < num_modes; i++) -+ modes[i] = &buf[i * GUD_CONNECTOR_TV_MODE_NAME_LEN]; -+ -+ ret = drm_mode_create_tv_properties(connector->dev, num_modes, modes); -+free: -+ kfree(buf); -+ if (ret < 0) -+ gud_conn_err(connector, "Failed to add TV modes", ret); -+ -+ return ret; -+} -+ -+static struct drm_property * -+gud_connector_property_lookup(struct drm_connector *connector, u16 prop) -+{ -+ struct drm_mode_config *config = &connector->dev->mode_config; -+ -+ switch (prop) { -+ case GUD_PROPERTY_TV_LEFT_MARGIN: -+ return config->tv_left_margin_property; -+ case GUD_PROPERTY_TV_RIGHT_MARGIN: -+ return config->tv_right_margin_property; -+ case GUD_PROPERTY_TV_TOP_MARGIN: -+ return config->tv_top_margin_property; -+ case GUD_PROPERTY_TV_BOTTOM_MARGIN: -+ return config->tv_bottom_margin_property; -+ case GUD_PROPERTY_TV_MODE: -+ return config->tv_mode_property; -+ case GUD_PROPERTY_TV_BRIGHTNESS: -+ return config->tv_brightness_property; -+ case GUD_PROPERTY_TV_CONTRAST: -+ return config->tv_contrast_property; -+ case GUD_PROPERTY_TV_FLICKER_REDUCTION: -+ return config->tv_flicker_reduction_property; -+ case GUD_PROPERTY_TV_OVERSCAN: -+ return config->tv_overscan_property; -+ case GUD_PROPERTY_TV_SATURATION: -+ return config->tv_saturation_property; -+ case GUD_PROPERTY_TV_HUE: -+ return config->tv_hue_property; -+ default: -+ return ERR_PTR(-EINVAL); -+ } -+} -+ -+static unsigned int *gud_connector_tv_state_val(u16 prop, struct drm_tv_connector_state *state) -+{ -+ switch (prop) { -+ case GUD_PROPERTY_TV_LEFT_MARGIN: -+ return &state->margins.left; -+ case GUD_PROPERTY_TV_RIGHT_MARGIN: -+ return &state->margins.right; -+ case GUD_PROPERTY_TV_TOP_MARGIN: -+ return &state->margins.top; -+ case GUD_PROPERTY_TV_BOTTOM_MARGIN: -+ return &state->margins.bottom; -+ case GUD_PROPERTY_TV_MODE: -+ return &state->mode; -+ case GUD_PROPERTY_TV_BRIGHTNESS: -+ return &state->brightness; -+ case GUD_PROPERTY_TV_CONTRAST: -+ return &state->contrast; -+ case GUD_PROPERTY_TV_FLICKER_REDUCTION: -+ return &state->flicker_reduction; -+ case GUD_PROPERTY_TV_OVERSCAN: -+ return &state->overscan; -+ case GUD_PROPERTY_TV_SATURATION: -+ return &state->saturation; -+ case GUD_PROPERTY_TV_HUE: -+ return &state->hue; -+ default: -+ return ERR_PTR(-EINVAL); -+ } -+} -+ -+static int gud_connector_add_properties(struct gud_device *gdrm, struct gud_connector *gconn) -+{ -+ struct drm_connector *connector = &gconn->connector; -+ struct drm_device *drm = &gdrm->drm; -+ struct gud_property_req *properties; -+ unsigned int i, num_properties; -+ int ret; -+ -+ properties = kcalloc(GUD_CONNECTOR_PROPERTIES_MAX_NUM, sizeof(*properties), GFP_KERNEL); -+ if (!properties) -+ return -ENOMEM; -+ -+ ret = gud_usb_get(gdrm, GUD_REQ_GET_CONNECTOR_PROPERTIES, connector->index, -+ properties, GUD_CONNECTOR_PROPERTIES_MAX_NUM * sizeof(*properties)); -+ if (ret <= 0) -+ goto out; -+ if (ret % sizeof(*properties)) { -+ ret = -EIO; -+ goto out; -+ } -+ -+ num_properties = ret / sizeof(*properties); -+ ret = 0; -+ -+ gconn->properties = kcalloc(num_properties, sizeof(*gconn->properties), GFP_KERNEL); -+ if (!gconn->properties) { -+ ret = -ENOMEM; -+ goto out; -+ } -+ -+ for (i = 0; i < num_properties; i++) { -+ u16 prop = le16_to_cpu(properties[i].prop); -+ u64 val = le64_to_cpu(properties[i].val); -+ struct drm_property *property; -+ unsigned int *state_val; -+ -+ drm_dbg(drm, "property: %u = %llu(0x%llx)\n", prop, val, val); -+ -+ switch (prop) { -+ case GUD_PROPERTY_TV_LEFT_MARGIN: -+ fallthrough; -+ case GUD_PROPERTY_TV_RIGHT_MARGIN: -+ fallthrough; -+ case GUD_PROPERTY_TV_TOP_MARGIN: -+ fallthrough; -+ case GUD_PROPERTY_TV_BOTTOM_MARGIN: -+ ret = drm_mode_create_tv_margin_properties(drm); -+ if (ret) -+ goto out; -+ break; -+ case GUD_PROPERTY_TV_MODE: -+ ret = gud_connector_add_tv_mode(gdrm, connector); -+ if (ret) -+ goto out; -+ break; -+ case GUD_PROPERTY_TV_BRIGHTNESS: -+ fallthrough; -+ case GUD_PROPERTY_TV_CONTRAST: -+ fallthrough; -+ case GUD_PROPERTY_TV_FLICKER_REDUCTION: -+ fallthrough; -+ case GUD_PROPERTY_TV_OVERSCAN: -+ fallthrough; -+ case GUD_PROPERTY_TV_SATURATION: -+ fallthrough; -+ case GUD_PROPERTY_TV_HUE: -+ /* This is a no-op if already added. */ -+ ret = drm_mode_create_tv_properties(drm, 0, NULL); -+ if (ret) -+ goto out; -+ break; -+ case GUD_PROPERTY_BACKLIGHT_BRIGHTNESS: -+ if (val > 100) { -+ ret = -EINVAL; -+ goto out; -+ } -+ gconn->initial_brightness = val; -+ break; -+ default: -+ /* New ones might show up in future devices, skip those we don't know. */ -+ drm_dbg(drm, "Ignoring unknown property: %u\n", prop); -+ continue; -+ } -+ -+ gconn->properties[gconn->num_properties++] = prop; -+ -+ if (prop == GUD_PROPERTY_BACKLIGHT_BRIGHTNESS) -+ continue; /* not a DRM property */ -+ -+ property = gud_connector_property_lookup(connector, prop); -+ if (WARN_ON(IS_ERR(property))) -+ continue; -+ -+ state_val = gud_connector_tv_state_val(prop, &gconn->initial_tv_state); -+ if (WARN_ON(IS_ERR(state_val))) -+ continue; -+ -+ *state_val = val; -+ drm_object_attach_property(&connector->base, property, 0); -+ } -+out: -+ kfree(properties); -+ -+ return ret; -+} -+ -+int gud_connector_fill_properties(struct drm_connector_state *connector_state, -+ struct gud_property_req *properties) -+{ -+ struct gud_connector *gconn = to_gud_connector(connector_state->connector); -+ unsigned int i; -+ -+ for (i = 0; i < gconn->num_properties; i++) { -+ u16 prop = gconn->properties[i]; -+ u64 val; -+ -+ if (prop == GUD_PROPERTY_BACKLIGHT_BRIGHTNESS) { -+ val = connector_state->tv.brightness; -+ } else { -+ unsigned int *state_val; -+ -+ state_val = gud_connector_tv_state_val(prop, &connector_state->tv); -+ if (WARN_ON_ONCE(IS_ERR(state_val))) -+ return PTR_ERR(state_val); -+ -+ val = *state_val; -+ } -+ -+ properties[i].prop = cpu_to_le16(prop); -+ properties[i].val = cpu_to_le64(val); -+ } -+ -+ return gconn->num_properties; -+} -+ -+static int gud_connector_create(struct gud_device *gdrm, unsigned int index, -+ struct gud_connector_descriptor_req *desc) -+{ -+ struct drm_device *drm = &gdrm->drm; -+ struct gud_connector *gconn; -+ struct drm_connector *connector; -+ struct drm_encoder *encoder; -+ int ret, connector_type; -+ u32 flags; -+ -+ gconn = kzalloc(sizeof(*gconn), GFP_KERNEL); -+ if (!gconn) -+ return -ENOMEM; -+ -+ INIT_WORK(&gconn->backlight_work, gud_connector_backlight_update_status_work); -+ gconn->initial_brightness = -ENODEV; -+ flags = le32_to_cpu(desc->flags); -+ connector = &gconn->connector; -+ -+ drm_dbg(drm, "Connector: index=%u type=%u flags=0x%x\n", index, desc->connector_type, flags); -+ -+ switch (desc->connector_type) { -+ case GUD_CONNECTOR_TYPE_PANEL: -+ connector_type = DRM_MODE_CONNECTOR_USB; -+ break; -+ case GUD_CONNECTOR_TYPE_VGA: -+ connector_type = DRM_MODE_CONNECTOR_VGA; -+ break; -+ case GUD_CONNECTOR_TYPE_DVI: -+ connector_type = DRM_MODE_CONNECTOR_DVID; -+ break; -+ case GUD_CONNECTOR_TYPE_COMPOSITE: -+ connector_type = DRM_MODE_CONNECTOR_Composite; -+ break; -+ case GUD_CONNECTOR_TYPE_SVIDEO: -+ connector_type = DRM_MODE_CONNECTOR_SVIDEO; -+ break; -+ case GUD_CONNECTOR_TYPE_COMPONENT: -+ connector_type = DRM_MODE_CONNECTOR_Component; -+ break; -+ case GUD_CONNECTOR_TYPE_DISPLAYPORT: -+ connector_type = DRM_MODE_CONNECTOR_DisplayPort; -+ break; -+ case GUD_CONNECTOR_TYPE_HDMI: -+ connector_type = DRM_MODE_CONNECTOR_HDMIA; -+ break; -+ default: /* future types */ -+ connector_type = DRM_MODE_CONNECTOR_USB; -+ break; -+ } -+ -+ drm_connector_helper_add(connector, &gud_connector_helper_funcs); -+ ret = drm_connector_init(drm, connector, &gud_connector_funcs, connector_type); -+ if (ret) { -+ kfree(connector); -+ return ret; -+ } -+ -+ if (WARN_ON(connector->index != index)) -+ return -EINVAL; -+ -+ if (flags & GUD_CONNECTOR_FLAGS_POLL_STATUS) -+ connector->polled = (DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT); -+ if (flags & GUD_CONNECTOR_FLAGS_INTERLACE) -+ connector->interlace_allowed = true; -+ if (flags & GUD_CONNECTOR_FLAGS_DOUBLESCAN) -+ connector->doublescan_allowed = true; -+ -+ ret = gud_connector_add_properties(gdrm, gconn); -+ if (ret) { -+ gud_conn_err(connector, "Failed to add properties", ret); -+ return ret; -+ } -+ -+ /* The first connector is attached to the existing simple pipe encoder */ -+ if (!connector->index) { -+ encoder = &gdrm->pipe.encoder; -+ } else { -+ encoder = &gconn->encoder; -+ -+ ret = drm_simple_encoder_init(drm, encoder, DRM_MODE_ENCODER_NONE); -+ if (ret) -+ return ret; -+ -+ encoder->possible_crtcs = 1; -+ } -+ -+ return drm_connector_attach_encoder(connector, encoder); -+} -+ -+int gud_get_connectors(struct gud_device *gdrm) -+{ -+ struct gud_connector_descriptor_req *descs; -+ unsigned int i, num_connectors; -+ int ret; -+ -+ descs = kmalloc_array(GUD_CONNECTORS_MAX_NUM, sizeof(*descs), GFP_KERNEL); -+ if (!descs) -+ return -ENOMEM; -+ -+ ret = gud_usb_get(gdrm, GUD_REQ_GET_CONNECTORS, 0, -+ descs, GUD_CONNECTORS_MAX_NUM * sizeof(*descs)); -+ if (ret < 0) -+ goto free; -+ if (!ret || ret % sizeof(*descs)) { -+ ret = -EIO; -+ goto free; -+ } -+ -+ num_connectors = ret / sizeof(*descs); -+ -+ for (i = 0; i < num_connectors; i++) { -+ ret = gud_connector_create(gdrm, i, &descs[i]); -+ if (ret) -+ goto free; -+ } -+free: -+ kfree(descs); -+ -+ return ret; -+} -diff --git a/drivers/gpu/drm/gud/gud_drv.c b/drivers/gpu/drm/gud/gud_drv.c -new file mode 100644 -index 000000000000..3afad229bb78 ---- /dev/null -+++ b/drivers/gpu/drm/gud/gud_drv.c -@@ -0,0 +1,696 @@ -+// SPDX-License-Identifier: MIT -+/* -+ * Copyright 2020 Noralf Trønnes -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "gud_internal.h" -+ -+/* Only used internally */ -+static const struct drm_format_info gud_drm_format_r1 = { -+ .format = GUD_DRM_FORMAT_R1, -+ .num_planes = 1, -+ .char_per_block = { 1, 0, 0 }, -+ .block_w = { 8, 0, 0 }, -+ .block_h = { 1, 0, 0 }, -+ .hsub = 1, -+ .vsub = 1, -+}; -+ -+static const struct drm_format_info gud_drm_format_xrgb1111 = { -+ .format = GUD_DRM_FORMAT_XRGB1111, -+ .num_planes = 1, -+ .char_per_block = { 1, 0, 0 }, -+ .block_w = { 2, 0, 0 }, -+ .block_h = { 1, 0, 0 }, -+ .hsub = 1, -+ .vsub = 1, -+}; -+ -+static int gud_usb_control_msg(struct usb_interface *intf, bool in, -+ u8 request, u16 value, void *buf, size_t len) -+{ -+ u8 requesttype = USB_TYPE_VENDOR | USB_RECIP_INTERFACE; -+ u8 ifnum = intf->cur_altsetting->desc.bInterfaceNumber; -+ struct usb_device *usb = interface_to_usbdev(intf); -+ unsigned int pipe; -+ -+ if (len && !buf) -+ return -EINVAL; -+ -+ if (in) { -+ pipe = usb_rcvctrlpipe(usb, 0); -+ requesttype |= USB_DIR_IN; -+ } else { -+ pipe = usb_sndctrlpipe(usb, 0); -+ requesttype |= USB_DIR_OUT; -+ } -+ -+ return usb_control_msg(usb, pipe, request, requesttype, value, -+ ifnum, buf, len, USB_CTRL_GET_TIMEOUT); -+} -+ -+static int gud_get_display_descriptor(struct usb_interface *intf, -+ struct gud_display_descriptor_req *desc) -+{ -+ void *buf; -+ int ret; -+ -+ buf = kmalloc(sizeof(*desc), GFP_KERNEL); -+ if (!buf) -+ return -ENOMEM; -+ -+ ret = gud_usb_control_msg(intf, true, GUD_REQ_GET_DESCRIPTOR, 0, buf, sizeof(*desc)); -+ memcpy(desc, buf, sizeof(*desc)); -+ kfree(buf); -+ if (ret < 0) -+ return ret; -+ if (ret != sizeof(*desc)) -+ return -EIO; -+ -+ if (desc->magic != le32_to_cpu(GUD_DISPLAY_MAGIC)) -+ return -ENODATA; -+ -+ DRM_DEV_DEBUG_DRIVER(&intf->dev, -+ "version=%u flags=0x%x compression=0x%x max_buffer_size=%u\n", -+ desc->version, le32_to_cpu(desc->flags), desc->compression, -+ le32_to_cpu(desc->max_buffer_size)); -+ -+ if (!desc->version || !desc->max_width || !desc->max_height || -+ le32_to_cpu(desc->min_width) > le32_to_cpu(desc->max_width) || -+ le32_to_cpu(desc->min_height) > le32_to_cpu(desc->max_height)) -+ return -EINVAL; -+ -+ return 0; -+} -+ -+static int gud_status_to_errno(u8 status) -+{ -+ switch (status) { -+ case GUD_STATUS_OK: -+ return 0; -+ case GUD_STATUS_BUSY: -+ return -EBUSY; -+ case GUD_STATUS_REQUEST_NOT_SUPPORTED: -+ return -EOPNOTSUPP; -+ case GUD_STATUS_PROTOCOL_ERROR: -+ return -EPROTO; -+ case GUD_STATUS_INVALID_PARAMETER: -+ return -EINVAL; -+ case GUD_STATUS_ERROR: -+ return -EREMOTEIO; -+ default: -+ return -EREMOTEIO; -+ } -+} -+ -+static int gud_usb_get_status(struct usb_interface *intf) -+{ -+ int ret, status = -EIO; -+ u8 *buf; -+ -+ buf = kmalloc(sizeof(*buf), GFP_KERNEL); -+ if (!buf) -+ return -ENOMEM; -+ -+ ret = gud_usb_control_msg(intf, true, GUD_REQ_GET_STATUS, 0, buf, sizeof(*buf)); -+ if (ret == sizeof(*buf)) -+ status = gud_status_to_errno(*buf); -+ kfree(buf); -+ -+ if (ret < 0) -+ return ret; -+ -+ return status; -+} -+ -+static int gud_usb_transfer(struct gud_device *gdrm, bool in, u8 request, u16 index, -+ void *buf, size_t len) -+{ -+ struct usb_interface *intf = to_usb_interface(gdrm->drm.dev); -+ int idx, ret; -+ -+ drm_dbg(&gdrm->drm, "%s: request=0x%x index=%u len=%zu\n", -+ in ? "get" : "set", request, index, len); -+ -+ if (!drm_dev_enter(&gdrm->drm, &idx)) -+ return -ENODEV; -+ -+ mutex_lock(&gdrm->ctrl_lock); -+ -+ ret = gud_usb_control_msg(intf, in, request, index, buf, len); -+ if (ret == -EPIPE || ((gdrm->flags & GUD_DISPLAY_FLAG_STATUS_ON_SET) && !in && ret >= 0)) { -+ int status; -+ -+ status = gud_usb_get_status(intf); -+ if (status < 0) { -+ ret = status; -+ } else if (ret < 0) { -+ dev_err_once(gdrm->drm.dev, -+ "Unexpected status OK for failed transfer\n"); -+ ret = -EPIPE; -+ } -+ } -+ -+ if (ret < 0) { -+ drm_dbg(&gdrm->drm, "ret=%d\n", ret); -+ gdrm->stats_num_errors++; -+ } -+ -+ mutex_unlock(&gdrm->ctrl_lock); -+ drm_dev_exit(idx); -+ -+ return ret; -+} -+ -+/* -+ * @buf cannot be allocated on the stack. -+ * Returns number of bytes received or negative error code on failure. -+ */ -+int gud_usb_get(struct gud_device *gdrm, u8 request, u16 index, void *buf, size_t max_len) -+{ -+ return gud_usb_transfer(gdrm, true, request, index, buf, max_len); -+} -+ -+/* -+ * @buf can be allocated on the stack or NULL. -+ * Returns zero on success or negative error code on failure. -+ */ -+int gud_usb_set(struct gud_device *gdrm, u8 request, u16 index, void *buf, size_t len) -+{ -+ void *trbuf = NULL; -+ int ret; -+ -+ if (buf && len) { -+ trbuf = kmemdup(buf, len, GFP_KERNEL); -+ if (!trbuf) -+ return -ENOMEM; -+ } -+ -+ ret = gud_usb_transfer(gdrm, false, request, index, trbuf, len); -+ kfree(trbuf); -+ if (ret < 0) -+ return ret; -+ -+ return ret != len ? -EIO : 0; -+} -+ -+/* -+ * @val can be allocated on the stack. -+ * Returns zero on success or negative error code on failure. -+ */ -+int gud_usb_get_u8(struct gud_device *gdrm, u8 request, u16 index, u8 *val) -+{ -+ u8 *buf; -+ int ret; -+ -+ buf = kmalloc(sizeof(*val), GFP_KERNEL); -+ if (!buf) -+ return -ENOMEM; -+ -+ ret = gud_usb_get(gdrm, request, index, buf, sizeof(*val)); -+ *val = *buf; -+ kfree(buf); -+ if (ret < 0) -+ return ret; -+ -+ return ret != sizeof(*val) ? -EIO : 0; -+} -+ -+/* Returns zero on success or negative error code on failure. */ -+int gud_usb_set_u8(struct gud_device *gdrm, u8 request, u8 val) -+{ -+ return gud_usb_set(gdrm, request, 0, &val, sizeof(val)); -+} -+ -+static int gud_get_properties(struct gud_device *gdrm) -+{ -+ struct gud_property_req *properties; -+ unsigned int i, num_properties; -+ int ret; -+ -+ properties = kcalloc(GUD_PROPERTIES_MAX_NUM, sizeof(*properties), GFP_KERNEL); -+ if (!properties) -+ return -ENOMEM; -+ -+ ret = gud_usb_get(gdrm, GUD_REQ_GET_PROPERTIES, 0, -+ properties, GUD_PROPERTIES_MAX_NUM * sizeof(*properties)); -+ if (ret <= 0) -+ goto out; -+ if (ret % sizeof(*properties)) { -+ ret = -EIO; -+ goto out; -+ } -+ -+ num_properties = ret / sizeof(*properties); -+ ret = 0; -+ -+ gdrm->properties = drmm_kcalloc(&gdrm->drm, num_properties, sizeof(*gdrm->properties), -+ GFP_KERNEL); -+ if (!gdrm->properties) { -+ ret = -ENOMEM; -+ goto out; -+ } -+ -+ for (i = 0; i < num_properties; i++) { -+ u16 prop = le16_to_cpu(properties[i].prop); -+ u64 val = le64_to_cpu(properties[i].val); -+ -+ switch (prop) { -+ case GUD_PROPERTY_ROTATION: -+ /* -+ * DRM UAPI matches the protocol so use the value directly, -+ * but mask out any additions on future devices. -+ */ -+ val &= GUD_ROTATION_MASK; -+ ret = drm_plane_create_rotation_property(&gdrm->pipe.plane, -+ DRM_MODE_ROTATE_0, val); -+ break; -+ default: -+ /* New ones might show up in future devices, skip those we don't know. */ -+ drm_dbg(&gdrm->drm, "Ignoring unknown property: %u\n", prop); -+ continue; -+ } -+ -+ if (ret) -+ goto out; -+ -+ gdrm->properties[gdrm->num_properties++] = prop; -+ } -+out: -+ kfree(properties); -+ -+ return ret; -+} -+ -+static struct drm_gem_object *gud_gem_create_object(struct drm_device *dev, size_t size) -+{ -+ struct drm_gem_shmem_object *shmem; -+ -+ shmem = kzalloc(sizeof(*shmem), GFP_KERNEL); -+ if (!shmem) -+ return NULL; -+ -+ shmem->map_cached = true; -+ -+ return &shmem->base; -+} -+ -+/* -+ * FIXME: Dma-buf sharing requires DMA support by the importing device. -+ * This function is a workaround to make USB devices work as well. -+ * See todo.rst for how to fix the issue in the dma-buf framework. -+ */ -+static struct drm_gem_object *gud_gem_prime_import(struct drm_device *drm, struct dma_buf *dma_buf) -+{ -+ struct gud_device *gdrm = to_gud_device(drm); -+ -+ if (!gdrm->dmadev) -+ return ERR_PTR(-ENODEV); -+ -+ return drm_gem_prime_import_dev(drm, dma_buf, gdrm->dmadev); -+} -+ -+static int gud_stats_debugfs(struct seq_file *m, void *data) -+{ -+ struct drm_info_node *node = m->private; -+ struct gud_device *gdrm = to_gud_device(node->minor->dev); -+ char buf[10]; -+ -+ string_get_size(gdrm->bulk_len, 1, STRING_UNITS_2, buf, sizeof(buf)); -+ seq_printf(m, "Max buffer size: %s\n", buf); -+ seq_printf(m, "Number of errors: %u\n", gdrm->stats_num_errors); -+ -+ seq_puts(m, "Compression: "); -+ if (gdrm->compression & GUD_COMPRESSION_LZ4) -+ seq_puts(m, " lz4"); -+ if (!gdrm->compression) -+ seq_puts(m, " none"); -+ seq_puts(m, "\n"); -+ -+ if (gdrm->compression) { -+ u64 remainder; -+ u64 ratio = div64_u64_rem(gdrm->stats_length, gdrm->stats_actual_length, -+ &remainder); -+ u64 ratio_frac = div64_u64(remainder * 10, gdrm->stats_actual_length); -+ -+ seq_printf(m, "Compression ratio: %llu.%llu\n", ratio, ratio_frac); -+ } -+ -+ return 0; -+} -+ -+static const struct drm_info_list gud_debugfs_list[] = { -+ { "stats", gud_stats_debugfs, 0, NULL }, -+}; -+ -+static void gud_debugfs_init(struct drm_minor *minor) -+{ -+ drm_debugfs_create_files(gud_debugfs_list, ARRAY_SIZE(gud_debugfs_list), -+ minor->debugfs_root, minor); -+} -+ -+static const struct drm_simple_display_pipe_funcs gud_pipe_funcs = { -+ .check = gud_pipe_check, -+ .update = gud_pipe_update, -+ .prepare_fb = drm_gem_fb_simple_display_pipe_prepare_fb, -+}; -+ -+static const struct drm_mode_config_funcs gud_mode_config_funcs = { -+ .fb_create = drm_gem_fb_create_with_dirty, -+ .atomic_check = drm_atomic_helper_check, -+ .atomic_commit = drm_atomic_helper_commit, -+}; -+ -+static const u64 gud_pipe_modifiers[] = { -+ DRM_FORMAT_MOD_LINEAR, -+ DRM_FORMAT_MOD_INVALID -+}; -+ -+DEFINE_DRM_GEM_FOPS(gud_fops); -+ -+static struct drm_driver gud_drm_driver = { -+ .driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_ATOMIC, -+ .fops = &gud_fops, -+ DRM_GEM_SHMEM_DRIVER_OPS, -+ .gem_create_object = gud_gem_create_object, -+ .gem_prime_import = gud_gem_prime_import, -+ .debugfs_init = gud_debugfs_init, -+ -+ .name = "gud", -+ .desc = "Generic USB Display", -+ .date = "20200422", -+ .major = 1, -+ .minor = 0, -+}; -+ -+static int gud_alloc_bulk_buffer(struct gud_device *gdrm) -+{ -+ unsigned int i, num_pages; -+ struct page **pages; -+ void *ptr; -+ int ret; -+ -+ gdrm->bulk_buf = vmalloc_32(gdrm->bulk_len); -+ if (!gdrm->bulk_buf) -+ return -ENOMEM; -+ -+ num_pages = DIV_ROUND_UP(gdrm->bulk_len, PAGE_SIZE); -+ pages = kmalloc_array(num_pages, sizeof(struct page *), GFP_KERNEL); -+ if (!pages) -+ return -ENOMEM; -+ -+ for (i = 0, ptr = gdrm->bulk_buf; i < num_pages; i++, ptr += PAGE_SIZE) -+ pages[i] = vmalloc_to_page(ptr); -+ -+ ret = sg_alloc_table_from_pages(&gdrm->bulk_sgt, pages, num_pages, -+ 0, gdrm->bulk_len, GFP_KERNEL); -+ kfree(pages); -+ -+ return ret; -+} -+ -+static void gud_free_buffers_and_mutex(void *data) -+{ -+ struct gud_device *gdrm = data; -+ -+ vfree(gdrm->compress_buf); -+ gdrm->compress_buf = NULL; -+ sg_free_table(&gdrm->bulk_sgt); -+ vfree(gdrm->bulk_buf); -+ gdrm->bulk_buf = NULL; -+ mutex_destroy(&gdrm->ctrl_lock); -+} -+ -+static int gud_probe(struct usb_interface *intf, const struct usb_device_id *id) -+{ -+ const struct drm_format_info *xrgb8888_emulation_format = NULL; -+ bool rgb565_supported = false, xrgb8888_supported = false; -+ unsigned int num_formats_dev, num_formats = 0; -+ struct usb_endpoint_descriptor *bulk_out; -+ struct gud_display_descriptor_req desc; -+ struct device *dev = &intf->dev; -+ size_t max_buffer_size = 0; -+ struct gud_device *gdrm; -+ struct drm_device *drm; -+ u8 *formats_dev; -+ u32 *formats; -+ int ret, i; -+ -+ ret = usb_find_bulk_out_endpoint(intf->cur_altsetting, &bulk_out); -+ if (ret) -+ return ret; -+ -+ ret = gud_get_display_descriptor(intf, &desc); -+ if (ret) { -+ DRM_DEV_DEBUG_DRIVER(dev, "Not a display interface: ret=%d\n", ret); -+ return -ENODEV; -+ } -+ -+ if (desc.version > 1) { -+ dev_err(dev, "Protocol version %u is not supported\n", desc.version); -+ return -ENODEV; -+ } -+ -+ gdrm = devm_drm_dev_alloc(dev, &gud_drm_driver, struct gud_device, drm); -+ if (IS_ERR(gdrm)) -+ return PTR_ERR(gdrm); -+ -+ drm = &gdrm->drm; -+ drm->mode_config.funcs = &gud_mode_config_funcs; -+ ret = drmm_mode_config_init(drm); -+ if (ret) -+ return ret; -+ -+ gdrm->flags = le32_to_cpu(desc.flags); -+ gdrm->compression = desc.compression & GUD_COMPRESSION_LZ4; -+ -+ if (gdrm->flags & GUD_DISPLAY_FLAG_FULL_UPDATE && gdrm->compression) -+ return -EINVAL; -+ -+ mutex_init(&gdrm->ctrl_lock); -+ mutex_init(&gdrm->damage_lock); -+ INIT_WORK(&gdrm->work, gud_flush_work); -+ gud_clear_damage(gdrm); -+ -+ ret = devm_add_action(dev, gud_free_buffers_and_mutex, gdrm); -+ if (ret) -+ return ret; -+ -+ drm->mode_config.min_width = le32_to_cpu(desc.min_width); -+ drm->mode_config.max_width = le32_to_cpu(desc.max_width); -+ drm->mode_config.min_height = le32_to_cpu(desc.min_height); -+ drm->mode_config.max_height = le32_to_cpu(desc.max_height); -+ -+ formats_dev = devm_kmalloc(dev, GUD_FORMATS_MAX_NUM, GFP_KERNEL); -+ /* Add room for emulated XRGB8888 */ -+ formats = devm_kmalloc_array(dev, GUD_FORMATS_MAX_NUM + 1, sizeof(*formats), GFP_KERNEL); -+ if (!formats_dev || !formats) -+ return -ENOMEM; -+ -+ ret = gud_usb_get(gdrm, GUD_REQ_GET_FORMATS, 0, formats_dev, GUD_FORMATS_MAX_NUM); -+ if (ret < 0) -+ return ret; -+ -+ num_formats_dev = ret; -+ for (i = 0; i < num_formats_dev; i++) { -+ const struct drm_format_info *info; -+ size_t fmt_buf_size; -+ u32 format; -+ -+ format = gud_to_fourcc(formats_dev[i]); -+ if (!format) { -+ drm_dbg(drm, "Unsupported format: 0x%02x\n", formats_dev[i]); -+ continue; -+ } -+ -+ if (format == GUD_DRM_FORMAT_R1) -+ info = &gud_drm_format_r1; -+ else if (format == GUD_DRM_FORMAT_XRGB1111) -+ info = &gud_drm_format_xrgb1111; -+ else -+ info = drm_format_info(format); -+ -+ switch (format) { -+ case GUD_DRM_FORMAT_R1: -+ fallthrough; -+ case GUD_DRM_FORMAT_XRGB1111: -+ if (!xrgb8888_emulation_format) -+ xrgb8888_emulation_format = info; -+ break; -+ case DRM_FORMAT_RGB565: -+ rgb565_supported = true; -+ if (!xrgb8888_emulation_format) -+ xrgb8888_emulation_format = info; -+ break; -+ case DRM_FORMAT_XRGB8888: -+ xrgb8888_supported = true; -+ break; -+ } -+ -+ fmt_buf_size = drm_format_info_min_pitch(info, 0, drm->mode_config.max_width) * -+ drm->mode_config.max_height; -+ max_buffer_size = max(max_buffer_size, fmt_buf_size); -+ -+ if (format == GUD_DRM_FORMAT_R1 || format == GUD_DRM_FORMAT_XRGB1111) -+ continue; /* Internal not for userspace */ -+ -+ formats[num_formats++] = format; -+ } -+ -+ if (!num_formats && !xrgb8888_emulation_format) { -+ dev_err(dev, "No supported pixel formats found\n"); -+ return -EINVAL; -+ } -+ -+ /* Prefer speed over color depth */ -+ if (rgb565_supported) -+ drm->mode_config.preferred_depth = 16; -+ -+ if (!xrgb8888_supported && xrgb8888_emulation_format) { -+ gdrm->xrgb8888_emulation_format = xrgb8888_emulation_format; -+ formats[num_formats++] = DRM_FORMAT_XRGB8888; -+ } -+ -+ if (desc.max_buffer_size) -+ max_buffer_size = le32_to_cpu(desc.max_buffer_size); -+ /* Prevent a misbehaving device from allocating loads of RAM. 4096x4096@XRGB8888 = 64 MB */ -+ if (max_buffer_size > SZ_64M) -+ max_buffer_size = SZ_64M; -+ -+ gdrm->bulk_pipe = usb_sndbulkpipe(interface_to_usbdev(intf), usb_endpoint_num(bulk_out)); -+ gdrm->bulk_len = max_buffer_size; -+ -+ ret = gud_alloc_bulk_buffer(gdrm); -+ if (ret) -+ return ret; -+ -+ if (gdrm->compression & GUD_COMPRESSION_LZ4) { -+ gdrm->lz4_comp_mem = devm_kmalloc(dev, LZ4_MEM_COMPRESS, GFP_KERNEL); -+ if (!gdrm->lz4_comp_mem) -+ return -ENOMEM; -+ -+ gdrm->compress_buf = vmalloc(gdrm->bulk_len); -+ if (!gdrm->compress_buf) -+ return -ENOMEM; -+ } -+ -+ ret = drm_simple_display_pipe_init(drm, &gdrm->pipe, &gud_pipe_funcs, -+ formats, num_formats, -+ gud_pipe_modifiers, NULL); -+ if (ret) -+ return ret; -+ -+ devm_kfree(dev, formats); -+ devm_kfree(dev, formats_dev); -+ -+ ret = gud_get_properties(gdrm); -+ if (ret) { -+ dev_err(dev, "Failed to get properties (error=%d)\n", ret); -+ return ret; -+ } -+ -+ drm_plane_enable_fb_damage_clips(&gdrm->pipe.plane); -+ -+ ret = gud_get_connectors(gdrm); -+ if (ret) { -+ dev_err(dev, "Failed to get connectors (error=%d)\n", ret); -+ return ret; -+ } -+ -+ drm_mode_config_reset(drm); -+ -+ usb_set_intfdata(intf, gdrm); -+ -+ gdrm->dmadev = usb_intf_get_dma_device(intf); -+ if (!gdrm->dmadev) -+ dev_warn(dev, "buffer sharing not supported"); -+ -+ ret = drm_dev_register(drm, 0); -+ if (ret) { -+ put_device(gdrm->dmadev); -+ return ret; -+ } -+ -+ drm_kms_helper_poll_init(drm); -+ -+ drm_fbdev_generic_setup(drm, 0); -+ -+ return 0; -+} -+ -+static void gud_disconnect(struct usb_interface *interface) -+{ -+ struct gud_device *gdrm = usb_get_intfdata(interface); -+ struct drm_device *drm = &gdrm->drm; -+ -+ drm_dbg(drm, "%s:\n", __func__); -+ -+ drm_kms_helper_poll_fini(drm); -+ drm_dev_unplug(drm); -+ drm_atomic_helper_shutdown(drm); -+ put_device(gdrm->dmadev); -+ gdrm->dmadev = NULL; -+} -+ -+static int gud_suspend(struct usb_interface *intf, pm_message_t message) -+{ -+ struct gud_device *gdrm = usb_get_intfdata(intf); -+ -+ return drm_mode_config_helper_suspend(&gdrm->drm); -+} -+ -+static int gud_resume(struct usb_interface *intf) -+{ -+ struct gud_device *gdrm = usb_get_intfdata(intf); -+ -+ drm_mode_config_helper_resume(&gdrm->drm); -+ -+ return 0; -+} -+ -+static const struct usb_device_id gud_id_table[] = { -+ { USB_DEVICE_INTERFACE_CLASS(0x1d50, 0x614d, USB_CLASS_VENDOR_SPEC) }, -+ { USB_DEVICE_INTERFACE_CLASS(0x16d0, 0x10a9, USB_CLASS_VENDOR_SPEC) }, -+ { } -+}; -+ -+MODULE_DEVICE_TABLE(usb, gud_id_table); -+ -+static struct usb_driver gud_usb_driver = { -+ .name = "gud", -+ .probe = gud_probe, -+ .disconnect = gud_disconnect, -+ .id_table = gud_id_table, -+ .suspend = gud_suspend, -+ .resume = gud_resume, -+ .reset_resume = gud_resume, -+}; -+ -+module_usb_driver(gud_usb_driver); -+ -+MODULE_AUTHOR("Noralf Trønnes"); -+MODULE_LICENSE("Dual MIT/GPL"); -diff --git a/drivers/gpu/drm/gud/gud_internal.h b/drivers/gpu/drm/gud/gud_internal.h -new file mode 100644 -index 000000000000..2a388e27d5d7 ---- /dev/null -+++ b/drivers/gpu/drm/gud/gud_internal.h -@@ -0,0 +1,156 @@ -+/* SPDX-License-Identifier: MIT */ -+ -+#ifndef __LINUX_GUD_INTERNAL_H -+#define __LINUX_GUD_INTERNAL_H -+ -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+ -+struct gud_device { -+ struct drm_device drm; -+ struct drm_simple_display_pipe pipe; -+ struct device *dmadev; -+ struct work_struct work; -+ u32 flags; -+ const struct drm_format_info *xrgb8888_emulation_format; -+ -+ u16 *properties; -+ unsigned int num_properties; -+ -+ unsigned int bulk_pipe; -+ void *bulk_buf; -+ size_t bulk_len; -+ struct sg_table bulk_sgt; -+ -+ u8 compression; -+ void *lz4_comp_mem; -+ void *compress_buf; -+ -+ u64 stats_length; -+ u64 stats_actual_length; -+ unsigned int stats_num_errors; -+ -+ struct mutex ctrl_lock; /* Serialize get/set and status transfers */ -+ -+ struct mutex damage_lock; /* Protects the following members: */ -+ struct drm_framebuffer *fb; -+ struct drm_rect damage; -+ bool prev_flush_failed; -+}; -+ -+static inline struct gud_device *to_gud_device(struct drm_device *drm) -+{ -+ return container_of(drm, struct gud_device, drm); -+} -+ -+static inline struct usb_device *gud_to_usb_device(struct gud_device *gdrm) -+{ -+ return interface_to_usbdev(to_usb_interface(gdrm->drm.dev)); -+} -+ -+int gud_usb_get(struct gud_device *gdrm, u8 request, u16 index, void *buf, size_t len); -+int gud_usb_set(struct gud_device *gdrm, u8 request, u16 index, void *buf, size_t len); -+int gud_usb_get_u8(struct gud_device *gdrm, u8 request, u16 index, u8 *val); -+int gud_usb_set_u8(struct gud_device *gdrm, u8 request, u8 val); -+ -+void gud_clear_damage(struct gud_device *gdrm); -+void gud_flush_work(struct work_struct *work); -+int gud_pipe_check(struct drm_simple_display_pipe *pipe, -+ struct drm_plane_state *new_plane_state, -+ struct drm_crtc_state *new_crtc_state); -+void gud_pipe_update(struct drm_simple_display_pipe *pipe, -+ struct drm_plane_state *old_state); -+int gud_connector_fill_properties(struct drm_connector_state *connector_state, -+ struct gud_property_req *properties); -+int gud_get_connectors(struct gud_device *gdrm); -+ -+/* Driver internal fourcc transfer formats */ -+#define GUD_DRM_FORMAT_R1 0x00000122 -+#define GUD_DRM_FORMAT_XRGB1111 0x03121722 -+ -+static inline u8 gud_from_fourcc(u32 fourcc) -+{ -+ switch (fourcc) { -+ case GUD_DRM_FORMAT_R1: -+ return GUD_PIXEL_FORMAT_R1; -+ case GUD_DRM_FORMAT_XRGB1111: -+ return GUD_PIXEL_FORMAT_XRGB1111; -+ case DRM_FORMAT_RGB565: -+ return GUD_PIXEL_FORMAT_RGB565; -+ case DRM_FORMAT_XRGB8888: -+ return GUD_PIXEL_FORMAT_XRGB8888; -+ case DRM_FORMAT_ARGB8888: -+ return GUD_PIXEL_FORMAT_ARGB8888; -+ } -+ -+ return 0; -+} -+ -+static inline u32 gud_to_fourcc(u8 format) -+{ -+ switch (format) { -+ case GUD_PIXEL_FORMAT_R1: -+ return GUD_DRM_FORMAT_R1; -+ case GUD_PIXEL_FORMAT_XRGB1111: -+ return GUD_DRM_FORMAT_XRGB1111; -+ case GUD_PIXEL_FORMAT_RGB565: -+ return DRM_FORMAT_RGB565; -+ case GUD_PIXEL_FORMAT_XRGB8888: -+ return DRM_FORMAT_XRGB8888; -+ case GUD_PIXEL_FORMAT_ARGB8888: -+ return DRM_FORMAT_ARGB8888; -+ } -+ -+ return 0; -+} -+ -+static inline void gud_from_display_mode(struct gud_display_mode_req *dst, -+ const struct drm_display_mode *src) -+{ -+ u32 flags = src->flags & GUD_DISPLAY_MODE_FLAG_USER_MASK; -+ -+ if (src->type & DRM_MODE_TYPE_PREFERRED) -+ flags |= GUD_DISPLAY_MODE_FLAG_PREFERRED; -+ -+ dst->clock = cpu_to_le32(src->clock); -+ dst->hdisplay = cpu_to_le16(src->hdisplay); -+ dst->hsync_start = cpu_to_le16(src->hsync_start); -+ dst->hsync_end = cpu_to_le16(src->hsync_end); -+ dst->htotal = cpu_to_le16(src->htotal); -+ dst->vdisplay = cpu_to_le16(src->vdisplay); -+ dst->vsync_start = cpu_to_le16(src->vsync_start); -+ dst->vsync_end = cpu_to_le16(src->vsync_end); -+ dst->vtotal = cpu_to_le16(src->vtotal); -+ dst->flags = cpu_to_le32(flags); -+} -+ -+static inline void gud_to_display_mode(struct drm_display_mode *dst, -+ const struct gud_display_mode_req *src) -+{ -+ u32 flags = le32_to_cpu(src->flags); -+ -+ memset(dst, 0, sizeof(*dst)); -+ dst->clock = le32_to_cpu(src->clock); -+ dst->hdisplay = le16_to_cpu(src->hdisplay); -+ dst->hsync_start = le16_to_cpu(src->hsync_start); -+ dst->hsync_end = le16_to_cpu(src->hsync_end); -+ dst->htotal = le16_to_cpu(src->htotal); -+ dst->vdisplay = le16_to_cpu(src->vdisplay); -+ dst->vsync_start = le16_to_cpu(src->vsync_start); -+ dst->vsync_end = le16_to_cpu(src->vsync_end); -+ dst->vtotal = le16_to_cpu(src->vtotal); -+ dst->flags = flags & GUD_DISPLAY_MODE_FLAG_USER_MASK; -+ dst->type = DRM_MODE_TYPE_DRIVER; -+ if (flags & GUD_DISPLAY_MODE_FLAG_PREFERRED) -+ dst->type |= DRM_MODE_TYPE_PREFERRED; -+ drm_mode_set_name(dst); -+} -+ -+#endif -diff --git a/drivers/gpu/drm/gud/gud_pipe.c b/drivers/gpu/drm/gud/gud_pipe.c -new file mode 100644 -index 000000000000..d04e777ccb37 ---- /dev/null -+++ b/drivers/gpu/drm/gud/gud_pipe.c -@@ -0,0 +1,601 @@ -+// SPDX-License-Identifier: MIT -+/* -+ * Copyright 2020 Noralf Trønnes -+ */ -+ -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include "gud_internal.h" -+ -+/* -+ * Some userspace rendering loops runs all displays in the same loop. -+ * This means that a fast display will have to wait for a slow one. -+ * For this reason gud does flushing asynchronous by default. -+ * The down side is that in e.g. a single display setup userspace thinks -+ * the display is insanely fast since the driver reports back immediately -+ * that the flush/pageflip is done. This wastes CPU and power. -+ * Such users might want to set this module parameter to false. -+ */ -+static bool gud_async_flush = true; -+module_param_named(async_flush, gud_async_flush, bool, 0644); -+MODULE_PARM_DESC(async_flush, "Enable asynchronous flushing [default=true]"); -+ -+/* -+ * FIXME: The driver is probably broken on Big Endian machines. -+ * See discussion: -+ * https://lore.kernel.org/dri-devel/CAKb7UvihLX0hgBOP3VBG7O+atwZcUVCPVuBdfmDMpg0NjXe-cQ@mail.gmail.com/ -+ */ -+ -+static bool gud_is_big_endian(void) -+{ -+#if defined(__BIG_ENDIAN) -+ return true; -+#else -+ return false; -+#endif -+} -+ -+static size_t gud_xrgb8888_to_r124(u8 *dst, const struct drm_format_info *format, -+ void *src, struct drm_framebuffer *fb, -+ struct drm_rect *rect) -+{ -+ unsigned int block_width = drm_format_info_block_width(format, 0); -+ unsigned int bits_per_pixel = 8 / block_width; -+ unsigned int x, y, width, height; -+ u8 pix, *pix8, *block = dst; /* Assign to silence compiler warning */ -+ size_t len; -+ void *buf; -+ -+ WARN_ON_ONCE(format->char_per_block[0] != 1); -+ -+ /* Start on a byte boundary */ -+ rect->x1 = ALIGN_DOWN(rect->x1, block_width); -+ width = drm_rect_width(rect); -+ height = drm_rect_height(rect); -+ len = drm_format_info_min_pitch(format, 0, width) * height; -+ -+ buf = kmalloc(width * height, GFP_KERNEL); -+ if (!buf) -+ return 0; -+ -+ drm_fb_xrgb8888_to_gray8(buf, src, fb, rect); -+ pix8 = buf; -+ -+ for (y = 0; y < height; y++) { -+ for (x = 0; x < width; x++) { -+ unsigned int pixpos = x % block_width; /* within byte from the left */ -+ unsigned int pixshift = (block_width - pixpos - 1) * bits_per_pixel; -+ -+ if (!pixpos) { -+ block = dst++; -+ *block = 0; -+ } -+ -+ pix = (*pix8++) >> (8 - bits_per_pixel); -+ *block |= pix << pixshift; -+ } -+ } -+ -+ kfree(buf); -+ -+ return len; -+} -+ -+static size_t gud_xrgb8888_to_color(u8 *dst, const struct drm_format_info *format, -+ void *src, struct drm_framebuffer *fb, -+ struct drm_rect *rect) -+{ -+ unsigned int block_width = drm_format_info_block_width(format, 0); -+ unsigned int bits_per_pixel = 8 / block_width; -+ u8 r, g, b, pix, *block = dst; /* Assign to silence compiler warning */ -+ unsigned int x, y, width; -+ u32 *pix32; -+ size_t len; -+ -+ /* Start on a byte boundary */ -+ rect->x1 = ALIGN_DOWN(rect->x1, block_width); -+ width = drm_rect_width(rect); -+ len = drm_format_info_min_pitch(format, 0, width) * drm_rect_height(rect); -+ -+ for (y = rect->y1; y < rect->y2; y++) { -+ pix32 = src + (y * fb->pitches[0]); -+ pix32 += rect->x1; -+ -+ for (x = 0; x < width; x++) { -+ unsigned int pixpos = x % block_width; /* within byte from the left */ -+ unsigned int pixshift = (block_width - pixpos - 1) * bits_per_pixel; -+ -+ if (!pixpos) { -+ block = dst++; -+ *block = 0; -+ } -+ -+ r = *pix32 >> 16; -+ g = *pix32 >> 8; -+ b = *pix32++; -+ -+ switch (format->format) { -+ case GUD_DRM_FORMAT_XRGB1111: -+ pix = ((r >> 7) << 2) | ((g >> 7) << 1) | (b >> 7); -+ break; -+ default: -+ WARN_ON_ONCE(1); -+ return len; -+ } -+ -+ *block |= pix << pixshift; -+ } -+ } -+ -+ return len; -+} -+ -+static int gud_prep_flush(struct gud_device *gdrm, struct drm_framebuffer *fb, -+ const struct drm_format_info *format, struct drm_rect *rect, -+ struct gud_set_buffer_req *req) -+{ -+ struct dma_buf_attachment *import_attach = fb->obj[0]->import_attach; -+ u8 compression = gdrm->compression; -+ void *vmap, *vaddr, *buf; -+ size_t pitch, len; -+ int ret = 0; -+ -+ pitch = drm_format_info_min_pitch(format, 0, drm_rect_width(rect)); -+ len = pitch * drm_rect_height(rect); -+ if (len > gdrm->bulk_len) -+ return -E2BIG; -+ -+ vmap = drm_gem_shmem_vmap(fb->obj[0]); -+ if (!vmap) -+ return -ENOMEM; -+ -+ vaddr = vmap + fb->offsets[0]; -+ -+ if (import_attach) { -+ ret = dma_buf_begin_cpu_access(import_attach->dmabuf, DMA_FROM_DEVICE); -+ if (ret) -+ goto vunmap; -+ } -+retry: -+ if (compression) -+ buf = gdrm->compress_buf; -+ else -+ buf = gdrm->bulk_buf; -+ -+ /* -+ * Imported buffers are assumed to be write-combined and thus uncached -+ * with slow reads (at least on ARM). -+ */ -+ if (format != fb->format) { -+ if (format->format == GUD_DRM_FORMAT_R1) { -+ len = gud_xrgb8888_to_r124(buf, format, vaddr, fb, rect); -+ if (!len) { -+ ret = -ENOMEM; -+ goto end_cpu_access; -+ } -+ } else if (format->format == DRM_FORMAT_RGB565) { -+ drm_fb_xrgb8888_to_rgb565(buf, vaddr, fb, rect, gud_is_big_endian()); -+ } else { -+ len = gud_xrgb8888_to_color(buf, format, vaddr, fb, rect); -+ } -+ } else if (gud_is_big_endian() && format->cpp[0] > 1) { -+ drm_fb_swab(buf, vaddr, fb, rect, !import_attach); -+ } else if (compression && !import_attach && pitch == fb->pitches[0]) { -+ /* can compress directly from the framebuffer */ -+ buf = vaddr + rect->y1 * pitch; -+ } else { -+ drm_fb_memcpy(buf, vaddr, fb, rect); -+ } -+ -+ memset(req, 0, sizeof(*req)); -+ req->x = cpu_to_le32(rect->x1); -+ req->y = cpu_to_le32(rect->y1); -+ req->width = cpu_to_le32(drm_rect_width(rect)); -+ req->height = cpu_to_le32(drm_rect_height(rect)); -+ req->length = cpu_to_le32(len); -+ -+ if (compression & GUD_COMPRESSION_LZ4) { -+ int complen; -+ -+ complen = LZ4_compress_default(buf, gdrm->bulk_buf, len, len, gdrm->lz4_comp_mem); -+ if (complen <= 0) { -+ compression = 0; -+ goto retry; -+ } -+ -+ req->compression = GUD_COMPRESSION_LZ4; -+ req->compressed_length = cpu_to_le32(complen); -+ } -+ -+end_cpu_access: -+ if (import_attach) -+ dma_buf_end_cpu_access(import_attach->dmabuf, DMA_FROM_DEVICE); -+vunmap: -+ drm_gem_shmem_vunmap(fb->obj[0], vmap); -+ -+ return ret; -+} -+ -+struct gud_usb_bulk_context { -+ struct timer_list timer; -+ struct usb_sg_request sgr; -+}; -+ -+static void gud_usb_bulk_timeout(struct timer_list *t) -+{ -+ struct gud_usb_bulk_context *ctx = from_timer(ctx, t, timer); -+ -+ usb_sg_cancel(&ctx->sgr); -+} -+ -+static int gud_usb_bulk(struct gud_device *gdrm, size_t len) -+{ -+ struct gud_usb_bulk_context ctx; -+ int ret; -+ -+ ret = usb_sg_init(&ctx.sgr, gud_to_usb_device(gdrm), gdrm->bulk_pipe, 0, -+ gdrm->bulk_sgt.sgl, gdrm->bulk_sgt.nents, len, GFP_KERNEL); -+ if (ret) -+ return ret; -+ -+ timer_setup_on_stack(&ctx.timer, gud_usb_bulk_timeout, 0); -+ mod_timer(&ctx.timer, jiffies + msecs_to_jiffies(3000)); -+ -+ usb_sg_wait(&ctx.sgr); -+ -+ if (!del_timer_sync(&ctx.timer)) -+ ret = -ETIMEDOUT; -+ else if (ctx.sgr.status < 0) -+ ret = ctx.sgr.status; -+ else if (ctx.sgr.bytes != len) -+ ret = -EIO; -+ -+ destroy_timer_on_stack(&ctx.timer); -+ -+ return ret; -+} -+ -+static int gud_flush_rect(struct gud_device *gdrm, struct drm_framebuffer *fb, -+ const struct drm_format_info *format, struct drm_rect *rect) -+{ -+ struct gud_set_buffer_req req; -+ size_t len, trlen; -+ int ret; -+ -+ drm_dbg(&gdrm->drm, "Flushing [FB:%d] " DRM_RECT_FMT "\n", fb->base.id, DRM_RECT_ARG(rect)); -+ -+ ret = gud_prep_flush(gdrm, fb, format, rect, &req); -+ if (ret) -+ return ret; -+ -+ len = le32_to_cpu(req.length); -+ -+ if (req.compression) -+ trlen = le32_to_cpu(req.compressed_length); -+ else -+ trlen = len; -+ -+ gdrm->stats_length += len; -+ /* Did it wrap around? */ -+ if (gdrm->stats_length <= len && gdrm->stats_actual_length) { -+ gdrm->stats_length = len; -+ gdrm->stats_actual_length = 0; -+ } -+ gdrm->stats_actual_length += trlen; -+ -+ if (!(gdrm->flags & GUD_DISPLAY_FLAG_FULL_UPDATE) || gdrm->prev_flush_failed) { -+ ret = gud_usb_set(gdrm, GUD_REQ_SET_BUFFER, 0, &req, sizeof(req)); -+ if (ret) -+ return ret; -+ } -+ -+ ret = gud_usb_bulk(gdrm, trlen); -+ if (ret) -+ gdrm->stats_num_errors++; -+ -+ return ret; -+} -+ -+void gud_clear_damage(struct gud_device *gdrm) -+{ -+ gdrm->damage.x1 = INT_MAX; -+ gdrm->damage.y1 = INT_MAX; -+ gdrm->damage.x2 = 0; -+ gdrm->damage.y2 = 0; -+} -+ -+static void gud_add_damage(struct gud_device *gdrm, struct drm_rect *damage) -+{ -+ gdrm->damage.x1 = min(gdrm->damage.x1, damage->x1); -+ gdrm->damage.y1 = min(gdrm->damage.y1, damage->y1); -+ gdrm->damage.x2 = max(gdrm->damage.x2, damage->x2); -+ gdrm->damage.y2 = max(gdrm->damage.y2, damage->y2); -+} -+ -+static void gud_retry_failed_flush(struct gud_device *gdrm, struct drm_framebuffer *fb, -+ struct drm_rect *damage) -+{ -+ /* -+ * pipe_update waits for the worker when the display mode is going to change. -+ * This ensures that the width and height is still the same making it safe to -+ * add back the damage. -+ */ -+ -+ mutex_lock(&gdrm->damage_lock); -+ if (!gdrm->fb) { -+ drm_framebuffer_get(fb); -+ gdrm->fb = fb; -+ } -+ gud_add_damage(gdrm, damage); -+ mutex_unlock(&gdrm->damage_lock); -+ -+ /* Retry only once to avoid a possible storm in case of continues errors. */ -+ if (!gdrm->prev_flush_failed) -+ queue_work(system_long_wq, &gdrm->work); -+ gdrm->prev_flush_failed = true; -+} -+ -+void gud_flush_work(struct work_struct *work) -+{ -+ struct gud_device *gdrm = container_of(work, struct gud_device, work); -+ const struct drm_format_info *format; -+ struct drm_framebuffer *fb; -+ struct drm_rect damage; -+ unsigned int i, lines; -+ int idx, ret = 0; -+ size_t pitch; -+ -+ if (!drm_dev_enter(&gdrm->drm, &idx)) -+ return; -+ -+ mutex_lock(&gdrm->damage_lock); -+ fb = gdrm->fb; -+ gdrm->fb = NULL; -+ damage = gdrm->damage; -+ gud_clear_damage(gdrm); -+ mutex_unlock(&gdrm->damage_lock); -+ -+ if (!fb) -+ goto out; -+ -+ format = fb->format; -+ if (format->format == DRM_FORMAT_XRGB8888 && gdrm->xrgb8888_emulation_format) -+ format = gdrm->xrgb8888_emulation_format; -+ -+ /* Split update if it's too big */ -+ pitch = drm_format_info_min_pitch(format, 0, drm_rect_width(&damage)); -+ lines = drm_rect_height(&damage); -+ -+ if (gdrm->bulk_len < lines * pitch) -+ lines = gdrm->bulk_len / pitch; -+ -+ for (i = 0; i < DIV_ROUND_UP(drm_rect_height(&damage), lines); i++) { -+ struct drm_rect rect = damage; -+ -+ rect.y1 += i * lines; -+ rect.y2 = min_t(u32, rect.y1 + lines, damage.y2); -+ -+ ret = gud_flush_rect(gdrm, fb, format, &rect); -+ if (ret) { -+ if (ret != -ENODEV && ret != -ECONNRESET && -+ ret != -ESHUTDOWN && ret != -EPROTO) { -+ bool prev_flush_failed = gdrm->prev_flush_failed; -+ -+ gud_retry_failed_flush(gdrm, fb, &damage); -+ if (!prev_flush_failed) -+ dev_err_ratelimited(fb->dev->dev, -+ "Failed to flush framebuffer: error=%d\n", ret); -+ } -+ break; -+ } -+ -+ gdrm->prev_flush_failed = false; -+ } -+ -+ drm_framebuffer_put(fb); -+out: -+ drm_dev_exit(idx); -+} -+ -+static void gud_fb_queue_damage(struct gud_device *gdrm, struct drm_framebuffer *fb, -+ struct drm_rect *damage) -+{ -+ struct drm_framebuffer *old_fb = NULL; -+ -+ mutex_lock(&gdrm->damage_lock); -+ -+ if (fb != gdrm->fb) { -+ old_fb = gdrm->fb; -+ drm_framebuffer_get(fb); -+ gdrm->fb = fb; -+ } -+ -+ gud_add_damage(gdrm, damage); -+ -+ mutex_unlock(&gdrm->damage_lock); -+ -+ queue_work(system_long_wq, &gdrm->work); -+ -+ if (old_fb) -+ drm_framebuffer_put(old_fb); -+} -+ -+int gud_pipe_check(struct drm_simple_display_pipe *pipe, -+ struct drm_plane_state *new_plane_state, -+ struct drm_crtc_state *new_crtc_state) -+{ -+ struct gud_device *gdrm = to_gud_device(pipe->crtc.dev); -+ struct drm_plane_state *old_plane_state = pipe->plane.state; -+ const struct drm_display_mode *mode = &new_crtc_state->mode; -+ struct drm_atomic_state *state = new_plane_state->state; -+ struct drm_framebuffer *old_fb = old_plane_state->fb; -+ struct drm_connector_state *connector_state = NULL; -+ struct drm_framebuffer *fb = new_plane_state->fb; -+ const struct drm_format_info *format = fb->format; -+ struct drm_connector *connector; -+ unsigned int i, num_properties; -+ struct gud_state_req *req; -+ int idx, ret; -+ size_t len; -+ -+ if (WARN_ON_ONCE(!fb)) -+ return -EINVAL; -+ -+ if (old_plane_state->rotation != new_plane_state->rotation) -+ new_crtc_state->mode_changed = true; -+ -+ if (old_fb && old_fb->format != format) -+ new_crtc_state->mode_changed = true; -+ -+ if (!new_crtc_state->mode_changed && !new_crtc_state->connectors_changed) -+ return 0; -+ -+ /* Only one connector is supported */ -+ if (hweight32(new_crtc_state->connector_mask) != 1) -+ return -EINVAL; -+ -+ if (format->format == DRM_FORMAT_XRGB8888 && gdrm->xrgb8888_emulation_format) -+ format = gdrm->xrgb8888_emulation_format; -+ -+ for_each_new_connector_in_state(state, connector, connector_state, i) { -+ if (connector_state->crtc) -+ break; -+ } -+ -+ /* -+ * DRM_IOCTL_MODE_OBJ_SETPROPERTY on the rotation property will not have -+ * the connector included in the state. -+ */ -+ if (!connector_state) { -+ struct drm_connector_list_iter conn_iter; -+ -+ drm_connector_list_iter_begin(pipe->crtc.dev, &conn_iter); -+ drm_for_each_connector_iter(connector, &conn_iter) { -+ if (connector->state->crtc) { -+ connector_state = connector->state; -+ break; -+ } -+ } -+ drm_connector_list_iter_end(&conn_iter); -+ } -+ -+ if (WARN_ON_ONCE(!connector_state)) -+ return -ENOENT; -+ -+ len = struct_size(req, properties, -+ GUD_PROPERTIES_MAX_NUM + GUD_CONNECTOR_PROPERTIES_MAX_NUM); -+ req = kzalloc(len, GFP_KERNEL); -+ if (!req) -+ return -ENOMEM; -+ -+ gud_from_display_mode(&req->mode, mode); -+ -+ req->format = gud_from_fourcc(format->format); -+ if (WARN_ON_ONCE(!req->format)) { -+ ret = -EINVAL; -+ goto out; -+ } -+ -+ req->connector = drm_connector_index(connector_state->connector); -+ -+ ret = gud_connector_fill_properties(connector_state, req->properties); -+ if (ret < 0) -+ goto out; -+ -+ num_properties = ret; -+ for (i = 0; i < gdrm->num_properties; i++) { -+ u16 prop = gdrm->properties[i]; -+ u64 val; -+ -+ switch (prop) { -+ case GUD_PROPERTY_ROTATION: -+ /* DRM UAPI matches the protocol so use value directly */ -+ val = new_plane_state->rotation; -+ break; -+ default: -+ WARN_ON_ONCE(1); -+ ret = -EINVAL; -+ goto out; -+ } -+ -+ req->properties[num_properties + i].prop = cpu_to_le16(prop); -+ req->properties[num_properties + i].val = cpu_to_le64(val); -+ num_properties++; -+ } -+ -+ if (drm_dev_enter(fb->dev, &idx)) { -+ len = struct_size(req, properties, num_properties); -+ ret = gud_usb_set(gdrm, GUD_REQ_SET_STATE_CHECK, 0, req, len); -+ drm_dev_exit(idx); -+ } else { -+ ret = -ENODEV; -+ } -+out: -+ kfree(req); -+ -+ return ret; -+} -+ -+void gud_pipe_update(struct drm_simple_display_pipe *pipe, -+ struct drm_plane_state *old_state) -+{ -+ struct drm_device *drm = pipe->crtc.dev; -+ struct gud_device *gdrm = to_gud_device(drm); -+ struct drm_plane_state *state = pipe->plane.state; -+ struct drm_framebuffer *fb = state->fb; -+ struct drm_crtc *crtc = &pipe->crtc; -+ struct drm_rect damage; -+ int idx; -+ -+ if (crtc->state->mode_changed || !crtc->state->enable) { -+ cancel_work_sync(&gdrm->work); -+ mutex_lock(&gdrm->damage_lock); -+ if (gdrm->fb) { -+ drm_framebuffer_put(gdrm->fb); -+ gdrm->fb = NULL; -+ } -+ gud_clear_damage(gdrm); -+ mutex_unlock(&gdrm->damage_lock); -+ } -+ -+ if (!drm_dev_enter(drm, &idx)) -+ return; -+ -+ if (!old_state->fb) -+ gud_usb_set_u8(gdrm, GUD_REQ_SET_CONTROLLER_ENABLE, 1); -+ -+ if (fb && (crtc->state->mode_changed || crtc->state->connectors_changed)) -+ gud_usb_set(gdrm, GUD_REQ_SET_STATE_COMMIT, 0, NULL, 0); -+ -+ if (crtc->state->active_changed) -+ gud_usb_set_u8(gdrm, GUD_REQ_SET_DISPLAY_ENABLE, crtc->state->active); -+ -+ if (drm_atomic_helper_damage_merged(old_state, state, &damage)) { -+ if (gdrm->flags & GUD_DISPLAY_FLAG_FULL_UPDATE) -+ drm_rect_init(&damage, 0, 0, fb->width, fb->height); -+ gud_fb_queue_damage(gdrm, fb, &damage); -+ if (!gud_async_flush) -+ flush_work(&gdrm->work); -+ } -+ -+ if (!crtc->state->enable) -+ gud_usb_set_u8(gdrm, GUD_REQ_SET_CONTROLLER_ENABLE, 0); -+ -+ drm_dev_exit(idx); -+} -diff --git a/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c b/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c -index 4d57ec688f82..567f578740bd 100644 ---- a/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c -+++ b/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c -@@ -172,7 +172,7 @@ static void hibmc_crtc_dpms(struct drm_crtc *crtc, int dpms) - } - - static void hibmc_crtc_atomic_enable(struct drm_crtc *crtc, -- struct drm_crtc_state *old_state) -+ struct drm_atomic_state *state) - { - unsigned int reg; - struct hibmc_drm_private *priv = crtc->dev->dev_private; -@@ -191,7 +191,7 @@ static void hibmc_crtc_atomic_enable(struct drm_crtc *crtc, - } - - static void hibmc_crtc_atomic_disable(struct drm_crtc *crtc, -- struct drm_crtc_state *old_state) -+ struct drm_atomic_state *state) - { - unsigned int reg; - struct hibmc_drm_private *priv = crtc->dev->dev_private; -@@ -393,7 +393,7 @@ static void hibmc_crtc_mode_set_nofb(struct drm_crtc *crtc) - } - - static void hibmc_crtc_atomic_begin(struct drm_crtc *crtc, -- struct drm_crtc_state *old_state) -+ struct drm_atomic_state *state) - { - unsigned int reg; - struct drm_device *dev = crtc->dev; -@@ -413,7 +413,7 @@ static void hibmc_crtc_atomic_begin(struct drm_crtc *crtc, - } - - static void hibmc_crtc_atomic_flush(struct drm_crtc *crtc, -- struct drm_crtc_state *old_state) -+ struct drm_atomic_state *state) - - { - unsigned long flags; -diff --git a/drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c b/drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c -index e1108c1735ad..d84d41f3e78f 100644 ---- a/drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c -+++ b/drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c -@@ -436,7 +436,7 @@ static void ade_dump_regs(void __iomem *base) { } - #endif - - static void ade_crtc_atomic_enable(struct drm_crtc *crtc, -- struct drm_crtc_state *old_state) -+ struct drm_atomic_state *state) - { - struct kirin_crtc *kcrtc = to_kirin_crtc(crtc); - struct ade_hw_ctx *ctx = kcrtc->hw_ctx; -@@ -459,7 +459,7 @@ static void ade_crtc_atomic_enable(struct drm_crtc *crtc, - } - - static void ade_crtc_atomic_disable(struct drm_crtc *crtc, -- struct drm_crtc_state *old_state) -+ struct drm_atomic_state *state) - { - struct kirin_crtc *kcrtc = to_kirin_crtc(crtc); - struct ade_hw_ctx *ctx = kcrtc->hw_ctx; -@@ -485,7 +485,7 @@ static void ade_crtc_mode_set_nofb(struct drm_crtc *crtc) - } - - static void ade_crtc_atomic_begin(struct drm_crtc *crtc, -- struct drm_crtc_state *old_state) -+ struct drm_atomic_state *state) - { - struct kirin_crtc *kcrtc = to_kirin_crtc(crtc); - struct ade_hw_ctx *ctx = kcrtc->hw_ctx; -@@ -498,7 +498,7 @@ static void ade_crtc_atomic_begin(struct drm_crtc *crtc, - } - - static void ade_crtc_atomic_flush(struct drm_crtc *crtc, -- struct drm_crtc_state *old_state) -+ struct drm_atomic_state *state) - - { - struct kirin_crtc *kcrtc = to_kirin_crtc(crtc); -diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c b/drivers/gpu/drm/i915/display/intel_atomic.c -index 86be032bcf96..b18417a393af 100644 ---- a/drivers/gpu/drm/i915/display/intel_atomic.c -+++ b/drivers/gpu/drm/i915/display/intel_atomic.c -@@ -109,16 +109,6 @@ int intel_digital_connector_atomic_set_property(struct drm_connector *connector, - return -EINVAL; - } - --static bool blob_equal(const struct drm_property_blob *a, -- const struct drm_property_blob *b) --{ -- if (a && b) -- return a->length == b->length && -- !memcmp(a->data, b->data, a->length); -- -- return !a == !b; --} -- - int intel_digital_connector_atomic_check(struct drm_connector *conn, - struct drm_atomic_state *state) - { -@@ -150,8 +140,7 @@ int intel_digital_connector_atomic_check(struct drm_connector *conn, - new_conn_state->base.picture_aspect_ratio != old_conn_state->base.picture_aspect_ratio || - new_conn_state->base.content_type != old_conn_state->base.content_type || - new_conn_state->base.scaling_mode != old_conn_state->base.scaling_mode || -- !blob_equal(new_conn_state->base.hdr_output_metadata, -- old_conn_state->base.hdr_output_metadata)) -+ !drm_connector_atomic_hdr_metadata_equal(old_state, new_state)) - crtc_state->mode_changed = true; - - return 0; -diff --git a/drivers/gpu/drm/i915/display/intel_connector.c b/drivers/gpu/drm/i915/display/intel_connector.c -index 406e96785c76..d1f8c7f3d197 100644 ---- a/drivers/gpu/drm/i915/display/intel_connector.c -+++ b/drivers/gpu/drm/i915/display/intel_connector.c -@@ -297,6 +297,5 @@ intel_attach_colorspace_property(struct drm_connector *connector) - return; - } - -- drm_object_attach_property(&connector->base, -- connector->colorspace_property, 0); -+ drm_connector_attach_colorspace_property(connector); - } + static void __intel_backlight_enable(const struct intel_crtc_state *crtc_state, diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c -index 45c2556d6395..32f440223bd1 100644 +index a072fbb9872a..066a3cd74df1 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c -@@ -16562,7 +16562,6 @@ intel_cursor_plane_create(struct drm_i915_private *dev_priv, - } - - #define INTEL_CRTC_FUNCS \ -- .gamma_set = drm_atomic_helper_legacy_gamma_set, \ - .set_config = drm_atomic_helper_set_config, \ - .destroy = intel_crtc_destroy, \ - .page_flip = drm_atomic_helper_page_flip, \ -diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c -index ecaa538b2d35..3e5558def1c5 100644 ---- a/drivers/gpu/drm/i915/display/intel_dp_mst.c -+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c -@@ -23,6 +23,7 @@ - * - */ - -+#include - #include - #include - #include -@@ -708,11 +709,13 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector *connector, - } - - static struct drm_encoder *intel_mst_atomic_best_encoder(struct drm_connector *connector, -- struct drm_connector_state *state) -+ struct drm_atomic_state *state) - { -+ struct drm_connector_state *connector_state = drm_atomic_get_new_connector_state(state, -+ connector); - struct intel_connector *intel_connector = to_intel_connector(connector); - struct intel_dp *intel_dp = intel_connector->mst_port; -- struct intel_crtc *crtc = to_intel_crtc(state->crtc); -+ struct intel_crtc *crtc = to_intel_crtc(connector_state->crtc); - - return &intel_dp->mst_encoders[crtc->pipe]->base.base; - } -diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c -index 1d616da4f165..030b4d5ab829 100644 ---- a/drivers/gpu/drm/i915/display/intel_hdmi.c -+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c -@@ -746,7 +746,7 @@ intel_hdmi_compute_avi_infoframe(struct intel_encoder *encoder, - else - frame->colorspace = HDMI_COLORSPACE_RGB; - -- drm_hdmi_avi_infoframe_colorspace(frame, conn_state); -+ drm_hdmi_avi_infoframe_colorimetry(frame, conn_state); - - /* nonsense combination */ - drm_WARN_ON(encoder->base.dev, crtc_state->limited_color_range && -@@ -2971,8 +2971,7 @@ intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *c - drm_connector_attach_content_type_property(connector); - - if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) -- drm_object_attach_property(&connector->base, -- connector->dev->mode_config.hdr_output_metadata_property, 0); -+ drm_connector_attach_hdr_output_metadata_property(connector); - - if (!HAS_GMCH(dev_priv)) - drm_connector_attach_max_bpc_property(connector, 8, 12); -diff --git a/drivers/gpu/drm/imx/dcss/dcss-crtc.c b/drivers/gpu/drm/imx/dcss/dcss-crtc.c -index 36abff0890b2..31267c00782f 100644 ---- a/drivers/gpu/drm/imx/dcss/dcss-crtc.c -+++ b/drivers/gpu/drm/imx/dcss/dcss-crtc.c -@@ -3,6 +3,7 @@ - * Copyright 2019 NXP. - */ - -+#include - #include - #include - #include -@@ -52,13 +53,13 @@ static const struct drm_crtc_funcs dcss_crtc_funcs = { - }; - - static void dcss_crtc_atomic_begin(struct drm_crtc *crtc, -- struct drm_crtc_state *old_crtc_state) -+ struct drm_atomic_state *state) - { - drm_crtc_vblank_on(crtc); - } - - static void dcss_crtc_atomic_flush(struct drm_crtc *crtc, -- struct drm_crtc_state *old_crtc_state) -+ struct drm_atomic_state *state) - { - struct dcss_crtc *dcss_crtc = container_of(crtc, struct dcss_crtc, - base); -@@ -77,8 +78,10 @@ static void dcss_crtc_atomic_flush(struct drm_crtc *crtc, - } - - static void dcss_crtc_atomic_enable(struct drm_crtc *crtc, -- struct drm_crtc_state *old_crtc_state) -+ struct drm_atomic_state *state) - { -+ struct drm_crtc_state *old_crtc_state = drm_atomic_get_old_crtc_state(state, -+ crtc); - struct dcss_crtc *dcss_crtc = container_of(crtc, struct dcss_crtc, - base); - struct dcss_dev *dcss = dcss_crtc->base.dev->dev_private; -@@ -111,8 +114,10 @@ static void dcss_crtc_atomic_enable(struct drm_crtc *crtc, - } - - static void dcss_crtc_atomic_disable(struct drm_crtc *crtc, -- struct drm_crtc_state *old_crtc_state) -+ struct drm_atomic_state *state) - { -+ struct drm_crtc_state *old_crtc_state = drm_atomic_get_old_crtc_state(state, -+ crtc); - struct dcss_crtc *dcss_crtc = container_of(crtc, struct dcss_crtc, - base); - struct dcss_dev *dcss = dcss_crtc->base.dev->dev_private; -diff --git a/drivers/gpu/drm/imx/ipuv3-crtc.c b/drivers/gpu/drm/imx/ipuv3-crtc.c -index d412fc265395..7ebd99ee3240 100644 ---- a/drivers/gpu/drm/imx/ipuv3-crtc.c -+++ b/drivers/gpu/drm/imx/ipuv3-crtc.c -@@ -47,7 +47,7 @@ static inline struct ipu_crtc *to_ipu_crtc(struct drm_crtc *crtc) - } - - static void ipu_crtc_atomic_enable(struct drm_crtc *crtc, -- struct drm_crtc_state *old_state) -+ struct drm_atomic_state *state) - { - struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc); - struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent); -@@ -79,8 +79,10 @@ static void ipu_crtc_disable_planes(struct ipu_crtc *ipu_crtc, - } - - static void ipu_crtc_atomic_disable(struct drm_crtc *crtc, -- struct drm_crtc_state *old_crtc_state) -+ struct drm_atomic_state *state) - { -+ struct drm_crtc_state *old_crtc_state = drm_atomic_get_old_crtc_state(state, -+ crtc); - struct ipu_crtc *ipu_crtc = to_ipu_crtc(crtc); - struct ipu_soc *ipu = dev_get_drvdata(ipu_crtc->dev->parent); - -@@ -225,24 +227,26 @@ static bool ipu_crtc_mode_fixup(struct drm_crtc *crtc, - } - - static int ipu_crtc_atomic_check(struct drm_crtc *crtc, -- struct drm_crtc_state *state) -+ struct drm_atomic_state *state) - { -+ struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, -+ crtc); - u32 primary_plane_mask = drm_plane_mask(crtc->primary); - -- if (state->active && (primary_plane_mask & state->plane_mask) == 0) -+ if (crtc_state->active && (primary_plane_mask & crtc_state->plane_mask) == 0) - return -EINVAL; - - return 0; - } - - static void ipu_crtc_atomic_begin(struct drm_crtc *crtc, -- struct drm_crtc_state *old_crtc_state) -+ struct drm_atomic_state *state) - { - drm_crtc_vblank_on(crtc); - } - - static void ipu_crtc_atomic_flush(struct drm_crtc *crtc, -- struct drm_crtc_state *old_crtc_state) -+ struct drm_atomic_state *state) - { - spin_lock_irq(&crtc->dev->event_lock); - if (crtc->state->event) { -diff --git a/drivers/gpu/drm/ingenic/ingenic-drm-drv.c b/drivers/gpu/drm/ingenic/ingenic-drm-drv.c -index b6bb5fc7d183..0f52e5f4aa2f 100644 ---- a/drivers/gpu/drm/ingenic/ingenic-drm-drv.c -+++ b/drivers/gpu/drm/ingenic/ingenic-drm-drv.c -@@ -112,7 +112,7 @@ static inline struct ingenic_drm *drm_crtc_get_priv(struct drm_crtc *crtc) - } - - static void ingenic_drm_crtc_atomic_enable(struct drm_crtc *crtc, -- struct drm_crtc_state *state) -+ struct drm_atomic_state *state) - { - struct ingenic_drm *priv = drm_crtc_get_priv(crtc); - -@@ -126,7 +126,7 @@ static void ingenic_drm_crtc_atomic_enable(struct drm_crtc *crtc, - } - - static void ingenic_drm_crtc_atomic_disable(struct drm_crtc *crtc, -- struct drm_crtc_state *state) -+ struct drm_atomic_state *state) - { - struct ingenic_drm *priv = drm_crtc_get_priv(crtc); - unsigned int var; -@@ -195,22 +195,27 @@ static void ingenic_drm_crtc_update_timings(struct ingenic_drm *priv, - } - - static int ingenic_drm_crtc_atomic_check(struct drm_crtc *crtc, -- struct drm_crtc_state *state) -+ struct drm_atomic_state *state) - { -+ struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, -+ crtc); - struct ingenic_drm *priv = drm_crtc_get_priv(crtc); - struct drm_plane_state *f1_state, *f0_state, *ipu_state = NULL; - -- if (drm_atomic_crtc_needs_modeset(state) && priv->soc_info->has_osd) { -- f1_state = drm_atomic_get_plane_state(state->state, &priv->f1); -+ if (drm_atomic_crtc_needs_modeset(crtc_state) && priv->soc_info->has_osd) { -+ f1_state = drm_atomic_get_plane_state(crtc_state->state, -+ &priv->f1); - if (IS_ERR(f1_state)) - return PTR_ERR(f1_state); - -- f0_state = drm_atomic_get_plane_state(state->state, &priv->f0); -+ f0_state = drm_atomic_get_plane_state(crtc_state->state, -+ &priv->f0); - if (IS_ERR(f0_state)) - return PTR_ERR(f0_state); - - if (IS_ENABLED(CONFIG_DRM_INGENIC_IPU) && priv->ipu_plane) { -- ipu_state = drm_atomic_get_plane_state(state->state, priv->ipu_plane); -+ ipu_state = drm_atomic_get_plane_state(crtc_state->state, -+ priv->ipu_plane); - if (IS_ERR(ipu_state)) - return PTR_ERR(ipu_state); - -@@ -248,7 +253,7 @@ ingenic_drm_crtc_mode_valid(struct drm_crtc *crtc, const struct drm_display_mode - } - - static void ingenic_drm_crtc_atomic_begin(struct drm_crtc *crtc, -- struct drm_crtc_state *oldstate) -+ struct drm_atomic_state *state) - { - struct ingenic_drm *priv = drm_crtc_get_priv(crtc); - u32 ctrl = 0; -@@ -268,20 +273,20 @@ static void ingenic_drm_crtc_atomic_begin(struct drm_crtc *crtc, - } - - static void ingenic_drm_crtc_atomic_flush(struct drm_crtc *crtc, -- struct drm_crtc_state *oldstate) -+ struct drm_atomic_state *state) - { - struct ingenic_drm *priv = drm_crtc_get_priv(crtc); -- struct drm_crtc_state *state = crtc->state; -- struct drm_pending_vblank_event *event = state->event; -+ struct drm_crtc_state *crtc_state = crtc->state; -+ struct drm_pending_vblank_event *event = crtc_state->event; - -- if (drm_atomic_crtc_needs_modeset(state)) { -- ingenic_drm_crtc_update_timings(priv, &state->mode); -+ if (drm_atomic_crtc_needs_modeset(crtc_state)) { -+ ingenic_drm_crtc_update_timings(priv, &crtc_state->mode); - - clk_set_rate(priv->pix_clk, state->adjusted_mode.clock * 1000); +@@ -7267,6 +7267,19 @@ int intel_atomic_commit(struct drm_device *dev, struct drm_atomic_state *_state, + state->base.legacy_cursor_update = false; } - if (event) { -- state->event = NULL; -+ crtc_state->event = NULL; - - spin_lock_irq(&crtc->dev->event_lock); - if (drm_crtc_vblank_get(crtc) == 0) -@@ -642,8 +647,6 @@ static const struct drm_crtc_funcs ingenic_drm_crtc_funcs = { - - .enable_vblank = ingenic_drm_enable_vblank, - .disable_vblank = ingenic_drm_disable_vblank, -- -- .gamma_set = drm_atomic_helper_legacy_gamma_set, - }; - - static const struct drm_plane_helper_funcs ingenic_drm_plane_helper_funcs = { -diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c -index dfd5ed15a7f4..3d698cd10626 100644 ---- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c -+++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c -@@ -517,7 +517,7 @@ void mtk_drm_crtc_async_update(struct drm_crtc *crtc, struct drm_plane *plane, - } - - static void mtk_drm_crtc_atomic_enable(struct drm_crtc *crtc, -- struct drm_crtc_state *old_state) -+ struct drm_atomic_state *state) - { - struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); - struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0]; -@@ -542,7 +542,7 @@ static void mtk_drm_crtc_atomic_enable(struct drm_crtc *crtc, - } - - static void mtk_drm_crtc_atomic_disable(struct drm_crtc *crtc, -- struct drm_crtc_state *old_state) -+ struct drm_atomic_state *state) - { - struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); - struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0]; -@@ -575,24 +575,24 @@ static void mtk_drm_crtc_atomic_disable(struct drm_crtc *crtc, - } - - static void mtk_drm_crtc_atomic_begin(struct drm_crtc *crtc, -- struct drm_crtc_state *old_crtc_state) -+ struct drm_atomic_state *state) - { -- struct mtk_crtc_state *state = to_mtk_crtc_state(crtc->state); -+ struct mtk_crtc_state *crtc_state = to_mtk_crtc_state(crtc->state); - struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); - -- if (mtk_crtc->event && state->base.event) -+ if (mtk_crtc->event && crtc_state->base.event) - DRM_ERROR("new event while there is still a pending event\n"); - -- if (state->base.event) { -- state->base.event->pipe = drm_crtc_index(crtc); -+ if (crtc_state->base.event) { -+ crtc_state->base.event->pipe = drm_crtc_index(crtc); - WARN_ON(drm_crtc_vblank_get(crtc) != 0); -- mtk_crtc->event = state->base.event; -- state->base.event = NULL; -+ mtk_crtc->event = crtc_state->base.event; -+ crtc_state->base.event = NULL; - } - } - - static void mtk_drm_crtc_atomic_flush(struct drm_crtc *crtc, -- struct drm_crtc_state *old_crtc_state) -+ struct drm_atomic_state *state) - { - struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc); - int i; -@@ -614,7 +614,6 @@ static const struct drm_crtc_funcs mtk_crtc_funcs = { - .reset = mtk_drm_crtc_reset, - .atomic_duplicate_state = mtk_drm_crtc_duplicate_state, - .atomic_destroy_state = mtk_drm_crtc_destroy_state, -- .gamma_set = drm_atomic_helper_legacy_gamma_set, - .enable_vblank = mtk_drm_crtc_enable_vblank, - .disable_vblank = mtk_drm_crtc_disable_vblank, - }; -diff --git a/drivers/gpu/drm/meson/meson_crtc.c b/drivers/gpu/drm/meson/meson_crtc.c -index 2854272dc2d9..d70616da8ce2 100644 ---- a/drivers/gpu/drm/meson/meson_crtc.c -+++ b/drivers/gpu/drm/meson/meson_crtc.c -@@ -82,7 +82,7 @@ static const struct drm_crtc_funcs meson_crtc_funcs = { - }; - - static void meson_g12a_crtc_atomic_enable(struct drm_crtc *crtc, -- struct drm_crtc_state *old_state) -+ struct drm_atomic_state *state) - { - struct meson_crtc *meson_crtc = to_meson_crtc(crtc); - struct drm_crtc_state *crtc_state = crtc->state; -@@ -118,7 +118,7 @@ static void meson_g12a_crtc_atomic_enable(struct drm_crtc *crtc, - } - - static void meson_crtc_atomic_enable(struct drm_crtc *crtc, -- struct drm_crtc_state *old_state) -+ struct drm_atomic_state *state) - { - struct meson_crtc *meson_crtc = to_meson_crtc(crtc); - struct drm_crtc_state *crtc_state = crtc->state; -@@ -146,7 +146,7 @@ static void meson_crtc_atomic_enable(struct drm_crtc *crtc, - } - - static void meson_g12a_crtc_atomic_disable(struct drm_crtc *crtc, -- struct drm_crtc_state *old_state) -+ struct drm_atomic_state *state) - { - struct meson_crtc *meson_crtc = to_meson_crtc(crtc); - struct meson_drm *priv = meson_crtc->priv; -@@ -171,7 +171,7 @@ static void meson_g12a_crtc_atomic_disable(struct drm_crtc *crtc, - } - - static void meson_crtc_atomic_disable(struct drm_crtc *crtc, -- struct drm_crtc_state *old_state) -+ struct drm_atomic_state *state) - { - struct meson_crtc *meson_crtc = to_meson_crtc(crtc); - struct meson_drm *priv = meson_crtc->priv; -@@ -201,7 +201,7 @@ static void meson_crtc_atomic_disable(struct drm_crtc *crtc, - } - - static void meson_crtc_atomic_begin(struct drm_crtc *crtc, -- struct drm_crtc_state *state) -+ struct drm_atomic_state *state) - { - struct meson_crtc *meson_crtc = to_meson_crtc(crtc); - unsigned long flags; -@@ -217,7 +217,7 @@ static void meson_crtc_atomic_begin(struct drm_crtc *crtc, - } - - static void meson_crtc_atomic_flush(struct drm_crtc *crtc, -- struct drm_crtc_state *old_crtc_state) -+ struct drm_atomic_state *state) - { - struct meson_crtc *meson_crtc = to_meson_crtc(crtc); - struct meson_drm *priv = meson_crtc->priv; -diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c -index f56414a06ec4..5bc1ead269d3 100644 ---- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c -+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c -@@ -11,6 +11,7 @@ - #include - #include - -+#include - #include - #include - #include -@@ -485,7 +486,7 @@ static void _dpu_crtc_setup_cp_blocks(struct drm_crtc *crtc) - } - - static void dpu_crtc_atomic_begin(struct drm_crtc *crtc, -- struct drm_crtc_state *old_state) -+ struct drm_atomic_state *state) - { - struct dpu_crtc_state *cstate = to_dpu_crtc_state(crtc->state); - struct drm_encoder *encoder; -@@ -526,7 +527,7 @@ static void dpu_crtc_atomic_begin(struct drm_crtc *crtc, - } - - static void dpu_crtc_atomic_flush(struct drm_crtc *crtc, -- struct drm_crtc_state *old_crtc_state) -+ struct drm_atomic_state *state) - { - struct dpu_crtc *dpu_crtc; - struct drm_device *dev; -@@ -706,10 +707,12 @@ static struct drm_crtc_state *dpu_crtc_duplicate_state(struct drm_crtc *crtc) - } - - static void dpu_crtc_disable(struct drm_crtc *crtc, -- struct drm_crtc_state *old_crtc_state) -+ struct drm_atomic_state *state) - { - struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc); - struct dpu_crtc_state *cstate = to_dpu_crtc_state(crtc->state); -+ struct drm_crtc_state *old_crtc_state = drm_atomic_get_old_crtc_state(state, -+ crtc); - struct drm_encoder *encoder; - unsigned long flags; - bool release_bandwidth = false; -@@ -770,7 +773,7 @@ static void dpu_crtc_disable(struct drm_crtc *crtc, - } - - static void dpu_crtc_enable(struct drm_crtc *crtc, -- struct drm_crtc_state *old_crtc_state) -+ struct drm_atomic_state *state) - { - struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc); - struct drm_encoder *encoder; -@@ -812,10 +815,12 @@ struct plane_state { - }; - - static int dpu_crtc_atomic_check(struct drm_crtc *crtc, -- struct drm_crtc_state *state) -+ struct drm_atomic_state *state) - { -+ struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, -+ crtc); - struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc); -- struct dpu_crtc_state *cstate = to_dpu_crtc_state(state); -+ struct dpu_crtc_state *cstate = to_dpu_crtc_state(crtc_state); - struct plane_state *pstates; - - const struct drm_plane_state *pstate; -@@ -832,32 +837,33 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc, - - pstates = kzalloc(sizeof(*pstates) * DPU_STAGE_MAX * 4, GFP_KERNEL); - -- if (!state->enable || !state->active) { -+ if (!crtc_state->enable || !crtc_state->active) { - DPU_DEBUG("crtc%d -> enable %d, active %d, skip atomic_check\n", -- crtc->base.id, state->enable, state->active); -+ crtc->base.id, crtc_state->enable, -+ crtc_state->active); - goto end; - } - -- mode = &state->adjusted_mode; -+ mode = &crtc_state->adjusted_mode; - DPU_DEBUG("%s: check", dpu_crtc->name); - - /* force a full mode set if active state changed */ -- if (state->active_changed) -- state->mode_changed = true; -+ if (crtc_state->active_changed) -+ crtc_state->mode_changed = true; - - memset(pipe_staged, 0, sizeof(pipe_staged)); - - if (cstate->num_mixers) { - mixer_width = mode->hdisplay / cstate->num_mixers; - -- _dpu_crtc_setup_lm_bounds(crtc, state); -+ _dpu_crtc_setup_lm_bounds(crtc, crtc_state); - } - - crtc_rect.x2 = mode->hdisplay; - crtc_rect.y2 = mode->vdisplay; - - /* get plane state for all drm planes associated with crtc state */ -- drm_atomic_crtc_state_for_each_plane_state(plane, pstate, state) { -+ drm_atomic_crtc_state_for_each_plane_state(plane, pstate, crtc_state) { - struct drm_rect dst, clip = crtc_rect; - - if (IS_ERR_OR_NULL(pstate)) { -@@ -963,7 +969,7 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc, - - atomic_inc(&_dpu_crtc_get_kms(crtc)->bandwidth_ref); - -- rc = dpu_core_perf_crtc_check(crtc, state); -+ rc = dpu_core_perf_crtc_check(crtc, crtc_state); - if (rc) { - DPU_ERROR("crtc%d failed performance check %d\n", - crtc->base.id, rc); -diff --git a/drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c b/drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c -index a0253297bc76..34e3186e236d 100644 ---- a/drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c -+++ b/drivers/gpu/drm/msm/disp/mdp4/mdp4_crtc.c -@@ -264,7 +264,7 @@ static void mdp4_crtc_mode_set_nofb(struct drm_crtc *crtc) - } - - static void mdp4_crtc_atomic_disable(struct drm_crtc *crtc, -- struct drm_crtc_state *old_state) -+ struct drm_atomic_state *state) - { - struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc); - struct mdp4_kms *mdp4_kms = get_kms(crtc); -@@ -284,7 +284,7 @@ static void mdp4_crtc_atomic_disable(struct drm_crtc *crtc, - } - - static void mdp4_crtc_atomic_enable(struct drm_crtc *crtc, -- struct drm_crtc_state *old_state) -+ struct drm_atomic_state *state) - { - struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc); - struct mdp4_kms *mdp4_kms = get_kms(crtc); -@@ -307,7 +307,7 @@ static void mdp4_crtc_atomic_enable(struct drm_crtc *crtc, - } - - static int mdp4_crtc_atomic_check(struct drm_crtc *crtc, -- struct drm_crtc_state *state) -+ struct drm_atomic_state *state) - { - struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc); - DBG("%s: check", mdp4_crtc->name); -@@ -316,14 +316,14 @@ static int mdp4_crtc_atomic_check(struct drm_crtc *crtc, - } - - static void mdp4_crtc_atomic_begin(struct drm_crtc *crtc, -- struct drm_crtc_state *old_crtc_state) -+ struct drm_atomic_state *state) - { - struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc); - DBG("%s: begin", mdp4_crtc->name); - } - - static void mdp4_crtc_atomic_flush(struct drm_crtc *crtc, -- struct drm_crtc_state *old_crtc_state) -+ struct drm_atomic_state *state) - { - struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc); - struct drm_device *dev = crtc->dev; -diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c b/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c -index a8fa084dfa49..58dd302950d9 100644 ---- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c -+++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c -@@ -7,6 +7,7 @@ - - #include - -+#include - #include - #include - #include -@@ -483,7 +484,7 @@ static u32 mdp5_crtc_get_vblank_counter(struct drm_crtc *crtc) - } - - static void mdp5_crtc_atomic_disable(struct drm_crtc *crtc, -- struct drm_crtc_state *old_state) -+ struct drm_atomic_state *state) - { - struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc); - struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state); -@@ -529,7 +530,7 @@ static void mdp5_crtc_vblank_on(struct drm_crtc *crtc) - } - - static void mdp5_crtc_atomic_enable(struct drm_crtc *crtc, -- struct drm_crtc_state *old_state) -+ struct drm_atomic_state *state) - { - struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc); - struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state); -@@ -682,15 +683,17 @@ static enum mdp_mixer_stage_id get_start_stage(struct drm_crtc *crtc, - } - - static int mdp5_crtc_atomic_check(struct drm_crtc *crtc, -- struct drm_crtc_state *state) -+ struct drm_atomic_state *state) - { -+ struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, -+ crtc); - struct mdp5_kms *mdp5_kms = get_kms(crtc); - struct drm_plane *plane; - struct drm_device *dev = crtc->dev; - struct plane_state pstates[STAGE_MAX + 1]; - const struct mdp5_cfg_hw *hw_cfg; - const struct drm_plane_state *pstate; -- const struct drm_display_mode *mode = &state->adjusted_mode; -+ const struct drm_display_mode *mode = &crtc_state->adjusted_mode; - bool cursor_plane = false; - bool need_right_mixer = false; - int cnt = 0, i; -@@ -699,7 +702,7 @@ static int mdp5_crtc_atomic_check(struct drm_crtc *crtc, - - DBG("%s: check", crtc->name); - -- drm_atomic_crtc_state_for_each_plane_state(plane, pstate, state) { -+ drm_atomic_crtc_state_for_each_plane_state(plane, pstate, crtc_state) { - if (!pstate->visible) - continue; - -@@ -731,7 +734,7 @@ static int mdp5_crtc_atomic_check(struct drm_crtc *crtc, - if (mode->hdisplay > hw_cfg->lm.max_width) - need_right_mixer = true; - -- ret = mdp5_crtc_setup_pipeline(crtc, state, need_right_mixer); -+ ret = mdp5_crtc_setup_pipeline(crtc, crtc_state, need_right_mixer); ++ /* ++ * FIXME: Cut over to (async) commit helpers instead of hand-rolling ++ * everything. ++ */ ++ if (state->base.legacy_cursor_update) { ++ struct intel_crtc_state *new_crtc_state; ++ struct intel_crtc *crtc; ++ int i; ++ ++ for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) ++ complete_all(&new_crtc_state->uapi.commit->flip_done); ++ } ++ + ret = intel_atomic_prepare_commit(state); if (ret) { - DRM_DEV_ERROR(dev->dev, "couldn't assign mixers %d\n", ret); - return ret; -@@ -744,7 +747,7 @@ static int mdp5_crtc_atomic_check(struct drm_crtc *crtc, - WARN_ON(cursor_plane && - (pstates[cnt - 1].plane->type != DRM_PLANE_TYPE_CURSOR)); + drm_dbg_atomic(&dev_priv->drm, +diff --git a/drivers/gpu/drm/msm/msm_atomic.c b/drivers/gpu/drm/msm/msm_atomic.c +index 9c45d641b521..5c8e5611304f 100644 +--- a/drivers/gpu/drm/msm/msm_atomic.c ++++ b/drivers/gpu/drm/msm/msm_atomic.c +@@ -242,6 +242,8 @@ void msm_atomic_commit_tail(struct drm_atomic_state *state) + /* async updates are limited to single-crtc updates: */ + WARN_ON(crtc_mask != drm_crtc_mask(async_crtc)); -- start = get_start_stage(crtc, state, &pstates[0].state->base); -+ start = get_start_stage(crtc, crtc_state, &pstates[0].state->base); ++ complete_all(&async_crtc->state->commit->flip_done); ++ + /* + * Start timer if we don't already have an update pending + * on this crtc: +diff --git a/drivers/gpu/drm/panel/Kconfig b/drivers/gpu/drm/panel/Kconfig +index 869e535faefa..d3109ea534fe 100644 +--- a/drivers/gpu/drm/panel/Kconfig ++++ b/drivers/gpu/drm/panel/Kconfig +@@ -194,6 +194,17 @@ config DRM_PANEL_ILITEK_ILI9341 + QVGA (240x320) RGB panels. support serial & parallel rgb + interface. - /* verify that there are not too many planes attached to crtc - * and that we don't have conflicting mixer stages: -@@ -769,13 +772,13 @@ static int mdp5_crtc_atomic_check(struct drm_crtc *crtc, - } ++config DRM_PANEL_ILITEK_ILI9806E ++ tristate "Ilitek ILI9806E-based panels" ++ depends on OF && SPI ++ select DRM_KMS_HELPER ++ depends on DRM_GEM_DMA_HELPER ++ depends on BACKLIGHT_CLASS_DEVICE ++ select DRM_MIPI_DBI ++ help ++ Say Y if you want to enable support for panels based on the ++ Ilitek ILI9806e controller. ++ + config DRM_PANEL_ILITEK_ILI9881C + tristate "Ilitek ILI9881C-based panels" + depends on OF +@@ -756,6 +767,17 @@ config DRM_PANEL_TDO_TL070WSH30 + 24 bit RGB per pixel. It provides a MIPI DSI interface to + the host, a built-in LED backlight and touch controller. - static void mdp5_crtc_atomic_begin(struct drm_crtc *crtc, -- struct drm_crtc_state *old_crtc_state) -+ struct drm_atomic_state *state) - { - DBG("%s: begin", crtc->name); - } ++config DRM_PANEL_TPO_Y17P ++ tristate "TDO Y17P-based panels" ++ depends on OF && SPI ++ select DRM_KMS_HELPER ++ depends on DRM_GEM_DMA_HELPER ++ depends on BACKLIGHT_CLASS_DEVICE ++ select DRM_MIPI_DBI ++ help ++ Say Y if you want to enable support for panels based on the ++ TDO Y17P controller. ++ + config DRM_PANEL_TPO_TD028TTEC1 + tristate "Toppoly (TPO) TD028TTEC1 panel driver" + depends on OF && SPI +@@ -816,6 +838,16 @@ config DRM_PANEL_VISIONOX_R66451 + Say Y here if you want to enable support for Visionox + R66451 1080x2340 AMOLED DSI panel. - static void mdp5_crtc_atomic_flush(struct drm_crtc *crtc, -- struct drm_crtc_state *old_crtc_state) -+ struct drm_atomic_state *state) - { - struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc); - struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state); -diff --git a/drivers/gpu/drm/mxsfb/mxsfb_kms.c b/drivers/gpu/drm/mxsfb/mxsfb_kms.c -index b535621f4f78..d2f747d3695a 100644 ---- a/drivers/gpu/drm/mxsfb/mxsfb_kms.c -+++ b/drivers/gpu/drm/mxsfb/mxsfb_kms.c -@@ -310,21 +310,23 @@ static void mxsfb_crtc_mode_set_nofb(struct mxsfb_drm_private *mxsfb) - } - - static int mxsfb_crtc_atomic_check(struct drm_crtc *crtc, -- struct drm_crtc_state *state) -+ struct drm_atomic_state *state) - { -- bool has_primary = state->plane_mask & -+ struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, -+ crtc); -+ bool has_primary = crtc_state->plane_mask & - drm_plane_mask(crtc->primary); - - /* The primary plane has to be enabled when the CRTC is active. */ -- if (state->active && !has_primary) -+ if (crtc_state->active && !has_primary) - return -EINVAL; - - /* TODO: Is this needed ? */ -- return drm_atomic_add_affected_planes(state->state, crtc); -+ return drm_atomic_add_affected_planes(state, crtc); - } - - static void mxsfb_crtc_atomic_flush(struct drm_crtc *crtc, -- struct drm_crtc_state *old_state) -+ struct drm_atomic_state *state) - { - struct drm_pending_vblank_event *event; - -@@ -343,7 +345,7 @@ static void mxsfb_crtc_atomic_flush(struct drm_crtc *crtc, - } - - static void mxsfb_crtc_atomic_enable(struct drm_crtc *crtc, -- struct drm_crtc_state *old_state) -+ struct drm_atomic_state *state) - { - struct mxsfb_drm_private *mxsfb = to_mxsfb_drm_private(crtc->dev); - struct drm_device *drm = mxsfb->drm; -@@ -367,7 +369,7 @@ static void mxsfb_crtc_atomic_enable(struct drm_crtc *crtc, - } - - static void mxsfb_crtc_atomic_disable(struct drm_crtc *crtc, -- struct drm_crtc_state *old_state) -+ struct drm_atomic_state *state) - { - struct mxsfb_drm_private *mxsfb = to_mxsfb_drm_private(crtc->dev); - struct drm_device *drm = mxsfb->drm; -diff --git a/drivers/gpu/drm/nouveau/dispnv50/disp.c b/drivers/gpu/drm/nouveau/dispnv50/disp.c -index c2d34c91e840..afd2736f040d 100644 ---- a/drivers/gpu/drm/nouveau/dispnv50/disp.c -+++ b/drivers/gpu/drm/nouveau/dispnv50/disp.c -@@ -32,6 +32,7 @@ - #include - #include - -+#include - #include - #include - #include -@@ -1161,8 +1162,10 @@ nv50_msto_new(struct drm_device *dev, struct nv50_head *head, int id) - - static struct drm_encoder * - nv50_mstc_atomic_best_encoder(struct drm_connector *connector, -- struct drm_connector_state *connector_state) -+ struct drm_atomic_state *state) - { -+ struct drm_connector_state *connector_state = drm_atomic_get_new_connector_state(state, -+ connector); - struct nv50_mstc *mstc = nv50_mstc(connector); - struct drm_crtc *crtc = connector_state->crtc; - -diff --git a/drivers/gpu/drm/nouveau/dispnv50/head.c b/drivers/gpu/drm/nouveau/dispnv50/head.c -index be649d14f879..32f80b69f9a7 100644 ---- a/drivers/gpu/drm/nouveau/dispnv50/head.c -+++ b/drivers/gpu/drm/nouveau/dispnv50/head.c -@@ -30,6 +30,7 @@ - #include - #include - -+#include - #include - #include - #include -@@ -315,12 +316,14 @@ nv50_head_atomic_check_mode(struct nv50_head *head, struct nv50_head_atom *asyh) - } - - static int --nv50_head_atomic_check(struct drm_crtc *crtc, struct drm_crtc_state *state) -+nv50_head_atomic_check(struct drm_crtc *crtc, struct drm_atomic_state *state) - { -+ struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, -+ crtc); - struct nouveau_drm *drm = nouveau_drm(crtc->dev); - struct nv50_head *head = nv50_head(crtc); - struct nv50_head_atom *armh = nv50_head_atom(crtc->state); -- struct nv50_head_atom *asyh = nv50_head_atom(state); -+ struct nv50_head_atom *asyh = nv50_head_atom(crtc_state); - struct nouveau_conn_atom *asyc = NULL; - struct drm_connector_state *conns; - struct drm_connector *conn; -@@ -503,7 +506,6 @@ nv50_head_destroy(struct drm_crtc *crtc) - static const struct drm_crtc_funcs - nv50_head_func = { - .reset = nv50_head_reset, -- .gamma_set = drm_atomic_helper_legacy_gamma_set, - .destroy = nv50_head_destroy, - .set_config = drm_atomic_helper_set_config, - .page_flip = drm_atomic_helper_page_flip, -@@ -518,7 +520,6 @@ nv50_head_func = { - static const struct drm_crtc_funcs - nvd9_head_func = { - .reset = nv50_head_reset, -- .gamma_set = drm_atomic_helper_legacy_gamma_set, - .destroy = nv50_head_destroy, - .set_config = drm_atomic_helper_set_config, - .page_flip = drm_atomic_helper_page_flip, -diff --git a/drivers/gpu/drm/omapdrm/omap_crtc.c b/drivers/gpu/drm/omapdrm/omap_crtc.c -index 328a4a74f534..84101e27cfb7 100644 ---- a/drivers/gpu/drm/omapdrm/omap_crtc.c -+++ b/drivers/gpu/drm/omapdrm/omap_crtc.c -@@ -436,7 +436,7 @@ static void omap_crtc_arm_event(struct drm_crtc *crtc) - } - - static void omap_crtc_atomic_enable(struct drm_crtc *crtc, -- struct drm_crtc_state *old_state) -+ struct drm_atomic_state *state) - { - struct omap_drm_private *priv = crtc->dev->dev_private; - struct omap_crtc *omap_crtc = to_omap_crtc(crtc); -@@ -462,7 +462,7 @@ static void omap_crtc_atomic_enable(struct drm_crtc *crtc, - } - - static void omap_crtc_atomic_disable(struct drm_crtc *crtc, -- struct drm_crtc_state *old_state) -+ struct drm_atomic_state *state) - { - struct omap_drm_private *priv = crtc->dev->dev_private; - struct omap_crtc *omap_crtc = to_omap_crtc(crtc); -@@ -569,22 +569,25 @@ static bool omap_crtc_is_manually_updated(struct drm_crtc *crtc) - } - - static int omap_crtc_atomic_check(struct drm_crtc *crtc, -- struct drm_crtc_state *state) -+ struct drm_atomic_state *state) - { -+ struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, -+ crtc); - struct drm_plane_state *pri_state; - -- if (state->color_mgmt_changed && state->gamma_lut) { -- unsigned int length = state->gamma_lut->length / -+ if (crtc_state->color_mgmt_changed && crtc_state->gamma_lut) { -+ unsigned int length = crtc_state->gamma_lut->length / - sizeof(struct drm_color_lut); - - if (length < 2) - return -EINVAL; - } - -- pri_state = drm_atomic_get_new_plane_state(state->state, crtc->primary); -+ pri_state = drm_atomic_get_new_plane_state(state, -+ crtc->primary); - if (pri_state) { - struct omap_crtc_state *omap_crtc_state = -- to_omap_crtc_state(state); -+ to_omap_crtc_state(crtc_state); - - /* Mirror new values for zpos and rotation in omap_crtc_state */ - omap_crtc_state->zpos = pri_state->zpos; -@@ -598,12 +601,12 @@ static int omap_crtc_atomic_check(struct drm_crtc *crtc, - } - - static void omap_crtc_atomic_begin(struct drm_crtc *crtc, -- struct drm_crtc_state *old_crtc_state) -+ struct drm_atomic_state *state) - { - } - - static void omap_crtc_atomic_flush(struct drm_crtc *crtc, -- struct drm_crtc_state *old_crtc_state) -+ struct drm_atomic_state *state) - { - struct omap_drm_private *priv = crtc->dev->dev_private; - struct omap_crtc *omap_crtc = to_omap_crtc(crtc); -@@ -738,7 +741,6 @@ static const struct drm_crtc_funcs omap_crtc_funcs = { - .set_config = drm_atomic_helper_set_config, - .destroy = omap_crtc_destroy, - .page_flip = drm_atomic_helper_page_flip, -- .gamma_set = drm_atomic_helper_legacy_gamma_set, - .atomic_duplicate_state = omap_crtc_duplicate_state, - .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state, - .atomic_set_property = omap_crtc_atomic_set_property, ++config DRM_PANEL_WAVESHARE_TOUCHSCREEN ++ tristate "Waveshare touchscreen panels" ++ depends on DRM_MIPI_DSI ++ depends on I2C ++ depends on BACKLIGHT_CLASS_DEVICE ++ help ++ Say Y here if you want to enable support for the Waveshare ++ DSI Touchscreens. To compile this driver as a module, ++ choose M here. ++ + config DRM_PANEL_WIDECHIPS_WS2401 + tristate "Widechips WS2401 DPI panel driver" + depends on SPI && GPIOLIB +diff --git a/drivers/gpu/drm/panel/Makefile b/drivers/gpu/drm/panel/Makefile +index 433e93d57949..9dd9b3503802 100644 +--- a/drivers/gpu/drm/panel/Makefile ++++ b/drivers/gpu/drm/panel/Makefile +@@ -17,6 +17,7 @@ obj-$(CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D) += panel-feiyang-fy07024di26a30d + obj-$(CONFIG_DRM_PANEL_HIMAX_HX8394) += panel-himax-hx8394.o + obj-$(CONFIG_DRM_PANEL_ILITEK_IL9322) += panel-ilitek-ili9322.o + obj-$(CONFIG_DRM_PANEL_ILITEK_ILI9341) += panel-ilitek-ili9341.o ++obj-$(CONFIG_DRM_PANEL_ILITEK_ILI9806E) += panel-ilitek-ili9806e.o + obj-$(CONFIG_DRM_PANEL_ILITEK_ILI9881C) += panel-ilitek-ili9881c.o + obj-$(CONFIG_DRM_PANEL_INNOLUX_EJ030NA) += panel-innolux-ej030na.o + obj-$(CONFIG_DRM_PANEL_INNOLUX_P079ZCA) += panel-innolux-p079zca.o +@@ -76,6 +77,7 @@ obj-$(CONFIG_DRM_PANEL_SONY_TD4353_JDI) += panel-sony-td4353-jdi.o + obj-$(CONFIG_DRM_PANEL_SONY_TULIP_TRULY_NT35521) += panel-sony-tulip-truly-nt35521.o + obj-$(CONFIG_DRM_PANEL_STARTEK_KD070FHFID015) += panel-startek-kd070fhfid015.o + obj-$(CONFIG_DRM_PANEL_TDO_TL070WSH30) += panel-tdo-tl070wsh30.o ++obj-$(CONFIG_DRM_PANEL_TPO_Y17P) += panel-tdo-y17p.o + obj-$(CONFIG_DRM_PANEL_TPO_TD028TTEC1) += panel-tpo-td028ttec1.o + obj-$(CONFIG_DRM_PANEL_TPO_TD043MTEA1) += panel-tpo-td043mtea1.o + obj-$(CONFIG_DRM_PANEL_TPO_TPG110) += panel-tpo-tpg110.o +@@ -83,5 +85,6 @@ obj-$(CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA) += panel-truly-nt35597.o + obj-$(CONFIG_DRM_PANEL_VISIONOX_RM69299) += panel-visionox-rm69299.o + obj-$(CONFIG_DRM_PANEL_VISIONOX_VTDR6130) += panel-visionox-vtdr6130.o + obj-$(CONFIG_DRM_PANEL_VISIONOX_R66451) += panel-visionox-r66451.o ++obj-$(CONFIG_DRM_PANEL_WAVESHARE_TOUCHSCREEN) += panel-waveshare-dsi.o + obj-$(CONFIG_DRM_PANEL_WIDECHIPS_WS2401) += panel-widechips-ws2401.o + obj-$(CONFIG_DRM_PANEL_XINPENG_XPP055C272) += panel-xinpeng-xpp055c272.o +diff --git a/drivers/gpu/drm/panel/panel-ilitek-ili9806e.c b/drivers/gpu/drm/panel/panel-ilitek-ili9806e.c +new file mode 100644 +index 000000000000..80e5bbe7a041 +--- /dev/null ++++ b/drivers/gpu/drm/panel/panel-ilitek-ili9806e.c +@@ -0,0 +1,484 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++/* ++ * Ilitek ILI9806E TFT LCD drm_panel driver. ++ * ++ * Copyright (C) 2022 Raspberry Pi Ltd ++ * ++ * Derived from drivers/drm/gpu/panel/panel-sitronix-st7789v.c ++ * Copyright (C) 2017 Free Electrons ++ */ ++ ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include