From 03ec49e6b94be984127c37e179ac998705e38693 Mon Sep 17 00:00:00 2001 From: Mingzheng Xing Date: Mon, 20 May 2024 04:02:37 +0800 Subject: [PATCH] riscv: Update riscv-kernel patch Rebase 6.6.0-27.0.0 For sg2042, the following features have been added: - SPI Flash driver - kexec file raw image - HIGHMEM Build and boot testing passed. Signed-off-by: Mingzheng Xing --- 0001-riscv-kernel.patch | 9263 +++++++++++++++++++++++++++------------ kernel.spec | 135 +- 2 files changed, 6472 insertions(+), 2926 deletions(-) diff --git a/0001-riscv-kernel.patch b/0001-riscv-kernel.patch index 73c773f..6bc9f68 100644 --- a/0001-riscv-kernel.patch +++ b/0001-riscv-kernel.patch @@ -1,95 +1,123 @@ -From f551c7894f6c8be820845b67bab027708d4c9e3e Mon Sep 17 00:00:00 2001 +From 70706e9fba0cc87e88f6ec2b8db4f58c44e582f5 Mon Sep 17 00:00:00 2001 From: Mingzheng Xing -Date: Sat, 11 May 2024 10:34:28 +0800 +Date: Fri, 24 May 2024 14:47:38 +0800 Subject: [PATCH] riscv kernel Signed-off-by: Mingzheng Xing --- .../bindings/gpio/snps,dw-apb-gpio.yaml | 2 + - .../sifive,plic-1.0.0.yaml | 1 + - .../thead,c900-aclint-mswi.yaml | 43 + .../bindings/mmc/snps,dwcmshc-sdhci.yaml | 1 + .../devicetree/bindings/net/snps,dwmac.yaml | 2 + - .../devicetree/bindings/net/thead,dwmac.yaml | 77 + - .../pinctrl/thead,th1520-pinctrl.yaml | 372 +++ + .../devicetree/bindings/net/thead,dwmac.yaml | 77 ++ + .../pinctrl/thead,th1520-pinctrl.yaml | 372 ++++++ .../bindings/pwm/thead,th1520-pwm.yaml | 44 + .../bindings/reset/thead,th1520-reset.yaml | 44 + - .../devicetree/bindings/riscv/cpus.yaml | 1 + - .../devicetree/bindings/riscv/sophgo.yaml | 28 + - .../timer/thead,c900-aclint-mtimer.yaml | 50 + - .../bindings/usb/thead,th1520-usb.yaml | 73 + - .../devicetree/bindings/vendor-prefixes.yaml | 4 + - MAINTAINERS | 9 + - arch/riscv/Kconfig | 2 +- + .../bindings/usb/thead,th1520-usb.yaml | 73 ++ + MAINTAINERS | 2 + + arch/riscv/Kconfig | 14 +- arch/riscv/Kconfig.errata | 1 + - arch/riscv/Kconfig.socs | 6 + - arch/riscv/Makefile | 2 +- + arch/riscv/Kconfig.socs | 14 + + arch/riscv/Makefile | 19 +- + arch/riscv/Makefile.isa | 18 + arch/riscv/boot/dts/Makefile | 1 + - arch/riscv/boot/dts/sophgo/Makefile | 5 + - .../boot/dts/sophgo/mango-clock-socket0.dtsi | 124 + - .../boot/dts/sophgo/mango-cpus-socket0.dtsi | 1148 ++++++++++ - .../boot/dts/sophgo/mango-milkv-pioneer.dts | 163 ++ - .../riscv/boot/dts/sophgo/mango-pcie-2rc.dtsi | 83 + - .../boot/dts/sophgo/mango-pcie-3rc-v2.dtsi | 118 + - .../riscv/boot/dts/sophgo/mango-pcie-3rc.dtsi | 115 + - .../riscv/boot/dts/sophgo/mango-pcie-4rc.dtsi | 151 ++ - arch/riscv/boot/dts/sophgo/mango-pinctrl.dtsi | 434 ++++ - .../boot/dts/sophgo/mango-sophgo-x4evb.dts | 137 ++ - .../boot/dts/sophgo/mango-sophgo-x8evb.dts | 165 ++ + arch/riscv/boot/dts/sophgo/Makefile | 7 + + .../riscv/boot/dts/sophgo/mango-2sockets.dtsi | 699 ++++++++++ + .../boot/dts/sophgo/mango-clock-socket0.dtsi | 124 ++ + .../boot/dts/sophgo/mango-clock-socket1.dtsi | 124 ++ + .../boot/dts/sophgo/mango-cpus-socket0.dtsi | 1148 ++++++++++++++++ + .../boot/dts/sophgo/mango-cpus-socket1.dtsi | 1149 +++++++++++++++++ + .../boot/dts/sophgo/mango-milkv-pioneer.dts | 170 +++ + .../riscv/boot/dts/sophgo/mango-pcie-2rc.dtsi | 81 ++ + .../dts/sophgo/mango-pcie-3rc-capricorn.dtsi | 116 ++ + .../boot/dts/sophgo/mango-pcie-3rc-v2.dtsi | 115 ++ + .../riscv/boot/dts/sophgo/mango-pcie-3rc.dtsi | 112 ++ + .../boot/dts/sophgo/mango-pcie-4rc-v2.dtsi | 155 +++ + .../riscv/boot/dts/sophgo/mango-pcie-4rc.dtsi | 151 +++ + arch/riscv/boot/dts/sophgo/mango-pinctrl.dtsi | 434 +++++++ + .../dts/sophgo/mango-sophgo-capricorn.dts | 57 + + .../boot/dts/sophgo/mango-sophgo-pisces.dts | 58 + + .../boot/dts/sophgo/mango-sophgo-x4evb.dts | 144 +++ + .../boot/dts/sophgo/mango-sophgo-x8evb.dts | 172 +++ .../boot/dts/sophgo/mango-top-intc2.dtsi | 62 + - arch/riscv/boot/dts/sophgo/mango.dtsi | 941 ++++++++ - arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi | 2000 +++++++++++++++++ - .../boot/dts/sophgo/sg2042-milkv-pioneer.dts | 19 + - arch/riscv/boot/dts/sophgo/sg2042.dtsi | 341 +++ + .../boot/dts/sophgo/mango-yixin-s2110.dts | 63 + + arch/riscv/boot/dts/sophgo/mango.dtsi | 938 ++++++++++++++ arch/riscv/boot/dts/thead/Makefile | 3 + - .../boot/dts/thead/th1520-beaglev-ahead.dts | 199 +- + .../boot/dts/thead/th1520-beaglev-ahead.dts | 199 ++- .../thead/th1520-lichee-cluster-4a-16g.dts | 18 + .../dts/thead/th1520-lichee-cluster-4a.dts | 45 + - .../dts/thead/th1520-lichee-module-4a.dtsi | 151 +- + .../dts/thead/th1520-lichee-module-4a.dtsi | 151 ++- .../dts/thead/th1520-lichee-pi-4a-16g.dts | 18 + - .../boot/dts/thead/th1520-lichee-pi-4a.dts | 712 ++++++ + .../boot/dts/thead/th1520-lichee-pi-4a.dts | 712 ++++++++++ .../boot/dts/thead/th1520-milkv-meles-4g.dts | 19 + - .../boot/dts/thead/th1520-milkv-meles.dts | 441 ++++ - arch/riscv/boot/dts/thead/th1520.dtsi | 573 ++++- - arch/riscv/configs/defconfig | 6 +- - arch/riscv/configs/openeuler_defconfig | 141 +- + .../boot/dts/thead/th1520-milkv-meles.dts | 441 +++++++ + arch/riscv/boot/dts/thead/th1520.dtsi | 573 +++++++- + arch/riscv/configs/defconfig | 3 + + arch/riscv/configs/openeuler_defconfig | 265 +++- arch/riscv/errata/thead/errata.c | 69 +- + arch/riscv/include/asm/barrier.h | 22 + arch/riscv/include/asm/errata_list.h | 50 +- + arch/riscv/include/asm/fixmap.h | 13 + + arch/riscv/include/asm/highmem.h | 13 + + arch/riscv/include/asm/io.h | 4 + + arch/riscv/include/asm/kexec.h | 1 + arch/riscv/include/asm/pgtable-64.h | 14 +- + arch/riscv/include/asm/pgtable.h | 34 +- + arch/riscv/include/asm/sparsemem.h | 2 +- + arch/riscv/include/asm/switch_to.h | 15 + + arch/riscv/include/asm/timex.h | 15 + + arch/riscv/include/asm/vdso/gettimeofday.h | 20 + + arch/riscv/kernel/Makefile | 2 +- + arch/riscv/kernel/elf_kexec.c | 6 + + arch/riscv/kernel/image_kexec.c | 305 +++++ + arch/riscv/kernel/machine_kexec_file.c | 1 + + arch/riscv/kernel/module.c | 83 +- + arch/riscv/kernel/process.c | 3 + + arch/riscv/kvm/vcpu_timer.c | 8 + + arch/riscv/mm/init.c | 177 ++- + arch/riscv/mm/pageattr.c | 275 +--- + drivers/base/arch_numa.c | 4 + + drivers/char/ipmi/ipmi_si_hardcode.c | 26 +- + drivers/char/ipmi/ipmi_si_intf.c | 3 +- + drivers/char/ipmi/ipmi_si_pci.c | 6 + drivers/clk/Kconfig | 1 + drivers/clk/Makefile | 2 + drivers/clk/sophgo/Makefile | 3 + - drivers/clk/sophgo/clk-dummy.c | 600 +++++ - drivers/clk/sophgo/clk-mango.c | 977 ++++++++ - drivers/clk/sophgo/clk.c | 883 ++++++++ - drivers/clk/sophgo/clk.h | 152 ++ + drivers/clk/sophgo/clk-dummy.c | 600 +++++++++ + drivers/clk/sophgo/clk-mango.c | 977 ++++++++++++++ + drivers/clk/sophgo/clk.c | 883 +++++++++++++ + drivers/clk/sophgo/clk.h | 152 +++ drivers/clk/thead/Kconfig | 19 + drivers/clk/thead/Makefile | 8 + - drivers/clk/thead/clk-light-fm.c | 646 ++++++ - drivers/clk/thead/clk-light-mpw.c | 492 ++++ - drivers/clk/thead/clk.c | 739 ++++++ - drivers/clk/thead/clk.h | 117 + + drivers/clk/thead/clk-light-fm.c | 646 +++++++++ + drivers/clk/thead/clk-light-mpw.c | 492 +++++++ + drivers/clk/thead/clk.c | 739 +++++++++++ + drivers/clk/thead/clk.h | 117 ++ drivers/clk/thead/gate/Makefile | 3 + drivers/clk/thead/gate/clk-gate.h | 35 + - drivers/clk/thead/gate/dspsys-gate.c | 109 + - drivers/clk/thead/gate/thead-gate.c | 114 + - drivers/clk/thead/gate/visys-gate.c | 144 ++ - drivers/clk/thead/gate/vosys-gate.c | 111 + - drivers/clk/thead/gate/vpsys-gate.c | 94 + + drivers/clk/thead/gate/dspsys-gate.c | 109 ++ + drivers/clk/thead/gate/thead-gate.c | 114 ++ + drivers/clk/thead/gate/visys-gate.c | 144 +++ + drivers/clk/thead/gate/vosys-gate.c | 111 ++ + drivers/clk/thead/gate/vpsys-gate.c | 94 ++ + drivers/clocksource/dw_apb_timer_of.c | 24 + drivers/cpufreq/Kconfig | 10 + drivers/cpufreq/Makefile | 1 + - drivers/cpufreq/light-mpw-cpufreq.c | 491 ++++ + drivers/cpufreq/light-mpw-cpufreq.c | 491 +++++++ drivers/firmware/Kconfig | 1 + drivers/firmware/Makefile | 1 + drivers/firmware/thead/Kconfig | 18 + drivers/firmware/thead/Makefile | 3 + - drivers/firmware/thead/light_aon.c | 261 +++ - drivers/firmware/thead/light_aon_misc.c | 74 + - drivers/firmware/thead/light_aon_pd.c | 417 ++++ - drivers/firmware/thead/light_aon_test.c | 163 ++ + drivers/firmware/thead/light_aon.c | 261 ++++ + drivers/firmware/thead/light_aon_misc.c | 74 ++ + drivers/firmware/thead/light_aon_pd.c | 417 ++++++ + drivers/firmware/thead/light_aon_test.c | 163 +++ drivers/gpio/gpio-dwapb.c | 15 +- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 + + drivers/gpu/drm/amd/display/Kconfig | 1 + + .../gpu/drm/amd/display/amdgpu_dm/dc_fpu.c | 6 +- + drivers/gpu/drm/amd/display/dc/dml/Makefile | 6 + drivers/gpu/drm/drm_gem_vram_helper.c | 2 +- + drivers/gpu/drm/radeon/radeon_drv.c | 7 +- drivers/gpu/drm/radeon/radeon_irq_kms.c | 2 + drivers/gpu/drm/ttm/ttm_bo_util.c | 5 +- drivers/gpu/drm/ttm/ttm_module.c | 3 +- @@ -97,113 +125,132 @@ Signed-off-by: Mingzheng Xing drivers/gpu/drm/ttm/ttm_tt.c | 2 +- drivers/mailbox/Kconfig | 8 + drivers/mailbox/Makefile | 3 + - drivers/mailbox/light-mailbox-client.c | 242 ++ - drivers/mailbox/light-mailbox.c | 507 +++++ + drivers/mailbox/light-mailbox-client.c | 242 ++++ + drivers/mailbox/light-mailbox.c | 507 ++++++++ drivers/mmc/host/Kconfig | 14 + drivers/mmc/host/Makefile | 1 + - drivers/mmc/host/sdhci-of-dwcmshc.c | 349 +++ - drivers/mmc/host/sdhci-sophgo.c | 619 +++++ - drivers/mmc/host/sdhci-sophgo.h | 121 + + drivers/mmc/host/sdhci-of-dwcmshc.c | 349 +++++ + drivers/mmc/host/sdhci-sophgo.c | 619 +++++++++ + drivers/mmc/host/sdhci-sophgo.h | 121 ++ drivers/mmc/host/sdhci.c | 12 +- drivers/mmc/host/sdhci.h | 4 + + drivers/mtd/spi-nor/controllers/Kconfig | 11 + + drivers/mtd/spi-nor/controllers/Makefile | 1 + + .../mtd/spi-nor/controllers/sophgo-spifmc.c | 445 +++++++ + drivers/mtd/spi-nor/gigadevice.c | 14 + + drivers/net/ethernet/intel/i40e/i40e_common.c | 3 +- + drivers/net/ethernet/intel/ixgbe/ixgbe_type.h | 2 +- drivers/net/ethernet/stmicro/stmmac/Kconfig | 11 + drivers/net/ethernet/stmicro/stmmac/Makefile | 2 + - .../ethernet/stmicro/stmmac/dwmac-sophgo.c | 268 +++ - .../net/ethernet/stmicro/stmmac/dwmac-thead.c | 289 +++ + .../ethernet/stmicro/stmmac/dwmac-sophgo.c | 268 ++++ + .../net/ethernet/stmicro/stmmac/dwmac-thead.c | 289 +++++ drivers/pci/controller/cadence/Kconfig | 11 + drivers/pci/controller/cadence/Makefile | 1 + - .../controller/cadence/pcie-cadence-sophgo.c | 963 ++++++++ + .../controller/cadence/pcie-cadence-sophgo.c | 972 ++++++++++++++ .../controller/cadence/pcie-cadence-sophgo.h | 17 + + drivers/pci/msi/msi.c | 97 +- drivers/pci/pcie/portdrv.c | 2 +- drivers/pinctrl/Kconfig | 11 +- drivers/pinctrl/Makefile | 2 + - drivers/pinctrl/pinctrl-th1520.c | 860 +++++++ + drivers/pinctrl/pinctrl-th1520.c | 860 ++++++++++++ drivers/pinctrl/sophgo/Makefile | 2 + - drivers/pinctrl/sophgo/pinctrl-mango.c | 453 ++++ - drivers/pinctrl/sophgo/pinctrl-sophgo.c | 292 +++ + drivers/pinctrl/sophgo/pinctrl-mango.c | 453 +++++++ + drivers/pinctrl/sophgo/pinctrl-sophgo.c | 292 +++++ drivers/pinctrl/sophgo/pinctrl-sophgo.h | 70 + drivers/pwm/Kconfig | 11 + drivers/pwm/Makefile | 2 + - drivers/pwm/pwm-sophgo.c | 276 +++ - drivers/pwm/pwm-thead.c | 269 +++ + drivers/pwm/pwm-sophgo.c | 276 ++++ + drivers/pwm/pwm-thead.c | 269 ++++ drivers/regulator/Kconfig | 9 + drivers/regulator/Makefile | 1 + - drivers/regulator/light-regulator-aon.c | 888 ++++++++ + drivers/regulator/light-regulator-aon.c | 888 +++++++++++++ drivers/reset/Kconfig | 10 + drivers/reset/Makefile | 2 + - drivers/reset/reset-sophgo.c | 163 ++ - drivers/reset/reset-th1520.c | 109 + + drivers/reset/reset-sophgo.c | 163 +++ + drivers/reset/reset-th1520.c | 109 ++ drivers/rpmsg/Kconfig | 4 + drivers/rpmsg/Makefile | 1 + - drivers/rpmsg/light_rpmsg.c | 864 +++++++ + drivers/rpmsg/light_rpmsg.c | 864 +++++++++++++ + drivers/rtc/Kconfig | 6 + + drivers/rtc/Makefile | 1 + + drivers/rtc/rtc-astbmc.c | 535 ++++++++ drivers/soc/Kconfig | 1 + drivers/soc/Makefile | 2 + drivers/soc/sophgo/Makefile | 3 + - drivers/soc/sophgo/tach/sophgo-tach.c | 330 +++ - drivers/soc/sophgo/top/top_intc.c | 412 ++++ - drivers/soc/sophgo/umcu/mcu.c | 1144 ++++++++++ + drivers/soc/sophgo/tach/sophgo-tach.c | 330 +++++ + drivers/soc/sophgo/top/top_intc.c | 412 ++++++ + drivers/soc/sophgo/umcu/mcu.c | 1144 ++++++++++++++++ drivers/soc/thead/Kconfig | 10 + drivers/soc/thead/Makefile | 2 + - drivers/soc/thead/light_event.c | 279 +++ + drivers/soc/thead/light_event.c | 279 ++++ drivers/usb/dwc3/Kconfig | 20 + drivers/usb/dwc3/Makefile | 2 + - drivers/usb/dwc3/dwc3-thead.c | 112 + + drivers/usb/dwc3/dwc3-thead.c | 112 ++ drivers/watchdog/Kconfig | 14 + drivers/watchdog/Makefile | 1 + - drivers/watchdog/light_wdt.c | 376 ++++ + drivers/watchdog/light_wdt.c | 376 ++++++ include/dt-bindings/clock/light-dspsys.h | 25 + - include/dt-bindings/clock/light-fm-ap-clock.h | 513 +++++ - include/dt-bindings/clock/light-mpw-clock.h | 222 ++ + include/dt-bindings/clock/light-fm-ap-clock.h | 513 ++++++++ + include/dt-bindings/clock/light-mpw-clock.h | 222 ++++ include/dt-bindings/clock/light-visys.h | 54 + include/dt-bindings/clock/light-vosys.h | 41 + include/dt-bindings/clock/light-vpsys.h | 24 + - .../dt-bindings/clock/sophgo-mango-clock.h | 165 ++ + .../dt-bindings/clock/sophgo-mango-clock.h | 165 +++ include/dt-bindings/clock/sophgo.h | 15 + include/dt-bindings/firmware/thead/rsrc.h | 17 + - .../dt-bindings/reset/sophgo-mango-resets.h | 96 + + .../dt-bindings/reset/sophgo-mango-resets.h | 96 ++ .../dt-bindings/reset/thead,th1520-reset.h | 9 + - include/linux/firmware/thead/ipc.h | 74 + + include/linux/firmware/thead/ipc.h | 74 ++ include/linux/firmware/thead/light_event.h | 35 + - include/linux/light_rpmsg.h | 92 + + include/linux/light_rpmsg.h | 92 ++ + kernel/kexec_core.c | 2 +- kernel/panic.c | 6 + - mm/memblock.c | 6 +- + kernel/sched/fair.c | 3 + + kernel/time/tick-oneshot.c | 2 +- + mm/memblock.c | 28 +- scripts/package/builddeb | 2 +- sound/pci/hda/hda_intel.c | 5 +- + tools/lib/perf/cpumap.c | 10 +- tools/perf/pmu-events/arch/riscv/mapfile.csv | 1 + .../arch/riscv/thead/c900-legacy/cache.json | 67 + .../riscv/thead/c900-legacy/firmware.json | 68 + - .../riscv/thead/c900-legacy/instruction.json | 72 + - .../riscv/thead/c900-legacy/microarch.json | 80 + - 169 files changed, 27979 insertions(+), 116 deletions(-) - create mode 100644 Documentation/devicetree/bindings/interrupt-controller/thead,c900-aclint-mswi.yaml + .../riscv/thead/c900-legacy/instruction.json | 72 ++ + .../riscv/thead/c900-legacy/microarch.json | 80 ++ + 211 files changed, 29954 insertions(+), 501 deletions(-) create mode 100644 Documentation/devicetree/bindings/net/thead,dwmac.yaml create mode 100644 Documentation/devicetree/bindings/pinctrl/thead,th1520-pinctrl.yaml create mode 100644 Documentation/devicetree/bindings/pwm/thead,th1520-pwm.yaml create mode 100644 Documentation/devicetree/bindings/reset/thead,th1520-reset.yaml - create mode 100644 Documentation/devicetree/bindings/riscv/sophgo.yaml - create mode 100644 Documentation/devicetree/bindings/timer/thead,c900-aclint-mtimer.yaml create mode 100644 Documentation/devicetree/bindings/usb/thead,th1520-usb.yaml + create mode 100644 arch/riscv/Makefile.isa create mode 100644 arch/riscv/boot/dts/sophgo/Makefile + create mode 100644 arch/riscv/boot/dts/sophgo/mango-2sockets.dtsi create mode 100644 arch/riscv/boot/dts/sophgo/mango-clock-socket0.dtsi + create mode 100644 arch/riscv/boot/dts/sophgo/mango-clock-socket1.dtsi create mode 100644 arch/riscv/boot/dts/sophgo/mango-cpus-socket0.dtsi + create mode 100644 arch/riscv/boot/dts/sophgo/mango-cpus-socket1.dtsi create mode 100644 arch/riscv/boot/dts/sophgo/mango-milkv-pioneer.dts create mode 100644 arch/riscv/boot/dts/sophgo/mango-pcie-2rc.dtsi + create mode 100644 arch/riscv/boot/dts/sophgo/mango-pcie-3rc-capricorn.dtsi create mode 100644 arch/riscv/boot/dts/sophgo/mango-pcie-3rc-v2.dtsi create mode 100644 arch/riscv/boot/dts/sophgo/mango-pcie-3rc.dtsi + create mode 100644 arch/riscv/boot/dts/sophgo/mango-pcie-4rc-v2.dtsi create mode 100644 arch/riscv/boot/dts/sophgo/mango-pcie-4rc.dtsi create mode 100644 arch/riscv/boot/dts/sophgo/mango-pinctrl.dtsi + create mode 100644 arch/riscv/boot/dts/sophgo/mango-sophgo-capricorn.dts + create mode 100644 arch/riscv/boot/dts/sophgo/mango-sophgo-pisces.dts create mode 100644 arch/riscv/boot/dts/sophgo/mango-sophgo-x4evb.dts create mode 100644 arch/riscv/boot/dts/sophgo/mango-sophgo-x8evb.dts create mode 100644 arch/riscv/boot/dts/sophgo/mango-top-intc2.dtsi + create mode 100644 arch/riscv/boot/dts/sophgo/mango-yixin-s2110.dts create mode 100644 arch/riscv/boot/dts/sophgo/mango.dtsi - create mode 100644 arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi - create mode 100644 arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts - create mode 100644 arch/riscv/boot/dts/sophgo/sg2042.dtsi create mode 100644 arch/riscv/boot/dts/thead/th1520-lichee-cluster-4a-16g.dts create mode 100644 arch/riscv/boot/dts/thead/th1520-lichee-cluster-4a.dts create mode 100644 arch/riscv/boot/dts/thead/th1520-lichee-pi-4a-16g.dts create mode 100644 arch/riscv/boot/dts/thead/th1520-milkv-meles-4g.dts create mode 100644 arch/riscv/boot/dts/thead/th1520-milkv-meles.dts + create mode 100644 arch/riscv/include/asm/highmem.h + create mode 100644 arch/riscv/kernel/image_kexec.c create mode 100644 drivers/clk/sophgo/Makefile create mode 100644 drivers/clk/sophgo/clk-dummy.c create mode 100644 drivers/clk/sophgo/clk-mango.c @@ -233,6 +280,7 @@ Signed-off-by: Mingzheng Xing create mode 100644 drivers/mailbox/light-mailbox.c create mode 100644 drivers/mmc/host/sdhci-sophgo.c create mode 100644 drivers/mmc/host/sdhci-sophgo.h + create mode 100644 drivers/mtd/spi-nor/controllers/sophgo-spifmc.c create mode 100644 drivers/net/ethernet/stmicro/stmmac/dwmac-sophgo.c create mode 100644 drivers/net/ethernet/stmicro/stmmac/dwmac-thead.c create mode 100644 drivers/pci/controller/cadence/pcie-cadence-sophgo.c @@ -248,6 +296,7 @@ Signed-off-by: Mingzheng Xing create mode 100644 drivers/reset/reset-sophgo.c create mode 100644 drivers/reset/reset-th1520.c create mode 100644 drivers/rpmsg/light_rpmsg.c + create mode 100644 drivers/rtc/rtc-astbmc.c create mode 100644 drivers/soc/sophgo/Makefile create mode 100644 drivers/soc/sophgo/tach/sophgo-tach.c create mode 100644 drivers/soc/sophgo/top/top_intc.c @@ -289,67 +338,6 @@ index eefe7b345286..ab2afc0e4153 100644 ngpios: default: 32 minimum: 1 -diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml -index dc1f28e55266..16f9c4760c0f 100644 ---- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml -+++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml -@@ -65,6 +65,7 @@ properties: - - items: - - enum: - - allwinner,sun20i-d1-plic -+ - sophgo,sg2042-plic - - thead,th1520-plic - - const: thead,c900-plic - - items: -diff --git a/Documentation/devicetree/bindings/interrupt-controller/thead,c900-aclint-mswi.yaml b/Documentation/devicetree/bindings/interrupt-controller/thead,c900-aclint-mswi.yaml -new file mode 100644 -index 000000000000..065f2544b63b ---- /dev/null -+++ b/Documentation/devicetree/bindings/interrupt-controller/thead,c900-aclint-mswi.yaml -@@ -0,0 +1,43 @@ -+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -+%YAML 1.2 -+--- -+$id: http://devicetree.org/schemas/interrupt-controller/thead,c900-aclint-mswi.yaml# -+$schema: http://devicetree.org/meta-schemas/core.yaml# -+ -+title: Sophgo sg2042 CLINT Machine-level Software Interrupt Device -+ -+maintainers: -+ - Inochi Amaoto -+ -+properties: -+ compatible: -+ items: -+ - enum: -+ - sophgo,sg2042-aclint-mswi -+ - const: thead,c900-aclint-mswi -+ -+ reg: -+ maxItems: 1 -+ -+ interrupts-extended: -+ minItems: 1 -+ maxItems: 4095 -+ -+additionalProperties: false -+ -+required: -+ - compatible -+ - reg -+ - interrupts-extended -+ -+examples: -+ - | -+ interrupt-controller@94000000 { -+ compatible = "sophgo,sg2042-aclint-mswi", "thead,c900-aclint-mswi"; -+ interrupts-extended = <&cpu1intc 3>, -+ <&cpu2intc 3>, -+ <&cpu3intc 3>, -+ <&cpu4intc 3>; -+ reg = <0x94000000 0x00010000>; -+ }; -+... diff --git a/Documentation/devicetree/bindings/mmc/snps,dwcmshc-sdhci.yaml b/Documentation/devicetree/bindings/mmc/snps,dwcmshc-sdhci.yaml index a43eb837f8da..42804d955293 100644 --- a/Documentation/devicetree/bindings/mmc/snps,dwcmshc-sdhci.yaml @@ -943,108 +931,6 @@ index 000000000000..49ea8c6a331f + #reset-cells = <1>; + }; + }; -diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml -index 97e8441eda1c..f392e367d673 100644 ---- a/Documentation/devicetree/bindings/riscv/cpus.yaml -+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml -@@ -47,6 +47,7 @@ properties: - - sifive,u74-mc - - thead,c906 - - thead,c910 -+ - thead,c920 - - const: riscv - - items: - - enum: -diff --git a/Documentation/devicetree/bindings/riscv/sophgo.yaml b/Documentation/devicetree/bindings/riscv/sophgo.yaml -new file mode 100644 -index 000000000000..8adb5f39ca53 ---- /dev/null -+++ b/Documentation/devicetree/bindings/riscv/sophgo.yaml -@@ -0,0 +1,28 @@ -+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -+%YAML 1.2 -+--- -+$id: http://devicetree.org/schemas/riscv/sophgo.yaml# -+$schema: http://devicetree.org/meta-schemas/core.yaml# -+ -+title: Sophgo SoC-based boards -+ -+maintainers: -+ - Chao Wei -+ - Chen Wang -+ -+description: -+ Sophgo SoC-based boards -+ -+properties: -+ $nodename: -+ const: '/' -+ compatible: -+ oneOf: -+ - items: -+ - enum: -+ - milkv,pioneer -+ - const: sophgo,sg2042 -+ -+additionalProperties: true -+ -+... -diff --git a/Documentation/devicetree/bindings/timer/thead,c900-aclint-mtimer.yaml b/Documentation/devicetree/bindings/timer/thead,c900-aclint-mtimer.yaml -new file mode 100644 -index 000000000000..2e92bcdeb423 ---- /dev/null -+++ b/Documentation/devicetree/bindings/timer/thead,c900-aclint-mtimer.yaml -@@ -0,0 +1,50 @@ -+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -+%YAML 1.2 -+--- -+$id: http://devicetree.org/schemas/timer/thead,c900-aclint-mtimer.yaml# -+$schema: http://devicetree.org/meta-schemas/core.yaml# -+ -+title: Sophgo CLINT Timer -+ -+maintainers: -+ - Inochi Amaoto -+ -+properties: -+ compatible: -+ items: -+ - enum: -+ - sophgo,sg2042-aclint-mtimer -+ - const: thead,c900-aclint-mtimer -+ -+ reg: -+ items: -+ - description: MTIMECMP Registers -+ -+ reg-names: -+ items: -+ - const: mtimecmp -+ -+ interrupts-extended: -+ minItems: 1 -+ maxItems: 4095 -+ -+additionalProperties: false -+ -+required: -+ - compatible -+ - reg -+ - reg-names -+ - interrupts-extended -+ -+examples: -+ - | -+ timer@ac000000 { -+ compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; -+ interrupts-extended = <&cpu1intc 7>, -+ <&cpu2intc 7>, -+ <&cpu3intc 7>, -+ <&cpu4intc 7>; -+ reg = <0xac000000 0x00010000>; -+ reg-names = "mtimecmp"; -+ }; -+... diff --git a/Documentation/devicetree/bindings/usb/thead,th1520-usb.yaml b/Documentation/devicetree/bindings/usb/thead,th1520-usb.yaml new file mode 100644 index 000000000000..afb618eb5013 @@ -1124,30 +1010,8 @@ index 000000000000..afb618eb5013 + dr_mode = "host"; + }; + }; -diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml -index 133cfb2bb05c..2a8938bfe447 100644 ---- a/Documentation/devicetree/bindings/vendor-prefixes.yaml -+++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml -@@ -863,6 +863,8 @@ patternProperties: - description: MikroElektronika d.o.o. - "^mikrotik,.*": - description: MikroTik -+ "^milkv,.*": -+ description: MilkV Technology Co., Ltd - "^miniand,.*": - description: Miniand Tech - "^minix,.*": -@@ -1275,6 +1277,8 @@ patternProperties: - description: Solomon Systech Limited - "^sony,.*": - description: Sony Corporation -+ "^sophgo,.*": -+ description: Sophgo Technology Inc. - "^sourceparts,.*": - description: Source Parts Inc. - "^spansion,.*": diff --git a/MAINTAINERS b/MAINTAINERS -index 1c70622103e0..895c255561d3 100644 +index 1c70622103e0..e41153dd877b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -18529,6 +18529,8 @@ M: Fu Wei @@ -1159,25 +1023,44 @@ index 1c70622103e0..895c255561d3 100644 RNBD BLOCK DRIVERS M: Md. Haris Iqbal -@@ -20108,6 +20110,13 @@ F: drivers/char/sonypi.c - F: drivers/platform/x86/sony-laptop.c - F: include/linux/sony-laptop.h - -+SOPHGO DEVICETREES -+M: Chao Wei -+M: Chen Wang -+S: Maintained -+F: arch/riscv/boot/dts/sophgo/ -+F: Documentation/devicetree/bindings/riscv/sophgo.yaml -+ - SOUND - M: Jaroslav Kysela - M: Takashi Iwai diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig -index bb40f2eae472..94aaa8c17ccb 100644 +index bb40f2eae472..12aba075395c 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig -@@ -501,7 +501,7 @@ config RISCV_ISA_V +@@ -39,6 +39,7 @@ config RISCV + select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST + select ARCH_HAS_UBSAN_SANITIZE_ALL + select ARCH_HAS_VDSO_DATA ++ select ARCH_KEEP_MEMBLOCK + select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX + select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT + select ARCH_STACKWALK +@@ -155,7 +156,7 @@ config RISCV + select PCI_MSI if PCI + select RISCV_ALTERNATIVE if !XIP_KERNEL + select RISCV_INTC +- select RISCV_TIMER if RISCV_SBI ++ select RISCV_TIMER if RISCV_SBI && !SOPHGO_MULTI_CHIP_CLOCK_SYNC + select SIFIVE_PLIC + select SPARSE_IRQ + select SYSCTL_EXCEPTION_TRACE +@@ -402,6 +403,15 @@ config TUNE_GENERIC + + endchoice + ++config HIGHMEM ++ bool "High Memory Support" ++ depends on MMU ++ select KMAP_LOCAL ++ default y ++ help ++ Enable high memory support on riscv64 which uses supports ++ max 39-bit virtual address spaces. ++ + # Common NUMA Features + config NUMA + bool "NUMA Memory Allocation and Scheduler Support" +@@ -501,7 +511,7 @@ config RISCV_ISA_V depends on TOOLCHAIN_HAS_V depends on FPU select DYNAMIC_SIGFRAME @@ -1199,10 +1082,10 @@ index e2c731cfed8c..dedb8b238e73 100644 help This will apply the cache management errata to handle the diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs -index 30fd6a512828..88ce9f0182be 100644 +index 30fd6a512828..1adb9086fa42 100644 --- a/arch/riscv/Kconfig.socs +++ b/arch/riscv/Kconfig.socs -@@ -22,6 +22,12 @@ config SOC_SIFIVE +@@ -22,6 +22,20 @@ config SOC_SIFIVE help This enables support for SiFive SoC platform hardware. @@ -1211,15 +1094,47 @@ index 30fd6a512828..88ce9f0182be 100644 + select DW_APB_TIMER_OF + help + This enables support for Sophgo SoC platform hardware. ++ ++config SOPHGO_MULTI_CHIP_CLOCK_SYNC ++ bool "Sophgo multi-chip clock synchronous" ++ depends on ARCH_SOPHGO ++ default n ++ help ++ To solve the problem of asynchronous multi-chip clocks, ++ the local timer has been replaced with an APB timer. + config ARCH_STARFIVE def_bool SOC_STARFIVE diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile -index b43a6bb7e4dc..ecf81ab9bd9e 100644 +index b43a6bb7e4dc..c33a055a06f3 100644 --- a/arch/riscv/Makefile +++ b/arch/riscv/Makefile -@@ -152,7 +152,7 @@ ifeq ($(CONFIG_RISCV_M_MODE)$(CONFIG_ARCH_CANAAN),yy) +@@ -54,22 +54,7 @@ endif + endif + endif + +-# ISA string setting +-riscv-march-$(CONFIG_ARCH_RV32I) := rv32ima +-riscv-march-$(CONFIG_ARCH_RV64I) := rv64ima +-riscv-march-$(CONFIG_FPU) := $(riscv-march-y)fd +-riscv-march-$(CONFIG_RISCV_ISA_C) := $(riscv-march-y)c +-riscv-march-$(CONFIG_RISCV_ISA_V) := $(riscv-march-y)v +- +-ifdef CONFIG_TOOLCHAIN_NEEDS_OLD_ISA_SPEC +-KBUILD_CFLAGS += -Wa,-misa-spec=2.2 +-KBUILD_AFLAGS += -Wa,-misa-spec=2.2 +-else +-riscv-march-$(CONFIG_TOOLCHAIN_NEEDS_EXPLICIT_ZICSR_ZIFENCEI) := $(riscv-march-y)_zicsr_zifencei +-endif +- +-# Check if the toolchain supports Zihintpause extension +-riscv-march-$(CONFIG_TOOLCHAIN_HAS_ZIHINTPAUSE) := $(riscv-march-y)_zihintpause ++include $(srctree)/arch/riscv/Makefile.isa + + # Remove F,D,V from isa string for all. Keep extensions between "fd" and "v" by + # matching non-v and non-multi-letter extensions out with the filter ([^v_]*) +@@ -152,7 +137,7 @@ ifeq ($(CONFIG_RISCV_M_MODE)$(CONFIG_ARCH_CANAAN),yy) KBUILD_IMAGE := $(boot)/loader.bin else ifeq ($(CONFIG_EFI_ZBOOT),) @@ -1228,6 +1143,30 @@ index b43a6bb7e4dc..ecf81ab9bd9e 100644 else KBUILD_IMAGE := $(boot)/vmlinuz.efi endif +diff --git a/arch/riscv/Makefile.isa b/arch/riscv/Makefile.isa +new file mode 100644 +index 000000000000..322a83958b96 +--- /dev/null ++++ b/arch/riscv/Makefile.isa +@@ -0,0 +1,18 @@ ++# SPDX-License-Identifier: GPL-2.0-only ++ ++# ISA string setting ++riscv-march-$(CONFIG_ARCH_RV32I) := rv32ima ++riscv-march-$(CONFIG_ARCH_RV64I) := rv64ima ++riscv-march-$(CONFIG_FPU) := $(riscv-march-y)fd ++riscv-march-$(CONFIG_RISCV_ISA_C) := $(riscv-march-y)c ++riscv-march-$(CONFIG_RISCV_ISA_V) := $(riscv-march-y)v ++ ++ifdef CONFIG_TOOLCHAIN_NEEDS_OLD_ISA_SPEC ++KBUILD_CFLAGS += -Wa,-misa-spec=2.2 ++KBUILD_AFLAGS += -Wa,-misa-spec=2.2 ++else ++riscv-march-$(CONFIG_TOOLCHAIN_NEEDS_EXPLICIT_ZICSR_ZIFENCEI) := $(riscv-march-y)_zicsr_zifencei ++endif ++ ++# Check if the toolchain supports Zihintpause extension ++riscv-march-$(CONFIG_TOOLCHAIN_HAS_ZIHINTPAUSE) := $(riscv-march-y)_zihintpause diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile index f60a280abb15..72030fd727af 100644 --- a/arch/riscv/boot/dts/Makefile @@ -1242,15 +1181,722 @@ index f60a280abb15..72030fd727af 100644 diff --git a/arch/riscv/boot/dts/sophgo/Makefile b/arch/riscv/boot/dts/sophgo/Makefile new file mode 100644 -index 000000000000..37f481ea87bb +index 000000000000..6e7c7763b0a9 --- /dev/null +++ b/arch/riscv/boot/dts/sophgo/Makefile -@@ -0,0 +1,5 @@ +@@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0 -+dtb-$(CONFIG_ARCH_SOPHGO) += sg2042-milkv-pioneer.dtb -+dtb-$(CONFIG_ARCH_SOPHGO) += mango-milkv-pioneer.dtb +dtb-$(CONFIG_ARCH_SOPHGO) += mango-sophgo-x4evb.dtb +dtb-$(CONFIG_ARCH_SOPHGO) += mango-sophgo-x8evb.dtb ++dtb-$(CONFIG_ARCH_SOPHGO) += mango-sophgo-pisces.dtb ++dtb-$(CONFIG_ARCH_SOPHGO) += mango-sophgo-capricorn.dtb ++dtb-$(CONFIG_ARCH_SOPHGO) += mango-milkv-pioneer.dtb ++dtb-$(CONFIG_ARCH_SOPHGO) += mango-yixin-s2110.dtb +diff --git a/arch/riscv/boot/dts/sophgo/mango-2sockets.dtsi b/arch/riscv/boot/dts/sophgo/mango-2sockets.dtsi +new file mode 100644 +index 000000000000..8c6e22c33cef +--- /dev/null ++++ b/arch/riscv/boot/dts/sophgo/mango-2sockets.dtsi +@@ -0,0 +1,699 @@ ++#define NR_CPUS 128 ++ ++#include "mango.dtsi" ++#if NR_CPUS > 64 ++#include "mango-cpus-socket1.dtsi" ++#endif ++#include "mango-clock-socket1.dtsi" ++ ++/ { ++ /delete-node/ distance-map; ++ distance-map { ++ compatible = "numa-distance-map-v1"; ++ distance-matrix = <0 0 10>, //chip0 ++ <0 1 15>, ++ <0 2 25>, ++ <0 3 30>, ++ <0 4 110>, ++ <0 5 115>, ++ <0 6 125>, ++ <0 7 130>, ++ <1 0 15>, ++ <1 1 10>, ++ <1 2 30>, ++ <1 3 25>, ++ <1 4 115>, ++ <1 5 110>, ++ <1 6 130>, ++ <1 7 125>, ++ <2 0 25>, ++ <2 1 30>, ++ <2 2 10>, ++ <2 3 15>, ++ <2 4 125>, ++ <2 5 130>, ++ <2 6 110>, ++ <2 7 115>, ++ <3 0 30>, ++ <3 1 25>, ++ <3 2 15>, ++ <3 3 10>, ++ <3 4 130>, ++ <3 5 125>, ++ <3 6 115>, ++ <3 7 110>, ++ <4 0 110>, //chip1 ++ <4 1 115>, ++ <4 2 125>, ++ <4 3 130>, ++ <4 4 10>, ++ <4 5 15>, ++ <4 6 25>, ++ <4 7 30>, ++ <5 0 115>, ++ <5 1 110>, ++ <5 2 130>, ++ <5 3 125>, ++ <5 4 15>, ++ <5 5 10>, ++ <5 6 30>, ++ <5 7 25>, ++ <6 0 125>, ++ <6 1 130>, ++ <6 2 110>, ++ <6 3 115>, ++ <6 4 25>, ++ <6 5 30>, ++ <6 6 10>, ++ <6 7 15>, ++ <7 0 130>, ++ <7 1 125>, ++ <7 2 115>, ++ <7 3 110>, ++ <7 4 30>, ++ <7 5 25>, ++ <7 6 15>, ++ <7 7 10>; ++ }; ++ ++ soc { ++#if NR_CPUS > 64 ++ /delete-node/ clint-mswi@7094000000; ++ clint_mswi: clint-mswi@7094000000 { ++ compatible = "thead,c900-clint-mswi"; ++ reg = <0x00000070 0x94000000 0x00000000 0x00004000>; ++ interrupts-extended = < ++ &cpu0_intc 3 ++ &cpu1_intc 3 ++ &cpu2_intc 3 ++ &cpu3_intc 3 ++ &cpu4_intc 3 ++ &cpu5_intc 3 ++ &cpu6_intc 3 ++ &cpu7_intc 3 ++ &cpu8_intc 3 ++ &cpu9_intc 3 ++ &cpu10_intc 3 ++ &cpu11_intc 3 ++ &cpu12_intc 3 ++ &cpu13_intc 3 ++ &cpu14_intc 3 ++ &cpu15_intc 3 ++ &cpu16_intc 3 ++ &cpu17_intc 3 ++ &cpu18_intc 3 ++ &cpu19_intc 3 ++ &cpu20_intc 3 ++ &cpu21_intc 3 ++ &cpu22_intc 3 ++ &cpu23_intc 3 ++ &cpu24_intc 3 ++ &cpu25_intc 3 ++ &cpu26_intc 3 ++ &cpu27_intc 3 ++ &cpu28_intc 3 ++ &cpu29_intc 3 ++ &cpu30_intc 3 ++ &cpu31_intc 3 ++ &cpu32_intc 3 ++ &cpu33_intc 3 ++ &cpu34_intc 3 ++ &cpu35_intc 3 ++ &cpu36_intc 3 ++ &cpu37_intc 3 ++ &cpu38_intc 3 ++ &cpu39_intc 3 ++ &cpu40_intc 3 ++ &cpu41_intc 3 ++ &cpu42_intc 3 ++ &cpu43_intc 3 ++ &cpu44_intc 3 ++ &cpu45_intc 3 ++ &cpu46_intc 3 ++ &cpu47_intc 3 ++ &cpu48_intc 3 ++ &cpu49_intc 3 ++ &cpu50_intc 3 ++ &cpu51_intc 3 ++ &cpu52_intc 3 ++ &cpu53_intc 3 ++ &cpu54_intc 3 ++ &cpu55_intc 3 ++ &cpu56_intc 3 ++ &cpu57_intc 3 ++ &cpu58_intc 3 ++ &cpu59_intc 3 ++ &cpu60_intc 3 ++ &cpu61_intc 3 ++ &cpu62_intc 3 ++ &cpu63_intc 3 ++ ++ // chip 1 ++ &cpu64_intc 3 ++ &cpu65_intc 3 ++ &cpu66_intc 3 ++ &cpu67_intc 3 ++ &cpu68_intc 3 ++ &cpu69_intc 3 ++ &cpu70_intc 3 ++ &cpu71_intc 3 ++ &cpu72_intc 3 ++ &cpu73_intc 3 ++ &cpu74_intc 3 ++ &cpu75_intc 3 ++ &cpu76_intc 3 ++ &cpu77_intc 3 ++ &cpu78_intc 3 ++ &cpu79_intc 3 ++ &cpu80_intc 3 ++ &cpu81_intc 3 ++ &cpu82_intc 3 ++ &cpu83_intc 3 ++ &cpu84_intc 3 ++ &cpu85_intc 3 ++ &cpu86_intc 3 ++ &cpu87_intc 3 ++ &cpu88_intc 3 ++ &cpu89_intc 3 ++ &cpu90_intc 3 ++ &cpu91_intc 3 ++ &cpu92_intc 3 ++ &cpu93_intc 3 ++ &cpu94_intc 3 ++ &cpu95_intc 3 ++ &cpu96_intc 3 ++ &cpu97_intc 3 ++ &cpu98_intc 3 ++ &cpu99_intc 3 ++ &cpu100_intc 3 ++ &cpu101_intc 3 ++ &cpu102_intc 3 ++ &cpu103_intc 3 ++ &cpu104_intc 3 ++ &cpu105_intc 3 ++ &cpu106_intc 3 ++ &cpu107_intc 3 ++ &cpu108_intc 3 ++ &cpu109_intc 3 ++ &cpu110_intc 3 ++ &cpu111_intc 3 ++ &cpu112_intc 3 ++ &cpu113_intc 3 ++ &cpu114_intc 3 ++ &cpu115_intc 3 ++ &cpu116_intc 3 ++ &cpu117_intc 3 ++ &cpu118_intc 3 ++ &cpu119_intc 3 ++ &cpu120_intc 3 ++ &cpu121_intc 3 ++ &cpu122_intc 3 ++ &cpu123_intc 3 ++ &cpu124_intc 3 ++ &cpu125_intc 3 ++ &cpu126_intc 3 ++ &cpu127_intc 3 ++ >; ++ }; ++ ++ clint_mtimer16: clint-mtimer@70ac100000 { ++ compatible = "thead,c900-clint-mtimer"; ++ reg = <0x00000070 0xac100000 0x00000000 0x00007ff8>; ++ interrupts-extended = < ++ &cpu64_intc 7 ++ &cpu65_intc 7 ++ &cpu66_intc 7 ++ &cpu67_intc 7 ++ >; ++ }; ++ ++ clint_mtimer17: clint-mtimer@70ac110000 { ++ compatible = "thead,c900-clint-mtimer"; ++ reg = <0x00000070 0xac110000 0x00000000 0x00007ff8>; ++ interrupts-extended = < ++ &cpu68_intc 7 ++ &cpu69_intc 7 ++ &cpu70_intc 7 ++ &cpu71_intc 7 ++ >; ++ }; ++ ++ clint_mtimer18: clint-mtimer@70ac120000 { ++ compatible = "thead,c900-clint-mtimer"; ++ reg = <0x00000070 0xac120000 0x00000000 0x00007ff8>; ++ interrupts-extended = < ++ &cpu72_intc 7 ++ &cpu73_intc 7 ++ &cpu74_intc 7 ++ &cpu75_intc 7 ++ >; ++ }; ++ ++ clint_mtimer19: clint-mtimer@70ac130000 { ++ compatible = "thead,c900-clint-mtimer"; ++ reg = <0x00000070 0xac130000 0x00000000 0x00007ff8>; ++ interrupts-extended = < ++ &cpu76_intc 7 ++ &cpu77_intc 7 ++ &cpu78_intc 7 ++ &cpu79_intc 7 ++ >; ++ }; ++ ++ clint_mtimer20: clint-mtimer@70ac140000 { ++ compatible = "thead,c900-clint-mtimer"; ++ reg = <0x00000070 0xac140000 0x00000000 0x00007ff8>; ++ interrupts-extended = < ++ &cpu80_intc 7 ++ &cpu81_intc 7 ++ &cpu82_intc 7 ++ &cpu83_intc 7 ++ >; ++ }; ++ ++ clint_mtimer21: clint-mtimer@70ac150000 { ++ compatible = "thead,c900-clint-mtimer"; ++ reg = <0x00000070 0xac150000 0x00000000 0x00007ff8>; ++ interrupts-extended = < ++ &cpu84_intc 7 ++ &cpu85_intc 7 ++ &cpu86_intc 7 ++ &cpu87_intc 7 ++ >; ++ }; ++ ++ clint_mtimer22: clint-mtimer@70ac160000 { ++ compatible = "thead,c900-clint-mtimer"; ++ reg = <0x00000070 0xac160000 0x00000000 0x00007ff8>; ++ interrupts-extended = < ++ &cpu88_intc 7 ++ &cpu89_intc 7 ++ &cpu90_intc 7 ++ &cpu91_intc 7 ++ >; ++ }; ++ ++ clint_mtimer23: clint-mtimer@70ac170000 { ++ compatible = "thead,c900-clint-mtimer"; ++ reg = <0x00000070 0xac170000 0x00000000 0x00007ff8>; ++ interrupts-extended = < ++ &cpu92_intc 7 ++ &cpu93_intc 7 ++ &cpu94_intc 7 ++ &cpu95_intc 7 ++ >; ++ }; ++ ++ clint_mtimer24: clint-mtimer@70ac180000 { ++ compatible = "thead,c900-clint-mtimer"; ++ reg = <0x00000070 0xac180000 0x00000000 0x00007ff8>; ++ interrupts-extended = < ++ &cpu96_intc 7 ++ &cpu97_intc 7 ++ &cpu98_intc 7 ++ &cpu99_intc 7 ++ >; ++ }; ++ ++ clint_mtimer25: clint-mtimer@70ac190000 { ++ compatible = "thead,c900-clint-mtimer"; ++ reg = <0x00000070 0xac190000 0x00000000 0x00007ff8>; ++ interrupts-extended = < ++ &cpu100_intc 7 ++ &cpu101_intc 7 ++ &cpu102_intc 7 ++ &cpu103_intc 7 ++ >; ++ }; ++ ++ clint_mtimer26: clint-mtimer@70ac1a0000 { ++ compatible = "thead,c900-clint-mtimer"; ++ reg = <0x00000070 0xac1a0000 0x00000000 0x00007ff8>; ++ interrupts-extended = < ++ &cpu104_intc 7 ++ &cpu105_intc 7 ++ &cpu106_intc 7 ++ &cpu107_intc 7 ++ >; ++ }; ++ ++ clint_mtimer27: clint-mtimer@70ac1b0000 { ++ compatible = "thead,c900-clint-mtimer"; ++ reg = <0x00000070 0xac1b0000 0x00000000 0x00007ff8>; ++ interrupts-extended = < ++ &cpu108_intc 7 ++ &cpu109_intc 7 ++ &cpu110_intc 7 ++ &cpu111_intc 7 ++ >; ++ }; ++ ++ clint_mtimer28: clint-mtimer@70ac1c0000 { ++ compatible = "thead,c900-clint-mtimer"; ++ reg = <0x00000070 0xac1c0000 0x00000000 0x00007ff8>; ++ interrupts-extended = < ++ &cpu112_intc 7 ++ &cpu113_intc 7 ++ &cpu114_intc 7 ++ &cpu115_intc 7 ++ >; ++ }; ++ ++ clint_mtimer29: clint-mtimer@70ac1d0000 { ++ compatible = "thead,c900-clint-mtimer"; ++ reg = <0x00000070 0xac1d0000 0x00000000 0x00007ff8>; ++ interrupts-extended = < ++ &cpu116_intc 7 ++ &cpu117_intc 7 ++ &cpu118_intc 7 ++ &cpu119_intc 7 ++ >; ++ }; ++ ++ clint_mtimer30: clint-mtimer@70ac1e0000 { ++ compatible = "thead,c900-clint-mtimer"; ++ reg = <0x00000070 0xac1e0000 0x00000000 0x00007ff8>; ++ interrupts-extended = < ++ &cpu120_intc 7 ++ &cpu121_intc 7 ++ &cpu122_intc 7 ++ &cpu123_intc 7 ++ >; ++ }; ++ ++ clint_mtimer31: clint-mtimer@70ac1f0000 { ++ compatible = "thead,c900-clint-mtimer"; ++ reg = <0x00000070 0xac1f0000 0x00000000 0x00007ff8>; ++ interrupts-extended = < ++ &cpu124_intc 7 ++ &cpu125_intc 7 ++ &cpu126_intc 7 ++ &cpu127_intc 7 ++ >; ++ }; ++#endif ++ ++ /delete-node/ interrupt-controller@7090000000; ++ intc: interrupt-controller@7090000000 { ++ #address-cells = <0>; ++ #interrupt-cells = <2>; ++ compatible = "thead,c900-plic"; ++ interrupt-controller; ++ interrupts-extended = < ++ &cpu0_intc 11 &cpu0_intc 9 ++ &cpu1_intc 11 &cpu1_intc 9 ++ &cpu2_intc 11 &cpu2_intc 9 ++ &cpu3_intc 11 &cpu3_intc 9 ++ &cpu4_intc 11 &cpu4_intc 9 ++ &cpu5_intc 11 &cpu5_intc 9 ++ &cpu6_intc 11 &cpu6_intc 9 ++ &cpu7_intc 11 &cpu7_intc 9 ++ &cpu8_intc 11 &cpu8_intc 9 ++ &cpu9_intc 11 &cpu9_intc 9 ++ &cpu10_intc 11 &cpu10_intc 9 ++ &cpu11_intc 11 &cpu11_intc 9 ++ &cpu12_intc 11 &cpu12_intc 9 ++ &cpu13_intc 11 &cpu13_intc 9 ++ &cpu14_intc 11 &cpu14_intc 9 ++ &cpu15_intc 11 &cpu15_intc 9 ++ &cpu16_intc 11 &cpu16_intc 9 ++ &cpu17_intc 11 &cpu17_intc 9 ++ &cpu18_intc 11 &cpu18_intc 9 ++ &cpu19_intc 11 &cpu19_intc 9 ++ &cpu20_intc 11 &cpu20_intc 9 ++ &cpu21_intc 11 &cpu21_intc 9 ++ &cpu22_intc 11 &cpu22_intc 9 ++ &cpu23_intc 11 &cpu23_intc 9 ++ &cpu24_intc 11 &cpu24_intc 9 ++ &cpu25_intc 11 &cpu25_intc 9 ++ &cpu26_intc 11 &cpu26_intc 9 ++ &cpu27_intc 11 &cpu27_intc 9 ++ &cpu28_intc 11 &cpu28_intc 9 ++ &cpu29_intc 11 &cpu29_intc 9 ++ &cpu30_intc 11 &cpu30_intc 9 ++ &cpu31_intc 11 &cpu31_intc 9 ++ &cpu32_intc 11 &cpu32_intc 9 ++ &cpu33_intc 11 &cpu33_intc 9 ++ &cpu34_intc 11 &cpu34_intc 9 ++ &cpu35_intc 11 &cpu35_intc 9 ++ &cpu36_intc 11 &cpu36_intc 9 ++ &cpu37_intc 11 &cpu37_intc 9 ++ &cpu38_intc 11 &cpu38_intc 9 ++ &cpu39_intc 11 &cpu39_intc 9 ++ &cpu40_intc 11 &cpu40_intc 9 ++ &cpu41_intc 11 &cpu41_intc 9 ++ &cpu42_intc 11 &cpu42_intc 9 ++ &cpu43_intc 11 &cpu43_intc 9 ++ &cpu44_intc 11 &cpu44_intc 9 ++ &cpu45_intc 11 &cpu45_intc 9 ++ &cpu46_intc 11 &cpu46_intc 9 ++ &cpu47_intc 11 &cpu47_intc 9 ++ &cpu48_intc 11 &cpu48_intc 9 ++ &cpu49_intc 11 &cpu49_intc 9 ++ &cpu50_intc 11 &cpu50_intc 9 ++ &cpu51_intc 11 &cpu51_intc 9 ++ &cpu52_intc 11 &cpu52_intc 9 ++ &cpu53_intc 11 &cpu53_intc 9 ++ &cpu54_intc 11 &cpu54_intc 9 ++ &cpu55_intc 11 &cpu55_intc 9 ++ &cpu56_intc 11 &cpu56_intc 9 ++ &cpu57_intc 11 &cpu57_intc 9 ++ &cpu58_intc 11 &cpu58_intc 9 ++ &cpu59_intc 11 &cpu59_intc 9 ++ &cpu60_intc 11 &cpu60_intc 9 ++ &cpu61_intc 11 &cpu61_intc 9 ++ &cpu62_intc 11 &cpu62_intc 9 ++ &cpu63_intc 11 &cpu63_intc 9 ++ ++#if NR_CPUS > 64 ++ //chip 1 ++ &cpu64_intc 11 &cpu64_intc 9 ++ &cpu65_intc 11 &cpu65_intc 9 ++ &cpu66_intc 11 &cpu66_intc 9 ++ &cpu67_intc 11 &cpu67_intc 9 ++ &cpu68_intc 11 &cpu68_intc 9 ++ &cpu69_intc 11 &cpu69_intc 9 ++ &cpu70_intc 11 &cpu70_intc 9 ++ &cpu71_intc 11 &cpu71_intc 9 ++ &cpu72_intc 11 &cpu72_intc 9 ++ &cpu73_intc 11 &cpu73_intc 9 ++ &cpu74_intc 11 &cpu74_intc 9 ++ &cpu75_intc 11 &cpu75_intc 9 ++ &cpu76_intc 11 &cpu76_intc 9 ++ &cpu77_intc 11 &cpu77_intc 9 ++ &cpu78_intc 11 &cpu78_intc 9 ++ &cpu79_intc 11 &cpu79_intc 9 ++ &cpu80_intc 11 &cpu80_intc 9 ++ &cpu81_intc 11 &cpu81_intc 9 ++ &cpu82_intc 11 &cpu82_intc 9 ++ &cpu83_intc 11 &cpu83_intc 9 ++ &cpu84_intc 11 &cpu84_intc 9 ++ &cpu85_intc 11 &cpu85_intc 9 ++ &cpu86_intc 11 &cpu86_intc 9 ++ &cpu87_intc 11 &cpu87_intc 9 ++ &cpu88_intc 11 &cpu88_intc 9 ++ &cpu89_intc 11 &cpu89_intc 9 ++ &cpu90_intc 11 &cpu90_intc 9 ++ &cpu91_intc 11 &cpu91_intc 9 ++ &cpu92_intc 11 &cpu92_intc 9 ++ &cpu93_intc 11 &cpu93_intc 9 ++ &cpu94_intc 11 &cpu94_intc 9 ++ &cpu95_intc 11 &cpu95_intc 9 ++ &cpu96_intc 11 &cpu96_intc 9 ++ &cpu97_intc 11 &cpu97_intc 9 ++ &cpu98_intc 11 &cpu98_intc 9 ++ &cpu99_intc 11 &cpu99_intc 9 ++ &cpu100_intc 11 &cpu100_intc 9 ++ &cpu101_intc 11 &cpu101_intc 9 ++ &cpu102_intc 11 &cpu102_intc 9 ++ &cpu103_intc 11 &cpu103_intc 9 ++ &cpu104_intc 11 &cpu104_intc 9 ++ &cpu105_intc 11 &cpu105_intc 9 ++ &cpu106_intc 11 &cpu106_intc 9 ++ &cpu107_intc 11 &cpu107_intc 9 ++ &cpu108_intc 11 &cpu108_intc 9 ++ &cpu109_intc 11 &cpu109_intc 9 ++ &cpu110_intc 11 &cpu110_intc 9 ++ &cpu111_intc 11 &cpu111_intc 9 ++ &cpu112_intc 11 &cpu112_intc 9 ++ &cpu113_intc 11 &cpu113_intc 9 ++ &cpu114_intc 11 &cpu114_intc 9 ++ &cpu115_intc 11 &cpu115_intc 9 ++ &cpu116_intc 11 &cpu116_intc 9 ++ &cpu117_intc 11 &cpu117_intc 9 ++ &cpu118_intc 11 &cpu118_intc 9 ++ &cpu119_intc 11 &cpu119_intc 9 ++ &cpu120_intc 11 &cpu120_intc 9 ++ &cpu121_intc 11 &cpu121_intc 9 ++ &cpu122_intc 11 &cpu122_intc 9 ++ &cpu123_intc 11 &cpu123_intc 9 ++ &cpu124_intc 11 &cpu124_intc 9 ++ &cpu125_intc 11 &cpu125_intc 9 ++ &cpu126_intc 11 &cpu126_intc 9 ++ &cpu127_intc 11 &cpu127_intc 9 ++#endif ++ >; ++ reg = <0x00000070 0x90000000 0x00000000 0x04000000>; ++ reg-names = "control"; ++ riscv,max-priority = <7>; ++ riscv,ndev = <448>; ++ }; ++ ++ top1_misc: top_misc_ctrl@f030010000 { ++ compatible = "syscon"; ++ reg = <0xf0 0x30010000 0x0 0x8000>; ++ }; ++ ++ rst1: reset1-controller { ++ #reset-cells = <1>; ++ compatible = "bitmain,reset"; ++ subctrl-syscon = <&top1_misc>; ++ top_rst_offset = <0x3000>; ++ nr_resets = ; ++ }; ++ ++ gpio3: gpio@f030009000 { ++ compatible = "snps,dw-apb-gpio"; ++ reg = <0xf0 0x30009000 0x0 0x400>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ clocks = <&s1_div_clk GATE_CLK_APB_GPIO>, ++ <&s1_div_clk GATE_CLK_GPIO_DB>; ++ clock-names = "bus", "db"; ++ ++ port3a: gpio-controller@0 { ++ compatible = "snps,dw-apb-gpio-port"; ++ bank-name = "port0a"; ++ gpio-controller; ++ #gpio-cells = <2>; ++ snps,nr-gpios = <32>; ++ reg = <0>; ++ interrupt-controller; ++ #interrupt-cells = <2>; ++ interrupt-parent = <&intc>; ++ interrupts = ; ++ }; ++ }; ++ ++ ethernet1: ethernet@f040026000 { ++ compatible = "bitmain,ethernet"; ++ reg = <0xf0 0x40026000 0x0 0x4000>; ++ interrupt-parent = <&intc>; ++ interrupts = ; ++ interrupt-names = "macirq"; ++ clock-names = "clk_tx", "gate_clk_tx", "stmmaceth", "ptp_ref", "gate_clk_ref"; ++ clocks = <&s1_div_clk DIV_CLK_FPLL_TX_ETH0>, ++ <&s1_div_clk GATE_CLK_TX_ETH0>, ++ <&s1_div_clk GATE_CLK_AXI_ETH0>, ++ <&s1_div_clk GATE_CLK_PTP_REF_I_ETH0>, ++ <&s1_div_clk GATE_CLK_REF_ETH0>; ++ ++ /* no hash filter and perfect filter support */ ++ snps,multicast-filter-bins = <0>; ++ snps,perfect-filter-entries = <1>; ++ ++ snps,txpbl = <32>; ++ snps,rxpbl = <32>; ++ snps,aal; ++ ++ snps,axi-config = <&stmmac_axi_setup>; ++ snps,mtl-rx-config = <&mtl_rx_setup>; ++ snps,mtl-tx-config = <&mtl_tx_setup>; ++ ++ phy-mode = "rgmii-txid"; ++ phy-reset-gpios = <&port3a 27 0>; ++ phy-handle = <&phy1>; ++ mdio { ++ #address-cells = <0x1>; ++ #size-cells = <0x0>; ++ compatible = "snps,dwmac-mdio"; ++ phy1: phy@0 { ++ compatible = "ethernet-phy-ieee802.3-c22"; ++ device_type = "ethernet-phy"; ++ reg = <0x0>; ++ }; ++ }; ++ }; ++ ++ emmc1: bm-emmc@f04002A000 { ++ compatible = "bitmain,bm-emmc"; ++ reg = <0xf0 0x4002A000 0x0 0x1000>; ++ reg-names = "core_mem"; ++ interrupt-parent = <&intc>; ++ interrupts = ; ++ bus-width = <4>; ++ non-removable; ++ no-sdio; ++ no-sd; ++ resets = <&rst1 RST_EMMC>; ++ reset-names = "emmc"; ++ clocks = ++ <&s1_div_clk GATE_CLK_EMMC_100M>, ++ <&s1_div_clk GATE_CLK_AXI_EMMC>, ++ <&s1_div_clk GATE_CLK_100K_EMMC>; ++ clock-names = ++ "clk_gate_emmc", ++ "clk_gate_axi_emmc", ++ "clk_gate_100k_emmc"; ++ }; ++ ++ sd1: bm-sd@f04002B000 { ++ compatible = "bitmain,bm-sd"; ++ reg = <0xf0 0x4002B000 0x0 0x1000>; ++ reg-names = "core_mem"; ++ interrupt-parent = <&intc>; ++ interrupts = ; ++ bus-width = <4>; ++ no-sdio; ++ no-mmc; ++ resets = <&rst1 RST_SD>; ++ reset-names = "sdio"; ++ clocks = ++ <&s1_div_clk GATE_CLK_SD_100M>, ++ <&s1_div_clk GATE_CLK_AXI_SD>, ++ <&s1_div_clk GATE_CLK_100K_SD>; ++ clock-names = ++ "clk_gate_sd", ++ "clk_gate_axi_sd", ++ "clk_gate_100k_sd"; ++ }; ++ }; ++ ++ spifmc2: flash-controller@f000180000 { ++ compatible = "sophgo,spifmc"; ++ reg = <0xf0 0x00180000 0x0 0x1000000>; ++ reg-names = "memory"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ interrupt-parent = <&intc>; ++ interrupts = ; ++ clock-frequency = <100000000>; ++ clocks = <&s1_div_clk GATE_CLK_AHB_SF>; ++ flash@0 { ++ reg = <0>; ++ compatible = "jedec,spi-nor"; ++ }; ++ }; ++ ++ spifmc3: flash-controller@f002180000 { ++ compatible = "sophgo,spifmc"; ++ reg = <0xf0 0x02180000 0x0 0x1000000>; ++ reg-names = "memory"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ interrupt-parent = <&intc>; ++ interrupts = ; ++ clock-frequency = <100000000>; ++ clocks = <&s1_div_clk GATE_CLK_AHB_SF>; ++ flash@0 { ++ reg = <0>; ++ compatible = "jedec,spi-nor"; ++ }; ++ }; ++ ++ aliases { ++ serial0 = &uart0; ++ ethernet0 = ðernet0; ++ ethernet1 = ðernet1; ++ }; ++}; diff --git a/arch/riscv/boot/dts/sophgo/mango-clock-socket0.dtsi b/arch/riscv/boot/dts/sophgo/mango-clock-socket0.dtsi new file mode 100644 index 000000000000..af3380412f1d @@ -1381,9 +2027,139 @@ index 000000000000..af3380412f1d + }; + }; +}; +diff --git a/arch/riscv/boot/dts/sophgo/mango-clock-socket1.dtsi b/arch/riscv/boot/dts/sophgo/mango-clock-socket1.dtsi +new file mode 100644 +index 000000000000..cfe34495e4fd +--- /dev/null ++++ b/arch/riscv/boot/dts/sophgo/mango-clock-socket1.dtsi +@@ -0,0 +1,124 @@ ++/ { ++ socket1-clocks { ++ #address-cells = <2>; ++ #size-cells = <2>; ++ ranges; ++ ++ cgi1: ctrystal1 { ++ compatible = "fixed-clock"; ++ clock-frequency = <25000000>; ++ clock-output-names = "s1_cgi"; ++ #clock-cells = <0>; ++ }; ++ ++ /* pll clock */ ++ mpll1: mpll1 { ++ compatible = "mango, pll-clock"; ++ #clock-cells = <0>; ++ id = ; ++ mode = ; ++ subctrl-syscon = <&top1_misc>; ++ clocks = <&cgi1>; ++ clock-output-names = "s1_mpll_clock"; ++ }; ++ ++ fpll1: fpll1 { ++ compatible = "mango, pll-clock"; ++ #clock-cells = <0>; ++ id = ; ++ mode = ; ++ subctrl-syscon = <&top1_misc>; ++ clocks = <&cgi1>; ++ clock-output-names = "s1_fpll_clock"; ++ }; ++ ++ dpll01: dpll01 { ++ compatible = "mango, pll-clock"; ++ #clock-cells = <0>; ++ id = ; ++ mode = ; ++ subctrl-syscon = <&top1_misc>; ++ clocks = <&cgi1>; ++ clock-output-names = "s1_dpll0_clock"; ++ }; ++ ++ dpll11: dpll11 { ++ compatible = "mango, pll-clock"; ++ #clock-cells = <0>; ++ mode = ; ++ subctrl-syscon = <&top1_misc>; ++ clocks = <&cgi1>; ++ id = ; ++ clock-output-names = "s1_dpll1_clock"; ++ }; ++ ++ s1_div_clk: s1_div_clk { ++ compatible = "mango, pll-child-clock"; ++ #clock-cells = <1>; ++ id = ; ++ subctrl-syscon = <&top1_misc>; ++ }; ++ ++ s1_mux_clk: s1_mux_clk { ++ compatible = "mango, pll-mux-clock"; ++ #clock-cells = <1>; ++ id = ; ++ subctrl-syscon = <&top1_misc>; ++ }; ++ ++ socket1_default_rates { ++ compatible = "mango, clk-default-rates"; ++ #clock-cells = <1>; ++ subctrl-syscon = <&top1_misc>; ++ clocks = \ ++ <&mpll1>, <&fpll1>, ++ ++ <&s1_div_clk DIV_CLK_FPLL_RP_CPU_NORMAL_1>, ++ <&s1_div_clk DIV_CLK_FPLL_50M_A53>, ++ <&s1_div_clk DIV_CLK_FPLL_TOP_RP_CMN_DIV2>, ++ <&s1_div_clk DIV_CLK_FPLL_UART_500M>, ++ <&s1_div_clk DIV_CLK_FPLL_AHB_LPC>, ++ <&s1_div_clk DIV_CLK_FPLL_EFUSE>, ++ <&s1_div_clk DIV_CLK_FPLL_TX_ETH0>, ++ <&s1_div_clk DIV_CLK_FPLL_PTP_REF_I_ETH0>, ++ <&s1_div_clk DIV_CLK_FPLL_REF_ETH0>, ++ <&s1_div_clk DIV_CLK_FPLL_EMMC>, ++ <&s1_div_clk DIV_CLK_FPLL_SD>, ++ <&s1_div_clk DIV_CLK_FPLL_TOP_AXI0>, ++ <&s1_div_clk DIV_CLK_FPLL_TOP_AXI_HSPERI>, ++ <&s1_div_clk DIV_CLK_FPLL_AXI_DDR_1>, ++ <&s1_div_clk DIV_CLK_FPLL_DIV_TIMER1>, ++ <&s1_div_clk DIV_CLK_FPLL_DIV_TIMER2>, ++ <&s1_div_clk DIV_CLK_FPLL_DIV_TIMER3>, ++ <&s1_div_clk DIV_CLK_FPLL_DIV_TIMER4>, ++ <&s1_div_clk DIV_CLK_FPLL_DIV_TIMER5>, ++ <&s1_div_clk DIV_CLK_FPLL_DIV_TIMER6>, ++ <&s1_div_clk DIV_CLK_FPLL_DIV_TIMER7>, ++ <&s1_div_clk DIV_CLK_FPLL_DIV_TIMER8>, ++ <&s1_div_clk DIV_CLK_FPLL_100K_EMMC>, ++ <&s1_div_clk DIV_CLK_FPLL_100K_SD>, ++ <&s1_div_clk DIV_CLK_FPLL_GPIO_DB>, ++ ++ <&s1_div_clk DIV_CLK_MPLL_RP_CPU_NORMAL_0>, ++ <&s1_div_clk DIV_CLK_MPLL_AXI_DDR_0>; ++ ++ clock-rates = \ ++ <2000000000>, <1000000000>, ++ ++ <2000000000>, <50000000>, ++ <1000000000>, <500000000>, ++ <200000000>, <25000000>, ++ <125000000>, <50000000>, ++ <25000000>, <100000000>, ++ <100000000>, <100000000>, ++ <250000000>, <1000000000>, ++ <50000000>, <50000000>, ++ <50000000>, <50000000>, ++ <50000000>, <50000000>, ++ <50000000>, <50000000>, ++ <100000>, <100000>, <100000>, ++ ++ <2000000001>, <1000000001>; ++ }; ++ }; ++}; diff --git a/arch/riscv/boot/dts/sophgo/mango-cpus-socket0.dtsi b/arch/riscv/boot/dts/sophgo/mango-cpus-socket0.dtsi new file mode 100644 -index 000000000000..9165f0a658b0 +index 000000000000..7efc9741f3e7 --- /dev/null +++ b/arch/riscv/boot/dts/sophgo/mango-cpus-socket0.dtsi @@ -0,0 +1,1148 @@ @@ -1642,7 +2418,7 @@ index 000000000000..9165f0a658b0 + reg = <0>; + status = "okay"; + compatible = "riscv"; -+ riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <0>; + cpu0_intc: interrupt-controller { @@ -1656,7 +2432,7 @@ index 000000000000..9165f0a658b0 + reg = <1>; + status = "okay"; + compatible = "riscv"; -+ riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <0>; + cpu1_intc: interrupt-controller { @@ -1670,7 +2446,7 @@ index 000000000000..9165f0a658b0 + reg = <2>; + status = "okay"; + compatible = "riscv"; -+ riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <0>; + cpu2_intc: interrupt-controller { @@ -1684,7 +2460,7 @@ index 000000000000..9165f0a658b0 + reg = <3>; + status = "okay"; + compatible = "riscv"; -+ riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <0>; + cpu3_intc: interrupt-controller { @@ -1698,7 +2474,7 @@ index 000000000000..9165f0a658b0 + reg = <4>; + status = "okay"; + compatible = "riscv"; -+ riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <0>; + cpu4_intc: interrupt-controller { @@ -1712,7 +2488,7 @@ index 000000000000..9165f0a658b0 + reg = <5>; + status = "okay"; + compatible = "riscv"; -+ riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <0>; + cpu5_intc: interrupt-controller { @@ -1726,7 +2502,7 @@ index 000000000000..9165f0a658b0 + reg = <6>; + status = "okay"; + compatible = "riscv"; -+ riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <0>; + cpu6_intc: interrupt-controller { @@ -1740,7 +2516,7 @@ index 000000000000..9165f0a658b0 + reg = <7>; + status = "okay"; + compatible = "riscv"; -+ riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <0>; + cpu7_intc: interrupt-controller { @@ -1754,7 +2530,7 @@ index 000000000000..9165f0a658b0 + reg = <8>; + status = "okay"; + compatible = "riscv"; -+ riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <1>; + cpu8_intc: interrupt-controller { @@ -1768,7 +2544,7 @@ index 000000000000..9165f0a658b0 + reg = <9>; + status = "okay"; + compatible = "riscv"; -+ riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <1>; + cpu9_intc: interrupt-controller { @@ -1782,7 +2558,7 @@ index 000000000000..9165f0a658b0 + reg = <10>; + status = "okay"; + compatible = "riscv"; -+ riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <1>; + cpu10_intc: interrupt-controller { @@ -1796,7 +2572,7 @@ index 000000000000..9165f0a658b0 + reg = <11>; + status = "okay"; + compatible = "riscv"; -+ riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <1>; + cpu11_intc: interrupt-controller { @@ -1810,7 +2586,7 @@ index 000000000000..9165f0a658b0 + reg = <12>; + status = "okay"; + compatible = "riscv"; -+ riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <1>; + cpu12_intc: interrupt-controller { @@ -1824,7 +2600,7 @@ index 000000000000..9165f0a658b0 + reg = <13>; + status = "okay"; + compatible = "riscv"; -+ riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <1>; + cpu13_intc: interrupt-controller { @@ -1838,7 +2614,7 @@ index 000000000000..9165f0a658b0 + reg = <14>; + status = "okay"; + compatible = "riscv"; -+ riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <1>; + cpu14_intc: interrupt-controller { @@ -1852,7 +2628,7 @@ index 000000000000..9165f0a658b0 + reg = <15>; + status = "okay"; + compatible = "riscv"; -+ riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <1>; + cpu15_intc: interrupt-controller { @@ -1866,7 +2642,7 @@ index 000000000000..9165f0a658b0 + reg = <16>; + status = "okay"; + compatible = "riscv"; -+ riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <0>; + cpu16_intc: interrupt-controller { @@ -1880,7 +2656,7 @@ index 000000000000..9165f0a658b0 + reg = <17>; + status = "okay"; + compatible = "riscv"; -+ riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <0>; + cpu17_intc: interrupt-controller { @@ -1894,7 +2670,7 @@ index 000000000000..9165f0a658b0 + reg = <18>; + status = "okay"; + compatible = "riscv"; -+ riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <0>; + cpu18_intc: interrupt-controller { @@ -1908,7 +2684,7 @@ index 000000000000..9165f0a658b0 + reg = <19>; + status = "okay"; + compatible = "riscv"; -+ riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <0>; + cpu19_intc: interrupt-controller { @@ -1922,7 +2698,7 @@ index 000000000000..9165f0a658b0 + reg = <20>; + status = "okay"; + compatible = "riscv"; -+ riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <0>; + cpu20_intc: interrupt-controller { @@ -1936,7 +2712,7 @@ index 000000000000..9165f0a658b0 + reg = <21>; + status = "okay"; + compatible = "riscv"; -+ riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <0>; + cpu21_intc: interrupt-controller { @@ -1950,7 +2726,7 @@ index 000000000000..9165f0a658b0 + reg = <22>; + status = "okay"; + compatible = "riscv"; -+ riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <0>; + cpu22_intc: interrupt-controller { @@ -1964,7 +2740,7 @@ index 000000000000..9165f0a658b0 + reg = <23>; + status = "okay"; + compatible = "riscv"; -+ riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <0>; + cpu23_intc: interrupt-controller { @@ -1978,7 +2754,7 @@ index 000000000000..9165f0a658b0 + reg = <24>; + status = "okay"; + compatible = "riscv"; -+ riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <1>; + cpu24_intc: interrupt-controller { @@ -1992,7 +2768,7 @@ index 000000000000..9165f0a658b0 + reg = <25>; + status = "okay"; + compatible = "riscv"; -+ riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <1>; + cpu25_intc: interrupt-controller { @@ -2006,7 +2782,7 @@ index 000000000000..9165f0a658b0 + reg = <26>; + status = "okay"; + compatible = "riscv"; -+ riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <1>; + cpu26_intc: interrupt-controller { @@ -2020,7 +2796,7 @@ index 000000000000..9165f0a658b0 + reg = <27>; + status = "okay"; + compatible = "riscv"; -+ riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <1>; + cpu27_intc: interrupt-controller { @@ -2034,7 +2810,7 @@ index 000000000000..9165f0a658b0 + reg = <28>; + status = "okay"; + compatible = "riscv"; -+ riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <1>; + cpu28_intc: interrupt-controller { @@ -2048,7 +2824,7 @@ index 000000000000..9165f0a658b0 + reg = <29>; + status = "okay"; + compatible = "riscv"; -+ riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <1>; + cpu29_intc: interrupt-controller { @@ -2062,7 +2838,7 @@ index 000000000000..9165f0a658b0 + reg = <30>; + status = "okay"; + compatible = "riscv"; -+ riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <1>; + cpu30_intc: interrupt-controller { @@ -2076,7 +2852,7 @@ index 000000000000..9165f0a658b0 + reg = <31>; + status = "okay"; + compatible = "riscv"; -+ riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <1>; + cpu31_intc: interrupt-controller { @@ -2090,7 +2866,7 @@ index 000000000000..9165f0a658b0 + reg = <32>; + status = "okay"; + compatible = "riscv"; -+ riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <2>; + cpu32_intc: interrupt-controller { @@ -2104,7 +2880,7 @@ index 000000000000..9165f0a658b0 + reg = <33>; + status = "okay"; + compatible = "riscv"; -+ riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <2>; + cpu33_intc: interrupt-controller { @@ -2118,7 +2894,7 @@ index 000000000000..9165f0a658b0 + reg = <34>; + status = "okay"; + compatible = "riscv"; -+ riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <2>; + cpu34_intc: interrupt-controller { @@ -2132,7 +2908,7 @@ index 000000000000..9165f0a658b0 + reg = <35>; + status = "okay"; + compatible = "riscv"; -+ riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <2>; + cpu35_intc: interrupt-controller { @@ -2146,7 +2922,7 @@ index 000000000000..9165f0a658b0 + reg = <36>; + status = "okay"; + compatible = "riscv"; -+ riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <2>; + cpu36_intc: interrupt-controller { @@ -2160,7 +2936,7 @@ index 000000000000..9165f0a658b0 + reg = <37>; + status = "okay"; + compatible = "riscv"; -+ riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <2>; + cpu37_intc: interrupt-controller { @@ -2174,7 +2950,7 @@ index 000000000000..9165f0a658b0 + reg = <38>; + status = "okay"; + compatible = "riscv"; -+ riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <2>; + cpu38_intc: interrupt-controller { @@ -2188,7 +2964,7 @@ index 000000000000..9165f0a658b0 + reg = <39>; + status = "okay"; + compatible = "riscv"; -+ riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <2>; + cpu39_intc: interrupt-controller { @@ -2202,7 +2978,7 @@ index 000000000000..9165f0a658b0 + reg = <40>; + status = "okay"; + compatible = "riscv"; -+ riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <3>; + cpu40_intc: interrupt-controller { @@ -2216,7 +2992,7 @@ index 000000000000..9165f0a658b0 + reg = <41>; + status = "okay"; + compatible = "riscv"; -+ riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <3>; + cpu41_intc: interrupt-controller { @@ -2230,7 +3006,7 @@ index 000000000000..9165f0a658b0 + reg = <42>; + status = "okay"; + compatible = "riscv"; -+ riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <3>; + cpu42_intc: interrupt-controller { @@ -2244,7 +3020,7 @@ index 000000000000..9165f0a658b0 + reg = <43>; + status = "okay"; + compatible = "riscv"; -+ riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <3>; + cpu43_intc: interrupt-controller { @@ -2258,7 +3034,7 @@ index 000000000000..9165f0a658b0 + reg = <44>; + status = "okay"; + compatible = "riscv"; -+ riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <3>; + cpu44_intc: interrupt-controller { @@ -2272,7 +3048,7 @@ index 000000000000..9165f0a658b0 + reg = <45>; + status = "okay"; + compatible = "riscv"; -+ riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <3>; + cpu45_intc: interrupt-controller { @@ -2286,7 +3062,7 @@ index 000000000000..9165f0a658b0 + reg = <46>; + status = "okay"; + compatible = "riscv"; -+ riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <3>; + cpu46_intc: interrupt-controller { @@ -2300,7 +3076,7 @@ index 000000000000..9165f0a658b0 + reg = <47>; + status = "okay"; + compatible = "riscv"; -+ riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <3>; + cpu47_intc: interrupt-controller { @@ -2314,7 +3090,7 @@ index 000000000000..9165f0a658b0 + reg = <48>; + status = "okay"; + compatible = "riscv"; -+ riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <2>; + cpu48_intc: interrupt-controller { @@ -2328,7 +3104,7 @@ index 000000000000..9165f0a658b0 + reg = <49>; + status = "okay"; + compatible = "riscv"; -+ riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <2>; + cpu49_intc: interrupt-controller { @@ -2342,7 +3118,7 @@ index 000000000000..9165f0a658b0 + reg = <50>; + status = "okay"; + compatible = "riscv"; -+ riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <2>; + cpu50_intc: interrupt-controller { @@ -2356,7 +3132,7 @@ index 000000000000..9165f0a658b0 + reg = <51>; + status = "okay"; + compatible = "riscv"; -+ riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <2>; + cpu51_intc: interrupt-controller { @@ -2370,7 +3146,7 @@ index 000000000000..9165f0a658b0 + reg = <52>; + status = "okay"; + compatible = "riscv"; -+ riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <2>; + cpu52_intc: interrupt-controller { @@ -2384,7 +3160,7 @@ index 000000000000..9165f0a658b0 + reg = <53>; + status = "okay"; + compatible = "riscv"; -+ riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <2>; + cpu53_intc: interrupt-controller { @@ -2398,7 +3174,7 @@ index 000000000000..9165f0a658b0 + reg = <54>; + status = "okay"; + compatible = "riscv"; -+ riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <2>; + cpu54_intc: interrupt-controller { @@ -2412,7 +3188,7 @@ index 000000000000..9165f0a658b0 + reg = <55>; + status = "okay"; + compatible = "riscv"; -+ riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <2>; + cpu55_intc: interrupt-controller { @@ -2426,7 +3202,7 @@ index 000000000000..9165f0a658b0 + reg = <56>; + status = "okay"; + compatible = "riscv"; -+ riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <3>; + cpu56_intc: interrupt-controller { @@ -2440,7 +3216,7 @@ index 000000000000..9165f0a658b0 + reg = <57>; + status = "okay"; + compatible = "riscv"; -+ riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <3>; + cpu57_intc: interrupt-controller { @@ -2454,7 +3230,7 @@ index 000000000000..9165f0a658b0 + reg = <58>; + status = "okay"; + compatible = "riscv"; -+ riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <3>; + cpu58_intc: interrupt-controller { @@ -2468,7 +3244,7 @@ index 000000000000..9165f0a658b0 + reg = <59>; + status = "okay"; + compatible = "riscv"; -+ riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <3>; + cpu59_intc: interrupt-controller { @@ -2482,7 +3258,7 @@ index 000000000000..9165f0a658b0 + reg = <60>; + status = "okay"; + compatible = "riscv"; -+ riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <3>; + cpu60_intc: interrupt-controller { @@ -2496,7 +3272,7 @@ index 000000000000..9165f0a658b0 + reg = <61>; + status = "okay"; + compatible = "riscv"; -+ riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <3>; + cpu61_intc: interrupt-controller { @@ -2510,7 +3286,7 @@ index 000000000000..9165f0a658b0 + reg = <62>; + status = "okay"; + compatible = "riscv"; -+ riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <3>; + cpu62_intc: interrupt-controller { @@ -2524,7 +3300,7 @@ index 000000000000..9165f0a658b0 + reg = <63>; + status = "okay"; + compatible = "riscv"; -+ riscv,isa = "rv64imafdcv"; ++ riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + numa-node-id = <3>; + cpu63_intc: interrupt-controller { @@ -2535,12 +3311,1167 @@ index 000000000000..9165f0a658b0 + }; + }; +}; +diff --git a/arch/riscv/boot/dts/sophgo/mango-cpus-socket1.dtsi b/arch/riscv/boot/dts/sophgo/mango-cpus-socket1.dtsi +new file mode 100644 +index 000000000000..255306410f40 +--- /dev/null ++++ b/arch/riscv/boot/dts/sophgo/mango-cpus-socket1.dtsi +@@ -0,0 +1,1149 @@ ++/ { ++ cpus { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ timebase-frequency = <50000000>; ++ ++ cpu-map { ++ socket1 { ++ cluster0 { ++ core0 { ++ cpu = <&cpu64>; ++ }; ++ core1 { ++ cpu = <&cpu65>; ++ }; ++ core2 { ++ cpu = <&cpu66>; ++ }; ++ core3 { ++ cpu = <&cpu67>; ++ }; ++ }; ++ ++ cluster1 { ++ core0 { ++ cpu = <&cpu68>; ++ }; ++ core1 { ++ cpu = <&cpu69>; ++ }; ++ core2 { ++ cpu = <&cpu70>; ++ }; ++ core3 { ++ cpu = <&cpu71>; ++ }; ++ }; ++ ++ cluster2 { ++ core0 { ++ cpu = <&cpu80>; ++ }; ++ core1 { ++ cpu = <&cpu81>; ++ }; ++ core2 { ++ cpu = <&cpu82>; ++ }; ++ core3 { ++ cpu = <&cpu83>; ++ }; ++ }; ++ ++ cluster3 { ++ core0 { ++ cpu = <&cpu84>; ++ }; ++ core1 { ++ cpu = <&cpu85>; ++ }; ++ core2 { ++ cpu = <&cpu86>; ++ }; ++ core3 { ++ cpu = <&cpu87>; ++ }; ++ }; ++ ++ cluster4 { ++ core0 { ++ cpu = <&cpu72>; ++ }; ++ core1 { ++ cpu = <&cpu73>; ++ }; ++ core2 { ++ cpu = <&cpu74>; ++ }; ++ core3 { ++ cpu = <&cpu75>; ++ }; ++ }; ++ ++ cluster5 { ++ core0 { ++ cpu = <&cpu76>; ++ }; ++ core1 { ++ cpu = <&cpu77>; ++ }; ++ core2 { ++ cpu = <&cpu78>; ++ }; ++ core3 { ++ cpu = <&cpu79>; ++ }; ++ }; ++ ++ cluster6 { ++ core0 { ++ cpu = <&cpu88>; ++ }; ++ core1 { ++ cpu = <&cpu89>; ++ }; ++ core2 { ++ cpu = <&cpu90>; ++ }; ++ core3 { ++ cpu = <&cpu91>; ++ }; ++ }; ++ ++ cluster7 { ++ core0 { ++ cpu = <&cpu92>; ++ }; ++ core1 { ++ cpu = <&cpu93>; ++ }; ++ core2 { ++ cpu = <&cpu94>; ++ }; ++ core3 { ++ cpu = <&cpu95>; ++ }; ++ }; ++ ++ cluster8 { ++ core0 { ++ cpu = <&cpu96>; ++ }; ++ core1 { ++ cpu = <&cpu97>; ++ }; ++ core2 { ++ cpu = <&cpu98>; ++ }; ++ core3 { ++ cpu = <&cpu99>; ++ }; ++ }; ++ ++ cluster9 { ++ core0 { ++ cpu = <&cpu100>; ++ }; ++ core1 { ++ cpu = <&cpu101>; ++ }; ++ core2 { ++ cpu = <&cpu102>; ++ }; ++ core3 { ++ cpu = <&cpu103>; ++ }; ++ }; ++ ++ cluster10 { ++ core0 { ++ cpu = <&cpu112>; ++ }; ++ core1 { ++ cpu = <&cpu113>; ++ }; ++ core2 { ++ cpu = <&cpu114>; ++ }; ++ core3 { ++ cpu = <&cpu115>; ++ }; ++ }; ++ ++ cluster11 { ++ core0 { ++ cpu = <&cpu116>; ++ }; ++ core1 { ++ cpu = <&cpu117>; ++ }; ++ core2 { ++ cpu = <&cpu118>; ++ }; ++ core3 { ++ cpu = <&cpu119>; ++ }; ++ }; ++ ++ cluster12 { ++ core0 { ++ cpu = <&cpu104>; ++ }; ++ core1 { ++ cpu = <&cpu105>; ++ }; ++ core2 { ++ cpu = <&cpu106>; ++ }; ++ core3 { ++ cpu = <&cpu107>; ++ }; ++ }; ++ ++ cluster13 { ++ core0 { ++ cpu = <&cpu108>; ++ }; ++ core1 { ++ cpu = <&cpu109>; ++ }; ++ core2 { ++ cpu = <&cpu110>; ++ }; ++ core3 { ++ cpu = <&cpu111>; ++ }; ++ }; ++ ++ cluster14 { ++ core0 { ++ cpu = <&cpu120>; ++ }; ++ core1 { ++ cpu = <&cpu121>; ++ }; ++ core2 { ++ cpu = <&cpu122>; ++ }; ++ core3 { ++ cpu = <&cpu123>; ++ }; ++ }; ++ ++ cluster15 { ++ core0 { ++ cpu = <&cpu124>; ++ }; ++ core1 { ++ cpu = <&cpu125>; ++ }; ++ core2 { ++ cpu = <&cpu126>; ++ }; ++ core3 { ++ cpu = <&cpu127>; ++ }; ++ }; ++ }; ++ }; ++ ++ ++ cpu64: cpu@64 { ++ device_type = "cpu"; ++ reg = <64>; ++ status = "okay"; ++ compatible = "riscv"; ++ riscv,isa = "rv64imafdc"; ++ mmu-type = "riscv,sv39"; ++ numa-node-id = <4>; ++ cpu64_intc: interrupt-controller { ++ #interrupt-cells = <1>; ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ }; ++ }; ++ cpu65: cpu@65 { ++ device_type = "cpu"; ++ reg = <65>; ++ status = "okay"; ++ compatible = "riscv"; ++ riscv,isa = "rv64imafdc"; ++ mmu-type = "riscv,sv39"; ++ numa-node-id = <4>; ++ cpu65_intc: interrupt-controller { ++ #interrupt-cells = <1>; ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ }; ++ }; ++ cpu66: cpu@66 { ++ device_type = "cpu"; ++ reg = <66>; ++ status = "okay"; ++ compatible = "riscv"; ++ riscv,isa = "rv64imafdc"; ++ mmu-type = "riscv,sv39"; ++ numa-node-id = <4>; ++ cpu66_intc: interrupt-controller { ++ #interrupt-cells = <1>; ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ }; ++ }; ++ cpu67: cpu@67 { ++ device_type = "cpu"; ++ reg = <67>; ++ status = "okay"; ++ compatible = "riscv"; ++ riscv,isa = "rv64imafdc"; ++ mmu-type = "riscv,sv39"; ++ numa-node-id = <4>; ++ cpu67_intc: interrupt-controller { ++ #interrupt-cells = <1>; ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ }; ++ }; ++ cpu68: cpu@68 { ++ device_type = "cpu"; ++ reg = <68>; ++ status = "okay"; ++ compatible = "riscv"; ++ riscv,isa = "rv64imafdc"; ++ mmu-type = "riscv,sv39"; ++ numa-node-id = <4>; ++ cpu68_intc: interrupt-controller { ++ #interrupt-cells = <1>; ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ }; ++ }; ++ cpu69: cpu@69 { ++ device_type = "cpu"; ++ reg = <69>; ++ status = "okay"; ++ compatible = "riscv"; ++ riscv,isa = "rv64imafdc"; ++ mmu-type = "riscv,sv39"; ++ numa-node-id = <4>; ++ cpu69_intc: interrupt-controller { ++ #interrupt-cells = <1>; ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ }; ++ }; ++ cpu70: cpu@70 { ++ device_type = "cpu"; ++ reg = <70>; ++ status = "okay"; ++ compatible = "riscv"; ++ riscv,isa = "rv64imafdc"; ++ mmu-type = "riscv,sv39"; ++ numa-node-id = <4>; ++ cpu70_intc: interrupt-controller { ++ #interrupt-cells = <1>; ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ }; ++ }; ++ cpu71: cpu@71 { ++ device_type = "cpu"; ++ reg = <71>; ++ status = "okay"; ++ compatible = "riscv"; ++ riscv,isa = "rv64imafdc"; ++ mmu-type = "riscv,sv39"; ++ numa-node-id = <4>; ++ cpu71_intc: interrupt-controller { ++ #interrupt-cells = <1>; ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ }; ++ }; ++ cpu72: cpu@72 { ++ device_type = "cpu"; ++ reg = <72>; ++ status = "okay"; ++ compatible = "riscv"; ++ riscv,isa = "rv64imafdc"; ++ mmu-type = "riscv,sv39"; ++ numa-node-id = <5>; ++ cpu72_intc: interrupt-controller { ++ #interrupt-cells = <1>; ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ }; ++ }; ++ cpu73: cpu@73 { ++ device_type = "cpu"; ++ reg = <73>; ++ status = "okay"; ++ compatible = "riscv"; ++ riscv,isa = "rv64imafdc"; ++ mmu-type = "riscv,sv39"; ++ numa-node-id = <5>; ++ cpu73_intc: interrupt-controller { ++ #interrupt-cells = <1>; ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ }; ++ }; ++ cpu74: cpu@74 { ++ device_type = "cpu"; ++ reg = <74>; ++ status = "okay"; ++ compatible = "riscv"; ++ riscv,isa = "rv64imafdc"; ++ mmu-type = "riscv,sv39"; ++ numa-node-id = <5>; ++ cpu74_intc: interrupt-controller { ++ #interrupt-cells = <1>; ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ }; ++ }; ++ cpu75: cpu@75 { ++ device_type = "cpu"; ++ reg = <75>; ++ status = "okay"; ++ compatible = "riscv"; ++ riscv,isa = "rv64imafdc"; ++ mmu-type = "riscv,sv39"; ++ numa-node-id = <5>; ++ cpu75_intc: interrupt-controller { ++ #interrupt-cells = <1>; ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ }; ++ }; ++ cpu76: cpu@76 { ++ device_type = "cpu"; ++ reg = <76>; ++ status = "okay"; ++ compatible = "riscv"; ++ riscv,isa = "rv64imafdc"; ++ mmu-type = "riscv,sv39"; ++ numa-node-id = <5>; ++ cpu76_intc: interrupt-controller { ++ #interrupt-cells = <1>; ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ }; ++ }; ++ cpu77: cpu@77 { ++ device_type = "cpu"; ++ reg = <77>; ++ status = "okay"; ++ compatible = "riscv"; ++ riscv,isa = "rv64imafdc"; ++ mmu-type = "riscv,sv39"; ++ numa-node-id = <5>; ++ cpu77_intc: interrupt-controller { ++ #interrupt-cells = <1>; ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ }; ++ }; ++ cpu78: cpu@78 { ++ device_type = "cpu"; ++ reg = <78>; ++ status = "okay"; ++ compatible = "riscv"; ++ riscv,isa = "rv64imafdc"; ++ mmu-type = "riscv,sv39"; ++ numa-node-id = <5>; ++ cpu78_intc: interrupt-controller { ++ #interrupt-cells = <1>; ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ }; ++ }; ++ cpu79: cpu@79 { ++ device_type = "cpu"; ++ reg = <79>; ++ status = "okay"; ++ compatible = "riscv"; ++ riscv,isa = "rv64imafdc"; ++ mmu-type = "riscv,sv39"; ++ numa-node-id = <5>; ++ cpu79_intc: interrupt-controller { ++ #interrupt-cells = <1>; ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ }; ++ }; ++ cpu80: cpu@80 { ++ device_type = "cpu"; ++ reg = <80>; ++ status = "okay"; ++ compatible = "riscv"; ++ riscv,isa = "rv64imafdc"; ++ mmu-type = "riscv,sv39"; ++ numa-node-id = <4>; ++ cpu80_intc: interrupt-controller { ++ #interrupt-cells = <1>; ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ }; ++ }; ++ cpu81: cpu@81 { ++ device_type = "cpu"; ++ reg = <81>; ++ status = "okay"; ++ compatible = "riscv"; ++ riscv,isa = "rv64imafdc"; ++ mmu-type = "riscv,sv39"; ++ numa-node-id = <4>; ++ cpu81_intc: interrupt-controller { ++ #interrupt-cells = <1>; ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ }; ++ }; ++ cpu82: cpu@82 { ++ device_type = "cpu"; ++ reg = <82>; ++ status = "okay"; ++ compatible = "riscv"; ++ riscv,isa = "rv64imafdc"; ++ mmu-type = "riscv,sv39"; ++ numa-node-id = <4>; ++ cpu82_intc: interrupt-controller { ++ #interrupt-cells = <1>; ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ }; ++ }; ++ cpu83: cpu@83 { ++ device_type = "cpu"; ++ reg = <83>; ++ status = "okay"; ++ compatible = "riscv"; ++ riscv,isa = "rv64imafdc"; ++ mmu-type = "riscv,sv39"; ++ numa-node-id = <4>; ++ cpu83_intc: interrupt-controller { ++ #interrupt-cells = <1>; ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ }; ++ }; ++ cpu84: cpu@84 { ++ device_type = "cpu"; ++ reg = <84>; ++ status = "okay"; ++ compatible = "riscv"; ++ riscv,isa = "rv64imafdc"; ++ mmu-type = "riscv,sv39"; ++ numa-node-id = <4>; ++ cpu84_intc: interrupt-controller { ++ #interrupt-cells = <1>; ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ }; ++ }; ++ cpu85: cpu@85 { ++ device_type = "cpu"; ++ reg = <85>; ++ status = "okay"; ++ compatible = "riscv"; ++ riscv,isa = "rv64imafdc"; ++ mmu-type = "riscv,sv39"; ++ numa-node-id = <4>; ++ cpu85_intc: interrupt-controller { ++ #interrupt-cells = <1>; ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ }; ++ }; ++ cpu86: cpu@86 { ++ device_type = "cpu"; ++ reg = <86>; ++ status = "okay"; ++ compatible = "riscv"; ++ riscv,isa = "rv64imafdc"; ++ mmu-type = "riscv,sv39"; ++ numa-node-id = <4>; ++ cpu86_intc: interrupt-controller { ++ #interrupt-cells = <1>; ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ }; ++ }; ++ cpu87: cpu@87 { ++ device_type = "cpu"; ++ reg = <87>; ++ status = "okay"; ++ compatible = "riscv"; ++ riscv,isa = "rv64imafdc"; ++ mmu-type = "riscv,sv39"; ++ numa-node-id = <4>; ++ cpu87_intc: interrupt-controller { ++ #interrupt-cells = <1>; ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ }; ++ }; ++ cpu88: cpu@88 { ++ device_type = "cpu"; ++ reg = <88>; ++ status = "okay"; ++ compatible = "riscv"; ++ riscv,isa = "rv64imafdc"; ++ mmu-type = "riscv,sv39"; ++ numa-node-id = <5>; ++ cpu88_intc: interrupt-controller { ++ #interrupt-cells = <1>; ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ }; ++ }; ++ cpu89: cpu@89 { ++ device_type = "cpu"; ++ reg = <89>; ++ status = "okay"; ++ compatible = "riscv"; ++ riscv,isa = "rv64imafdc"; ++ mmu-type = "riscv,sv39"; ++ numa-node-id = <5>; ++ cpu89_intc: interrupt-controller { ++ #interrupt-cells = <1>; ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ }; ++ }; ++ cpu90: cpu@90 { ++ device_type = "cpu"; ++ reg = <90>; ++ status = "okay"; ++ compatible = "riscv"; ++ riscv,isa = "rv64imafdc"; ++ mmu-type = "riscv,sv39"; ++ numa-node-id = <5>; ++ cpu90_intc: interrupt-controller { ++ #interrupt-cells = <1>; ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ }; ++ }; ++ cpu91: cpu@91 { ++ device_type = "cpu"; ++ reg = <91>; ++ status = "okay"; ++ compatible = "riscv"; ++ riscv,isa = "rv64imafdc"; ++ mmu-type = "riscv,sv39"; ++ numa-node-id = <5>; ++ cpu91_intc: interrupt-controller { ++ #interrupt-cells = <1>; ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ }; ++ }; ++ cpu92: cpu@92 { ++ device_type = "cpu"; ++ reg = <92>; ++ status = "okay"; ++ compatible = "riscv"; ++ riscv,isa = "rv64imafdc"; ++ mmu-type = "riscv,sv39"; ++ numa-node-id = <5>; ++ cpu92_intc: interrupt-controller { ++ #interrupt-cells = <1>; ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ }; ++ }; ++ cpu93: cpu@93 { ++ device_type = "cpu"; ++ reg = <93>; ++ status = "okay"; ++ compatible = "riscv"; ++ riscv,isa = "rv64imafdc"; ++ mmu-type = "riscv,sv39"; ++ numa-node-id = <5>; ++ cpu93_intc: interrupt-controller { ++ #interrupt-cells = <1>; ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ }; ++ }; ++ cpu94: cpu@94 { ++ device_type = "cpu"; ++ reg = <94>; ++ status = "okay"; ++ compatible = "riscv"; ++ riscv,isa = "rv64imafdc"; ++ mmu-type = "riscv,sv39"; ++ numa-node-id = <5>; ++ cpu94_intc: interrupt-controller { ++ #interrupt-cells = <1>; ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ }; ++ }; ++ cpu95: cpu@95 { ++ device_type = "cpu"; ++ reg = <95>; ++ status = "okay"; ++ compatible = "riscv"; ++ riscv,isa = "rv64imafdc"; ++ mmu-type = "riscv,sv39"; ++ numa-node-id = <5>; ++ cpu95_intc: interrupt-controller { ++ #interrupt-cells = <1>; ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ }; ++ }; ++ cpu96: cpu@96 { ++ device_type = "cpu"; ++ reg = <96>; ++ status = "okay"; ++ compatible = "riscv"; ++ riscv,isa = "rv64imafdc"; ++ mmu-type = "riscv,sv39"; ++ numa-node-id = <6>; ++ cpu96_intc: interrupt-controller { ++ #interrupt-cells = <1>; ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ }; ++ }; ++ cpu97: cpu@97 { ++ device_type = "cpu"; ++ reg = <97>; ++ status = "okay"; ++ compatible = "riscv"; ++ riscv,isa = "rv64imafdc"; ++ mmu-type = "riscv,sv39"; ++ numa-node-id = <6>; ++ cpu97_intc: interrupt-controller { ++ #interrupt-cells = <1>; ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ }; ++ }; ++ cpu98: cpu@98 { ++ device_type = "cpu"; ++ reg = <98>; ++ status = "okay"; ++ compatible = "riscv"; ++ riscv,isa = "rv64imafdc"; ++ mmu-type = "riscv,sv39"; ++ numa-node-id = <6>; ++ cpu98_intc: interrupt-controller { ++ #interrupt-cells = <1>; ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ }; ++ }; ++ cpu99: cpu@99 { ++ device_type = "cpu"; ++ reg = <99>; ++ status = "okay"; ++ compatible = "riscv"; ++ riscv,isa = "rv64imafdc"; ++ mmu-type = "riscv,sv39"; ++ numa-node-id = <6>; ++ cpu99_intc: interrupt-controller { ++ #interrupt-cells = <1>; ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ }; ++ }; ++ cpu100: cpu@100 { ++ device_type = "cpu"; ++ reg = <100>; ++ status = "okay"; ++ compatible = "riscv"; ++ riscv,isa = "rv64imafdc"; ++ mmu-type = "riscv,sv39"; ++ numa-node-id = <6>; ++ cpu100_intc: interrupt-controller { ++ #interrupt-cells = <1>; ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ }; ++ }; ++ cpu101: cpu@101 { ++ device_type = "cpu"; ++ reg = <101>; ++ status = "okay"; ++ compatible = "riscv"; ++ riscv,isa = "rv64imafdc"; ++ mmu-type = "riscv,sv39"; ++ numa-node-id = <6>; ++ cpu101_intc: interrupt-controller { ++ #interrupt-cells = <1>; ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ }; ++ }; ++ cpu102: cpu@102 { ++ device_type = "cpu"; ++ reg = <102>; ++ status = "okay"; ++ compatible = "riscv"; ++ riscv,isa = "rv64imafdc"; ++ mmu-type = "riscv,sv39"; ++ numa-node-id = <6>; ++ cpu102_intc: interrupt-controller { ++ #interrupt-cells = <1>; ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ }; ++ }; ++ cpu103: cpu@103 { ++ device_type = "cpu"; ++ reg = <103>; ++ status = "okay"; ++ compatible = "riscv"; ++ riscv,isa = "rv64imafdc"; ++ mmu-type = "riscv,sv39"; ++ numa-node-id = <6>; ++ cpu103_intc: interrupt-controller { ++ #interrupt-cells = <1>; ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ }; ++ }; ++ cpu104: cpu@104 { ++ device_type = "cpu"; ++ reg = <104>; ++ status = "okay"; ++ compatible = "riscv"; ++ riscv,isa = "rv64imafdc"; ++ mmu-type = "riscv,sv39"; ++ numa-node-id = <7>; ++ cpu104_intc: interrupt-controller { ++ #interrupt-cells = <1>; ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ }; ++ }; ++ cpu105: cpu@105 { ++ device_type = "cpu"; ++ reg = <105>; ++ status = "okay"; ++ compatible = "riscv"; ++ riscv,isa = "rv64imafdc"; ++ mmu-type = "riscv,sv39"; ++ numa-node-id = <7>; ++ cpu105_intc: interrupt-controller { ++ #interrupt-cells = <1>; ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ }; ++ }; ++ cpu106: cpu@106 { ++ device_type = "cpu"; ++ reg = <106>; ++ status = "okay"; ++ compatible = "riscv"; ++ riscv,isa = "rv64imafdc"; ++ mmu-type = "riscv,sv39"; ++ numa-node-id = <7>; ++ cpu106_intc: interrupt-controller { ++ #interrupt-cells = <1>; ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ }; ++ }; ++ cpu107: cpu@107 { ++ device_type = "cpu"; ++ reg = <107>; ++ status = "okay"; ++ compatible = "riscv"; ++ riscv,isa = "rv64imafdc"; ++ mmu-type = "riscv,sv39"; ++ numa-node-id = <7>; ++ cpu107_intc: interrupt-controller { ++ #interrupt-cells = <1>; ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ }; ++ }; ++ cpu108: cpu@108 { ++ device_type = "cpu"; ++ reg = <108>; ++ status = "okay"; ++ compatible = "riscv"; ++ riscv,isa = "rv64imafdc"; ++ mmu-type = "riscv,sv39"; ++ numa-node-id = <7>; ++ cpu108_intc: interrupt-controller { ++ #interrupt-cells = <1>; ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ }; ++ }; ++ cpu109: cpu@109 { ++ device_type = "cpu"; ++ reg = <109>; ++ status = "okay"; ++ compatible = "riscv"; ++ riscv,isa = "rv64imafdc"; ++ mmu-type = "riscv,sv39"; ++ numa-node-id = <7>; ++ cpu109_intc: interrupt-controller { ++ #interrupt-cells = <1>; ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ }; ++ }; ++ cpu110: cpu@110 { ++ device_type = "cpu"; ++ reg = <110>; ++ status = "okay"; ++ compatible = "riscv"; ++ riscv,isa = "rv64imafdc"; ++ mmu-type = "riscv,sv39"; ++ numa-node-id = <7>; ++ cpu110_intc: interrupt-controller { ++ #interrupt-cells = <1>; ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ }; ++ }; ++ cpu111: cpu@111 { ++ device_type = "cpu"; ++ reg = <111>; ++ status = "okay"; ++ compatible = "riscv"; ++ riscv,isa = "rv64imafdc"; ++ mmu-type = "riscv,sv39"; ++ numa-node-id = <7>; ++ cpu111_intc: interrupt-controller { ++ #interrupt-cells = <1>; ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ }; ++ }; ++ cpu112: cpu@112 { ++ device_type = "cpu"; ++ reg = <112>; ++ status = "okay"; ++ compatible = "riscv"; ++ riscv,isa = "rv64imafdc"; ++ mmu-type = "riscv,sv39"; ++ numa-node-id = <6>; ++ cpu112_intc: interrupt-controller { ++ #interrupt-cells = <1>; ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ }; ++ }; ++ cpu113: cpu@113 { ++ device_type = "cpu"; ++ reg = <113>; ++ status = "okay"; ++ compatible = "riscv"; ++ riscv,isa = "rv64imafdc"; ++ mmu-type = "riscv,sv39"; ++ numa-node-id = <6>; ++ cpu113_intc: interrupt-controller { ++ #interrupt-cells = <1>; ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ }; ++ }; ++ cpu114: cpu@114 { ++ device_type = "cpu"; ++ reg = <114>; ++ status = "okay"; ++ compatible = "riscv"; ++ riscv,isa = "rv64imafdc"; ++ mmu-type = "riscv,sv39"; ++ numa-node-id = <6>; ++ cpu114_intc: interrupt-controller { ++ #interrupt-cells = <1>; ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ }; ++ }; ++ cpu115: cpu@115 { ++ device_type = "cpu"; ++ reg = <115>; ++ status = "okay"; ++ compatible = "riscv"; ++ riscv,isa = "rv64imafdc"; ++ mmu-type = "riscv,sv39"; ++ numa-node-id = <6>; ++ cpu115_intc: interrupt-controller { ++ #interrupt-cells = <1>; ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ }; ++ }; ++ cpu116: cpu@116 { ++ device_type = "cpu"; ++ reg = <116>; ++ status = "okay"; ++ compatible = "riscv"; ++ riscv,isa = "rv64imafdc"; ++ mmu-type = "riscv,sv39"; ++ numa-node-id = <6>; ++ cpu116_intc: interrupt-controller { ++ #interrupt-cells = <1>; ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ }; ++ }; ++ cpu117: cpu@117 { ++ device_type = "cpu"; ++ reg = <117>; ++ status = "okay"; ++ compatible = "riscv"; ++ riscv,isa = "rv64imafdc"; ++ mmu-type = "riscv,sv39"; ++ numa-node-id = <6>; ++ cpu117_intc: interrupt-controller { ++ #interrupt-cells = <1>; ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ }; ++ }; ++ cpu118: cpu@118 { ++ device_type = "cpu"; ++ reg = <118>; ++ status = "okay"; ++ compatible = "riscv"; ++ riscv,isa = "rv64imafdc"; ++ mmu-type = "riscv,sv39"; ++ numa-node-id = <6>; ++ cpu118_intc: interrupt-controller { ++ #interrupt-cells = <1>; ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ }; ++ }; ++ cpu119: cpu@119 { ++ device_type = "cpu"; ++ reg = <119>; ++ status = "okay"; ++ compatible = "riscv"; ++ riscv,isa = "rv64imafdc"; ++ mmu-type = "riscv,sv39"; ++ numa-node-id = <6>; ++ cpu119_intc: interrupt-controller { ++ #interrupt-cells = <1>; ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ }; ++ }; ++ cpu120: cpu@120 { ++ device_type = "cpu"; ++ reg = <120>; ++ status = "okay"; ++ compatible = "riscv"; ++ riscv,isa = "rv64imafdc"; ++ mmu-type = "riscv,sv39"; ++ numa-node-id = <7>; ++ cpu120_intc: interrupt-controller { ++ #interrupt-cells = <1>; ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ }; ++ }; ++ cpu121: cpu@121 { ++ device_type = "cpu"; ++ reg = <121>; ++ status = "okay"; ++ compatible = "riscv"; ++ riscv,isa = "rv64imafdc"; ++ mmu-type = "riscv,sv39"; ++ numa-node-id = <7>; ++ cpu121_intc: interrupt-controller { ++ #interrupt-cells = <1>; ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ }; ++ }; ++ cpu122: cpu@122 { ++ device_type = "cpu"; ++ reg = <122>; ++ status = "okay"; ++ compatible = "riscv"; ++ riscv,isa = "rv64imafdc"; ++ mmu-type = "riscv,sv39"; ++ numa-node-id = <7>; ++ cpu122_intc: interrupt-controller { ++ #interrupt-cells = <1>; ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ }; ++ }; ++ cpu123: cpu@123 { ++ device_type = "cpu"; ++ reg = <123>; ++ status = "okay"; ++ compatible = "riscv"; ++ riscv,isa = "rv64imafdc"; ++ mmu-type = "riscv,sv39"; ++ numa-node-id = <7>; ++ cpu123_intc: interrupt-controller { ++ #interrupt-cells = <1>; ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ }; ++ }; ++ cpu124: cpu@124 { ++ device_type = "cpu"; ++ reg = <124>; ++ status = "okay"; ++ compatible = "riscv"; ++ riscv,isa = "rv64imafdc"; ++ mmu-type = "riscv,sv39"; ++ numa-node-id = <7>; ++ cpu124_intc: interrupt-controller { ++ #interrupt-cells = <1>; ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ }; ++ }; ++ cpu125: cpu@125 { ++ device_type = "cpu"; ++ reg = <125>; ++ status = "okay"; ++ compatible = "riscv"; ++ riscv,isa = "rv64imafdc"; ++ mmu-type = "riscv,sv39"; ++ numa-node-id = <7>; ++ cpu125_intc: interrupt-controller { ++ #interrupt-cells = <1>; ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ }; ++ }; ++ cpu126: cpu@126 { ++ device_type = "cpu"; ++ reg = <126>; ++ status = "okay"; ++ compatible = "riscv"; ++ riscv,isa = "rv64imafdc"; ++ mmu-type = "riscv,sv39"; ++ numa-node-id = <7>; ++ cpu126_intc: interrupt-controller { ++ #interrupt-cells = <1>; ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ }; ++ }; ++ cpu127: cpu@127 { ++ device_type = "cpu"; ++ reg = <127>; ++ status = "okay"; ++ compatible = "riscv"; ++ riscv,isa = "rv64imafdc"; ++ mmu-type = "riscv,sv39"; ++ numa-node-id = <7>; ++ cpu127_intc: interrupt-controller { ++ #interrupt-cells = <1>; ++ compatible = "riscv,cpu-intc"; ++ interrupt-controller; ++ }; ++ }; ++ }; ++}; diff --git a/arch/riscv/boot/dts/sophgo/mango-milkv-pioneer.dts b/arch/riscv/boot/dts/sophgo/mango-milkv-pioneer.dts new file mode 100644 -index 000000000000..00f2d5e2c674 +index 000000000000..3e9bd7ca6793 --- /dev/null +++ b/arch/riscv/boot/dts/sophgo/mango-milkv-pioneer.dts -@@ -0,0 +1,163 @@ +@@ -0,0 +1,170 @@ +#include "mango.dtsi" +#include "mango-pcie-4rc.dtsi" + @@ -2550,6 +4481,13 @@ index 000000000000..00f2d5e2c674 + }; +}; + ++&i2c0 { ++ rtc: rtc@68 { ++ compatible = "dallas,ds1307"; ++ reg = <0x68>; ++ }; ++}; ++ +&i2c1 { + mcu: sg2042mcu@17 { + compatible = "sophgo,sg20xx-mcu"; @@ -2706,10 +4644,10 @@ index 000000000000..00f2d5e2c674 +}; diff --git a/arch/riscv/boot/dts/sophgo/mango-pcie-2rc.dtsi b/arch/riscv/boot/dts/sophgo/mango-pcie-2rc.dtsi new file mode 100644 -index 000000000000..fb4eb57d82f0 +index 000000000000..e39b3a80bf06 --- /dev/null +++ b/arch/riscv/boot/dts/sophgo/mango-pcie-2rc.dtsi -@@ -0,0 +1,83 @@ +@@ -0,0 +1,81 @@ +#include + +#define SOC_PERIPHERAL_IRQ(nr) (nr) @@ -2721,7 +4659,7 @@ index 000000000000..fb4eb57d82f0 + #address-cells = <3>; + #size-cells = <2>; + -+ bus-range = <0x00 0x7f>; ++ bus-range = <0x00 0x3f>; + linux,pci-domain = <0>; + cdns,max-outbound-regions = <16>; + cdns,no-bar-match-nbits = <48>; @@ -2731,7 +4669,7 @@ index 000000000000..fb4eb57d82f0 + link-id = /bits/ 16 <0x0>; + top-intc-used = <1>; + top-intc-id = <0>; -+ msix-supported = <0>; ++ msix-supported = <1>; + interrupt-parent = <&intc1>; + //interrupts = ; + //interrupt-names = "msi"; @@ -2744,12 +4682,11 @@ index 000000000000..fb4eb57d82f0 + // 32bit non-prefetchable memory + // 64bit prefetchable memory + // 64bit non-prefetchable memory -+ ranges = <0x01000000 0x0 0x00000000 0x48 0x10000000 0x0 0x00800000>, -+ <0x42000000 0x0 0x20000000 0x48 0x20000000 0x0 0x50000000>, -+ <0x02000000 0x0 0x70000000 0x48 0x70000000 0x0 0x20000000>, -+ <0x43000000 0x49 0x00000000 0x49 0x00000000 0x2 0x00000000>, -+ <0x03000000 0x4b 0x00000000 0x4b 0x00000000 0x1 0x00000000>; -+ dma-ranges = <0x03000000 0x0 0x0 0x0 0x0 0x1f 0x0>; ++ ranges = <0x01000000 0x0 0xc0000000 0x48 0xc0000000 0x0 0x00400000>, ++ <0x42000000 0x0 0xd0000000 0x48 0xd0000000 0x0 0x10000000>, ++ <0x02000000 0x0 0xe0000000 0x48 0xe0000000 0x0 0x20000000>, ++ <0x43000000 0x4a 0x00000000 0x4a 0x00000000 0x2 0x00000000>, ++ <0x03000000 0x49 0x00000000 0x49 0x00000000 0x1 0x00000000>; + + status = "okay"; + }; @@ -2783,22 +4720,143 @@ index 000000000000..fb4eb57d82f0 + // 32bit non-prefetchable memory + // 64bit prefetchable memory + // 64bit non-prefetchable memory -+ ranges = <0x01000000 0x0 0x00800000 0xc0 0x10800000 0x0 0x00800000>, -+ <0x42000000 0x0 0x90000000 0xc0 0x90000000 0x0 0x50000000>, ++ ranges = <0x01000000 0x0 0xc0800000 0xc0 0xc0800000 0x0 0x00800000>, ++ <0x42000000 0x0 0xd0000000 0xc0 0xd0000000 0x0 0x10000000>, + <0x02000000 0x0 0xe0000000 0xc0 0xe0000000 0x0 0x20000000>, -+ <0x43000000 0xc1 0x00000000 0xc1 0x00000000 0x2 0x00000000>, -+ <0x03000000 0xc3 0x00000000 0xc3 0x00000000 0x1 0x00000000>; -+ dma-ranges = <0x03000000 0x0 0x0 0x0 0x0 0x1f 0x0>; ++ <0x43000000 0xc2 0x00000000 0xc2 0x00000000 0x2 0x00000000>, ++ <0x03000000 0xc1 0x00000000 0xc1 0x00000000 0x1 0x00000000>; ++ ++ status = "okay"; ++ }; ++}; +diff --git a/arch/riscv/boot/dts/sophgo/mango-pcie-3rc-capricorn.dtsi b/arch/riscv/boot/dts/sophgo/mango-pcie-3rc-capricorn.dtsi +new file mode 100644 +index 000000000000..776889585272 +--- /dev/null ++++ b/arch/riscv/boot/dts/sophgo/mango-pcie-3rc-capricorn.dtsi +@@ -0,0 +1,116 @@ ++#include ++ ++#define SOC_PERIPHERAL_IRQ(nr) (nr) ++ ++/ { ++ pcie@7060000000 { ++ compatible = "sophgo,cdns-pcie-host"; ++ device_type = "pci"; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ ++ bus-range = <0x0 0x3f>; ++ linux,pci-domain = <0>; ++ cdns,max-outbound-regions = <16>; ++ cdns,no-bar-match-nbits = <48>; ++ vendor-id = /bits/ 16 <0x1E30>; ++ device-id = /bits/ 16 <0x2042>; ++ pcie-id = /bits/ 16 <0x0>; ++ link-id = /bits/ 16 <0x0>; ++ top-intc-used = <1>; ++ top-intc-id = <0>; ++ msix-supported = <0>; ++ interrupt-parent = <&intc1>; ++ reg = <0x70 0x60000000 0x0 0x02000000>, ++ <0x40 0x00000000 0x0 0x00001000>; ++ reg-names = "reg", "cfg"; ++ ++ // IO, check IO_SPACE_LIMIT ++ // 32bit prefetchable memory ++ // 32bit non-prefetchable memory ++ // 64bit prefetchable memory ++ // 64bit non-prefetchable memory ++ ranges = <0x01000000 0x0 0xc0000000 0x40 0xc0000000 0x0 0x00400000>, ++ <0x42000000 0x0 0xd0000000 0x40 0xd0000000 0x0 0x10000000>, ++ <0x02000000 0x0 0xe0000000 0x40 0xe0000000 0x0 0x20000000>, ++ <0x43000000 0x42 0x00000000 0x42 0x00000000 0x2 0x00000000>, ++ <0x03000000 0x41 0x00000000 0x41 0x00000000 0x1 0x00000000>; ++ //dma-ranges = <0x03000000 0x0 0x0 0x0 0x0 0x1f 0x0>; ++ ++ status = "okay"; ++ }; ++ ++ pcie@7060800000 { ++ compatible = "sophgo,cdns-pcie-host"; ++ device_type = "pci"; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ ++ bus-range = <0x40 0x7f>; ++ linux,pci-domain = <1>; ++ cdns,max-outbound-regions = <16>; ++ cdns,no-bar-match-nbits = <48>; ++ vendor-id = /bits/ 16 <0x1E30>; ++ device-id = /bits/ 16 <0x2042>; ++ pcie-id = /bits/ 16 <0x0>; ++ link-id = /bits/ 16 <0x1>; ++ top-intc-used = <0>; ++ top-intc-id = <0>; ++ interrupt-parent = <&intc>; ++ interrupts = ; ++ interrupt-names = "msi"; ++ reg = <0x44 0x00000000 0x0 0x00001000>; ++ reg-names = "cfg"; ++ ++ // IO, check IO_SPACE_LIMIT ++ // 32bit prefetchable memory ++ // 32bit non-prefetchable memory ++ // 64bit prefetchable memory ++ // 64bit non-prefetchable memory ++ ranges = <0x01000000 0x0 0xc0400000 0x44 0xc0400000 0x0 0x00400000>, ++ <0x42000000 0x0 0xe0000000 0x44 0xe0000000 0x0 0x20000000>, ++ <0x02000000 0x0 0xd0000000 0x44 0xd0000000 0x0 0x10000000>, ++ <0x43000000 0x46 0x00000000 0x46 0x00000000 0x2 0x00000000>, ++ <0x03000000 0x45 0x00000000 0x45 0x00000000 0x1 0x00000000>; ++ //dma-ranges = <0x03000000 0x0 0x0 0x0 0x0 0x1f 0x0>; ++ ++ status = "okay"; ++ }; ++ ++ pcie@7062000000 { ++ compatible = "sophgo,cdns-pcie-host"; ++ device_type = "pci"; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ ++ bus-range = <0x80 0xff>; ++ linux,pci-domain = <2>; ++ cdns,max-outbound-regions = <16>; ++ cdns,no-bar-match-nbits = <48>; ++ vendor-id = /bits/ 16 <0x1E30>; ++ device-id = /bits/ 16 <0x2042>; ++ pcie-id = /bits/ 16 <0x1>; ++ link-id = /bits/ 16 <0x0>; ++ top-intc-used = <0>; ++ interrupt-parent = <&intc>; ++ interrupts = ; ++ interrupt-names = "msi"; ++ reg = <0x70 0x62000000 0x0 0x02000000>, ++ <0x48 0x00000000 0x0 0x00001000>; ++ reg-names = "reg", "cfg"; ++ ++ // IO, check IO_SPACE_LIMIT ++ // 32bit prefetchable memory ++ // 32bit non-prefetchable memory ++ // 64bit prefetchable memory ++ // 64bit non-prefetchable memory ++ ranges = <0x01000000 0x0 0xc0800000 0x48 0xc0800000 0x0 0x00800000>, ++ <0x42000000 0x0 0xd0000000 0x48 0xd0000000 0x0 0x10000000>, ++ <0x02000000 0x0 0xe0000000 0x48 0xe0000000 0x0 0x20000000>, ++ <0x43000000 0x4a 0x00000000 0x4a 0x00000000 0x2 0x00000000>, ++ <0x03000000 0x49 0x00000000 0x49 0x00000000 0x1 0x00000000>; ++ //dma-ranges = <0x03000000 0x0 0x0 0x0 0x0 0x1f 0x0>; + + status = "okay"; + }; +}; diff --git a/arch/riscv/boot/dts/sophgo/mango-pcie-3rc-v2.dtsi b/arch/riscv/boot/dts/sophgo/mango-pcie-3rc-v2.dtsi new file mode 100644 -index 000000000000..0414f892bfb7 +index 000000000000..9c4c9641e1c0 --- /dev/null +++ b/arch/riscv/boot/dts/sophgo/mango-pcie-3rc-v2.dtsi -@@ -0,0 +1,118 @@ +@@ -0,0 +1,115 @@ +#include + +#define SOC_PERIPHERAL_IRQ(nr) (nr) @@ -2832,12 +4890,11 @@ index 000000000000..0414f892bfb7 + // 32bit non-prefetchable memory + // 64bit prefetchable memory + // 64bit non-prefetchable memory -+ ranges = <0x01000000 0x0 0x00000000 0x40 0x10000000 0x0 0x00400000>, -+ <0x42000000 0x0 0xc0000000 0x40 0xc0000000 0x0 0x20000000>, ++ ranges = <0x01000000 0x0 0xc0000000 0x40 0xc0000000 0x0 0x00400000>, ++ <0x42000000 0x0 0xd0000000 0x40 0xd0000000 0x0 0x10000000>, + <0x02000000 0x0 0xe0000000 0x40 0xe0000000 0x0 0x20000000>, + <0x43000000 0x42 0x00000000 0x42 0x00000000 0x2 0x00000000>, + <0x03000000 0x41 0x00000000 0x41 0x00000000 0x1 0x00000000>; -+ dma-ranges = <0x03000000 0x0 0x0 0x0 0x0 0x1f 0x0>; + + status = "okay"; + }; @@ -2870,12 +4927,11 @@ index 000000000000..0414f892bfb7 + // 32bit non-prefetchable memory + // 64bit prefetchable memory + // 64bit non-prefetchable memory -+ ranges = <0x01000000 0x0 0x00400000 0x44 0x10400000 0x0 0x00400000>, ++ ranges = <0x01000000 0x0 0xc0400000 0x44 0xc0400000 0x0 0x00400000>, + <0x42000000 0x0 0xe0000000 0x44 0xe0000000 0x0 0x20000000>, -+ <0x02000000 0x0 0xc0000000 0x44 0xc0000000 0x0 0x20000000>, ++ <0x02000000 0x0 0xd0000000 0x44 0xd0000000 0x0 0x10000000>, + <0x43000000 0x46 0x00000000 0x46 0x00000000 0x2 0x00000000>, + <0x03000000 0x45 0x00000000 0x45 0x00000000 0x1 0x00000000>; -+ dma-ranges = <0x03000000 0x0 0x0 0x0 0x0 0x1f 0x0>; + + status = "okay"; + }; @@ -2907,22 +4963,21 @@ index 000000000000..0414f892bfb7 + // 32bit non-prefetchable memory + // 64bit prefetchable memory + // 64bit non-prefetchable memory -+ ranges = <0x01000000 0x0 0x00800000 0x48 0x10800000 0x0 0x00800000>, -+ <0x42000000 0x0 0xc0000000 0x48 0xc0000000 0x0 0x20000000>, ++ ranges = <0x01000000 0x0 0xc0800000 0x48 0xc0800000 0x0 0x00800000>, ++ <0x42000000 0x0 0xd0000000 0x48 0xd0000000 0x0 0x10000000>, + <0x02000000 0x0 0xe0000000 0x48 0xe0000000 0x0 0x20000000>, + <0x43000000 0x4a 0x00000000 0x4a 0x00000000 0x2 0x00000000>, + <0x03000000 0x49 0x00000000 0x49 0x00000000 0x1 0x00000000>; -+ dma-ranges = <0x03000000 0x0 0x0 0x0 0x0 0x1f 0x0>; + + status = "okay"; + }; +}; diff --git a/arch/riscv/boot/dts/sophgo/mango-pcie-3rc.dtsi b/arch/riscv/boot/dts/sophgo/mango-pcie-3rc.dtsi new file mode 100644 -index 000000000000..296d4207c9b2 +index 000000000000..63fb41b43809 --- /dev/null +++ b/arch/riscv/boot/dts/sophgo/mango-pcie-3rc.dtsi -@@ -0,0 +1,115 @@ +@@ -0,0 +1,112 @@ +#include + +#define SOC_PERIPHERAL_IRQ(nr) (nr) @@ -2955,12 +5010,11 @@ index 000000000000..296d4207c9b2 + // 32bit non-prefetchable memory + // 64bit prefetchable memory + // 64bit non-prefetchable memory -+ ranges = <0x01000000 0x0 0x00000000 0x40 0x10000000 0x0 0x00400000>, -+ <0x42000000 0x0 0xc0000000 0x40 0xc0000000 0x0 0x20000000>, ++ ranges = <0x01000000 0x0 0xc0000000 0x40 0xc0000000 0x0 0x00400000>, ++ <0x42000000 0x0 0xd0000000 0x40 0xd0000000 0x0 0x10000000>, + <0x02000000 0x0 0xe0000000 0x40 0xe0000000 0x0 0x20000000>, + <0x43000000 0x42 0x00000000 0x42 0x00000000 0x2 0x00000000>, + <0x03000000 0x41 0x00000000 0x41 0x00000000 0x1 0x00000000>; -+ dma-ranges = <0x03000000 0x0 0x0 0x0 0x0 0x1f 0x0>; + + status = "okay"; + }; @@ -2991,12 +5045,11 @@ index 000000000000..296d4207c9b2 + // 32bit non-prefetchable memory + // 64bit prefetchable memory + // 64bit non-prefetchable memory -+ ranges = <0x01000000 0x0 0x00400000 0x44 0x10400000 0x0 0x00400000>, -+ <0x42000000 0x0 0xc0000000 0x44 0xc0000000 0x0 0x20000000>, ++ ranges = <0x01000000 0x0 0xc0400000 0x44 0xc0400000 0x0 0x00400000>, ++ <0x42000000 0x0 0xd0000000 0x44 0xd0000000 0x0 0x10000000>, + <0x02000000 0x0 0xe0000000 0x44 0xe0000000 0x0 0x20000000>, + <0x43000000 0x46 0x00000000 0x46 0x00000000 0x2 0x00000000>, + <0x03000000 0x45 0x00000000 0x45 0x00000000 0x1 0x00000000>; -+ dma-ranges = <0x03000000 0x0 0x0 0x0 0x0 0x1f 0x0>; + + status = "okay"; + }; @@ -3028,19 +5081,179 @@ index 000000000000..296d4207c9b2 + // 32bit non-prefetchable memory + // 64bit prefetchable memory + // 64bit non-prefetchable memory -+ ranges = <0x01000000 0x0 0x00800000 0x48 0x10800000 0x0 0x00800000>, -+ <0x42000000 0x0 0xc0000000 0x48 0xc0000000 0x0 0x20000000>, ++ ranges = <0x01000000 0x0 0xc0800000 0x48 0xc0800000 0x0 0x00800000>, ++ <0x42000000 0x0 0xd0000000 0x48 0xd0000000 0x0 0x10000000>, + <0x02000000 0x0 0xe0000000 0x48 0xe0000000 0x0 0x20000000>, + <0x43000000 0x49 0x00000000 0x49 0x00000000 0x1 0x00000000>, + <0x03000000 0x4a 0x00000000 0x4a 0x00000000 0x2 0x00000000>; -+ dma-ranges = <0x03000000 0x0 0x0 0x0 0x0 0x1f 0x0>; ++ ++ status = "okay"; ++ }; ++}; +diff --git a/arch/riscv/boot/dts/sophgo/mango-pcie-4rc-v2.dtsi b/arch/riscv/boot/dts/sophgo/mango-pcie-4rc-v2.dtsi +new file mode 100644 +index 000000000000..efbcc5c04740 +--- /dev/null ++++ b/arch/riscv/boot/dts/sophgo/mango-pcie-4rc-v2.dtsi +@@ -0,0 +1,155 @@ ++#include ++ ++#define SOC_PERIPHERAL_IRQ(nr) (nr) ++ ++/ { ++ pcie@7062000000 { ++ compatible = "sophgo,cdns-pcie-host"; ++ device_type = "pci"; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ ++ bus-range = <0x00 0x3f>; ++ linux,pci-domain = <0>; ++ cdns,max-outbound-regions = <16>; ++ cdns,no-bar-match-nbits = <48>; ++ vendor-id = /bits/ 16 <0x1E30>; ++ device-id = /bits/ 16 <0x2042>; ++ pcie-id = /bits/ 16 <0x1>; ++ link-id = /bits/ 16 <0x0>; ++ top-intc-used = <1>; ++ top-intc-id = <0>; ++ msix-supported = <0>; ++ interrupt-parent = <&intc1>; ++ reg = <0x70 0x62000000 0x0 0x02000000>, ++ <0x48 0x00000000 0x0 0x00001000>; ++ reg-names = "reg", "cfg"; ++ ++ /* ++ * IO, check IO_SPACE_LIMIT ++ * 32bit prefetchable memory ++ * 32bit non-prefetchable memory ++ * 64bit prefetchable memory ++ * 64bit non-prefetchable memory ++ */ ++ ranges = <0x01000000 0x0 0xc0000000 0x48 0xc0000000 0x0 0x00400000>, ++ <0x42000000 0x0 0xd0000000 0x48 0xd0000000 0x0 0x10000000>, ++ <0x02000000 0x0 0xe0000000 0x48 0xe0000000 0x0 0x20000000>, ++ <0x43000000 0x4a 0x00000000 0x4a 0x00000000 0x2 0x00000000>, ++ <0x03000000 0x49 0x00000000 0x49 0x00000000 0x1 0x00000000>; ++ ++ status = "okay"; ++ }; ++ ++ pcie@7062800000 { ++ compatible = "sophgo,cdns-pcie-host"; ++ device_type = "pci"; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ ++ bus-range = <0x40 0x7f>; ++ linux,pci-domain = <1>; ++ cdns,max-outbound-regions = <16>; ++ cdns,no-bar-match-nbits = <48>; ++ vendor-id = /bits/ 16 <0x1E30>; ++ device-id = /bits/ 16 <0x2042>; ++ pcie-id = /bits/ 16 <0x1>; ++ link-id = /bits/ 16 <0x1>; ++ top-intc-used = <1>; ++ top-intc-id = <0>; ++ msix-supported = <0>; ++ interrupt-parent = <&intc1>; ++ reg = <0x4c 0x00000000 0x0 0x00001000>; ++ reg-names = "cfg"; ++ ++ /* ++ * IO, check IO_SPACE_LIMIT ++ * 32bit prefetchable memory ++ * 32bit non-prefetchable memory ++ * 64bit prefetchable memory ++ * 64bit non-prefetchable memory ++ */ ++ ranges = <0x01000000 0x0 0xc0000000 0x4c 0xc0000000 0x0 0x00400000>, ++ <0x42000000 0x0 0xd0000000 0x4c 0xd0000000 0x0 0x10000000>, ++ <0x02000000 0x0 0xe0000000 0x4c 0xe0000000 0x0 0x20000000>, ++ <0x43000000 0x4e 0x00000000 0x4e 0x00000000 0x2 0x00000000>, ++ <0x03000000 0x4d 0x00000000 0x4d 0x00000000 0x1 0x00000000>; ++ ++ status = "okay"; ++ }; ++ ++ pcie@f060000000 { ++ compatible = "sophgo,cdns-pcie-host"; ++ device_type = "pci"; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ ++ bus-range = <0x80 0xbf>; ++ linux,pci-domain = <2>; ++ cdns,max-outbound-regions = <16>; ++ cdns,no-bar-match-nbits = <48>; ++ vendor-id = /bits/ 16 <0x1E30>; ++ device-id = /bits/ 16 <0x2042>; ++ pcie-id = /bits/ 16 <0x0>; ++ link-id = /bits/ 16 <0x0>; ++ top-intc-used = <1>; ++ top-intc-id = <1>; ++ msix-supported = <0>; ++ interrupt-parent = <&intc2>; ++ reg = <0xf0 0x60000000 0x0 0x02000000>, ++ <0xc0 0x00000000 0x0 0x00001000>; ++ reg-names = "reg", "cfg"; ++ ++ /* ++ * IO, check IO_SPACE_LIMIT ++ * 32bit prefetchable memory ++ * 32bit non-prefetchable memory ++ * 64bit prefetchable memory ++ * 64bit non-prefetchable memory ++ */ ++ ranges = <0x01000000 0x0 0xc0000000 0xc0 0xc0000000 0x0 0x00400000>, ++ <0x42000000 0x0 0xd0000000 0xc0 0xd0000000 0x0 0x10000000>, ++ <0x02000000 0x0 0xe0000000 0xc0 0xe0000000 0x0 0x20000000>, ++ <0x43000000 0xc2 0x00000000 0xc2 0x00000000 0x2 0x00000000>, ++ <0x03000000 0xc1 0x00000000 0xc1 0x00000000 0x1 0x00000000>; ++ ++ status = "okay"; ++ }; ++ ++ pcie@f068000000 { ++ compatible = "sophgo,cdns-pcie-host"; ++ device_type = "pci"; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ ++ bus-range = <0xc0 0xff>; ++ linux,pci-domain = <3>; ++ cdns,max-outbound-regions = <16>; ++ cdns,no-bar-match-nbits = <48>; ++ vendor-id = /bits/ 16 <0x1E30>; ++ device-id = /bits/ 16 <0x2042>; ++ pcie-id = /bits/ 16 <0x0>; ++ link-id = /bits/ 16 <0x1>; ++ top-intc-used = <1>; ++ top-intc-id = <1>; ++ msix-supported = <0>; ++ interrupt-parent = <&intc2>; ++ reg = <0xc4 0x00000000 0x0 0x00001000>; ++ reg-names = "cfg"; ++ ++ /* ++ * IO, check IO_SPACE_LIMIT ++ * 32bit prefetchable memory ++ * 32bit non-prefetchable memory ++ * 64bit prefetchable memory ++ * 64bit non-prefetchable memory ++ */ ++ ranges = <0x01000000 0x0 0xc0000000 0xc4 0xc0000000 0x0 0x00400000>, ++ <0x42000000 0x0 0xd0000000 0xc4 0xd0000000 0x0 0x10000000>, ++ <0x02000000 0x0 0xe0000000 0xc4 0xe0000000 0x0 0x20000000>, ++ <0x43000000 0xc6 0x00000000 0xc6 0x00000000 0x2 0x00000000>, ++ <0x03000000 0xc5 0x00000000 0xc5 0x00000000 0x1 0x00000000>; + + status = "okay"; + }; +}; diff --git a/arch/riscv/boot/dts/sophgo/mango-pcie-4rc.dtsi b/arch/riscv/boot/dts/sophgo/mango-pcie-4rc.dtsi new file mode 100644 -index 000000000000..4fe6bd3f52a0 +index 000000000000..22bc466757bf --- /dev/null +++ b/arch/riscv/boot/dts/sophgo/mango-pcie-4rc.dtsi @@ -0,0 +1,151 @@ @@ -3063,10 +5276,14 @@ index 000000000000..4fe6bd3f52a0 + device-id = /bits/ 16 <0x2042>; + pcie-id = /bits/ 16 <0x0>; + link-id = /bits/ 16 <0x0>; -+ top-intc-used = <0>; -+ interrupt-parent = <&intc>; -+ interrupts = ; -+ interrupt-names = "msi"; ++ top-intc-used = <1>; ++ top-intc-id = <0>; ++ msix-supported = <1>; ++ interrupt-parent = <&intc1>; ++ //top-intc-used = <0>; ++ //interrupt-parent = <&intc>; ++ //interrupts = ; ++ //interrupt-names = "msi"; + reg = <0x70 0x60000000 0x0 0x02000000>, + <0x40 0x00000000 0x0 0x00001000>; + reg-names = "reg", "cfg"; @@ -3076,16 +5293,15 @@ index 000000000000..4fe6bd3f52a0 + // 32bit non-prefetchable memory + // 64bit prefetchable memory + // 64bit non-prefetchable memory -+ ranges = <0x01000000 0x0 0x00000000 0x40 0x10000000 0x0 0x00400000>, -+ <0x42000000 0x0 0xc0000000 0x40 0xc0000000 0x0 0x20000000>, ++ ranges = <0x01000000 0x0 0xc0000000 0x40 0xc0000000 0x0 0x00400000>, ++ <0x42000000 0x0 0xd0000000 0x40 0xd0000000 0x0 0x10000000>, + <0x02000000 0x0 0xe0000000 0x40 0xe0000000 0x0 0x20000000>, + <0x43000000 0x42 0x00000000 0x42 0x00000000 0x2 0x00000000>, + <0x03000000 0x41 0x00000000 0x41 0x00000000 0x1 0x00000000>; -+ dma-ranges = <0x03000000 0x0 0x0 0x0 0x0 0x1f 0x0>; + + status = "okay"; + }; -+ ++#if 0 + pcie@7060800000 { + compatible = "sophgo,cdns-pcie-host"; + device_type = "pci"; @@ -3112,16 +5328,15 @@ index 000000000000..4fe6bd3f52a0 + // 32bit non-prefetchable memory + // 64bit prefetchable memory + // 64bit non-prefetchable memory -+ ranges = <0x01000000 0x0 0x00400000 0x44 0x10400000 0x0 0x00400000>, -+ <0x42000000 0x0 0xc0000000 0x44 0xc0000000 0x0 0x20000000>, ++ ranges = <0x01000000 0x0 0xc0400000 0x44 0xc0400000 0x0 0x00400000>, ++ <0x42000000 0x0 0xd0000000 0x44 0xd0000000 0x0 0x10000000>, + <0x02000000 0x0 0xe0000000 0x44 0xe0000000 0x0 0x20000000>, + <0x43000000 0x46 0x00000000 0x46 0x00000000 0x2 0x00000000>, + <0x03000000 0x45 0x00000000 0x45 0x00000000 0x1 0x00000000>; -+ dma-ranges = <0x03000000 0x0 0x0 0x0 0x0 0x1f 0x0>; + + status = "okay"; + }; -+ ++#endif + pcie@7062000000 { + compatible = "sophgo,cdns-pcie-host"; + device_type = "pci"; @@ -3129,7 +5344,7 @@ index 000000000000..4fe6bd3f52a0 + #size-cells = <2>; + + bus-range = <0x80 0xbf>; -+ linux,pci-domain = <2>; ++ linux,pci-domain = <1>; + cdns,max-outbound-regions = <16>; + cdns,no-bar-match-nbits = <48>; + vendor-id = /bits/ 16 <0x1E30>; @@ -3149,12 +5364,11 @@ index 000000000000..4fe6bd3f52a0 + // 32bit non-prefetchable memory + // 64bit prefetchable memory + // 64bit non-prefetchable memory -+ ranges = <0x01000000 0x0 0x00800000 0x48 0x10800000 0x0 0x00400000>, -+ <0x42000000 0x0 0xc0000000 0x48 0xc0000000 0x0 0x20000000>, ++ ranges = <0x01000000 0x0 0xc0800000 0x48 0xc0800000 0x0 0x00400000>, ++ <0x42000000 0x0 0xd0000000 0x48 0xd0000000 0x0 0x10000000>, + <0x02000000 0x0 0xe0000000 0x48 0xe0000000 0x0 0x20000000>, + <0x03000000 0x49 0x00000000 0x49 0x00000000 0x1 0x00000000>, + <0x43000000 0x4a 0x00000000 0x4a 0x00000000 0x2 0x00000000>; -+ dma-ranges = <0x03000000 0x0 0x0 0x0 0x0 0x1f 0x0>; + + status = "okay"; + }; @@ -3166,7 +5380,7 @@ index 000000000000..4fe6bd3f52a0 + #size-cells = <2>; + + bus-range = <0xc0 0xff>; -+ linux,pci-domain = <3>; ++ linux,pci-domain = <2>; + cdns,max-outbound-regions = <16>; + cdns,no-bar-match-nbits = <48>; + vendor-id = /bits/ 16 <0x1E30>; @@ -3185,12 +5399,11 @@ index 000000000000..4fe6bd3f52a0 + // 32bit non-prefetchable memory + // 64bit prefetchable memory + // 64bit non-prefetchable memory -+ ranges = <0x01000000 0x0 0x00c00000 0x4c 0x10c00000 0x0 0x00400000>, -+ <0x42000000 0x0 0xd0000000 0x4c 0xd0000000 0x0 0x20000000>, -+ <0x02000000 0x0 0xf0000000 0x4c 0xf0000000 0x0 0x10000000>, -+ <0x43000000 0x4d 0x00000000 0x4d 0x00000000 0x2 0x00000000>, -+ <0x03000000 0x4f 0x00000000 0x4f 0x00000000 0x1 0x00000000>; -+ dma-ranges = <0x03000000 0x0 0x0 0x0 0x0 0x1f 0x0>; ++ ranges = <0x01000000 0x0 0xc0c00000 0x4c 0xc0c00000 0x0 0x00400000>, ++ <0x42000000 0x0 0xf8000000 0x4c 0xf8000000 0x0 0x04000000>, ++ <0x02000000 0x0 0xfc000000 0x4c 0xfc000000 0x0 0x04000000>, ++ <0x43000000 0x4e 0x00000000 0x4e 0x00000000 0x2 0x00000000>, ++ <0x03000000 0x4d 0x00000000 0x4d 0x00000000 0x1 0x00000000>; + + status = "okay"; + }; @@ -3635,12 +5848,139 @@ index 000000000000..f3fb2e39af26 + }; + }; +}; +diff --git a/arch/riscv/boot/dts/sophgo/mango-sophgo-capricorn.dts b/arch/riscv/boot/dts/sophgo/mango-sophgo-capricorn.dts +new file mode 100644 +index 000000000000..94892b74467f +--- /dev/null ++++ b/arch/riscv/boot/dts/sophgo/mango-sophgo-capricorn.dts +@@ -0,0 +1,57 @@ ++#include "mango.dtsi" ++#include "mango-pcie-3rc-capricorn.dtsi" ++ ++/ { ++ info { ++ file-name = "mango-sophgo-capricorn.dts"; ++ }; ++}; ++ ++ðernet0 { ++ max-speed = <1000>; ++ eth-sophgo-config { ++ autoneg = "enable"; ++ }; ++}; ++ ++&soc { ++ gpio-poweroff { ++ compatible = "gpio-keys"; ++ input-name = "gpio-keys"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&gpio2_acquire>; ++ ++ power { ++ label = "GPIO Key Power"; ++ linux,code = ; ++ gpios = <&port0a 2 GPIO_ACTIVE_HIGH>; ++ linux,input-type = <1>; ++ debounce-interval = <100>; ++ }; ++ }; ++}; ++ ++&port0a { ++ compatible = "snps,dw-apb-gpio-port", "sophgo,gpio0"; ++ ++ cpld_poweroff: cpld-poweroff { ++ compatible = "mango,cpld-poweroff"; ++ gpios = <&port0a 3 GPIO_ACTIVE_HIGH>; ++ }; ++ ++ cpld_reboot: cpld-reboot { ++ compatible = "mango,cpld-reboot"; ++ gpios = <&port0a 5 GPIO_ACTIVE_HIGH>; ++ }; ++}; ++ ++/ { ++ board-info { ++ /* compatible MUST be sophgo,board-info */ ++ compatible = "sophgo,board-info"; ++ /* valid values are: full-function, xmr */ ++ chip-package = "full-function"; ++ /* valid values are: x4, x8 */ ++ ddr-pcb-type = "x4"; ++ }; ++}; +diff --git a/arch/riscv/boot/dts/sophgo/mango-sophgo-pisces.dts b/arch/riscv/boot/dts/sophgo/mango-sophgo-pisces.dts +new file mode 100644 +index 000000000000..98761cbf42e8 +--- /dev/null ++++ b/arch/riscv/boot/dts/sophgo/mango-sophgo-pisces.dts +@@ -0,0 +1,58 @@ ++#include "mango-2sockets.dtsi" ++#include "mango-top-intc2.dtsi" ++#include "mango-pcie-2rc.dtsi" ++ ++/ { ++ info { ++ file-name = "mango-sophgo-pisces.dts"; ++ }; ++}; ++ ++ðernet0 { ++ max-speed = <1000>; ++ eth-sophgo-config { ++ autoneg = "enable"; ++ }; ++}; ++ ++&soc { ++ gpio-poweroff { ++ compatible = "gpio-keys"; ++ input-name = "gpio-keys"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&gpio2_acquire>; ++ ++ power { ++ label = "GPIO Key Power"; ++ linux,code = ; ++ gpios = <&port0a 2 GPIO_ACTIVE_HIGH>; ++ linux,input-type = <1>; ++ debounce-interval = <100>; ++ }; ++ }; ++}; ++ ++&port0a { ++ compatible = "snps,dw-apb-gpio-port", "sophgo,gpio0"; ++ ++ cpld_poweroff: cpld-poweroff { ++ compatible = "mango,cpld-poweroff"; ++ gpios = <&port0a 3 GPIO_ACTIVE_HIGH>; ++ }; ++ ++ cpld_reboot: cpld-reboot { ++ compatible = "mango,cpld-reboot"; ++ gpios = <&port0a 5 GPIO_ACTIVE_HIGH>; ++ }; ++}; ++ ++/ { ++ board-info { ++ /* compatible MUST be sophgo,board-info */ ++ compatible = "sophgo,board-info"; ++ /* valid values are: full-function, xmr */ ++ chip-package = "full-function"; ++ /* valid values are: x4, x8 */ ++ ddr-pcb-type = "x4"; ++ }; ++}; diff --git a/arch/riscv/boot/dts/sophgo/mango-sophgo-x4evb.dts b/arch/riscv/boot/dts/sophgo/mango-sophgo-x4evb.dts new file mode 100644 -index 000000000000..78495159bbb4 +index 000000000000..3fe655eaf69a --- /dev/null +++ b/arch/riscv/boot/dts/sophgo/mango-sophgo-x4evb.dts -@@ -0,0 +1,137 @@ +@@ -0,0 +1,144 @@ +#include "mango.dtsi" +#include "mango-pcie-3rc-v2.dtsi" + @@ -3650,6 +5990,13 @@ index 000000000000..78495159bbb4 + }; +}; + ++&i2c0 { ++ rtc: rtc@68 { ++ compatible = "dallas,ds1307"; ++ reg = <0x68>; ++ }; ++}; ++ +&i2c1 { + mcu: sg2042mcu@17 { + compatible = "sophgo,sg20xx-mcu"; @@ -3780,10 +6127,10 @@ index 000000000000..78495159bbb4 +}; diff --git a/arch/riscv/boot/dts/sophgo/mango-sophgo-x8evb.dts b/arch/riscv/boot/dts/sophgo/mango-sophgo-x8evb.dts new file mode 100644 -index 000000000000..83e4f1411f2e +index 000000000000..9e0cf5348051 --- /dev/null +++ b/arch/riscv/boot/dts/sophgo/mango-sophgo-x8evb.dts -@@ -0,0 +1,165 @@ +@@ -0,0 +1,172 @@ +#include "mango.dtsi" +#include "mango-pcie-3rc.dtsi" + @@ -3793,6 +6140,13 @@ index 000000000000..83e4f1411f2e + }; +}; + ++&i2c0 { ++ rtc: rtc@68 { ++ compatible = "dallas,ds1307"; ++ reg = <0x68>; ++ }; ++}; ++ +&i2c1 { + mcu: sg2042mcu@17 { + compatible = "sophgo,sg20xx-mcu"; @@ -4017,12 +6371,81 @@ index 000000000000..6d364cf6b3c5 + }; + +}; +diff --git a/arch/riscv/boot/dts/sophgo/mango-yixin-s2110.dts b/arch/riscv/boot/dts/sophgo/mango-yixin-s2110.dts +new file mode 100644 +index 000000000000..172421ffc196 +--- /dev/null ++++ b/arch/riscv/boot/dts/sophgo/mango-yixin-s2110.dts +@@ -0,0 +1,63 @@ ++#include "mango-2sockets.dtsi" ++#include "mango-top-intc2.dtsi" ++#include "mango-pcie-4rc-v2.dtsi" ++ ++/ { ++ info { ++ file-name = "mango-yixin-s2110.dts"; ++ }; ++}; ++ ++ðernet0 { ++ max-speed = <1000>; ++ eth-sophgo-config { ++ autoneg = "enable"; ++ }; ++}; ++ ++&soc { ++ gpio-poweroff { ++ compatible = "gpio-keys"; ++ input-name = "gpio-keys"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&gpio2_acquire>; ++ ++ power { ++ label = "GPIO Key Power"; ++ linux,code = ; ++ gpios = <&port0a 2 GPIO_ACTIVE_HIGH>; ++ linux,input-type = <1>; ++ debounce-interval = <100>; ++ }; ++ }; ++}; ++ ++&gpio0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&dbgi2c_release>; ++}; ++ ++&port0a { ++ compatible = "snps,dw-apb-gpio-port", "sophgo,gpio0"; ++ ++ cpld_poweroff: cpld-poweroff { ++ compatible = "mango,cpld-poweroff"; ++ gpios = <&port0a 3 GPIO_ACTIVE_HIGH>; ++ }; ++ ++ cpld_reboot: cpld-reboot { ++ compatible = "mango,cpld-reboot"; ++ gpios = <&port0a 29 GPIO_ACTIVE_HIGH>; ++ }; ++}; ++ ++/ { ++ board-info { ++ /* compatible MUST be sophgo,board-info */ ++ compatible = "sophgo,board-info"; ++ /* valid values are: full-function, xmr */ ++ chip-package = "full-function"; ++ /* valid values are: x4, x8 */ ++ ddr-pcb-type = "x8"; ++ }; ++}; diff --git a/arch/riscv/boot/dts/sophgo/mango.dtsi b/arch/riscv/boot/dts/sophgo/mango.dtsi new file mode 100644 -index 000000000000..9ac0898b0906 +index 000000000000..57f304fc778f --- /dev/null +++ b/arch/riscv/boot/dts/sophgo/mango.dtsi -@@ -0,0 +1,941 @@ +@@ -0,0 +1,938 @@ +/dts-v1/; +#include +#include @@ -4583,9 +7006,8 @@ index 000000000000..9ac0898b0906 + #address-cells = <1>; + #size-cells = <0>; + clocks = <&div_clk GATE_CLK_APB_GPIO>, -+ <&div_clk GATE_CLK_APB_GPIO_INTR>, + <&div_clk GATE_CLK_GPIO_DB>; -+ clock-names = "base_clk", "intr_clk", "db_clk"; ++ clock-names = "bus", "db"; + + port0a: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; @@ -4607,9 +7029,8 @@ index 000000000000..9ac0898b0906 + #address-cells = <1>; + #size-cells = <0>; + clocks = <&div_clk GATE_CLK_APB_GPIO>, -+ <&div_clk GATE_CLK_APB_GPIO_INTR>, + <&div_clk GATE_CLK_GPIO_DB>; -+ clock-names = "base_clk", "intr_clk", "db_clk"; ++ clock-names = "bus", "db"; + + port1a: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; @@ -4631,9 +7052,8 @@ index 000000000000..9ac0898b0906 + #address-cells = <1>; + #size-cells = <0>; + clocks = <&div_clk GATE_CLK_APB_GPIO>, -+ <&div_clk GATE_CLK_APB_GPIO_INTR>, + <&div_clk GATE_CLK_GPIO_DB>; -+ clock-names = "base_clk", "intr_clk", "db_clk"; ++ clock-names = "bus", "db"; + + port2a: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; @@ -4670,7 +7090,7 @@ index 000000000000..9ac0898b0906 + }; + + uart0: serial@7040000000 { -+ compatible = "sophgo,sg2042-uart", "snps,dw-apb-uart"; ++ compatible = "snps,dw-apb-uart"; + reg = <0x00000070 0x40000000 0x00000000 0x00001000>; + interrupt-parent = <&intc>; + interrupts = ; @@ -4683,7 +7103,7 @@ index 000000000000..9ac0898b0906 + }; + + uart1: serial@7040001000 { -+ compatible = "sophgo,sg2042-uart", "snps,dw-apb-uart"; ++ compatible = "snps,dw-apb-uart"; + reg = <0x00000070 0x40001000 0x00000000 0x00001000>; + interrupt-parent = <&intc>; + interrupts = ; @@ -4696,7 +7116,7 @@ index 000000000000..9ac0898b0906 + }; + + uart2: serial@7040002000 { -+ compatible = "sophgo,sg2042-uart", "snps,dw-apb-uart"; ++ compatible = "snps,dw-apb-uart"; + reg = <0x00000070 0x40002000 0x00000000 0x00001000>; + interrupt-parent = <&intc>; + interrupts = ; @@ -4709,7 +7129,7 @@ index 000000000000..9ac0898b0906 + }; + + uart3: serial@7040003000 { -+ compatible = "sophgo,sg2042-uart", "snps,dw-apb-uart"; ++ compatible = "snps,dw-apb-uart"; + reg = <0x00000070 0x40003000 0x00000000 0x00001000>; + interrupt-parent = <&intc>; + interrupts = ; @@ -4964,2384 +7384,6 @@ index 000000000000..9ac0898b0906 + stdout-path = "serial0"; + }; +}; -diff --git a/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi -new file mode 100644 -index 000000000000..b136b6c4128c ---- /dev/null -+++ b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi -@@ -0,0 +1,2000 @@ -+// SPDX-License-Identifier: (GPL-2.0 OR MIT) -+/* -+ * Copyright (C) 2022 Sophgo Technology Inc. All rights reserved. -+ */ -+ -+/ { -+ cpus { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ timebase-frequency = <50000000>; -+ -+ cpu-map { -+ socket0 { -+ cluster0 { -+ core0 { -+ cpu = <&cpu0>; -+ }; -+ core1 { -+ cpu = <&cpu1>; -+ }; -+ core2 { -+ cpu = <&cpu2>; -+ }; -+ core3 { -+ cpu = <&cpu3>; -+ }; -+ }; -+ -+ cluster1 { -+ core0 { -+ cpu = <&cpu4>; -+ }; -+ core1 { -+ cpu = <&cpu5>; -+ }; -+ core2 { -+ cpu = <&cpu6>; -+ }; -+ core3 { -+ cpu = <&cpu7>; -+ }; -+ }; -+ -+ cluster2 { -+ core0 { -+ cpu = <&cpu16>; -+ }; -+ core1 { -+ cpu = <&cpu17>; -+ }; -+ core2 { -+ cpu = <&cpu18>; -+ }; -+ core3 { -+ cpu = <&cpu19>; -+ }; -+ }; -+ -+ cluster3 { -+ core0 { -+ cpu = <&cpu20>; -+ }; -+ core1 { -+ cpu = <&cpu21>; -+ }; -+ core2 { -+ cpu = <&cpu22>; -+ }; -+ core3 { -+ cpu = <&cpu23>; -+ }; -+ }; -+ -+ cluster4 { -+ core0 { -+ cpu = <&cpu8>; -+ }; -+ core1 { -+ cpu = <&cpu9>; -+ }; -+ core2 { -+ cpu = <&cpu10>; -+ }; -+ core3 { -+ cpu = <&cpu11>; -+ }; -+ }; -+ -+ cluster5 { -+ core0 { -+ cpu = <&cpu12>; -+ }; -+ core1 { -+ cpu = <&cpu13>; -+ }; -+ core2 { -+ cpu = <&cpu14>; -+ }; -+ core3 { -+ cpu = <&cpu15>; -+ }; -+ }; -+ -+ cluster6 { -+ core0 { -+ cpu = <&cpu24>; -+ }; -+ core1 { -+ cpu = <&cpu25>; -+ }; -+ core2 { -+ cpu = <&cpu26>; -+ }; -+ core3 { -+ cpu = <&cpu27>; -+ }; -+ }; -+ -+ cluster7 { -+ core0 { -+ cpu = <&cpu28>; -+ }; -+ core1 { -+ cpu = <&cpu29>; -+ }; -+ core2 { -+ cpu = <&cpu30>; -+ }; -+ core3 { -+ cpu = <&cpu31>; -+ }; -+ }; -+ -+ cluster8 { -+ core0 { -+ cpu = <&cpu32>; -+ }; -+ core1 { -+ cpu = <&cpu33>; -+ }; -+ core2 { -+ cpu = <&cpu34>; -+ }; -+ core3 { -+ cpu = <&cpu35>; -+ }; -+ }; -+ -+ cluster9 { -+ core0 { -+ cpu = <&cpu36>; -+ }; -+ core1 { -+ cpu = <&cpu37>; -+ }; -+ core2 { -+ cpu = <&cpu38>; -+ }; -+ core3 { -+ cpu = <&cpu39>; -+ }; -+ }; -+ -+ cluster10 { -+ core0 { -+ cpu = <&cpu48>; -+ }; -+ core1 { -+ cpu = <&cpu49>; -+ }; -+ core2 { -+ cpu = <&cpu50>; -+ }; -+ core3 { -+ cpu = <&cpu51>; -+ }; -+ }; -+ -+ cluster11 { -+ core0 { -+ cpu = <&cpu52>; -+ }; -+ core1 { -+ cpu = <&cpu53>; -+ }; -+ core2 { -+ cpu = <&cpu54>; -+ }; -+ core3 { -+ cpu = <&cpu55>; -+ }; -+ }; -+ -+ cluster12 { -+ core0 { -+ cpu = <&cpu40>; -+ }; -+ core1 { -+ cpu = <&cpu41>; -+ }; -+ core2 { -+ cpu = <&cpu42>; -+ }; -+ core3 { -+ cpu = <&cpu43>; -+ }; -+ }; -+ -+ cluster13 { -+ core0 { -+ cpu = <&cpu44>; -+ }; -+ core1 { -+ cpu = <&cpu45>; -+ }; -+ core2 { -+ cpu = <&cpu46>; -+ }; -+ core3 { -+ cpu = <&cpu47>; -+ }; -+ }; -+ -+ cluster14 { -+ core0 { -+ cpu = <&cpu56>; -+ }; -+ core1 { -+ cpu = <&cpu57>; -+ }; -+ core2 { -+ cpu = <&cpu58>; -+ }; -+ core3 { -+ cpu = <&cpu59>; -+ }; -+ }; -+ -+ cluster15 { -+ core0 { -+ cpu = <&cpu60>; -+ }; -+ core1 { -+ cpu = <&cpu61>; -+ }; -+ core2 { -+ cpu = <&cpu62>; -+ }; -+ core3 { -+ cpu = <&cpu63>; -+ }; -+ }; -+ }; -+ }; -+ -+ cpu0: cpu@0 { -+ compatible = "thead,c920", "riscv"; -+ device_type = "cpu"; -+ riscv,isa = "rv64imafdc"; -+ riscv,isa-base = "rv64i"; -+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -+ "zicntr", "zicsr", "zifencei", -+ "zihpm"; -+ reg = <0>; -+ i-cache-block-size = <64>; -+ i-cache-size = <65536>; -+ i-cache-sets = <512>; -+ d-cache-block-size = <64>; -+ d-cache-size = <65536>; -+ d-cache-sets = <512>; -+ next-level-cache = <&l2_cache0>; -+ mmu-type = "riscv,sv39"; -+ -+ cpu0_intc: interrupt-controller { -+ compatible = "riscv,cpu-intc"; -+ interrupt-controller; -+ #interrupt-cells = <1>; -+ }; -+ }; -+ -+ cpu1: cpu@1 { -+ compatible = "thead,c920", "riscv"; -+ device_type = "cpu"; -+ riscv,isa = "rv64imafdc"; -+ riscv,isa-base = "rv64i"; -+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -+ "zicntr", "zicsr", "zifencei", -+ "zihpm"; -+ reg = <1>; -+ i-cache-block-size = <64>; -+ i-cache-size = <65536>; -+ i-cache-sets = <512>; -+ d-cache-block-size = <64>; -+ d-cache-size = <65536>; -+ d-cache-sets = <512>; -+ next-level-cache = <&l2_cache0>; -+ mmu-type = "riscv,sv39"; -+ -+ cpu1_intc: interrupt-controller { -+ compatible = "riscv,cpu-intc"; -+ interrupt-controller; -+ #interrupt-cells = <1>; -+ }; -+ }; -+ -+ cpu2: cpu@2 { -+ compatible = "thead,c920", "riscv"; -+ device_type = "cpu"; -+ riscv,isa = "rv64imafdc"; -+ riscv,isa-base = "rv64i"; -+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -+ "zicntr", "zicsr", "zifencei", -+ "zihpm"; -+ reg = <2>; -+ i-cache-block-size = <64>; -+ i-cache-size = <65536>; -+ i-cache-sets = <512>; -+ d-cache-block-size = <64>; -+ d-cache-size = <65536>; -+ d-cache-sets = <512>; -+ next-level-cache = <&l2_cache0>; -+ mmu-type = "riscv,sv39"; -+ -+ cpu2_intc: interrupt-controller { -+ compatible = "riscv,cpu-intc"; -+ interrupt-controller; -+ #interrupt-cells = <1>; -+ }; -+ }; -+ -+ cpu3: cpu@3 { -+ compatible = "thead,c920", "riscv"; -+ device_type = "cpu"; -+ riscv,isa = "rv64imafdc"; -+ riscv,isa-base = "rv64i"; -+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -+ "zicntr", "zicsr", "zifencei", -+ "zihpm"; -+ reg = <3>; -+ i-cache-block-size = <64>; -+ i-cache-size = <65536>; -+ i-cache-sets = <512>; -+ d-cache-block-size = <64>; -+ d-cache-size = <65536>; -+ d-cache-sets = <512>; -+ next-level-cache = <&l2_cache0>; -+ mmu-type = "riscv,sv39"; -+ -+ cpu3_intc: interrupt-controller { -+ compatible = "riscv,cpu-intc"; -+ interrupt-controller; -+ #interrupt-cells = <1>; -+ }; -+ }; -+ -+ cpu4: cpu@4 { -+ compatible = "thead,c920", "riscv"; -+ device_type = "cpu"; -+ riscv,isa = "rv64imafdc"; -+ riscv,isa-base = "rv64i"; -+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -+ "zicntr", "zicsr", "zifencei", -+ "zihpm"; -+ reg = <4>; -+ i-cache-block-size = <64>; -+ i-cache-size = <65536>; -+ i-cache-sets = <512>; -+ d-cache-block-size = <64>; -+ d-cache-size = <65536>; -+ d-cache-sets = <512>; -+ next-level-cache = <&l2_cache1>; -+ mmu-type = "riscv,sv39"; -+ -+ cpu4_intc: interrupt-controller { -+ compatible = "riscv,cpu-intc"; -+ interrupt-controller; -+ #interrupt-cells = <1>; -+ }; -+ }; -+ -+ cpu5: cpu@5 { -+ compatible = "thead,c920", "riscv"; -+ device_type = "cpu"; -+ riscv,isa = "rv64imafdc"; -+ riscv,isa-base = "rv64i"; -+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -+ "zicntr", "zicsr", "zifencei", -+ "zihpm"; -+ reg = <5>; -+ i-cache-block-size = <64>; -+ i-cache-size = <65536>; -+ i-cache-sets = <512>; -+ d-cache-block-size = <64>; -+ d-cache-size = <65536>; -+ d-cache-sets = <512>; -+ next-level-cache = <&l2_cache1>; -+ mmu-type = "riscv,sv39"; -+ -+ cpu5_intc: interrupt-controller { -+ compatible = "riscv,cpu-intc"; -+ interrupt-controller; -+ #interrupt-cells = <1>; -+ }; -+ }; -+ -+ cpu6: cpu@6 { -+ compatible = "thead,c920", "riscv"; -+ device_type = "cpu"; -+ riscv,isa = "rv64imafdc"; -+ riscv,isa-base = "rv64i"; -+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -+ "zicntr", "zicsr", "zifencei", -+ "zihpm"; -+ reg = <6>; -+ i-cache-block-size = <64>; -+ i-cache-size = <65536>; -+ i-cache-sets = <512>; -+ d-cache-block-size = <64>; -+ d-cache-size = <65536>; -+ d-cache-sets = <512>; -+ next-level-cache = <&l2_cache1>; -+ mmu-type = "riscv,sv39"; -+ -+ cpu6_intc: interrupt-controller { -+ compatible = "riscv,cpu-intc"; -+ interrupt-controller; -+ #interrupt-cells = <1>; -+ }; -+ }; -+ -+ cpu7: cpu@7 { -+ compatible = "thead,c920", "riscv"; -+ device_type = "cpu"; -+ riscv,isa = "rv64imafdc"; -+ riscv,isa-base = "rv64i"; -+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -+ "zicntr", "zicsr", "zifencei", -+ "zihpm"; -+ reg = <7>; -+ i-cache-block-size = <64>; -+ i-cache-size = <65536>; -+ i-cache-sets = <512>; -+ d-cache-block-size = <64>; -+ d-cache-size = <65536>; -+ d-cache-sets = <512>; -+ next-level-cache = <&l2_cache1>; -+ mmu-type = "riscv,sv39"; -+ -+ cpu7_intc: interrupt-controller { -+ compatible = "riscv,cpu-intc"; -+ interrupt-controller; -+ #interrupt-cells = <1>; -+ }; -+ }; -+ -+ cpu8: cpu@8 { -+ compatible = "thead,c920", "riscv"; -+ device_type = "cpu"; -+ riscv,isa = "rv64imafdc"; -+ riscv,isa-base = "rv64i"; -+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -+ "zicntr", "zicsr", "zifencei", -+ "zihpm"; -+ reg = <8>; -+ i-cache-block-size = <64>; -+ i-cache-size = <65536>; -+ i-cache-sets = <512>; -+ d-cache-block-size = <64>; -+ d-cache-size = <65536>; -+ d-cache-sets = <512>; -+ next-level-cache = <&l2_cache4>; -+ mmu-type = "riscv,sv39"; -+ -+ cpu8_intc: interrupt-controller { -+ compatible = "riscv,cpu-intc"; -+ interrupt-controller; -+ #interrupt-cells = <1>; -+ }; -+ }; -+ -+ cpu9: cpu@9 { -+ compatible = "thead,c920", "riscv"; -+ device_type = "cpu"; -+ riscv,isa = "rv64imafdc"; -+ riscv,isa-base = "rv64i"; -+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -+ "zicntr", "zicsr", "zifencei", -+ "zihpm"; -+ reg = <9>; -+ i-cache-block-size = <64>; -+ i-cache-size = <65536>; -+ i-cache-sets = <512>; -+ d-cache-block-size = <64>; -+ d-cache-size = <65536>; -+ d-cache-sets = <512>; -+ next-level-cache = <&l2_cache4>; -+ mmu-type = "riscv,sv39"; -+ -+ cpu9_intc: interrupt-controller { -+ compatible = "riscv,cpu-intc"; -+ interrupt-controller; -+ #interrupt-cells = <1>; -+ }; -+ }; -+ -+ cpu10: cpu@10 { -+ compatible = "thead,c920", "riscv"; -+ device_type = "cpu"; -+ riscv,isa = "rv64imafdc"; -+ riscv,isa-base = "rv64i"; -+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -+ "zicntr", "zicsr", "zifencei", -+ "zihpm"; -+ reg = <10>; -+ i-cache-block-size = <64>; -+ i-cache-size = <65536>; -+ i-cache-sets = <512>; -+ d-cache-block-size = <64>; -+ d-cache-size = <65536>; -+ d-cache-sets = <512>; -+ next-level-cache = <&l2_cache4>; -+ mmu-type = "riscv,sv39"; -+ -+ cpu10_intc: interrupt-controller { -+ compatible = "riscv,cpu-intc"; -+ interrupt-controller; -+ #interrupt-cells = <1>; -+ }; -+ }; -+ -+ cpu11: cpu@11 { -+ compatible = "thead,c920", "riscv"; -+ device_type = "cpu"; -+ riscv,isa = "rv64imafdc"; -+ riscv,isa-base = "rv64i"; -+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -+ "zicntr", "zicsr", "zifencei", -+ "zihpm"; -+ reg = <11>; -+ i-cache-block-size = <64>; -+ i-cache-size = <65536>; -+ i-cache-sets = <512>; -+ d-cache-block-size = <64>; -+ d-cache-size = <65536>; -+ d-cache-sets = <512>; -+ next-level-cache = <&l2_cache4>; -+ mmu-type = "riscv,sv39"; -+ -+ cpu11_intc: interrupt-controller { -+ compatible = "riscv,cpu-intc"; -+ interrupt-controller; -+ #interrupt-cells = <1>; -+ }; -+ }; -+ -+ cpu12: cpu@12 { -+ compatible = "thead,c920", "riscv"; -+ device_type = "cpu"; -+ riscv,isa = "rv64imafdc"; -+ riscv,isa-base = "rv64i"; -+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -+ "zicntr", "zicsr", "zifencei", -+ "zihpm"; -+ reg = <12>; -+ i-cache-block-size = <64>; -+ i-cache-size = <65536>; -+ i-cache-sets = <512>; -+ d-cache-block-size = <64>; -+ d-cache-size = <65536>; -+ d-cache-sets = <512>; -+ next-level-cache = <&l2_cache5>; -+ mmu-type = "riscv,sv39"; -+ -+ cpu12_intc: interrupt-controller { -+ compatible = "riscv,cpu-intc"; -+ interrupt-controller; -+ #interrupt-cells = <1>; -+ }; -+ }; -+ -+ cpu13: cpu@13 { -+ compatible = "thead,c920", "riscv"; -+ device_type = "cpu"; -+ riscv,isa = "rv64imafdc"; -+ riscv,isa-base = "rv64i"; -+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -+ "zicntr", "zicsr", "zifencei", -+ "zihpm"; -+ reg = <13>; -+ i-cache-block-size = <64>; -+ i-cache-size = <65536>; -+ i-cache-sets = <512>; -+ d-cache-block-size = <64>; -+ d-cache-size = <65536>; -+ d-cache-sets = <512>; -+ next-level-cache = <&l2_cache5>; -+ mmu-type = "riscv,sv39"; -+ -+ cpu13_intc: interrupt-controller { -+ compatible = "riscv,cpu-intc"; -+ interrupt-controller; -+ #interrupt-cells = <1>; -+ }; -+ }; -+ -+ cpu14: cpu@14 { -+ compatible = "thead,c920", "riscv"; -+ device_type = "cpu"; -+ riscv,isa = "rv64imafdc"; -+ riscv,isa-base = "rv64i"; -+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -+ "zicntr", "zicsr", "zifencei", -+ "zihpm"; -+ reg = <14>; -+ i-cache-block-size = <64>; -+ i-cache-size = <65536>; -+ i-cache-sets = <512>; -+ d-cache-block-size = <64>; -+ d-cache-size = <65536>; -+ d-cache-sets = <512>; -+ next-level-cache = <&l2_cache5>; -+ mmu-type = "riscv,sv39"; -+ -+ cpu14_intc: interrupt-controller { -+ compatible = "riscv,cpu-intc"; -+ interrupt-controller; -+ #interrupt-cells = <1>; -+ }; -+ }; -+ -+ cpu15: cpu@15 { -+ compatible = "thead,c920", "riscv"; -+ device_type = "cpu"; -+ riscv,isa = "rv64imafdc"; -+ riscv,isa-base = "rv64i"; -+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -+ "zicntr", "zicsr", "zifencei", -+ "zihpm"; -+ reg = <15>; -+ i-cache-block-size = <64>; -+ i-cache-size = <65536>; -+ i-cache-sets = <512>; -+ d-cache-block-size = <64>; -+ d-cache-size = <65536>; -+ d-cache-sets = <512>; -+ next-level-cache = <&l2_cache5>; -+ mmu-type = "riscv,sv39"; -+ -+ cpu15_intc: interrupt-controller { -+ compatible = "riscv,cpu-intc"; -+ interrupt-controller; -+ #interrupt-cells = <1>; -+ }; -+ }; -+ -+ cpu16: cpu@16 { -+ compatible = "thead,c920", "riscv"; -+ device_type = "cpu"; -+ riscv,isa = "rv64imafdc"; -+ riscv,isa-base = "rv64i"; -+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -+ "zicntr", "zicsr", "zifencei", -+ "zihpm"; -+ reg = <16>; -+ i-cache-block-size = <64>; -+ i-cache-size = <65536>; -+ i-cache-sets = <512>; -+ d-cache-block-size = <64>; -+ d-cache-size = <65536>; -+ d-cache-sets = <512>; -+ next-level-cache = <&l2_cache2>; -+ mmu-type = "riscv,sv39"; -+ -+ cpu16_intc: interrupt-controller { -+ compatible = "riscv,cpu-intc"; -+ interrupt-controller; -+ #interrupt-cells = <1>; -+ }; -+ }; -+ -+ cpu17: cpu@17 { -+ compatible = "thead,c920", "riscv"; -+ device_type = "cpu"; -+ riscv,isa = "rv64imafdc"; -+ riscv,isa-base = "rv64i"; -+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -+ "zicntr", "zicsr", "zifencei", -+ "zihpm"; -+ reg = <17>; -+ i-cache-block-size = <64>; -+ i-cache-size = <65536>; -+ i-cache-sets = <512>; -+ d-cache-block-size = <64>; -+ d-cache-size = <65536>; -+ d-cache-sets = <512>; -+ next-level-cache = <&l2_cache2>; -+ mmu-type = "riscv,sv39"; -+ -+ cpu17_intc: interrupt-controller { -+ compatible = "riscv,cpu-intc"; -+ interrupt-controller; -+ #interrupt-cells = <1>; -+ }; -+ }; -+ -+ cpu18: cpu@18 { -+ compatible = "thead,c920", "riscv"; -+ device_type = "cpu"; -+ riscv,isa = "rv64imafdc"; -+ riscv,isa-base = "rv64i"; -+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -+ "zicntr", "zicsr", "zifencei", -+ "zihpm"; -+ reg = <18>; -+ i-cache-block-size = <64>; -+ i-cache-size = <65536>; -+ i-cache-sets = <512>; -+ d-cache-block-size = <64>; -+ d-cache-size = <65536>; -+ d-cache-sets = <512>; -+ next-level-cache = <&l2_cache2>; -+ mmu-type = "riscv,sv39"; -+ -+ cpu18_intc: interrupt-controller { -+ compatible = "riscv,cpu-intc"; -+ interrupt-controller; -+ #interrupt-cells = <1>; -+ }; -+ }; -+ -+ cpu19: cpu@19 { -+ compatible = "thead,c920", "riscv"; -+ device_type = "cpu"; -+ riscv,isa = "rv64imafdc"; -+ riscv,isa-base = "rv64i"; -+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -+ "zicntr", "zicsr", "zifencei", -+ "zihpm"; -+ reg = <19>; -+ i-cache-block-size = <64>; -+ i-cache-size = <65536>; -+ i-cache-sets = <512>; -+ d-cache-block-size = <64>; -+ d-cache-size = <65536>; -+ d-cache-sets = <512>; -+ next-level-cache = <&l2_cache2>; -+ mmu-type = "riscv,sv39"; -+ -+ cpu19_intc: interrupt-controller { -+ compatible = "riscv,cpu-intc"; -+ interrupt-controller; -+ #interrupt-cells = <1>; -+ }; -+ }; -+ -+ cpu20: cpu@20 { -+ compatible = "thead,c920", "riscv"; -+ device_type = "cpu"; -+ riscv,isa = "rv64imafdc"; -+ riscv,isa-base = "rv64i"; -+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -+ "zicntr", "zicsr", "zifencei", -+ "zihpm"; -+ reg = <20>; -+ i-cache-block-size = <64>; -+ i-cache-size = <65536>; -+ i-cache-sets = <512>; -+ d-cache-block-size = <64>; -+ d-cache-size = <65536>; -+ d-cache-sets = <512>; -+ next-level-cache = <&l2_cache3>; -+ mmu-type = "riscv,sv39"; -+ -+ cpu20_intc: interrupt-controller { -+ compatible = "riscv,cpu-intc"; -+ interrupt-controller; -+ #interrupt-cells = <1>; -+ }; -+ }; -+ -+ cpu21: cpu@21 { -+ compatible = "thead,c920", "riscv"; -+ device_type = "cpu"; -+ riscv,isa = "rv64imafdc"; -+ riscv,isa-base = "rv64i"; -+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -+ "zicntr", "zicsr", "zifencei", -+ "zihpm"; -+ reg = <21>; -+ i-cache-block-size = <64>; -+ i-cache-size = <65536>; -+ i-cache-sets = <512>; -+ d-cache-block-size = <64>; -+ d-cache-size = <65536>; -+ d-cache-sets = <512>; -+ next-level-cache = <&l2_cache3>; -+ mmu-type = "riscv,sv39"; -+ -+ cpu21_intc: interrupt-controller { -+ compatible = "riscv,cpu-intc"; -+ interrupt-controller; -+ #interrupt-cells = <1>; -+ }; -+ }; -+ -+ cpu22: cpu@22 { -+ compatible = "thead,c920", "riscv"; -+ device_type = "cpu"; -+ riscv,isa = "rv64imafdc"; -+ riscv,isa-base = "rv64i"; -+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -+ "zicntr", "zicsr", "zifencei", -+ "zihpm"; -+ reg = <22>; -+ i-cache-block-size = <64>; -+ i-cache-size = <65536>; -+ i-cache-sets = <512>; -+ d-cache-block-size = <64>; -+ d-cache-size = <65536>; -+ d-cache-sets = <512>; -+ next-level-cache = <&l2_cache3>; -+ mmu-type = "riscv,sv39"; -+ -+ cpu22_intc: interrupt-controller { -+ compatible = "riscv,cpu-intc"; -+ interrupt-controller; -+ #interrupt-cells = <1>; -+ }; -+ }; -+ -+ cpu23: cpu@23 { -+ compatible = "thead,c920", "riscv"; -+ device_type = "cpu"; -+ riscv,isa = "rv64imafdc"; -+ riscv,isa-base = "rv64i"; -+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -+ "zicntr", "zicsr", "zifencei", -+ "zihpm"; -+ reg = <23>; -+ i-cache-block-size = <64>; -+ i-cache-size = <65536>; -+ i-cache-sets = <512>; -+ d-cache-block-size = <64>; -+ d-cache-size = <65536>; -+ d-cache-sets = <512>; -+ next-level-cache = <&l2_cache3>; -+ mmu-type = "riscv,sv39"; -+ -+ cpu23_intc: interrupt-controller { -+ compatible = "riscv,cpu-intc"; -+ interrupt-controller; -+ #interrupt-cells = <1>; -+ }; -+ }; -+ -+ cpu24: cpu@24 { -+ compatible = "thead,c920", "riscv"; -+ device_type = "cpu"; -+ riscv,isa = "rv64imafdc"; -+ riscv,isa-base = "rv64i"; -+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -+ "zicntr", "zicsr", "zifencei", -+ "zihpm"; -+ reg = <24>; -+ i-cache-block-size = <64>; -+ i-cache-size = <65536>; -+ i-cache-sets = <512>; -+ d-cache-block-size = <64>; -+ d-cache-size = <65536>; -+ d-cache-sets = <512>; -+ next-level-cache = <&l2_cache6>; -+ mmu-type = "riscv,sv39"; -+ -+ cpu24_intc: interrupt-controller { -+ compatible = "riscv,cpu-intc"; -+ interrupt-controller; -+ #interrupt-cells = <1>; -+ }; -+ }; -+ -+ cpu25: cpu@25 { -+ compatible = "thead,c920", "riscv"; -+ device_type = "cpu"; -+ riscv,isa = "rv64imafdc"; -+ riscv,isa-base = "rv64i"; -+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -+ "zicntr", "zicsr", "zifencei", -+ "zihpm"; -+ reg = <25>; -+ i-cache-block-size = <64>; -+ i-cache-size = <65536>; -+ i-cache-sets = <512>; -+ d-cache-block-size = <64>; -+ d-cache-size = <65536>; -+ d-cache-sets = <512>; -+ next-level-cache = <&l2_cache6>; -+ mmu-type = "riscv,sv39"; -+ -+ cpu25_intc: interrupt-controller { -+ compatible = "riscv,cpu-intc"; -+ interrupt-controller; -+ #interrupt-cells = <1>; -+ }; -+ }; -+ -+ cpu26: cpu@26 { -+ compatible = "thead,c920", "riscv"; -+ device_type = "cpu"; -+ riscv,isa = "rv64imafdc"; -+ riscv,isa-base = "rv64i"; -+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -+ "zicntr", "zicsr", "zifencei", -+ "zihpm"; -+ reg = <26>; -+ i-cache-block-size = <64>; -+ i-cache-size = <65536>; -+ i-cache-sets = <512>; -+ d-cache-block-size = <64>; -+ d-cache-size = <65536>; -+ d-cache-sets = <512>; -+ next-level-cache = <&l2_cache6>; -+ mmu-type = "riscv,sv39"; -+ -+ cpu26_intc: interrupt-controller { -+ compatible = "riscv,cpu-intc"; -+ interrupt-controller; -+ #interrupt-cells = <1>; -+ }; -+ }; -+ -+ cpu27: cpu@27 { -+ compatible = "thead,c920", "riscv"; -+ device_type = "cpu"; -+ riscv,isa = "rv64imafdc"; -+ riscv,isa-base = "rv64i"; -+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -+ "zicntr", "zicsr", "zifencei", -+ "zihpm"; -+ reg = <27>; -+ i-cache-block-size = <64>; -+ i-cache-size = <65536>; -+ i-cache-sets = <512>; -+ d-cache-block-size = <64>; -+ d-cache-size = <65536>; -+ d-cache-sets = <512>; -+ next-level-cache = <&l2_cache6>; -+ mmu-type = "riscv,sv39"; -+ -+ cpu27_intc: interrupt-controller { -+ compatible = "riscv,cpu-intc"; -+ interrupt-controller; -+ #interrupt-cells = <1>; -+ }; -+ }; -+ -+ cpu28: cpu@28 { -+ compatible = "thead,c920", "riscv"; -+ device_type = "cpu"; -+ riscv,isa = "rv64imafdc"; -+ riscv,isa-base = "rv64i"; -+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -+ "zicntr", "zicsr", "zifencei", -+ "zihpm"; -+ reg = <28>; -+ i-cache-block-size = <64>; -+ i-cache-size = <65536>; -+ i-cache-sets = <512>; -+ d-cache-block-size = <64>; -+ d-cache-size = <65536>; -+ d-cache-sets = <512>; -+ next-level-cache = <&l2_cache7>; -+ mmu-type = "riscv,sv39"; -+ -+ cpu28_intc: interrupt-controller { -+ compatible = "riscv,cpu-intc"; -+ interrupt-controller; -+ #interrupt-cells = <1>; -+ }; -+ }; -+ -+ cpu29: cpu@29 { -+ compatible = "thead,c920", "riscv"; -+ device_type = "cpu"; -+ riscv,isa = "rv64imafdc"; -+ riscv,isa-base = "rv64i"; -+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -+ "zicntr", "zicsr", "zifencei", -+ "zihpm"; -+ reg = <29>; -+ i-cache-block-size = <64>; -+ i-cache-size = <65536>; -+ i-cache-sets = <512>; -+ d-cache-block-size = <64>; -+ d-cache-size = <65536>; -+ d-cache-sets = <512>; -+ next-level-cache = <&l2_cache7>; -+ mmu-type = "riscv,sv39"; -+ -+ cpu29_intc: interrupt-controller { -+ compatible = "riscv,cpu-intc"; -+ interrupt-controller; -+ #interrupt-cells = <1>; -+ }; -+ }; -+ -+ cpu30: cpu@30 { -+ compatible = "thead,c920", "riscv"; -+ device_type = "cpu"; -+ riscv,isa = "rv64imafdc"; -+ riscv,isa-base = "rv64i"; -+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -+ "zicntr", "zicsr", "zifencei", -+ "zihpm"; -+ reg = <30>; -+ i-cache-block-size = <64>; -+ i-cache-size = <65536>; -+ i-cache-sets = <512>; -+ d-cache-block-size = <64>; -+ d-cache-size = <65536>; -+ d-cache-sets = <512>; -+ next-level-cache = <&l2_cache7>; -+ mmu-type = "riscv,sv39"; -+ -+ cpu30_intc: interrupt-controller { -+ compatible = "riscv,cpu-intc"; -+ interrupt-controller; -+ #interrupt-cells = <1>; -+ }; -+ }; -+ -+ cpu31: cpu@31 { -+ compatible = "thead,c920", "riscv"; -+ device_type = "cpu"; -+ riscv,isa = "rv64imafdc"; -+ riscv,isa-base = "rv64i"; -+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -+ "zicntr", "zicsr", "zifencei", -+ "zihpm"; -+ reg = <31>; -+ i-cache-block-size = <64>; -+ i-cache-size = <65536>; -+ i-cache-sets = <512>; -+ d-cache-block-size = <64>; -+ d-cache-size = <65536>; -+ d-cache-sets = <512>; -+ next-level-cache = <&l2_cache7>; -+ mmu-type = "riscv,sv39"; -+ -+ cpu31_intc: interrupt-controller { -+ compatible = "riscv,cpu-intc"; -+ interrupt-controller; -+ #interrupt-cells = <1>; -+ }; -+ }; -+ -+ cpu32: cpu@32 { -+ compatible = "thead,c920", "riscv"; -+ device_type = "cpu"; -+ riscv,isa = "rv64imafdc"; -+ riscv,isa-base = "rv64i"; -+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -+ "zicntr", "zicsr", "zifencei", -+ "zihpm"; -+ reg = <32>; -+ i-cache-block-size = <64>; -+ i-cache-size = <65536>; -+ i-cache-sets = <512>; -+ d-cache-block-size = <64>; -+ d-cache-size = <65536>; -+ d-cache-sets = <512>; -+ next-level-cache = <&l2_cache8>; -+ mmu-type = "riscv,sv39"; -+ -+ cpu32_intc: interrupt-controller { -+ compatible = "riscv,cpu-intc"; -+ interrupt-controller; -+ #interrupt-cells = <1>; -+ }; -+ }; -+ -+ cpu33: cpu@33 { -+ compatible = "thead,c920", "riscv"; -+ device_type = "cpu"; -+ riscv,isa = "rv64imafdc"; -+ riscv,isa-base = "rv64i"; -+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -+ "zicntr", "zicsr", "zifencei", -+ "zihpm"; -+ reg = <33>; -+ i-cache-block-size = <64>; -+ i-cache-size = <65536>; -+ i-cache-sets = <512>; -+ d-cache-block-size = <64>; -+ d-cache-size = <65536>; -+ d-cache-sets = <512>; -+ next-level-cache = <&l2_cache8>; -+ mmu-type = "riscv,sv39"; -+ -+ cpu33_intc: interrupt-controller { -+ compatible = "riscv,cpu-intc"; -+ interrupt-controller; -+ #interrupt-cells = <1>; -+ }; -+ }; -+ -+ cpu34: cpu@34 { -+ compatible = "thead,c920", "riscv"; -+ device_type = "cpu"; -+ riscv,isa = "rv64imafdc"; -+ riscv,isa-base = "rv64i"; -+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -+ "zicntr", "zicsr", "zifencei", -+ "zihpm"; -+ reg = <34>; -+ i-cache-block-size = <64>; -+ i-cache-size = <65536>; -+ i-cache-sets = <512>; -+ d-cache-block-size = <64>; -+ d-cache-size = <65536>; -+ d-cache-sets = <512>; -+ next-level-cache = <&l2_cache8>; -+ mmu-type = "riscv,sv39"; -+ -+ cpu34_intc: interrupt-controller { -+ compatible = "riscv,cpu-intc"; -+ interrupt-controller; -+ #interrupt-cells = <1>; -+ }; -+ }; -+ -+ cpu35: cpu@35 { -+ compatible = "thead,c920", "riscv"; -+ device_type = "cpu"; -+ riscv,isa = "rv64imafdc"; -+ riscv,isa-base = "rv64i"; -+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -+ "zicntr", "zicsr", "zifencei", -+ "zihpm"; -+ reg = <35>; -+ i-cache-block-size = <64>; -+ i-cache-size = <65536>; -+ i-cache-sets = <512>; -+ d-cache-block-size = <64>; -+ d-cache-size = <65536>; -+ d-cache-sets = <512>; -+ next-level-cache = <&l2_cache8>; -+ mmu-type = "riscv,sv39"; -+ -+ cpu35_intc: interrupt-controller { -+ compatible = "riscv,cpu-intc"; -+ interrupt-controller; -+ #interrupt-cells = <1>; -+ }; -+ }; -+ -+ cpu36: cpu@36 { -+ compatible = "thead,c920", "riscv"; -+ device_type = "cpu"; -+ riscv,isa = "rv64imafdc"; -+ riscv,isa-base = "rv64i"; -+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -+ "zicntr", "zicsr", "zifencei", -+ "zihpm"; -+ reg = <36>; -+ i-cache-block-size = <64>; -+ i-cache-size = <65536>; -+ i-cache-sets = <512>; -+ d-cache-block-size = <64>; -+ d-cache-size = <65536>; -+ d-cache-sets = <512>; -+ next-level-cache = <&l2_cache9>; -+ mmu-type = "riscv,sv39"; -+ -+ cpu36_intc: interrupt-controller { -+ compatible = "riscv,cpu-intc"; -+ interrupt-controller; -+ #interrupt-cells = <1>; -+ }; -+ }; -+ -+ cpu37: cpu@37 { -+ compatible = "thead,c920", "riscv"; -+ device_type = "cpu"; -+ riscv,isa = "rv64imafdc"; -+ riscv,isa-base = "rv64i"; -+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -+ "zicntr", "zicsr", "zifencei", -+ "zihpm"; -+ reg = <37>; -+ i-cache-block-size = <64>; -+ i-cache-size = <65536>; -+ i-cache-sets = <512>; -+ d-cache-block-size = <64>; -+ d-cache-size = <65536>; -+ d-cache-sets = <512>; -+ next-level-cache = <&l2_cache9>; -+ mmu-type = "riscv,sv39"; -+ -+ cpu37_intc: interrupt-controller { -+ compatible = "riscv,cpu-intc"; -+ interrupt-controller; -+ #interrupt-cells = <1>; -+ }; -+ }; -+ -+ cpu38: cpu@38 { -+ compatible = "thead,c920", "riscv"; -+ device_type = "cpu"; -+ riscv,isa = "rv64imafdc"; -+ riscv,isa-base = "rv64i"; -+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -+ "zicntr", "zicsr", "zifencei", -+ "zihpm"; -+ reg = <38>; -+ i-cache-block-size = <64>; -+ i-cache-size = <65536>; -+ i-cache-sets = <512>; -+ d-cache-block-size = <64>; -+ d-cache-size = <65536>; -+ d-cache-sets = <512>; -+ next-level-cache = <&l2_cache9>; -+ mmu-type = "riscv,sv39"; -+ -+ cpu38_intc: interrupt-controller { -+ compatible = "riscv,cpu-intc"; -+ interrupt-controller; -+ #interrupt-cells = <1>; -+ }; -+ }; -+ -+ cpu39: cpu@39 { -+ compatible = "thead,c920", "riscv"; -+ device_type = "cpu"; -+ riscv,isa = "rv64imafdc"; -+ riscv,isa-base = "rv64i"; -+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -+ "zicntr", "zicsr", "zifencei", -+ "zihpm"; -+ reg = <39>; -+ i-cache-block-size = <64>; -+ i-cache-size = <65536>; -+ i-cache-sets = <512>; -+ d-cache-block-size = <64>; -+ d-cache-size = <65536>; -+ d-cache-sets = <512>; -+ next-level-cache = <&l2_cache9>; -+ mmu-type = "riscv,sv39"; -+ -+ cpu39_intc: interrupt-controller { -+ compatible = "riscv,cpu-intc"; -+ interrupt-controller; -+ #interrupt-cells = <1>; -+ }; -+ }; -+ -+ cpu40: cpu@40 { -+ compatible = "thead,c920", "riscv"; -+ device_type = "cpu"; -+ riscv,isa = "rv64imafdc"; -+ riscv,isa-base = "rv64i"; -+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -+ "zicntr", "zicsr", "zifencei", -+ "zihpm"; -+ reg = <40>; -+ i-cache-block-size = <64>; -+ i-cache-size = <65536>; -+ i-cache-sets = <512>; -+ d-cache-block-size = <64>; -+ d-cache-size = <65536>; -+ d-cache-sets = <512>; -+ next-level-cache = <&l2_cache12>; -+ mmu-type = "riscv,sv39"; -+ -+ cpu40_intc: interrupt-controller { -+ compatible = "riscv,cpu-intc"; -+ interrupt-controller; -+ #interrupt-cells = <1>; -+ }; -+ }; -+ -+ cpu41: cpu@41 { -+ compatible = "thead,c920", "riscv"; -+ device_type = "cpu"; -+ riscv,isa = "rv64imafdc"; -+ riscv,isa-base = "rv64i"; -+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -+ "zicntr", "zicsr", "zifencei", -+ "zihpm"; -+ reg = <41>; -+ i-cache-block-size = <64>; -+ i-cache-size = <65536>; -+ i-cache-sets = <512>; -+ d-cache-block-size = <64>; -+ d-cache-size = <65536>; -+ d-cache-sets = <512>; -+ next-level-cache = <&l2_cache12>; -+ mmu-type = "riscv,sv39"; -+ -+ cpu41_intc: interrupt-controller { -+ compatible = "riscv,cpu-intc"; -+ interrupt-controller; -+ #interrupt-cells = <1>; -+ }; -+ }; -+ -+ cpu42: cpu@42 { -+ compatible = "thead,c920", "riscv"; -+ device_type = "cpu"; -+ riscv,isa = "rv64imafdc"; -+ riscv,isa-base = "rv64i"; -+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -+ "zicntr", "zicsr", "zifencei", -+ "zihpm"; -+ reg = <42>; -+ i-cache-block-size = <64>; -+ i-cache-size = <65536>; -+ i-cache-sets = <512>; -+ d-cache-block-size = <64>; -+ d-cache-size = <65536>; -+ d-cache-sets = <512>; -+ next-level-cache = <&l2_cache12>; -+ mmu-type = "riscv,sv39"; -+ -+ cpu42_intc: interrupt-controller { -+ compatible = "riscv,cpu-intc"; -+ interrupt-controller; -+ #interrupt-cells = <1>; -+ }; -+ }; -+ -+ cpu43: cpu@43 { -+ compatible = "thead,c920", "riscv"; -+ device_type = "cpu"; -+ riscv,isa = "rv64imafdc"; -+ riscv,isa-base = "rv64i"; -+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -+ "zicntr", "zicsr", "zifencei", -+ "zihpm"; -+ reg = <43>; -+ i-cache-block-size = <64>; -+ i-cache-size = <65536>; -+ i-cache-sets = <512>; -+ d-cache-block-size = <64>; -+ d-cache-size = <65536>; -+ d-cache-sets = <512>; -+ next-level-cache = <&l2_cache12>; -+ mmu-type = "riscv,sv39"; -+ -+ cpu43_intc: interrupt-controller { -+ compatible = "riscv,cpu-intc"; -+ interrupt-controller; -+ #interrupt-cells = <1>; -+ }; -+ }; -+ -+ cpu44: cpu@44 { -+ compatible = "thead,c920", "riscv"; -+ device_type = "cpu"; -+ riscv,isa = "rv64imafdc"; -+ riscv,isa-base = "rv64i"; -+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -+ "zicntr", "zicsr", "zifencei", -+ "zihpm"; -+ reg = <44>; -+ i-cache-block-size = <64>; -+ i-cache-size = <65536>; -+ i-cache-sets = <512>; -+ d-cache-block-size = <64>; -+ d-cache-size = <65536>; -+ d-cache-sets = <512>; -+ next-level-cache = <&l2_cache13>; -+ mmu-type = "riscv,sv39"; -+ -+ cpu44_intc: interrupt-controller { -+ compatible = "riscv,cpu-intc"; -+ interrupt-controller; -+ #interrupt-cells = <1>; -+ }; -+ }; -+ -+ cpu45: cpu@45 { -+ compatible = "thead,c920", "riscv"; -+ device_type = "cpu"; -+ riscv,isa = "rv64imafdc"; -+ riscv,isa-base = "rv64i"; -+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -+ "zicntr", "zicsr", "zifencei", -+ "zihpm"; -+ reg = <45>; -+ i-cache-block-size = <64>; -+ i-cache-size = <65536>; -+ i-cache-sets = <512>; -+ d-cache-block-size = <64>; -+ d-cache-size = <65536>; -+ d-cache-sets = <512>; -+ next-level-cache = <&l2_cache13>; -+ mmu-type = "riscv,sv39"; -+ -+ cpu45_intc: interrupt-controller { -+ compatible = "riscv,cpu-intc"; -+ interrupt-controller; -+ #interrupt-cells = <1>; -+ }; -+ }; -+ -+ cpu46: cpu@46 { -+ compatible = "thead,c920", "riscv"; -+ device_type = "cpu"; -+ riscv,isa = "rv64imafdc"; -+ riscv,isa-base = "rv64i"; -+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -+ "zicntr", "zicsr", "zifencei", -+ "zihpm"; -+ reg = <46>; -+ i-cache-block-size = <64>; -+ i-cache-size = <65536>; -+ i-cache-sets = <512>; -+ d-cache-block-size = <64>; -+ d-cache-size = <65536>; -+ d-cache-sets = <512>; -+ next-level-cache = <&l2_cache13>; -+ mmu-type = "riscv,sv39"; -+ -+ cpu46_intc: interrupt-controller { -+ compatible = "riscv,cpu-intc"; -+ interrupt-controller; -+ #interrupt-cells = <1>; -+ }; -+ }; -+ -+ cpu47: cpu@47 { -+ compatible = "thead,c920", "riscv"; -+ device_type = "cpu"; -+ riscv,isa = "rv64imafdc"; -+ riscv,isa-base = "rv64i"; -+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -+ "zicntr", "zicsr", "zifencei", -+ "zihpm"; -+ reg = <47>; -+ i-cache-block-size = <64>; -+ i-cache-size = <65536>; -+ i-cache-sets = <512>; -+ d-cache-block-size = <64>; -+ d-cache-size = <65536>; -+ d-cache-sets = <512>; -+ next-level-cache = <&l2_cache13>; -+ mmu-type = "riscv,sv39"; -+ -+ cpu47_intc: interrupt-controller { -+ compatible = "riscv,cpu-intc"; -+ interrupt-controller; -+ #interrupt-cells = <1>; -+ }; -+ }; -+ -+ cpu48: cpu@48 { -+ compatible = "thead,c920", "riscv"; -+ device_type = "cpu"; -+ riscv,isa = "rv64imafdc"; -+ riscv,isa-base = "rv64i"; -+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -+ "zicntr", "zicsr", "zifencei", -+ "zihpm"; -+ reg = <48>; -+ i-cache-block-size = <64>; -+ i-cache-size = <65536>; -+ i-cache-sets = <512>; -+ d-cache-block-size = <64>; -+ d-cache-size = <65536>; -+ d-cache-sets = <512>; -+ next-level-cache = <&l2_cache10>; -+ mmu-type = "riscv,sv39"; -+ -+ cpu48_intc: interrupt-controller { -+ compatible = "riscv,cpu-intc"; -+ interrupt-controller; -+ #interrupt-cells = <1>; -+ }; -+ }; -+ -+ cpu49: cpu@49 { -+ compatible = "thead,c920", "riscv"; -+ device_type = "cpu"; -+ riscv,isa = "rv64imafdc"; -+ riscv,isa-base = "rv64i"; -+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -+ "zicntr", "zicsr", "zifencei", -+ "zihpm"; -+ reg = <49>; -+ i-cache-block-size = <64>; -+ i-cache-size = <65536>; -+ i-cache-sets = <512>; -+ d-cache-block-size = <64>; -+ d-cache-size = <65536>; -+ d-cache-sets = <512>; -+ next-level-cache = <&l2_cache10>; -+ mmu-type = "riscv,sv39"; -+ -+ cpu49_intc: interrupt-controller { -+ compatible = "riscv,cpu-intc"; -+ interrupt-controller; -+ #interrupt-cells = <1>; -+ }; -+ }; -+ -+ cpu50: cpu@50 { -+ compatible = "thead,c920", "riscv"; -+ device_type = "cpu"; -+ riscv,isa = "rv64imafdc"; -+ riscv,isa-base = "rv64i"; -+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -+ "zicntr", "zicsr", "zifencei", -+ "zihpm"; -+ reg = <50>; -+ i-cache-block-size = <64>; -+ i-cache-size = <65536>; -+ i-cache-sets = <512>; -+ d-cache-block-size = <64>; -+ d-cache-size = <65536>; -+ d-cache-sets = <512>; -+ next-level-cache = <&l2_cache10>; -+ mmu-type = "riscv,sv39"; -+ -+ cpu50_intc: interrupt-controller { -+ compatible = "riscv,cpu-intc"; -+ interrupt-controller; -+ #interrupt-cells = <1>; -+ }; -+ }; -+ -+ cpu51: cpu@51 { -+ compatible = "thead,c920", "riscv"; -+ device_type = "cpu"; -+ riscv,isa = "rv64imafdc"; -+ riscv,isa-base = "rv64i"; -+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -+ "zicntr", "zicsr", "zifencei", -+ "zihpm"; -+ reg = <51>; -+ i-cache-block-size = <64>; -+ i-cache-size = <65536>; -+ i-cache-sets = <512>; -+ d-cache-block-size = <64>; -+ d-cache-size = <65536>; -+ d-cache-sets = <512>; -+ next-level-cache = <&l2_cache10>; -+ mmu-type = "riscv,sv39"; -+ -+ cpu51_intc: interrupt-controller { -+ compatible = "riscv,cpu-intc"; -+ interrupt-controller; -+ #interrupt-cells = <1>; -+ }; -+ }; -+ -+ cpu52: cpu@52 { -+ compatible = "thead,c920", "riscv"; -+ device_type = "cpu"; -+ riscv,isa = "rv64imafdc"; -+ riscv,isa-base = "rv64i"; -+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -+ "zicntr", "zicsr", "zifencei", -+ "zihpm"; -+ reg = <52>; -+ i-cache-block-size = <64>; -+ i-cache-size = <65536>; -+ i-cache-sets = <512>; -+ d-cache-block-size = <64>; -+ d-cache-size = <65536>; -+ d-cache-sets = <512>; -+ next-level-cache = <&l2_cache11>; -+ mmu-type = "riscv,sv39"; -+ -+ cpu52_intc: interrupt-controller { -+ compatible = "riscv,cpu-intc"; -+ interrupt-controller; -+ #interrupt-cells = <1>; -+ }; -+ }; -+ -+ cpu53: cpu@53 { -+ compatible = "thead,c920", "riscv"; -+ device_type = "cpu"; -+ riscv,isa = "rv64imafdc"; -+ riscv,isa-base = "rv64i"; -+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -+ "zicntr", "zicsr", "zifencei", -+ "zihpm"; -+ reg = <53>; -+ i-cache-block-size = <64>; -+ i-cache-size = <65536>; -+ i-cache-sets = <512>; -+ d-cache-block-size = <64>; -+ d-cache-size = <65536>; -+ d-cache-sets = <512>; -+ next-level-cache = <&l2_cache11>; -+ mmu-type = "riscv,sv39"; -+ -+ cpu53_intc: interrupt-controller { -+ compatible = "riscv,cpu-intc"; -+ interrupt-controller; -+ #interrupt-cells = <1>; -+ }; -+ }; -+ -+ cpu54: cpu@54 { -+ compatible = "thead,c920", "riscv"; -+ device_type = "cpu"; -+ riscv,isa = "rv64imafdc"; -+ riscv,isa-base = "rv64i"; -+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -+ "zicntr", "zicsr", "zifencei", -+ "zihpm"; -+ reg = <54>; -+ i-cache-block-size = <64>; -+ i-cache-size = <65536>; -+ i-cache-sets = <512>; -+ d-cache-block-size = <64>; -+ d-cache-size = <65536>; -+ d-cache-sets = <512>; -+ next-level-cache = <&l2_cache11>; -+ mmu-type = "riscv,sv39"; -+ -+ cpu54_intc: interrupt-controller { -+ compatible = "riscv,cpu-intc"; -+ interrupt-controller; -+ #interrupt-cells = <1>; -+ }; -+ }; -+ -+ cpu55: cpu@55 { -+ compatible = "thead,c920", "riscv"; -+ device_type = "cpu"; -+ riscv,isa = "rv64imafdc"; -+ riscv,isa-base = "rv64i"; -+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -+ "zicntr", "zicsr", "zifencei", -+ "zihpm"; -+ reg = <55>; -+ i-cache-block-size = <64>; -+ i-cache-size = <65536>; -+ i-cache-sets = <512>; -+ d-cache-block-size = <64>; -+ d-cache-size = <65536>; -+ d-cache-sets = <512>; -+ next-level-cache = <&l2_cache11>; -+ mmu-type = "riscv,sv39"; -+ -+ cpu55_intc: interrupt-controller { -+ compatible = "riscv,cpu-intc"; -+ interrupt-controller; -+ #interrupt-cells = <1>; -+ }; -+ }; -+ -+ cpu56: cpu@56 { -+ compatible = "thead,c920", "riscv"; -+ device_type = "cpu"; -+ riscv,isa = "rv64imafdc"; -+ riscv,isa-base = "rv64i"; -+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -+ "zicntr", "zicsr", "zifencei", -+ "zihpm"; -+ reg = <56>; -+ i-cache-block-size = <64>; -+ i-cache-size = <65536>; -+ i-cache-sets = <512>; -+ d-cache-block-size = <64>; -+ d-cache-size = <65536>; -+ d-cache-sets = <512>; -+ next-level-cache = <&l2_cache14>; -+ mmu-type = "riscv,sv39"; -+ -+ cpu56_intc: interrupt-controller { -+ compatible = "riscv,cpu-intc"; -+ interrupt-controller; -+ #interrupt-cells = <1>; -+ }; -+ }; -+ -+ cpu57: cpu@57 { -+ compatible = "thead,c920", "riscv"; -+ device_type = "cpu"; -+ riscv,isa = "rv64imafdc"; -+ riscv,isa-base = "rv64i"; -+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -+ "zicntr", "zicsr", "zifencei", -+ "zihpm"; -+ reg = <57>; -+ i-cache-block-size = <64>; -+ i-cache-size = <65536>; -+ i-cache-sets = <512>; -+ d-cache-block-size = <64>; -+ d-cache-size = <65536>; -+ d-cache-sets = <512>; -+ next-level-cache = <&l2_cache14>; -+ mmu-type = "riscv,sv39"; -+ -+ cpu57_intc: interrupt-controller { -+ compatible = "riscv,cpu-intc"; -+ interrupt-controller; -+ #interrupt-cells = <1>; -+ }; -+ }; -+ -+ cpu58: cpu@58 { -+ compatible = "thead,c920", "riscv"; -+ device_type = "cpu"; -+ riscv,isa = "rv64imafdc"; -+ riscv,isa-base = "rv64i"; -+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -+ "zicntr", "zicsr", "zifencei", -+ "zihpm"; -+ reg = <58>; -+ i-cache-block-size = <64>; -+ i-cache-size = <65536>; -+ i-cache-sets = <512>; -+ d-cache-block-size = <64>; -+ d-cache-size = <65536>; -+ d-cache-sets = <512>; -+ next-level-cache = <&l2_cache14>; -+ mmu-type = "riscv,sv39"; -+ -+ cpu58_intc: interrupt-controller { -+ compatible = "riscv,cpu-intc"; -+ interrupt-controller; -+ #interrupt-cells = <1>; -+ }; -+ }; -+ -+ cpu59: cpu@59 { -+ compatible = "thead,c920", "riscv"; -+ device_type = "cpu"; -+ riscv,isa = "rv64imafdc"; -+ riscv,isa-base = "rv64i"; -+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -+ "zicntr", "zicsr", "zifencei", -+ "zihpm"; -+ reg = <59>; -+ i-cache-block-size = <64>; -+ i-cache-size = <65536>; -+ i-cache-sets = <512>; -+ d-cache-block-size = <64>; -+ d-cache-size = <65536>; -+ d-cache-sets = <512>; -+ next-level-cache = <&l2_cache14>; -+ mmu-type = "riscv,sv39"; -+ -+ cpu59_intc: interrupt-controller { -+ compatible = "riscv,cpu-intc"; -+ interrupt-controller; -+ #interrupt-cells = <1>; -+ }; -+ }; -+ -+ cpu60: cpu@60 { -+ compatible = "thead,c920", "riscv"; -+ device_type = "cpu"; -+ riscv,isa = "rv64imafdc"; -+ riscv,isa-base = "rv64i"; -+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -+ "zicntr", "zicsr", "zifencei", -+ "zihpm"; -+ reg = <60>; -+ i-cache-block-size = <64>; -+ i-cache-size = <65536>; -+ i-cache-sets = <512>; -+ d-cache-block-size = <64>; -+ d-cache-size = <65536>; -+ d-cache-sets = <512>; -+ next-level-cache = <&l2_cache15>; -+ mmu-type = "riscv,sv39"; -+ -+ cpu60_intc: interrupt-controller { -+ compatible = "riscv,cpu-intc"; -+ interrupt-controller; -+ #interrupt-cells = <1>; -+ }; -+ }; -+ -+ cpu61: cpu@61 { -+ compatible = "thead,c920", "riscv"; -+ device_type = "cpu"; -+ riscv,isa = "rv64imafdc"; -+ riscv,isa-base = "rv64i"; -+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -+ "zicntr", "zicsr", "zifencei", -+ "zihpm"; -+ reg = <61>; -+ i-cache-block-size = <64>; -+ i-cache-size = <65536>; -+ i-cache-sets = <512>; -+ d-cache-block-size = <64>; -+ d-cache-size = <65536>; -+ d-cache-sets = <512>; -+ next-level-cache = <&l2_cache15>; -+ mmu-type = "riscv,sv39"; -+ -+ cpu61_intc: interrupt-controller { -+ compatible = "riscv,cpu-intc"; -+ interrupt-controller; -+ #interrupt-cells = <1>; -+ }; -+ }; -+ -+ cpu62: cpu@62 { -+ compatible = "thead,c920", "riscv"; -+ device_type = "cpu"; -+ riscv,isa = "rv64imafdc"; -+ riscv,isa-base = "rv64i"; -+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -+ "zicntr", "zicsr", "zifencei", -+ "zihpm"; -+ reg = <62>; -+ i-cache-block-size = <64>; -+ i-cache-size = <65536>; -+ i-cache-sets = <512>; -+ d-cache-block-size = <64>; -+ d-cache-size = <65536>; -+ d-cache-sets = <512>; -+ next-level-cache = <&l2_cache15>; -+ mmu-type = "riscv,sv39"; -+ -+ cpu62_intc: interrupt-controller { -+ compatible = "riscv,cpu-intc"; -+ interrupt-controller; -+ #interrupt-cells = <1>; -+ }; -+ }; -+ -+ cpu63: cpu@63 { -+ compatible = "thead,c920", "riscv"; -+ device_type = "cpu"; -+ riscv,isa = "rv64imafdc"; -+ riscv,isa-base = "rv64i"; -+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", -+ "zicntr", "zicsr", "zifencei", -+ "zihpm"; -+ reg = <63>; -+ i-cache-block-size = <64>; -+ i-cache-size = <65536>; -+ i-cache-sets = <512>; -+ d-cache-block-size = <64>; -+ d-cache-size = <65536>; -+ d-cache-sets = <512>; -+ next-level-cache = <&l2_cache15>; -+ mmu-type = "riscv,sv39"; -+ -+ cpu63_intc: interrupt-controller { -+ compatible = "riscv,cpu-intc"; -+ interrupt-controller; -+ #interrupt-cells = <1>; -+ }; -+ }; -+ -+ l2_cache0: cache-controller-0 { -+ compatible = "cache"; -+ cache-block-size = <64>; -+ cache-level = <2>; -+ cache-size = <1048576>; -+ cache-sets = <1024>; -+ cache-unified; -+ }; -+ -+ l2_cache1: cache-controller-1 { -+ compatible = "cache"; -+ cache-block-size = <64>; -+ cache-level = <2>; -+ cache-size = <1048576>; -+ cache-sets = <1024>; -+ cache-unified; -+ }; -+ -+ l2_cache2: cache-controller-2 { -+ compatible = "cache"; -+ cache-block-size = <64>; -+ cache-level = <2>; -+ cache-size = <1048576>; -+ cache-sets = <1024>; -+ cache-unified; -+ }; -+ -+ l2_cache3: cache-controller-3 { -+ compatible = "cache"; -+ cache-block-size = <64>; -+ cache-level = <2>; -+ cache-size = <1048576>; -+ cache-sets = <1024>; -+ cache-unified; -+ }; -+ -+ l2_cache4: cache-controller-4 { -+ compatible = "cache"; -+ cache-block-size = <64>; -+ cache-level = <2>; -+ cache-size = <1048576>; -+ cache-sets = <1024>; -+ cache-unified; -+ }; -+ -+ l2_cache5: cache-controller-5 { -+ compatible = "cache"; -+ cache-block-size = <64>; -+ cache-level = <2>; -+ cache-size = <1048576>; -+ cache-sets = <1024>; -+ cache-unified; -+ }; -+ -+ l2_cache6: cache-controller-6 { -+ compatible = "cache"; -+ cache-block-size = <64>; -+ cache-level = <2>; -+ cache-size = <1048576>; -+ cache-sets = <1024>; -+ cache-unified; -+ }; -+ -+ l2_cache7: cache-controller-7 { -+ compatible = "cache"; -+ cache-block-size = <64>; -+ cache-level = <2>; -+ cache-size = <1048576>; -+ cache-sets = <1024>; -+ cache-unified; -+ }; -+ -+ l2_cache8: cache-controller-8 { -+ compatible = "cache"; -+ cache-block-size = <64>; -+ cache-level = <2>; -+ cache-size = <1048576>; -+ cache-sets = <1024>; -+ cache-unified; -+ }; -+ -+ l2_cache9: cache-controller-9 { -+ compatible = "cache"; -+ cache-block-size = <64>; -+ cache-level = <2>; -+ cache-size = <1048576>; -+ cache-sets = <1024>; -+ cache-unified; -+ }; -+ -+ l2_cache10: cache-controller-10 { -+ compatible = "cache"; -+ cache-block-size = <64>; -+ cache-level = <2>; -+ cache-size = <1048576>; -+ cache-sets = <1024>; -+ cache-unified; -+ }; -+ -+ l2_cache11: cache-controller-11 { -+ compatible = "cache"; -+ cache-block-size = <64>; -+ cache-level = <2>; -+ cache-size = <1048576>; -+ cache-sets = <1024>; -+ cache-unified; -+ }; -+ -+ l2_cache12: cache-controller-12 { -+ compatible = "cache"; -+ cache-block-size = <64>; -+ cache-level = <2>; -+ cache-size = <1048576>; -+ cache-sets = <1024>; -+ cache-unified; -+ }; -+ -+ l2_cache13: cache-controller-13 { -+ compatible = "cache"; -+ cache-block-size = <64>; -+ cache-level = <2>; -+ cache-size = <1048576>; -+ cache-sets = <1024>; -+ cache-unified; -+ }; -+ -+ l2_cache14: cache-controller-14 { -+ compatible = "cache"; -+ cache-block-size = <64>; -+ cache-level = <2>; -+ cache-size = <1048576>; -+ cache-sets = <1024>; -+ cache-unified; -+ }; -+ -+ l2_cache15: cache-controller-15 { -+ compatible = "cache"; -+ cache-block-size = <64>; -+ cache-level = <2>; -+ cache-size = <1048576>; -+ cache-sets = <1024>; -+ cache-unified; -+ }; -+ }; -+}; -diff --git a/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts b/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts -new file mode 100644 -index 000000000000..49b4b9c2c101 ---- /dev/null -+++ b/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts -@@ -0,0 +1,19 @@ -+// SPDX-License-Identifier: GPL-2.0 OR MIT -+/* -+ * Copyright (C) 2022 Sophgo Technology Inc. All rights reserved. -+ */ -+ -+#include "sg2042.dtsi" -+ -+/ { -+ model = "Milk-V Pioneer"; -+ compatible = "milkv,pioneer", "sophgo,sg2042"; -+ -+ chosen { -+ stdout-path = "serial0"; -+ }; -+}; -+ -+&uart0 { -+ status = "okay"; -+}; -diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/sophgo/sg2042.dtsi -new file mode 100644 -index 000000000000..ead1cc35d88b ---- /dev/null -+++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi -@@ -0,0 +1,341 @@ -+// SPDX-License-Identifier: (GPL-2.0 OR MIT) -+/* -+ * Copyright (C) 2022 Sophgo Technology Inc. All rights reserved. -+ */ -+ -+/dts-v1/; -+#include -+ -+#include "sg2042-cpus.dtsi" -+ -+/ { -+ compatible = "sophgo,sg2042"; -+ #address-cells = <2>; -+ #size-cells = <2>; -+ dma-noncoherent; -+ -+ aliases { -+ serial0 = &uart0; -+ }; -+ -+ soc: soc { -+ compatible = "simple-bus"; -+ #address-cells = <2>; -+ #size-cells = <2>; -+ ranges; -+ -+ clint_mswi: interrupt-controller@7094000000 { -+ compatible = "sophgo,sg2042-aclint-mswi", "thead,c900-aclint-mswi"; -+ reg = <0x00000070 0x94000000 0x00000000 0x00004000>; -+ interrupts-extended = <&cpu0_intc 3>, -+ <&cpu1_intc 3>, -+ <&cpu2_intc 3>, -+ <&cpu3_intc 3>, -+ <&cpu4_intc 3>, -+ <&cpu5_intc 3>, -+ <&cpu6_intc 3>, -+ <&cpu7_intc 3>, -+ <&cpu8_intc 3>, -+ <&cpu9_intc 3>, -+ <&cpu10_intc 3>, -+ <&cpu11_intc 3>, -+ <&cpu12_intc 3>, -+ <&cpu13_intc 3>, -+ <&cpu14_intc 3>, -+ <&cpu15_intc 3>, -+ <&cpu16_intc 3>, -+ <&cpu17_intc 3>, -+ <&cpu18_intc 3>, -+ <&cpu19_intc 3>, -+ <&cpu20_intc 3>, -+ <&cpu21_intc 3>, -+ <&cpu22_intc 3>, -+ <&cpu23_intc 3>, -+ <&cpu24_intc 3>, -+ <&cpu25_intc 3>, -+ <&cpu26_intc 3>, -+ <&cpu27_intc 3>, -+ <&cpu28_intc 3>, -+ <&cpu29_intc 3>, -+ <&cpu30_intc 3>, -+ <&cpu31_intc 3>, -+ <&cpu32_intc 3>, -+ <&cpu33_intc 3>, -+ <&cpu34_intc 3>, -+ <&cpu35_intc 3>, -+ <&cpu36_intc 3>, -+ <&cpu37_intc 3>, -+ <&cpu38_intc 3>, -+ <&cpu39_intc 3>, -+ <&cpu40_intc 3>, -+ <&cpu41_intc 3>, -+ <&cpu42_intc 3>, -+ <&cpu43_intc 3>, -+ <&cpu44_intc 3>, -+ <&cpu45_intc 3>, -+ <&cpu46_intc 3>, -+ <&cpu47_intc 3>, -+ <&cpu48_intc 3>, -+ <&cpu49_intc 3>, -+ <&cpu50_intc 3>, -+ <&cpu51_intc 3>, -+ <&cpu52_intc 3>, -+ <&cpu53_intc 3>, -+ <&cpu54_intc 3>, -+ <&cpu55_intc 3>, -+ <&cpu56_intc 3>, -+ <&cpu57_intc 3>, -+ <&cpu58_intc 3>, -+ <&cpu59_intc 3>, -+ <&cpu60_intc 3>, -+ <&cpu61_intc 3>, -+ <&cpu62_intc 3>, -+ <&cpu63_intc 3>; -+ }; -+ -+ clint_mtimer0: timer@70ac004000 { -+ compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; -+ reg = <0x00000070 0xac004000 0x00000000 0x0000c000>; -+ reg-names = "mtimecmp"; -+ interrupts-extended = <&cpu0_intc 7>, -+ <&cpu1_intc 7>, -+ <&cpu2_intc 7>, -+ <&cpu3_intc 7>; -+ }; -+ -+ clint_mtimer1: timer@70ac014000 { -+ compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; -+ reg = <0x00000070 0xac014000 0x00000000 0x0000c000>; -+ reg-names = "mtimecmp"; -+ interrupts-extended = <&cpu4_intc 7>, -+ <&cpu5_intc 7>, -+ <&cpu6_intc 7>, -+ <&cpu7_intc 7>; -+ }; -+ -+ clint_mtimer2: timer@70ac024000 { -+ compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; -+ reg = <0x00000070 0xac024000 0x00000000 0x0000c000>; -+ reg-names = "mtimecmp"; -+ interrupts-extended = <&cpu8_intc 7>, -+ <&cpu9_intc 7>, -+ <&cpu10_intc 7>, -+ <&cpu11_intc 7>; -+ }; -+ -+ clint_mtimer3: timer@70ac034000 { -+ compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; -+ reg = <0x00000070 0xac034000 0x00000000 0x0000c000>; -+ reg-names = "mtimecmp"; -+ interrupts-extended = <&cpu12_intc 7>, -+ <&cpu13_intc 7>, -+ <&cpu14_intc 7>, -+ <&cpu15_intc 7>; -+ }; -+ -+ clint_mtimer4: timer@70ac044000 { -+ compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; -+ reg = <0x00000070 0xac044000 0x00000000 0x0000c000>; -+ reg-names = "mtimecmp"; -+ interrupts-extended = <&cpu16_intc 7>, -+ <&cpu17_intc 7>, -+ <&cpu18_intc 7>, -+ <&cpu19_intc 7>; -+ }; -+ -+ clint_mtimer5: timer@70ac054000 { -+ compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; -+ reg = <0x00000070 0xac054000 0x00000000 0x0000c000>; -+ reg-names = "mtimecmp"; -+ interrupts-extended = <&cpu20_intc 7>, -+ <&cpu21_intc 7>, -+ <&cpu22_intc 7>, -+ <&cpu23_intc 7>; -+ }; -+ -+ clint_mtimer6: timer@70ac064000 { -+ compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; -+ reg = <0x00000070 0xac064000 0x00000000 0x0000c000>; -+ reg-names = "mtimecmp"; -+ interrupts-extended = <&cpu24_intc 7>, -+ <&cpu25_intc 7>, -+ <&cpu26_intc 7>, -+ <&cpu27_intc 7>; -+ }; -+ -+ clint_mtimer7: timer@70ac074000 { -+ compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; -+ reg = <0x00000070 0xac074000 0x00000000 0x0000c000>; -+ reg-names = "mtimecmp"; -+ interrupts-extended = <&cpu28_intc 7>, -+ <&cpu29_intc 7>, -+ <&cpu30_intc 7>, -+ <&cpu31_intc 7>; -+ }; -+ -+ clint_mtimer8: timer@70ac084000 { -+ compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; -+ reg = <0x00000070 0xac084000 0x00000000 0x0000c000>; -+ reg-names = "mtimecmp"; -+ interrupts-extended = <&cpu32_intc 7>, -+ <&cpu33_intc 7>, -+ <&cpu34_intc 7>, -+ <&cpu35_intc 7>; -+ }; -+ -+ clint_mtimer9: timer@70ac094000 { -+ compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; -+ reg = <0x00000070 0xac094000 0x00000000 0x0000c000>; -+ reg-names = "mtimecmp"; -+ interrupts-extended = <&cpu36_intc 7>, -+ <&cpu37_intc 7>, -+ <&cpu38_intc 7>, -+ <&cpu39_intc 7>; -+ }; -+ -+ clint_mtimer10: timer@70ac0a4000 { -+ compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; -+ reg = <0x00000070 0xac0a4000 0x00000000 0x0000c000>; -+ reg-names = "mtimecmp"; -+ interrupts-extended = <&cpu40_intc 7>, -+ <&cpu41_intc 7>, -+ <&cpu42_intc 7>, -+ <&cpu43_intc 7>; -+ }; -+ -+ clint_mtimer11: timer@70ac0b4000 { -+ compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; -+ reg = <0x00000070 0xac0b4000 0x00000000 0x0000c000>; -+ reg-names = "mtimecmp"; -+ interrupts-extended = <&cpu44_intc 7>, -+ <&cpu45_intc 7>, -+ <&cpu46_intc 7>, -+ <&cpu47_intc 7>; -+ }; -+ -+ clint_mtimer12: timer@70ac0c4000 { -+ compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; -+ reg = <0x00000070 0xac0c4000 0x00000000 0x0000c000>; -+ reg-names = "mtimecmp"; -+ interrupts-extended = <&cpu48_intc 7>, -+ <&cpu49_intc 7>, -+ <&cpu50_intc 7>, -+ <&cpu51_intc 7>; -+ }; -+ -+ clint_mtimer13: timer@70ac0d4000 { -+ compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; -+ reg = <0x00000070 0xac0d4000 0x00000000 0x0000c000>; -+ reg-names = "mtimecmp"; -+ interrupts-extended = <&cpu52_intc 7>, -+ <&cpu53_intc 7>, -+ <&cpu54_intc 7>, -+ <&cpu55_intc 7>; -+ }; -+ -+ clint_mtimer14: timer@70ac0e4000 { -+ compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; -+ reg = <0x00000070 0xac0e4000 0x00000000 0x0000c000>; -+ reg-names = "mtimecmp"; -+ interrupts-extended = <&cpu56_intc 7>, -+ <&cpu57_intc 7>, -+ <&cpu58_intc 7>, -+ <&cpu59_intc 7>; -+ }; -+ -+ clint_mtimer15: timer@70ac0f4000 { -+ compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; -+ reg = <0x00000070 0xac0f4000 0x00000000 0x0000c000>; -+ reg-names = "mtimecmp"; -+ interrupts-extended = <&cpu60_intc 7>, -+ <&cpu61_intc 7>, -+ <&cpu62_intc 7>, -+ <&cpu63_intc 7>; -+ }; -+ -+ intc: interrupt-controller@7090000000 { -+ compatible = "sophgo,sg2042-plic", "thead,c900-plic"; -+ #address-cells = <0>; -+ #interrupt-cells = <2>; -+ reg = <0x00000070 0x90000000 0x00000000 0x04000000>; -+ interrupt-controller; -+ interrupts-extended = -+ <&cpu0_intc 11>, <&cpu0_intc 9>, -+ <&cpu1_intc 11>, <&cpu1_intc 9>, -+ <&cpu2_intc 11>, <&cpu2_intc 9>, -+ <&cpu3_intc 11>, <&cpu3_intc 9>, -+ <&cpu4_intc 11>, <&cpu4_intc 9>, -+ <&cpu5_intc 11>, <&cpu5_intc 9>, -+ <&cpu6_intc 11>, <&cpu6_intc 9>, -+ <&cpu7_intc 11>, <&cpu7_intc 9>, -+ <&cpu8_intc 11>, <&cpu8_intc 9>, -+ <&cpu9_intc 11>, <&cpu9_intc 9>, -+ <&cpu10_intc 11>, <&cpu10_intc 9>, -+ <&cpu11_intc 11>, <&cpu11_intc 9>, -+ <&cpu12_intc 11>, <&cpu12_intc 9>, -+ <&cpu13_intc 11>, <&cpu13_intc 9>, -+ <&cpu14_intc 11>, <&cpu14_intc 9>, -+ <&cpu15_intc 11>, <&cpu15_intc 9>, -+ <&cpu16_intc 11>, <&cpu16_intc 9>, -+ <&cpu17_intc 11>, <&cpu17_intc 9>, -+ <&cpu18_intc 11>, <&cpu18_intc 9>, -+ <&cpu19_intc 11>, <&cpu19_intc 9>, -+ <&cpu20_intc 11>, <&cpu20_intc 9>, -+ <&cpu21_intc 11>, <&cpu21_intc 9>, -+ <&cpu22_intc 11>, <&cpu22_intc 9>, -+ <&cpu23_intc 11>, <&cpu23_intc 9>, -+ <&cpu24_intc 11>, <&cpu24_intc 9>, -+ <&cpu25_intc 11>, <&cpu25_intc 9>, -+ <&cpu26_intc 11>, <&cpu26_intc 9>, -+ <&cpu27_intc 11>, <&cpu27_intc 9>, -+ <&cpu28_intc 11>, <&cpu28_intc 9>, -+ <&cpu29_intc 11>, <&cpu29_intc 9>, -+ <&cpu30_intc 11>, <&cpu30_intc 9>, -+ <&cpu31_intc 11>, <&cpu31_intc 9>, -+ <&cpu32_intc 11>, <&cpu32_intc 9>, -+ <&cpu33_intc 11>, <&cpu33_intc 9>, -+ <&cpu34_intc 11>, <&cpu34_intc 9>, -+ <&cpu35_intc 11>, <&cpu35_intc 9>, -+ <&cpu36_intc 11>, <&cpu36_intc 9>, -+ <&cpu37_intc 11>, <&cpu37_intc 9>, -+ <&cpu38_intc 11>, <&cpu38_intc 9>, -+ <&cpu39_intc 11>, <&cpu39_intc 9>, -+ <&cpu40_intc 11>, <&cpu40_intc 9>, -+ <&cpu41_intc 11>, <&cpu41_intc 9>, -+ <&cpu42_intc 11>, <&cpu42_intc 9>, -+ <&cpu43_intc 11>, <&cpu43_intc 9>, -+ <&cpu44_intc 11>, <&cpu44_intc 9>, -+ <&cpu45_intc 11>, <&cpu45_intc 9>, -+ <&cpu46_intc 11>, <&cpu46_intc 9>, -+ <&cpu47_intc 11>, <&cpu47_intc 9>, -+ <&cpu48_intc 11>, <&cpu48_intc 9>, -+ <&cpu49_intc 11>, <&cpu49_intc 9>, -+ <&cpu50_intc 11>, <&cpu50_intc 9>, -+ <&cpu51_intc 11>, <&cpu51_intc 9>, -+ <&cpu52_intc 11>, <&cpu52_intc 9>, -+ <&cpu53_intc 11>, <&cpu53_intc 9>, -+ <&cpu54_intc 11>, <&cpu54_intc 9>, -+ <&cpu55_intc 11>, <&cpu55_intc 9>, -+ <&cpu56_intc 11>, <&cpu56_intc 9>, -+ <&cpu57_intc 11>, <&cpu57_intc 9>, -+ <&cpu58_intc 11>, <&cpu58_intc 9>, -+ <&cpu59_intc 11>, <&cpu59_intc 9>, -+ <&cpu60_intc 11>, <&cpu60_intc 9>, -+ <&cpu61_intc 11>, <&cpu61_intc 9>, -+ <&cpu62_intc 11>, <&cpu62_intc 9>, -+ <&cpu63_intc 11>, <&cpu63_intc 9>; -+ riscv,ndev = <224>; -+ }; -+ -+ uart0: serial@7040000000 { -+ compatible = "snps,dw-apb-uart"; -+ reg = <0x00000070 0x40000000 0x00000000 0x00001000>; -+ interrupt-parent = <&intc>; -+ interrupts = <112 IRQ_TYPE_LEVEL_HIGH>; -+ clock-frequency = <500000000>; -+ reg-shift = <2>; -+ reg-io-width = <4>; -+ status = "disabled"; -+ }; -+ }; -+}; diff --git a/arch/riscv/boot/dts/thead/Makefile b/arch/riscv/boot/dts/thead/Makefile index b55a17127c2b..1f14fdaf6add 100644 --- a/arch/riscv/boot/dts/thead/Makefile @@ -9868,23 +9910,10 @@ index ff364709a6df..fab3b5f17f22 100644 }; }; diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig -index ab86ec3b9eab..3de25be550fd 100644 +index ab86ec3b9eab..b715550e3ed1 100644 --- a/arch/riscv/configs/defconfig +++ b/arch/riscv/configs/defconfig -@@ -27,10 +27,11 @@ CONFIG_EXPERT=y - CONFIG_PROFILING=y - CONFIG_SOC_MICROCHIP_POLARFIRE=y - CONFIG_ARCH_RENESAS=y --CONFIG_ARCH_THEAD=y - CONFIG_SOC_SIFIVE=y -+CONFIG_ARCH_SOPHGO=y - CONFIG_SOC_STARFIVE=y - CONFIG_ARCH_SUNXI=y -+CONFIG_ARCH_THEAD=y - CONFIG_SOC_VIRT=y - CONFIG_SMP=y - CONFIG_HOTPLUG_CPU=y -@@ -168,12 +169,15 @@ CONFIG_MMC=y +@@ -168,12 +168,15 @@ CONFIG_MMC=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_PLTFM=y CONFIG_MMC_SDHCI_CADENCE=y @@ -9901,17 +9930,26 @@ index ab86ec3b9eab..3de25be550fd 100644 CONFIG_VIRTIO_BALLOON=y CONFIG_VIRTIO_INPUT=y diff --git a/arch/riscv/configs/openeuler_defconfig b/arch/riscv/configs/openeuler_defconfig -index 026582613f2c..3f46297a8481 100644 +index 026582613f2c..a948aadd1d6f 100644 --- a/arch/riscv/configs/openeuler_defconfig +++ b/arch/riscv/configs/openeuler_defconfig @@ -2,6 +2,7 @@ # Automatically generated file; DO NOT EDIT. # Linux/riscv 6.6.0 Kernel Configuration # -+CONFIG_TOOLS_SUPPORT_RELR=y ++CONFIG_GCC_ASM_GOTO_OUTPUT_WORKAROUND=y CONFIG_IRQ_WORK=y CONFIG_BUILDTIME_TABLE_SORT=y CONFIG_THREAD_INFO_IN_TASK=y +@@ -148,7 +149,7 @@ CONFIG_GENERIC_SCHED_CLOCK=y + + CONFIG_ARCH_SUPPORTS_NUMA_BALANCING=y + CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5" +-CONFIG_GCC11_NO_ARRAY_BOUNDS=y ++CONFIG_GCC10_NO_ARRAY_BOUNDS=y + CONFIG_CC_NO_ARRAY_BOUNDS=y + CONFIG_ARCH_SUPPORTS_INT128=y + CONFIG_NUMA_BALANCING=y @@ -301,6 +302,7 @@ CONFIG_FIX_EARLYCON_MEM=y CONFIG_PGTABLE_LEVELS=5 CONFIG_LOCKDEP_SUPPORT=y @@ -9920,37 +9958,40 @@ index 026582613f2c..3f46297a8481 100644 # # SoC selection -@@ -309,6 +311,7 @@ CONFIG_RISCV_DMA_NONCOHERENT=y +@@ -309,6 +311,8 @@ CONFIG_RISCV_DMA_NONCOHERENT=y # CONFIG_ARCH_RENESAS is not set CONFIG_ARCH_SIFIVE=y CONFIG_SOC_SIFIVE=y +CONFIG_ARCH_SOPHGO=y ++# CONFIG_SOPHGO_MULTI_CHIP_CLOCK_SYNC is not set CONFIG_ARCH_STARFIVE=y CONFIG_SOC_STARFIVE=y # CONFIG_ARCH_SUNXI is not set -@@ -350,12 +353,8 @@ CONFIG_RISCV_ALTERNATIVE_EARLY=y +@@ -343,17 +347,19 @@ CONFIG_SMP=y + CONFIG_NR_CPUS=512 + CONFIG_HOTPLUG_CPU=y + CONFIG_TUNE_GENERIC=y ++CONFIG_HIGHMEM=y + CONFIG_NUMA=y + CONFIG_NODES_SHIFT=7 + CONFIG_RISCV_ALTERNATIVE=y + CONFIG_RISCV_ALTERNATIVE_EARLY=y CONFIG_RISCV_ISA_C=y - CONFIG_RISCV_ISA_SVNAPOT=y +-CONFIG_RISCV_ISA_SVNAPOT=y ++# CONFIG_RISCV_ISA_SVNAPOT is not set CONFIG_RISCV_ISA_SVPBMT=y --CONFIG_TOOLCHAIN_HAS_V=y + CONFIG_TOOLCHAIN_HAS_V=y -CONFIG_RISCV_ISA_V=y -CONFIG_RISCV_ISA_V_DEFAULT_ENABLE=y - CONFIG_RISCV_ISA_ZICBOM=y +-CONFIG_RISCV_ISA_ZICBOM=y ++# CONFIG_RISCV_ISA_V is not set ++CONFIG_TOOLCHAIN_HAS_ZBB=y ++CONFIG_RISCV_ISA_ZBB=y ++# CONFIG_RISCV_ISA_ZICBOM is not set CONFIG_RISCV_ISA_ZICBOZ=y --CONFIG_TOOLCHAIN_HAS_ZIHINTPAUSE=y + CONFIG_TOOLCHAIN_HAS_ZIHINTPAUSE=y CONFIG_TOOLCHAIN_NEEDS_EXPLICIT_ZICSR_ZIFENCEI=y - CONFIG_FPU=y - CONFIG_IRQ_STACKS=y -@@ -390,8 +389,6 @@ CONFIG_COMPAT=y - CONFIG_CMDLINE="" - CONFIG_EFI_STUB=y - CONFIG_EFI=y --CONFIG_CC_HAVE_STACKPROTECTOR_TLS=y --CONFIG_STACKPROTECTOR_PER_TASK=y - CONFIG_RISCV_ISA_FALLBACK=y - # end of Boot options - -@@ -471,6 +468,7 @@ CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y +@@ -471,6 +477,7 @@ CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y # CONFIG_CPUFREQ_DT=y CONFIG_CPUFREQ_DT_PLATDEV=y @@ -9958,7 +9999,27 @@ index 026582613f2c..3f46297a8481 100644 # end of CPU Frequency scaling # end of CPU Power Management -@@ -576,7 +574,6 @@ CONFIG_HAVE_PREEMPT_DYNAMIC_KEY=y +@@ -488,6 +495,19 @@ CONFIG_VIRTUALIZATION=y + CONFIG_KVM=m + CONFIG_ARCH_SUPPORTS_ACPI=y + # CONFIG_ACPI is not set ++CONFIG_HAVE_LIVEPATCH_WO_FTRACE=y ++ ++# ++# Enable Livepatch ++# ++CONFIG_LIVEPATCH=y ++CONFIG_LIVEPATCH_WO_FTRACE=y ++CONFIG_LIVEPATCH_STOP_MACHINE_CONSISTENCY=y ++CONFIG_LIVEPATCH_STACK=y ++CONFIG_LIVEPATCH_RESTRICT_KPROBE=y ++# end of Enable Livepatch ++ ++CONFIG_CPU_MITIGATIONS=y + + # + # General architecture-dependent options +@@ -576,7 +596,6 @@ CONFIG_HAVE_PREEMPT_DYNAMIC_KEY=y CONFIG_ARCH_WANT_LD_ORPHAN_WARN=y CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y CONFIG_ARCH_SUPPORTS_PAGE_TABLE_CHECK=y @@ -9966,7 +10027,87 @@ index 026582613f2c..3f46297a8481 100644 # # GCOV-based kernel profiling -@@ -1635,6 +1632,7 @@ CONFIG_PCIE_CADENCE_EP=y +@@ -753,9 +772,9 @@ CONFIG_ZSMALLOC_CHAIN_SIZE=8 + # CONFIG_SLAB_DEPRECATED is not set + CONFIG_SLUB=y + # CONFIG_SLUB_TINY is not set +-CONFIG_SLAB_MERGE_DEFAULT=y ++# CONFIG_SLAB_MERGE_DEFAULT is not set + CONFIG_SLAB_FREELIST_RANDOM=y +-# CONFIG_SLAB_FREELIST_HARDENED is not set ++CONFIG_SLAB_FREELIST_HARDENED=y + # CONFIG_SLUB_STATS is not set + CONFIG_SLUB_CPU_PARTIAL=y + # CONFIG_RANDOM_KMALLOC_CACHES is not set +@@ -768,8 +787,9 @@ CONFIG_SPARSEMEM_MANUAL=y + CONFIG_SPARSEMEM=y + CONFIG_SPARSEMEM_EXTREME=y + CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y +-CONFIG_SPARSEMEM_VMEMMAP=y ++# CONFIG_SPARSEMEM_VMEMMAP is not set + CONFIG_ARCH_WANT_OPTIMIZE_HUGETLB_VMEMMAP=y ++CONFIG_ARCH_KEEP_MEMBLOCK=y + CONFIG_MEMORY_ISOLATION=y + CONFIG_EXCLUSIVE_SYSTEM_RAM=y + CONFIG_SPLIT_PTLOCK_CPUS=4 +@@ -785,13 +805,15 @@ CONFIG_ARCH_ENABLE_THP_MIGRATION=y + CONFIG_CONTIG_ALLOC=y + CONFIG_PCP_BATCH_SCALE_MAX=5 + CONFIG_PHYS_ADDR_T_64BIT=y ++CONFIG_BOUNCE=y + CONFIG_MMU_NOTIFIER=y + CONFIG_KSM=y + CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 ++CONFIG_ARCH_WANT_GENERAL_HUGETLB=y + CONFIG_ARCH_WANTS_THP_SWAP=y + CONFIG_TRANSPARENT_HUGEPAGE=y +-CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS=y +-# CONFIG_TRANSPARENT_HUGEPAGE_MADVISE is not set ++# CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS is not set ++CONFIG_TRANSPARENT_HUGEPAGE_MADVISE=y + CONFIG_THP_SWAP=y + # CONFIG_READ_ONLY_THP_FOR_FS is not set + CONFIG_NEED_PER_CPU_EMBED_FIRST_CHUNK=y +@@ -808,19 +830,19 @@ CONFIG_IDLE_PAGE_TRACKING=y + CONFIG_ARCH_HAS_CURRENT_STACK_POINTER=y + CONFIG_ZONE_DMA32=y + CONFIG_HMM_MIRROR=y ++CONFIG_GET_FREE_REGION=y + CONFIG_VM_EVENT_COUNTERS=y + # CONFIG_PERCPU_STATS is not set + # CONFIG_GUP_TEST is not set + # CONFIG_DMAPOOL_TEST is not set + CONFIG_ARCH_HAS_PTE_SPECIAL=y ++CONFIG_KMAP_LOCAL=y + CONFIG_MEMFD_CREATE=y + CONFIG_SECRETMEM=y + # CONFIG_ANON_VMA_NAME is not set + CONFIG_USERFAULTFD=y + CONFIG_HAVE_ARCH_USERFAULTFD_MINOR=y +-CONFIG_LRU_GEN=y +-CONFIG_LRU_GEN_ENABLED=y +-# CONFIG_LRU_GEN_STATS is not set ++# CONFIG_LRU_GEN is not set + CONFIG_ARCH_SUPPORTS_PER_VMA_LOCK=y + CONFIG_PER_VMA_LOCK=y + CONFIG_LOCK_MM_AND_FIND_VMA=y +@@ -1585,6 +1607,7 @@ CONFIG_PCIEPORTBUS=y + CONFIG_HOTPLUG_PCI_PCIE=y + CONFIG_PCIEAER=y + CONFIG_PCIEAER_INJECT=m ++CONFIG_PCIEAER_CXL=y + CONFIG_PCIE_ECRC=y + CONFIG_PCIEASPM=y + CONFIG_PCIEASPM_DEFAULT=y +@@ -1601,6 +1624,7 @@ CONFIG_PCI_QUIRKS=y + CONFIG_PCI_STUB=y + # CONFIG_PCI_PF_STUB is not set + CONFIG_PCI_ATS=y ++CONFIG_PCI_DOE=y + CONFIG_PCI_ECAM=y + CONFIG_PCI_IOV=y + CONFIG_PCI_PRI=y +@@ -1635,6 +1659,7 @@ CONFIG_PCIE_CADENCE_EP=y CONFIG_PCIE_CADENCE_PLAT=y CONFIG_PCIE_CADENCE_PLAT_HOST=y CONFIG_PCIE_CADENCE_PLAT_EP=y @@ -9974,7 +10115,40 @@ index 026582613f2c..3f46297a8481 100644 CONFIG_PCI_J721E=y CONFIG_PCI_J721E_HOST=y # CONFIG_PCI_J721E_EP is not set -@@ -1709,7 +1707,7 @@ CONFIG_WANT_DEV_COREDUMP=y +@@ -1674,7 +1699,16 @@ CONFIG_PCI_ENDPOINT_CONFIGFS=y + # CONFIG_PCI_SW_SWITCHTEC is not set + # end of PCI switch controller drivers + +-# CONFIG_CXL_BUS is not set ++CONFIG_CXL_BUS=y ++CONFIG_CXL_PCI=y ++# CONFIG_CXL_MEM_RAW_COMMANDS is not set ++CONFIG_CXL_PMEM=m ++CONFIG_CXL_MEM=y ++CONFIG_CXL_PORT=y ++CONFIG_CXL_SUSPEND=y ++CONFIG_CXL_REGION=y ++# CONFIG_CXL_REGION_INVALIDATION_TEST is not set ++CONFIG_CXL_PMU=y + # CONFIG_PCCARD is not set + # CONFIG_RAPIDIO is not set + +@@ -1694,11 +1728,13 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y + # + CONFIG_FW_LOADER=y + CONFIG_FW_LOADER_DEBUG=y ++CONFIG_FW_LOADER_PAGED_BUF=y ++CONFIG_FW_LOADER_SYSFS=y + CONFIG_EXTRA_FIRMWARE="" + # CONFIG_FW_LOADER_USER_HELPER is not set + # CONFIG_FW_LOADER_COMPRESS is not set + CONFIG_FW_CACHE=y +-# CONFIG_FW_UPLOAD is not set ++CONFIG_FW_UPLOAD=y + # end of Firmware loader + + CONFIG_WANT_DEV_COREDUMP=y +@@ -1709,7 +1745,7 @@ CONFIG_WANT_DEV_COREDUMP=y # CONFIG_TEST_ASYNC_DRIVER_PROBE is not set CONFIG_GENERIC_CPU_DEVICES=y CONFIG_REGMAP=y @@ -9983,7 +10157,7 @@ index 026582613f2c..3f46297a8481 100644 CONFIG_REGMAP_SPI=m CONFIG_REGMAP_MMIO=y CONFIG_DMA_SHARED_BUFFER=y -@@ -1774,6 +1772,9 @@ CONFIG_EFI_EARLYCON=y +@@ -1774,6 +1810,9 @@ CONFIG_EFI_EARLYCON=y # Tegra firmware driver # # end of Tegra firmware driver @@ -9993,7 +10167,50 @@ index 026582613f2c..3f46297a8481 100644 # end of Firmware Drivers # CONFIG_GNSS is not set -@@ -2569,7 +2570,17 @@ CONFIG_EPIC100=m +@@ -1899,6 +1938,7 @@ CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y + # CONFIG_MTD_SPI_NOR_SWP_DISABLE is not set + CONFIG_MTD_SPI_NOR_SWP_DISABLE_ON_VOLATILE=y + # CONFIG_MTD_SPI_NOR_SWP_KEEP is not set ++CONFIG_SPI_SOPHGO_SPIFMC=m + CONFIG_MTD_UBI=m + CONFIG_MTD_UBI_WL_THRESHOLD=4096 + CONFIG_MTD_UBI_BEB_LIMIT=20 +@@ -2277,7 +2317,6 @@ CONFIG_DM_THIN_PROVISIONING=m + CONFIG_DM_CACHE=m + CONFIG_DM_CACHE_SMQ=m + # CONFIG_DM_WRITECACHE is not set +-# CONFIG_DM_EBS is not set + CONFIG_DM_ERA=m + # CONFIG_DM_CLONE is not set + CONFIG_DM_MIRROR=m +@@ -2365,6 +2404,7 @@ CONFIG_VSOCKMON=m + CONFIG_ETHERNET=y + CONFIG_MDIO=m + # CONFIG_NET_VENDOR_3COM is not set ++# CONFIG_NET_VENDOR_3SNIC is not set + # CONFIG_NET_VENDOR_ADAPTEC is not set + # CONFIG_NET_VENDOR_AGERE is not set + CONFIG_NET_VENDOR_ALACRITECH=y +@@ -2441,6 +2481,7 @@ CONFIG_NET_VENDOR_FUNGIBLE=y + # CONFIG_FUN_ETH is not set + CONFIG_NET_VENDOR_GOOGLE=y + CONFIG_NET_VENDOR_HUAWEI=y ++# CONFIG_BMA is not set + # CONFIG_NET_VENDOR_I825XX is not set + CONFIG_NET_VENDOR_INTEL=y + # CONFIG_E100 is not set +@@ -2465,6 +2506,10 @@ CONFIG_FM10K=m + # CONFIG_IGC is not set + CONFIG_NET_VENDOR_MUCSE=y + # CONFIG_MXGBE is not set ++# CONFIG_MXGBEVF is not set ++# CONFIG_MXGBEM is not set ++# CONFIG_MGBE is not set ++# CONFIG_MGBEVF is not set + # CONFIG_JME is not set + CONFIG_NET_VENDOR_ADI=y + # CONFIG_ADIN1110 is not set +@@ -2569,7 +2614,16 @@ CONFIG_EPIC100=m CONFIG_SMSC911X=m CONFIG_SMSC9420=m # CONFIG_NET_VENDOR_SOCIONEXT is not set @@ -10007,12 +10224,20 @@ index 026582613f2c..3f46297a8481 100644 +CONFIG_DWMAC_STARFIVE=m +CONFIG_DWMAC_THEAD=m +# CONFIG_DWMAC_INTEL_PLAT is not set -+# CONFIG_DWMAC_LOONGSON is not set +# CONFIG_STMMAC_PCI is not set # CONFIG_NET_VENDOR_SUN is not set # CONFIG_NET_VENDOR_SYNOPSYS is not set # CONFIG_NET_VENDOR_TEHUTI is not set -@@ -3366,6 +3377,7 @@ CONFIG_GENERIC_PINCONF=y +@@ -2583,6 +2637,8 @@ CONFIG_NGBE=m + CONFIG_TXGBE=m + # CONFIG_NET_VENDOR_WIZNET is not set + # CONFIG_NET_VENDOR_XILINX is not set ++CONFIG_NET_VENDOR_BZWX=y ++# CONFIG_NCE is not set + # CONFIG_FDDI is not set + # CONFIG_HIPPI is not set + CONFIG_PHYLINK=y +@@ -3366,6 +3422,7 @@ CONFIG_GENERIC_PINCONF=y # CONFIG_PINCTRL_SINGLE is not set # CONFIG_PINCTRL_STMFX is not set # CONFIG_PINCTRL_SX150X is not set @@ -10020,7 +10245,7 @@ index 026582613f2c..3f46297a8481 100644 # # Renesas pinctrl drivers -@@ -3416,7 +3428,8 @@ CONFIG_GPIO_SIFIVE=y +@@ -3416,7 +3473,8 @@ CONFIG_GPIO_SIFIVE=y # CONFIG_GPIO_GW_PLD is not set # CONFIG_GPIO_MAX7300 is not set # CONFIG_GPIO_MAX732X is not set @@ -10030,7 +10255,7 @@ index 026582613f2c..3f46297a8481 100644 # CONFIG_GPIO_PCA9570 is not set # CONFIG_GPIO_PCF857X is not set # CONFIG_GPIO_TPIC2810 is not set -@@ -3599,7 +3612,7 @@ CONFIG_SENSORS_MAX31790=m +@@ -3599,7 +3657,7 @@ CONFIG_SENSORS_MAX31790=m CONFIG_SENSORS_MCP3021=m # CONFIG_SENSORS_TC654 is not set # CONFIG_SENSORS_TPS23861 is not set @@ -10039,7 +10264,7 @@ index 026582613f2c..3f46297a8481 100644 CONFIG_SENSORS_ADCXX=m CONFIG_SENSORS_LM63=m CONFIG_SENSORS_LM70=m -@@ -3777,6 +3790,7 @@ CONFIG_ALIM7101_WDT=m +@@ -3777,6 +3835,7 @@ CONFIG_ALIM7101_WDT=m CONFIG_I6300ESB_WDT=m # CONFIG_MEN_A21_WDT is not set CONFIG_STARFIVE_WATCHDOG=y @@ -10047,7 +10272,15 @@ index 026582613f2c..3f46297a8481 100644 # # PCI-based Watchdog Cards -@@ -3998,6 +4012,7 @@ CONFIG_REGULATOR_PWM=y +@@ -3877,7 +3936,6 @@ CONFIG_MFD_CORE=m + # CONFIG_MFD_SKY81452 is not set + # CONFIG_MFD_STMPE is not set + CONFIG_MFD_SYSCON=y +-# CONFIG_MFD_TI_AM335X_TSCADC is not set + # CONFIG_MFD_LP3943 is not set + # CONFIG_MFD_LP8788 is not set + # CONFIG_MFD_TI_LMU is not set +@@ -3998,6 +4056,7 @@ CONFIG_REGULATOR_PWM=y # CONFIG_REGULATOR_TPS65132 is not set # CONFIG_REGULATOR_TPS6524X is not set # CONFIG_REGULATOR_VCTRL is not set @@ -10055,7 +10288,7 @@ index 026582613f2c..3f46297a8481 100644 # CONFIG_RC_CORE is not set # -@@ -5357,8 +5372,29 @@ CONFIG_USB_MICROTEK=m +@@ -5357,8 +5416,29 @@ CONFIG_USB_MICROTEK=m # USB dual-mode controller drivers # # CONFIG_USB_CDNS_SUPPORT is not set @@ -10087,7 +10320,7 @@ index 026582613f2c..3f46297a8481 100644 # CONFIG_USB_DWC2 is not set # CONFIG_USB_CHIPIDEA is not set # CONFIG_USB_ISP1760 is not set -@@ -5450,7 +5486,7 @@ CONFIG_USB_HSIC_USB3503=m +@@ -5450,7 +5530,7 @@ CONFIG_USB_HSIC_USB3503=m # CONFIG_USB_HSIC_USB4604 is not set # CONFIG_USB_LINK_LAYER_TEST is not set CONFIG_USB_CHAOSKEY=m @@ -10096,7 +10329,7 @@ index 026582613f2c..3f46297a8481 100644 CONFIG_USB_ATM=m # CONFIG_USB_SPEEDTOUCH is not set CONFIG_USB_CXACRU=m -@@ -5465,7 +5501,59 @@ CONFIG_USB_XUSBATM=m +@@ -5465,7 +5545,59 @@ CONFIG_USB_XUSBATM=m # CONFIG_USB_ISP1301 is not set # end of USB Physical Layer drivers @@ -10157,7 +10390,7 @@ index 026582613f2c..3f46297a8481 100644 CONFIG_TYPEC=m CONFIG_TYPEC_TCPM=m CONFIG_TYPEC_TCPCI=m -@@ -5520,12 +5608,13 @@ CONFIG_MMC_RICOH_MMC=y +@@ -5520,12 +5652,13 @@ CONFIG_MMC_RICOH_MMC=y CONFIG_MMC_SDHCI_PLTFM=y # CONFIG_MMC_SDHCI_OF_ARASAN is not set # CONFIG_MMC_SDHCI_OF_AT91 is not set @@ -10172,7 +10405,41 @@ index 026582613f2c..3f46297a8481 100644 CONFIG_MMC_CB710=m CONFIG_MMC_VIA_SDMMC=m CONFIG_MMC_DW=m -@@ -5824,10 +5913,11 @@ CONFIG_DMADEVICES=y +@@ -5546,8 +5679,6 @@ CONFIG_MMC_HSQ=m + CONFIG_MMC_TOSHIBA_PCI=m + CONFIG_MMC_MTK=m + CONFIG_MMC_SDHCI_XENON=m +-# CONFIG_MMC_SDHCI_OMAP is not set +-# CONFIG_MMC_SDHCI_AM654 is not set + # CONFIG_SCSI_UFSHCD is not set + CONFIG_MEMSTICK=m + # CONFIG_MEMSTICK_DEBUG is not set +@@ -5670,7 +5801,6 @@ CONFIG_INFINIBAND_USER_MEM=y + CONFIG_INFINIBAND_ON_DEMAND_PAGING=y + CONFIG_INFINIBAND_ADDR_TRANS=y + CONFIG_INFINIBAND_ADDR_TRANS_CONFIGFS=y +-CONFIG_INFINIBAND_VIRT_DMA=y + CONFIG_INFINIBAND_BNXT_RE=m + CONFIG_INFINIBAND_CXGB4=m + # CONFIG_INFINIBAND_EFA is not set +@@ -5681,8 +5811,6 @@ CONFIG_MLX5_INFINIBAND=m + # CONFIG_INFINIBAND_MTHCA is not set + # CONFIG_INFINIBAND_OCRDMA is not set + CONFIG_INFINIBAND_QEDR=m +-CONFIG_RDMA_RXE=m +-# CONFIG_RDMA_SIW is not set + CONFIG_INFINIBAND_IPOIB=m + CONFIG_INFINIBAND_IPOIB_CM=y + # CONFIG_INFINIBAND_IPOIB_DEBUG is not set +@@ -5817,6 +5945,7 @@ CONFIG_RTC_DRV_RP5C01=m + # HID Sensor RTC drivers + # + CONFIG_RTC_DRV_GOLDFISH=y ++# CONFIG_RTC_DRV_ASTBMC is not set + CONFIG_DMADEVICES=y + # CONFIG_DMADEVICES_DEBUG is not set + +@@ -5824,10 +5953,11 @@ CONFIG_DMADEVICES=y # DMA Devices # CONFIG_DMA_ENGINE=y @@ -10185,7 +10452,7 @@ index 026582613f2c..3f46297a8481 100644 # CONFIG_FSL_EDMA is not set # CONFIG_INTEL_IDMA64 is not set # CONFIG_PL330_DMA is not set -@@ -5959,6 +6049,9 @@ CONFIG_CLK_STARFIVE_JH7110_ISP=m +@@ -5959,6 +6089,9 @@ CONFIG_CLK_STARFIVE_JH7110_ISP=m CONFIG_CLK_STARFIVE_JH7110_VOUT=m # CONFIG_XILINX_VCU is not set # CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set @@ -10195,7 +10462,7 @@ index 026582613f2c..3f46297a8481 100644 CONFIG_HWSPINLOCK=y # -@@ -5966,6 +6059,8 @@ CONFIG_HWSPINLOCK=y +@@ -5966,6 +6099,8 @@ CONFIG_HWSPINLOCK=y # CONFIG_TIMER_OF=y CONFIG_TIMER_PROBE=y @@ -10204,7 +10471,7 @@ index 026582613f2c..3f46297a8481 100644 CONFIG_RISCV_TIMER=y # end of Clock Source drivers -@@ -5976,6 +6071,7 @@ CONFIG_MAILBOX=y +@@ -5976,6 +6111,7 @@ CONFIG_MAILBOX=y # CONFIG_PL320_MBOX is not set # CONFIG_ALTERA_MBOX is not set # CONFIG_MAILBOX_TEST is not set @@ -10212,7 +10479,7 @@ index 026582613f2c..3f46297a8481 100644 CONFIG_IOMMU_API=y CONFIG_IOMMU_SUPPORT=y -@@ -6005,6 +6101,7 @@ CONFIG_RPMSG_CHAR=y +@@ -6005,6 +6141,7 @@ CONFIG_RPMSG_CHAR=y CONFIG_RPMSG_CTRL=y CONFIG_RPMSG_NS=y # CONFIG_RPMSG_QCOM_GLINK_RPM is not set @@ -10220,7 +10487,7 @@ index 026582613f2c..3f46297a8481 100644 CONFIG_RPMSG_VIRTIO=y # end of Rpmsg drivers -@@ -6061,6 +6158,12 @@ CONFIG_JH71XX_PMU=y +@@ -6061,6 +6198,12 @@ CONFIG_JH71XX_PMU=y # Xilinx SoC drivers # # end of Xilinx SoC drivers @@ -10233,7 +10500,7 @@ index 026582613f2c..3f46297a8481 100644 # end of SOC (System On Chip) specific Drivers # CONFIG_PM_DEVFREQ is not set -@@ -6089,6 +6192,7 @@ CONFIG_PWM_SYSFS=y +@@ -6089,6 +6232,7 @@ CONFIG_PWM_SYSFS=y # CONFIG_PWM_FSL_FTM is not set # CONFIG_PWM_PCA9685 is not set CONFIG_PWM_SIFIVE=m @@ -10241,7 +10508,7 @@ index 026582613f2c..3f46297a8481 100644 # CONFIG_PWM_XILINX is not set # -@@ -6104,6 +6208,7 @@ CONFIG_SIFIVE_PLIC=y +@@ -6104,6 +6248,7 @@ CONFIG_SIFIVE_PLIC=y # CONFIG_IPACK_BUS is not set CONFIG_RESET_CONTROLLER=y CONFIG_RESET_SIMPLE=y @@ -10249,15 +10516,118 @@ index 026582613f2c..3f46297a8481 100644 # CONFIG_RESET_TI_SYSCON is not set # CONFIG_RESET_TI_TPS380X is not set CONFIG_RESET_STARFIVE_JH71X0=y -@@ -7338,7 +7443,7 @@ CONFIG_DYNAMIC_EVENTS=y - CONFIG_PROBE_EVENTS=y - # CONFIG_BPF_KPROBE_OVERRIDE is not set - CONFIG_FTRACE_MCOUNT_RECORD=y --CONFIG_FTRACE_MCOUNT_USE_RECORDMCOUNT=y -+CONFIG_FTRACE_MCOUNT_USE_CC=y - CONFIG_SYNTH_EVENTS=y - # CONFIG_USER_EVENTS is not set - # CONFIG_TRACE_EVENT_INJECT is not set +@@ -6178,6 +6323,7 @@ CONFIG_NVDIMM_KEYS=y + # CONFIG_NVDIMM_SECURITY_TEST is not set + CONFIG_DAX=y + CONFIG_DEV_DAX=m ++CONFIG_DEV_DAX_CXL=m + CONFIG_NVMEM=y + CONFIG_NVMEM_SYSFS=y + +@@ -6362,8 +6508,6 @@ CONFIG_TMPFS_XATTR=y + CONFIG_ARCH_SUPPORTS_HUGETLBFS=y + CONFIG_HUGETLBFS=y + CONFIG_HUGETLB_PAGE=y +-CONFIG_HUGETLB_PAGE_OPTIMIZE_VMEMMAP=y +-# CONFIG_HUGETLB_PAGE_OPTIMIZE_VMEMMAP_DEFAULT_ON is not set + # CONFIG_HUGETLB_ALLOC_LIMIT is not set + CONFIG_ARCH_HAS_GIGANTIC_PAGE=y + CONFIG_CONFIGFS_FS=y +@@ -6652,6 +6796,8 @@ CONFIG_LSM="lockdown,yama,loadpin,safesetid,integrity,selinux,smack,tomoyo,appar + # Memory initialization + # + CONFIG_INIT_STACK_NONE=y ++# CONFIG_INIT_STACK_ALL_PATTERN is not set ++# CONFIG_INIT_STACK_ALL_ZERO is not set + # CONFIG_INIT_ON_ALLOC_DEFAULT_ON is not set + # CONFIG_INIT_ON_FREE_DEFAULT_ON is not set + # CONFIG_ZERO_CALL_USED_REGS is not set +@@ -6866,6 +7012,7 @@ CONFIG_CRYPTO_HW=y + # CONFIG_CRYPTO_DEV_QAT_C3XXX is not set + # CONFIG_CRYPTO_DEV_QAT_C62X is not set + # CONFIG_CRYPTO_DEV_QAT_4XXX is not set ++# CONFIG_CRYPTO_DEV_QAT_420XX is not set + # CONFIG_CRYPTO_DEV_QAT_DH895xCCVF is not set + # CONFIG_CRYPTO_DEV_QAT_C3XXXVF is not set + # CONFIG_CRYPTO_DEV_QAT_C62XVF is not set +@@ -7108,6 +7255,7 @@ CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y + # CONFIG_DEBUG_INFO_REDUCED is not set + CONFIG_DEBUG_INFO_COMPRESSED_NONE=y + # CONFIG_DEBUG_INFO_COMPRESSED_ZLIB is not set ++# CONFIG_DEBUG_INFO_SPLIT is not set + CONFIG_DEBUG_INFO_BTF=y + CONFIG_PAHOLE_HAS_SPLIT_BTF=y + CONFIG_PAHOLE_HAS_LANG_EXCLUDE=y +@@ -7190,16 +7338,14 @@ CONFIG_DEBUG_KMEMLEAK_AUTO_SCAN=y + # CONFIG_DEBUG_STACK_USAGE is not set + # CONFIG_SCHED_STACK_END_CHECK is not set + CONFIG_ARCH_HAS_DEBUG_VM_PGTABLE=y +-CONFIG_DEBUG_VM_IRQSOFF=y +-CONFIG_DEBUG_VM=y +-# CONFIG_DEBUG_VM_MAPLE_TREE is not set +-# CONFIG_DEBUG_VM_RB is not set +-# CONFIG_DEBUG_VM_PGFLAGS is not set ++# CONFIG_DEBUG_VM is not set + # CONFIG_DEBUG_VM_PGTABLE is not set + CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y + # CONFIG_DEBUG_VIRTUAL is not set + CONFIG_DEBUG_MEMORY_INIT=y + CONFIG_DEBUG_PER_CPU_MAPS=y ++# CONFIG_DEBUG_KMAP_LOCAL is not set ++# CONFIG_DEBUG_HIGHMEM is not set + CONFIG_HAVE_ARCH_KASAN=y + CONFIG_HAVE_ARCH_KASAN_VMALLOC=y + # CONFIG_KASAN is not set +@@ -7353,7 +7499,38 @@ CONFIG_RING_BUFFER_BENCHMARK=m + # CONFIG_SYNTH_EVENT_GEN_TEST is not set + # CONFIG_KPROBE_EVENT_GEN_TEST is not set + # CONFIG_RV is not set +-# CONFIG_SAMPLES is not set ++CONFIG_SAMPLES=y ++# CONFIG_SAMPLE_AUXDISPLAY is not set ++# CONFIG_SAMPLE_TRACE_EVENTS is not set ++# CONFIG_SAMPLE_TRACE_CUSTOM_EVENTS is not set ++# CONFIG_SAMPLE_TRACE_PRINTK is not set ++# CONFIG_SAMPLE_FTRACE_OPS is not set ++# CONFIG_SAMPLE_TRACE_ARRAY is not set ++# CONFIG_SAMPLE_KOBJECT is not set ++# CONFIG_SAMPLE_KPROBES is not set ++# CONFIG_SAMPLE_KFIFO is not set ++# CONFIG_SAMPLE_KDB is not set ++# CONFIG_SAMPLE_RPMSG_CLIENT is not set ++CONFIG_SAMPLE_LIVEPATCH=m ++# CONFIG_SAMPLE_CONFIGFS is not set ++# CONFIG_SAMPLE_CONNECTOR is not set ++# CONFIG_SAMPLE_FANOTIFY_ERROR is not set ++# CONFIG_SAMPLE_HIDRAW is not set ++# CONFIG_SAMPLE_LANDLOCK is not set ++# CONFIG_SAMPLE_PIDFD is not set ++# CONFIG_SAMPLE_SECCOMP is not set ++# CONFIG_SAMPLE_TIMER is not set ++# CONFIG_SAMPLE_UHID is not set ++# CONFIG_SAMPLE_VFIO_MDEV_MTTY is not set ++# CONFIG_SAMPLE_VFIO_MDEV_MDPY is not set ++# CONFIG_SAMPLE_VFIO_MDEV_MDPY_FB is not set ++# CONFIG_SAMPLE_VFIO_MDEV_MBOCHS is not set ++# CONFIG_SAMPLE_ANDROID_BINDERFS is not set ++# CONFIG_SAMPLE_VFS is not set ++# CONFIG_SAMPLE_TPS6594_PFSM is not set ++# CONFIG_SAMPLE_WATCHDOG is not set ++# CONFIG_SAMPLE_WATCH_QUEUE is not set ++# CONFIG_SAMPLE_KMEMLEAK is not set + CONFIG_STRICT_DEVMEM=y + CONFIG_IO_STRICT_DEVMEM=y + +@@ -7383,9 +7560,3 @@ CONFIG_ARCH_USE_MEMTEST=y + # end of Kernel hacking + + # CONFIG_KWORKER_NUMA_AFFINITY is not set +- +-# enable openEuler livepatch +-CONFIG_LIVEPATCH=y +-CONFIG_LIVEPATCH_WO_FTRACE=y +-CONFIG_SAMPLES=y +-CONFIG_SAMPLE_LIVEPATCH=m diff --git a/arch/riscv/errata/thead/errata.c b/arch/riscv/errata/thead/errata.c index 0554ed4bf087..07c7ab6bcb4a 100644 --- a/arch/riscv/errata/thead/errata.c @@ -10361,6 +10731,52 @@ index 0554ed4bf087..07c7ab6bcb4a 100644 if (errata_probe_pmu(stage, archid, impid)) cpu_req_errata |= BIT(ERRATA_THEAD_PMU); +diff --git a/arch/riscv/include/asm/barrier.h b/arch/riscv/include/asm/barrier.h +index 110752594228..2b1f98b7e9bf 100644 +--- a/arch/riscv/include/asm/barrier.h ++++ b/arch/riscv/include/asm/barrier.h +@@ -29,12 +29,22 @@ + #define __smp_rmb() RISCV_FENCE(r,r) + #define __smp_wmb() RISCV_FENCE(w,w) + ++#ifdef CONFIG_ARCH_SOPHGO + #define __smp_store_release(p, v) \ + do { \ + compiletime_assert_atomic_type(*p); \ + RISCV_FENCE(rw,w); \ + WRITE_ONCE(*p, v); \ ++ RISCV_FENCE(w,rw); \ + } while (0) ++#else ++#define __smp_store_release(p, v) \ ++do { \ ++ compiletime_assert_atomic_type(*p); \ ++ RISCV_FENCE(rw,w); \ ++ WRITE_ONCE(*p, v); \ ++} while (0) ++#endif + + #define __smp_load_acquire(p) \ + ({ \ +@@ -44,6 +54,18 @@ do { \ + ___p1; \ + }) + ++#define smp_cond_load_acquire(ptr, cond_expr) ({ \ ++ typeof(ptr) __PTR = (ptr); \ ++ __unqual_scalar_typeof(*ptr) VAL; \ ++ for (;;) { \ ++ VAL = __smp_load_acquire(__PTR); \ ++ if (cond_expr) \ ++ break; \ ++ cpu_relax(); \ ++ } \ ++ (typeof(*ptr))VAL; \ ++}) ++ + /* + * This is a very specific barrier: it's currently only used in two places in + * the kernel, both in the scheduler. See include/linux/spinlock.h for the two diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/errata_list.h index b55b434f0059..ea33288f8a25 100644 --- a/arch/riscv/include/asm/errata_list.h @@ -10436,6 +10852,89 @@ index b55b434f0059..ea33288f8a25 100644 : : "r"(_cachesize), \ "r"((unsigned long)(_start) & ~((_cachesize) - 1UL)), \ "r"((unsigned long)(_start) + (_size)) \ +diff --git a/arch/riscv/include/asm/fixmap.h b/arch/riscv/include/asm/fixmap.h +index 0a55099bb734..672bfe1121fe 100644 +--- a/arch/riscv/include/asm/fixmap.h ++++ b/arch/riscv/include/asm/fixmap.h +@@ -10,6 +10,10 @@ + #include + #include + #include ++#ifdef CONFIG_HIGHMEM ++#include ++#include ++#endif + + #ifdef CONFIG_MMU + /* +@@ -37,6 +41,10 @@ enum fixed_addresses { + FIX_TEXT_POKE1, + FIX_TEXT_POKE0, + FIX_EARLYCON_MEM_BASE, ++#ifdef CONFIG_HIGHMEM ++ FIX_KMAP_BEGIN, ++ FIX_KMAP_END = FIX_KMAP_BEGIN + (KM_MAX_IDX * NR_CPUS) - 1, ++#endif + + __end_of_permanent_fixed_addresses, + /* +@@ -47,7 +55,12 @@ enum fixed_addresses { + #define FIX_BTMAPS_SLOTS 7 + #define TOTAL_FIX_BTMAPS (NR_FIX_BTMAPS * FIX_BTMAPS_SLOTS) + ++#ifdef CONFIG_HIGHMEM ++ FIX_BTMAP_END = __ALIGN_MASK(__end_of_permanent_fixed_addresses, ++ ((PMD_SIZE / PAGE_SIZE) - 1)) + 1, ++#else + FIX_BTMAP_END = __end_of_permanent_fixed_addresses, ++#endif + FIX_BTMAP_BEGIN = FIX_BTMAP_END + TOTAL_FIX_BTMAPS - 1, + + __end_of_fixed_addresses +diff --git a/arch/riscv/include/asm/highmem.h b/arch/riscv/include/asm/highmem.h +new file mode 100644 +index 000000000000..a36fc835b8ab +--- /dev/null ++++ b/arch/riscv/include/asm/highmem.h +@@ -0,0 +1,13 @@ ++/* SPDX-License-Identifier: GPL-2.0 */ ++ ++#ifndef _ASM_HIGHMEM_H ++#define _ASM_HIGHMEM_H ++ ++#include ++#include ++#include ++ ++#define flush_cache_kmaps() do {} while (0) ++ ++extern pte_t *pkmap_page_table; ++#endif +diff --git a/arch/riscv/include/asm/io.h b/arch/riscv/include/asm/io.h +index 42497d487a17..bbdc3c7ed6ca 100644 +--- a/arch/riscv/include/asm/io.h ++++ b/arch/riscv/include/asm/io.h +@@ -140,4 +140,8 @@ __io_writes_outs(outs, u64, q, __io_pbr(), __io_paw()) + ((__force void *)ioremap_prot((addr), (size), _PAGE_KERNEL)) + #endif + ++#undef ioremap_wc ++#define ioremap_wc(addr, size) \ ++ ioremap_prot((addr), (size), _PAGE_IOREMAP_WC) ++ + #endif /* _ASM_RISCV_IO_H */ +diff --git a/arch/riscv/include/asm/kexec.h b/arch/riscv/include/asm/kexec.h +index 2b56769cb530..62f3ddc7c498 100644 +--- a/arch/riscv/include/asm/kexec.h ++++ b/arch/riscv/include/asm/kexec.h +@@ -56,6 +56,7 @@ extern riscv_kexec_method riscv_kexec_norelocate; + + #ifdef CONFIG_KEXEC_FILE + extern const struct kexec_file_ops elf_kexec_ops; ++extern const struct kexec_file_ops image_kexec_ops; + + struct purgatory_info; + int arch_kexec_apply_relocations_add(struct purgatory_info *pi, diff --git a/arch/riscv/include/asm/pgtable-64.h b/arch/riscv/include/asm/pgtable-64.h index 7a5097202e15..783837bbd878 100644 --- a/arch/riscv/include/asm/pgtable-64.h @@ -10464,6 +10963,1438 @@ index 7a5097202e15..783837bbd878 100644 #define _PAGE_MTMASK_THEAD (_PAGE_PMA_THEAD | _PAGE_IO_THEAD | (1UL << 59)) static inline u64 riscv_page_mtmask(void) +diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h +index a16fcdf91f39..4774cd9e5a83 100644 +--- a/arch/riscv/include/asm/pgtable.h ++++ b/arch/riscv/include/asm/pgtable.h +@@ -94,7 +94,12 @@ + #ifdef CONFIG_64BIT + #define MAX_FDT_SIZE PMD_SIZE + #define FIX_FDT_SIZE (MAX_FDT_SIZE + SZ_2M) ++#ifdef CONFIG_HIGHMEM ++#define FIXADDR_PMD_NUM 20 ++#define FIXADDR_SIZE ((PMD_SIZE * FIXADDR_PMD_NUM) + FIX_FDT_SIZE) ++#else + #define FIXADDR_SIZE (PMD_SIZE + FIX_FDT_SIZE) ++#endif + #else + #define MAX_FDT_SIZE PGDIR_SIZE + #define FIX_FDT_SIZE MAX_FDT_SIZE +@@ -104,6 +109,14 @@ + + #endif + ++#ifdef CONFIG_HIGHMEM ++#define PKMAP_BASE ((FIXADDR_START - PMD_SIZE) & (PMD_MASK)) ++#define LAST_PKMAP (PMD_SIZE >> PAGE_SHIFT) ++#define LAST_PKMAP_MASK (LAST_PKMAP - 1) ++#define PKMAP_NR(virt) (((virt) - PKMAP_BASE) >> PAGE_SHIFT) ++#define PKMAP_ADDR(nr) (PKMAP_BASE + ((nr) << PAGE_SHIFT)) ++#endif ++ + #ifdef CONFIG_XIP_KERNEL + #define XIP_OFFSET SZ_32M + #define XIP_OFFSET_MASK (SZ_32M - 1) +@@ -205,7 +218,8 @@ extern struct pt_alloc_ops pt_ops __initdata; + + #define PAGE_TABLE __pgprot(_PAGE_TABLE) + +-#define _PAGE_IOREMAP ((_PAGE_KERNEL & ~_PAGE_MTMASK) | _PAGE_IO) ++#define _PAGE_IOREMAP ((_PAGE_KERNEL & ~_PAGE_MTMASK) | _PAGE_IO) ++#define _PAGE_IOREMAP_WC ((_PAGE_KERNEL & ~_PAGE_MTMASK) | _PAGE_NOCACHE) + #define PAGE_KERNEL_IO __pgprot(_PAGE_IOREMAP) + + extern pgd_t swapper_pg_dir[]; +@@ -520,12 +534,17 @@ static inline void set_pte(pte_t *ptep, pte_t pteval) + + void flush_icache_pte(pte_t pte); + +-static inline void __set_pte_at(pte_t *ptep, pte_t pteval) ++static inline void __set_pte_at(struct mm_struct *mm, unsigned long addr, ++ pte_t *ptep, pte_t pteval) + { + if (pte_present(pteval) && pte_exec(pteval)) + flush_icache_pte(pteval); + + set_pte(ptep, pteval); ++ ++#ifdef CONFIG_HIGHMEM ++ local_flush_tlb_page(addr); ++#endif + } + + #define PFN_PTE_SHIFT _PAGE_PFN_SHIFT +@@ -536,9 +555,10 @@ static inline void set_ptes(struct mm_struct *mm, unsigned long addr, + page_table_check_ptes_set(mm, ptep, pteval, nr); + + for (;;) { +- __set_pte_at(ptep, pteval); ++ __set_pte_at(mm, addr, ptep, pteval); + if (--nr == 0) + break; ++ addr += PAGE_SIZE; + ptep++; + pte_val(pteval) += 1 << _PAGE_PFN_SHIFT; + } +@@ -548,7 +568,7 @@ static inline void set_ptes(struct mm_struct *mm, unsigned long addr, + static inline void pte_clear(struct mm_struct *mm, + unsigned long addr, pte_t *ptep) + { +- __set_pte_at(ptep, __pte(0)); ++ __set_pte_at(mm, addr, ptep, __pte(0)); + } + + #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS +@@ -557,7 +577,7 @@ static inline int ptep_set_access_flags(struct vm_area_struct *vma, + pte_t entry, int dirty) + { + if (!pte_same(*ptep, entry)) +- __set_pte_at(ptep, entry); ++ __set_pte_at(vma->vm_mm, address, ptep, entry); + /* + * update_mmu_cache will unconditionally execute, handling both + * the case that the PTE changed and the spurious fault case. +@@ -730,14 +750,14 @@ static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr, + pmd_t *pmdp, pmd_t pmd) + { + page_table_check_pmd_set(mm, pmdp, pmd); +- return __set_pte_at((pte_t *)pmdp, pmd_pte(pmd)); ++ return __set_pte_at(mm, addr, (pte_t *)pmdp, pmd_pte(pmd)); + } + + static inline void set_pud_at(struct mm_struct *mm, unsigned long addr, + pud_t *pudp, pud_t pud) + { + page_table_check_pud_set(mm, pudp, pud); +- return __set_pte_at((pte_t *)pudp, pud_pte(pud)); ++ return __set_pte_at(mm, addr, (pte_t *)pudp, pud_pte(pud)); + } + + #ifdef CONFIG_PAGE_TABLE_CHECK +diff --git a/arch/riscv/include/asm/sparsemem.h b/arch/riscv/include/asm/sparsemem.h +index 63acaecc3374..7ed3519b2d77 100644 +--- a/arch/riscv/include/asm/sparsemem.h ++++ b/arch/riscv/include/asm/sparsemem.h +@@ -5,7 +5,7 @@ + + #ifdef CONFIG_SPARSEMEM + #ifdef CONFIG_64BIT +-#define MAX_PHYSMEM_BITS 56 ++#define MAX_PHYSMEM_BITS 44 + #else + #define MAX_PHYSMEM_BITS 34 + #endif /* CONFIG_64BIT */ +diff --git a/arch/riscv/include/asm/switch_to.h b/arch/riscv/include/asm/switch_to.h +index a727be723c56..1da3f54d52f0 100644 +--- a/arch/riscv/include/asm/switch_to.h ++++ b/arch/riscv/include/asm/switch_to.h +@@ -63,6 +63,21 @@ static __always_inline bool has_fpu(void) + return riscv_has_extension_likely(RISCV_ISA_EXT_f) || + riscv_has_extension_likely(RISCV_ISA_EXT_d); + } ++ ++ ++static inline void kernel_fpu_begin(void) ++{ ++ preempt_disable(); ++ fstate_save(current, task_pt_regs(current)); ++ csr_set(CSR_SSTATUS, SR_FS); ++} ++ ++static inline void kernel_fpu_end(void) ++{ ++ csr_clear(CSR_SSTATUS, SR_FS); ++ fstate_restore(current, task_pt_regs(current)); ++ preempt_enable(); ++} + #else + static __always_inline bool has_fpu(void) { return false; } + #define fstate_save(task, regs) do { } while (0) +diff --git a/arch/riscv/include/asm/timex.h b/arch/riscv/include/asm/timex.h +index a06697846e69..a0e24f329381 100644 +--- a/arch/riscv/include/asm/timex.h ++++ b/arch/riscv/include/asm/timex.h +@@ -9,6 +9,10 @@ + #include + + typedef unsigned long cycles_t; ++#ifdef CONFIG_SOPHGO_MULTI_CHIP_CLOCK_SYNC ++extern u64 dw_timer_read_counter(void); ++extern void __iomem *sched_io_base; ++#endif + + #ifdef CONFIG_RISCV_M_MODE + +@@ -52,7 +56,18 @@ static inline cycles_t get_cycles(void) + { + return csr_read(CSR_TIME); + } ++#ifdef CONFIG_SOPHGO_MULTI_CHIP_CLOCK_SYNC ++static inline cycles_t dw_get_cycles(void) ++{ ++ if (sched_io_base) ++ return dw_timer_read_counter(); ++ else ++ return csr_read(CSR_TIME); ++} ++#define get_cycles dw_get_cycles ++#else + #define get_cycles get_cycles ++#endif + + static inline u32 get_cycles_hi(void) + { +diff --git a/arch/riscv/include/asm/vdso/gettimeofday.h b/arch/riscv/include/asm/vdso/gettimeofday.h +index ba3283cf7acc..ece0654e5767 100644 +--- a/arch/riscv/include/asm/vdso/gettimeofday.h ++++ b/arch/riscv/include/asm/vdso/gettimeofday.h +@@ -84,6 +84,26 @@ static __always_inline const struct vdso_data *__arch_get_vdso_data(void) + return _vdso_data; + } + ++#ifdef CONFIG_SOPHGO_MULTI_CHIP_CLOCK_SYNC ++static inline bool sophgo_vdso_hres_capable(void) ++{ ++ return false; ++} ++#define __arch_vdso_hres_capable sophgo_vdso_hres_capable ++ ++static inline bool sophgo_vdso_clocksource_ok(const struct vdso_data *vd) ++{ ++ return false; ++} ++#define vdso_clocksource_ok sophgo_vdso_clocksource_ok ++ ++static inline bool sophgo_vdso_cycles_ok(u64 cycles) ++{ ++ return false; ++} ++#define vdso_cycles_ok sophgo_vdso_cycles_ok ++#endif ++ + #ifdef CONFIG_TIME_NS + static __always_inline + const struct vdso_data *__arch_get_timens_vdso_data(const struct vdso_data *vd) +diff --git a/arch/riscv/kernel/Makefile b/arch/riscv/kernel/Makefile +index a2499fcc1cf3..668e5e5c8e41 100644 +--- a/arch/riscv/kernel/Makefile ++++ b/arch/riscv/kernel/Makefile +@@ -88,7 +88,7 @@ endif + obj-$(CONFIG_HOTPLUG_CPU) += cpu-hotplug.o + obj-$(CONFIG_KGDB) += kgdb.o + obj-$(CONFIG_KEXEC_CORE) += kexec_relocate.o crash_save_regs.o machine_kexec.o +-obj-$(CONFIG_KEXEC_FILE) += elf_kexec.o machine_kexec_file.o ++obj-$(CONFIG_KEXEC_FILE) += elf_kexec.o image_kexec.o machine_kexec_file.o + obj-$(CONFIG_CRASH_DUMP) += crash_dump.o + obj-$(CONFIG_CRASH_CORE) += crash_core.o + +diff --git a/arch/riscv/kernel/elf_kexec.c b/arch/riscv/kernel/elf_kexec.c +index e60fbd8660c4..3b80befe0519 100644 +--- a/arch/riscv/kernel/elf_kexec.c ++++ b/arch/riscv/kernel/elf_kexec.c +@@ -450,6 +450,12 @@ int arch_kexec_apply_relocations_add(struct purgatory_info *pi, + case R_RISCV_SUB32: + *(u32 *)loc -= val; + break; ++ case R_RISCV_ADD16: ++ *(u16 *)loc += val; ++ break; ++ case R_RISCV_SUB16: ++ *(u16 *)loc -= val; ++ break; + /* It has been applied by R_RISCV_PCREL_HI20 sym */ + case R_RISCV_PCREL_LO12_I: + case R_RISCV_ALIGN: +diff --git a/arch/riscv/kernel/image_kexec.c b/arch/riscv/kernel/image_kexec.c +new file mode 100644 +index 000000000000..37c5bd813958 +--- /dev/null ++++ b/arch/riscv/kernel/image_kexec.c +@@ -0,0 +1,305 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Kexec image loader ++ ++ * Adapted from arch/arm64/kernel/kexec_image.c ++ * Copyright (C) 2018 Linaro Limited ++ * Author: AKASHI Takahiro ++ */ ++#define pr_fmt(fmt) "kexec_file(Image): " fmt ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++static int prepare_elf_headers(void **addr, unsigned long *sz) ++{ ++ struct crash_mem *cmem; ++ unsigned int nr_ranges; ++ int ret; ++ u64 i; ++ phys_addr_t start, end; ++ ++ nr_ranges = 2; /* for exclusion of crashkernel region */ ++ for_each_mem_range(i, &start, &end) ++ nr_ranges++; ++ ++ cmem = kmalloc(struct_size(cmem, ranges, nr_ranges), GFP_KERNEL); ++ if (!cmem) ++ return -ENOMEM; ++ ++ cmem->max_nr_ranges = nr_ranges; ++ cmem->nr_ranges = 0; ++ for_each_mem_range(i, &start, &end) { ++ cmem->ranges[cmem->nr_ranges].start = start; ++ cmem->ranges[cmem->nr_ranges].end = end - 1; ++ cmem->nr_ranges++; ++ } ++ ++ /* Exclude crashkernel region */ ++ ret = crash_exclude_mem_range(cmem, crashk_res.start, crashk_res.end); ++ if (ret) ++ goto out; ++ ++ if (crashk_low_res.end) { ++ ret = crash_exclude_mem_range(cmem, crashk_low_res.start, crashk_low_res.end); ++ if (ret) ++ goto out; ++ } ++ ++ ret = crash_prepare_elf64_headers(cmem, true, addr, sz); ++ ++out: ++ kfree(cmem); ++ return ret; ++} ++ ++/* ++ * Tries to add the initrd and DTB to the image. If it is not possible to find ++ * valid locations, this function will undo changes to the image and return non ++ * zero. ++ */ ++static int load_other_segments(struct kimage *image, ++ unsigned long kernel_load_addr, ++ unsigned long kernel_size, ++ char *initrd, unsigned long initrd_len, ++ char *cmdline) ++{ ++ struct kexec_buf kbuf; ++ void *headers, *fdt = NULL; ++ unsigned long headers_sz, initrd_load_addr = 0, ++ orig_segments = image->nr_segments; ++ int ret = 0; ++ ++ kbuf.image = image; ++ /* not allocate anything below the kernel */ ++ kbuf.buf_min = kernel_load_addr + kernel_size; ++ ++ /* load elf core header */ ++ if (image->type == KEXEC_TYPE_CRASH) { ++ ret = prepare_elf_headers(&headers, &headers_sz); ++ if (ret) { ++ pr_err("Preparing elf core header failed\n"); ++ goto out_err; ++ } ++ ++ kbuf.buffer = headers; ++ kbuf.bufsz = headers_sz; ++ kbuf.mem = KEXEC_BUF_MEM_UNKNOWN; ++ kbuf.memsz = headers_sz; ++ kbuf.buf_align = PAGE_SIZE; ++ kbuf.buf_max = ULONG_MAX; ++ kbuf.top_down = true; ++ ++ ret = kexec_add_buffer(&kbuf); ++ if (ret) { ++ vfree(headers); ++ goto out_err; ++ } ++ image->elf_headers = headers; ++ image->elf_load_addr = kbuf.mem; ++ image->elf_headers_sz = headers_sz; ++ ++ pr_debug("Loaded elf core header at 0x%lx bufsz=0x%lx memsz=0x%lx\n", ++ image->elf_load_addr, kbuf.bufsz, kbuf.memsz); ++ } ++ ++ /* load initrd */ ++ if (initrd) { ++ kbuf.buffer = initrd; ++ kbuf.bufsz = initrd_len; ++ kbuf.mem = KEXEC_BUF_MEM_UNKNOWN; ++ kbuf.memsz = initrd_len; ++ kbuf.buf_align = PAGE_SIZE; ++ /* avoid to overlap kernel address */ ++ kbuf.buf_min = round_up(kernel_load_addr, SZ_1G); ++ kbuf.buf_max = ULONG_MAX; ++ kbuf.top_down = false; ++ ++ ret = kexec_add_buffer(&kbuf); ++ if (ret) ++ goto out_err; ++ initrd_load_addr = kbuf.mem; ++ ++ pr_debug("Loaded initrd at 0x%lx bufsz=0x%lx memsz=0x%lx\n", ++ initrd_load_addr, kbuf.bufsz, kbuf.memsz); ++ } ++ ++ /* load dtb */ ++ fdt = of_kexec_alloc_and_setup_fdt(image, initrd_load_addr, ++ initrd_len, cmdline, 0); ++ if (!fdt) { ++ pr_err("Preparing for new dtb failed\n"); ++ ret = -EINVAL; ++ goto out_err; ++ } ++ ++ /* trim it */ ++ fdt_pack(fdt); ++ kbuf.buffer = fdt; ++ kbuf.bufsz = kbuf.memsz = fdt_totalsize(fdt); ++ kbuf.buf_align = PAGE_SIZE; ++ kbuf.buf_max = ULONG_MAX; ++ kbuf.mem = KEXEC_BUF_MEM_UNKNOWN; ++ kbuf.top_down = false; ++ ++ ret = kexec_add_buffer(&kbuf); ++ if (ret) ++ goto out_err; ++ /* Cache the fdt buffer address for memory cleanup */ ++ image->arch.fdt = fdt; ++ image->arch.fdt_addr = kbuf.mem; ++ ++ pr_debug("Loaded dtb at 0x%lx bufsz=0x%lx memsz=0x%lx\n", ++ kbuf.mem, kbuf.bufsz, kbuf.memsz); ++ ++ return 0; ++ ++out_err: ++ image->nr_segments = orig_segments; ++ kvfree(fdt); ++ return ret; ++} ++ ++static int image_probe(const char *kernel_buf, unsigned long kernel_len) ++{ ++ const struct riscv_image_header *h = ++ (const struct riscv_image_header *)(kernel_buf); ++ ++ if (!h || (kernel_len < sizeof(*h))) ++ return -EINVAL; ++ ++ if (memcmp(&h->magic2, RISCV_IMAGE_MAGIC2, sizeof(h->magic2))) ++ return -EINVAL; ++ ++ return 0; ++} ++ ++static void *image_load(struct kimage *image, ++ char *kernel, unsigned long kernel_len, ++ char *initrd, unsigned long initrd_len, ++ char *cmdline, unsigned long cmdline_len) ++{ ++ struct riscv_image_header *h; ++ u64 flags; ++ bool be_image, be_kernel; ++ struct kexec_buf kbuf; ++ unsigned long text_offset, kernel_segment_number; ++ unsigned long kernel_start; ++ struct kexec_segment *kernel_segment; ++ int ret; ++ ++ h = (struct riscv_image_header *)kernel; ++ if (!h->image_size) ++ return ERR_PTR(-EINVAL); ++ ++ /* Check cpu features */ ++ flags = le64_to_cpu(h->flags); ++ be_image = __HEAD_FLAG(BE); ++ be_kernel = IS_ENABLED(CONFIG_CPU_BIG_ENDIAN); ++ if (be_image != be_kernel) ++ return ERR_PTR(-EINVAL); ++ ++ /* Load the kernel */ ++ kbuf.image = image; ++ kbuf.buf_min = 0; ++ kbuf.buf_max = ULONG_MAX; ++ kbuf.top_down = false; ++ ++ kbuf.buffer = kernel; ++ kbuf.bufsz = kernel_len; ++ kbuf.mem = KEXEC_BUF_MEM_UNKNOWN; ++ kbuf.memsz = le64_to_cpu(h->image_size); ++ text_offset = le64_to_cpu(h->text_offset); ++ kbuf.buf_align = PMD_SIZE; ++ ++ /* Adjust kernel segment with TEXT_OFFSET */ ++ kbuf.memsz += text_offset; ++ ++ kernel_segment_number = image->nr_segments; ++ ++ /* ++ * The location of the kernel segment may make it impossible to satisfy ++ * the other segment requirements, so we try repeatedly to find a ++ * location that will work. ++ */ ++ while ((ret = kexec_add_buffer(&kbuf)) == 0) { ++ /* Try to load additional data */ ++ kernel_segment = &image->segment[kernel_segment_number]; ++ ret = load_other_segments(image, kernel_segment->mem, ++ kernel_segment->memsz, initrd, ++ initrd_len, cmdline); ++ if (!ret) ++ break; ++ ++ /* ++ * We couldn't find space for the other segments; erase the ++ * kernel segment and try the next available hole. ++ */ ++ image->nr_segments -= 1; ++ kbuf.buf_min = kernel_segment->mem + kernel_segment->memsz; ++ kbuf.mem = KEXEC_BUF_MEM_UNKNOWN; ++ } ++ ++ if (ret) { ++ pr_err("Could not find any suitable kernel location!"); ++ return ERR_PTR(ret); ++ } ++ ++ kernel_segment = &image->segment[kernel_segment_number]; ++ kernel_segment->mem += text_offset; ++ kernel_segment->memsz -= text_offset; ++ kernel_start = kernel_segment->mem; ++ image->start = kernel_start; ++ ++ ++ pr_debug("Loaded kernel at 0x%lx bufsz=0x%lx memsz=0x%lx\n", ++ kernel_segment->mem, kbuf.bufsz, ++ kernel_segment->memsz); ++ ++#ifdef CONFIG_ARCH_SUPPORTS_KEXEC_PURGATORY ++ /* Add purgatory to the image */ ++ kbuf.top_down = true; ++ kbuf.mem = KEXEC_BUF_MEM_UNKNOWN; ++ ret = kexec_load_purgatory(image, &kbuf); ++ if (ret) { ++ pr_err("Error loading purgatory ret=%d\n", ret); ++ return ERR_PTR(ret); ++ } ++ ret = kexec_purgatory_get_set_symbol(image, "riscv_kernel_entry", ++ &kernel_start, ++ sizeof(kernel_start), 0); ++ if (ret) ++ pr_err("Error update purgatory ret=%d\n", ret); ++#endif /* CONFIG_ARCH_SUPPORTS_KEXEC_PURGATORY */ ++ ++ return ret ? ERR_PTR(ret) : NULL; ++} ++ ++#ifdef CONFIG_KEXEC_IMAGE_VERIFY_SIG ++static int image_verify_sig(const char *kernel, unsigned long kernel_len) ++{ ++ return verify_pefile_signature(kernel, kernel_len, NULL, ++ VERIFYING_KEXEC_PE_SIGNATURE); ++} ++#endif ++ ++const struct kexec_file_ops image_kexec_ops = { ++ .probe = image_probe, ++ .load = image_load, ++#ifdef CONFIG_KEXEC_IMAGE_VERIFY_SIG ++ .verify_sig = image_verify_sig, ++#endif ++}; +diff --git a/arch/riscv/kernel/machine_kexec_file.c b/arch/riscv/kernel/machine_kexec_file.c +index b0bf8c1722c0..401edfd1774f 100644 +--- a/arch/riscv/kernel/machine_kexec_file.c ++++ b/arch/riscv/kernel/machine_kexec_file.c +@@ -9,6 +9,7 @@ + #include + + const struct kexec_file_ops * const kexec_file_loaders[] = { ++ &image_kexec_ops, + &elf_kexec_ops, + NULL + }; +diff --git a/arch/riscv/kernel/module.c b/arch/riscv/kernel/module.c +index df4f6fec5d17..ced5a09abaaa 100644 +--- a/arch/riscv/kernel/module.c ++++ b/arch/riscv/kernel/module.c +@@ -337,6 +337,45 @@ static int (*reloc_handlers_rela[]) (struct module *me, u32 *location, + [R_RISCV_SUB64] = apply_r_riscv_sub64_rela, + }; + ++static inline unsigned int apply_calc_pcrel_lo12(Elf_Shdr *sechdrs, ++ Elf_Rela *rel, Elf_Sym *sym, unsigned int idx, ++ unsigned int symindex, unsigned int relsec, ++ struct module *me, Elf_Addr *v) ++{ ++ unsigned long hi20_loc = ++ sechdrs[sechdrs[relsec].sh_info].sh_addr ++ + rel[idx].r_offset; ++ u32 hi20_type = ELF_RISCV_R_TYPE(rel[idx].r_info); ++ unsigned int found = 0; ++ ++ /* Find the corresponding HI20 relocation entry */ ++ if (hi20_loc == sym->st_value ++ && (hi20_type == R_RISCV_PCREL_HI20 ++ || hi20_type == R_RISCV_GOT_HI20)) { ++ s32 hi20, lo12; ++ Elf_Sym *hi20_sym = ++ (Elf_Sym *)sechdrs[symindex].sh_addr ++ + ELF_RISCV_R_SYM(rel[idx].r_info); ++ unsigned long hi20_sym_val = ++ hi20_sym->st_value + rel[idx].r_addend; ++ ++ /* Calculate lo12 */ ++ size_t offset = hi20_sym_val - hi20_loc; ++ if (IS_ENABLED(CONFIG_MODULE_SECTIONS) ++ && hi20_type == R_RISCV_GOT_HI20) { ++ offset = module_emit_got_entry(me, hi20_sym_val); ++ offset = offset - hi20_loc; ++ } ++ hi20 = (offset + 0x800) & 0xfffff000; ++ lo12 = offset - hi20; ++ *v = (Elf_Addr)lo12; ++ ++ found = 1; ++ } ++ ++ return found; ++} ++ + int apply_relocate_add(Elf_Shdr *sechdrs, const char *strtab, + unsigned int symindex, unsigned int relsec, + struct module *me) +@@ -385,40 +424,24 @@ int apply_relocate_add(Elf_Shdr *sechdrs, const char *strtab, + + if (type == R_RISCV_PCREL_LO12_I || type == R_RISCV_PCREL_LO12_S) { + unsigned int j; ++ unsigned int found = 0; + +- for (j = 0; j < sechdrs[relsec].sh_size / sizeof(*rel); j++) { +- unsigned long hi20_loc = +- sechdrs[sechdrs[relsec].sh_info].sh_addr +- + rel[j].r_offset; +- u32 hi20_type = ELF_RISCV_R_TYPE(rel[j].r_info); +- +- /* Find the corresponding HI20 relocation entry */ +- if (hi20_loc == sym->st_value +- && (hi20_type == R_RISCV_PCREL_HI20 +- || hi20_type == R_RISCV_GOT_HI20)) { +- s32 hi20, lo12; +- Elf_Sym *hi20_sym = +- (Elf_Sym *)sechdrs[symindex].sh_addr +- + ELF_RISCV_R_SYM(rel[j].r_info); +- unsigned long hi20_sym_val = +- hi20_sym->st_value +- + rel[j].r_addend; +- +- /* Calculate lo12 */ +- size_t offset = hi20_sym_val - hi20_loc; +- if (IS_ENABLED(CONFIG_MODULE_SECTIONS) +- && hi20_type == R_RISCV_GOT_HI20) { +- offset = module_emit_got_entry( +- me, hi20_sym_val); +- offset = offset - hi20_loc; +- } +- hi20 = (offset + 0x800) & 0xfffff000; +- lo12 = offset - hi20; +- v = lo12; ++ if (i > 0) { ++ j = i - 1; ++ found = apply_calc_pcrel_lo12(sechdrs, rel, sym, j, ++ symindex, relsec, me, &v); ++ } + +- break; ++ if (found == 0) { ++ for (j = 0; j < sechdrs[relsec].sh_size/sizeof(*rel); j++) { ++ found = apply_calc_pcrel_lo12(sechdrs, rel, sym, ++ j, symindex, relsec, me, &v); ++ if (found) { ++ break; ++ } + } + } ++ + if (j == sechdrs[relsec].sh_size / sizeof(*rel)) { + pr_err( + "%s: Can not find HI20 relocation information\n", +diff --git a/arch/riscv/kernel/process.c b/arch/riscv/kernel/process.c +index 83e223318822..dd973216e31c 100644 +--- a/arch/riscv/kernel/process.c ++++ b/arch/riscv/kernel/process.c +@@ -204,3 +204,6 @@ int copy_thread(struct task_struct *p, const struct kernel_clone_args *args) + p->thread.sp = (unsigned long)childregs; /* kernel sp */ + return 0; + } ++ ++EXPORT_SYMBOL_GPL(__fstate_save); ++EXPORT_SYMBOL_GPL(__fstate_restore); +diff --git a/arch/riscv/kvm/vcpu_timer.c b/arch/riscv/kvm/vcpu_timer.c +index 75486b25ac45..ba803aa15b89 100644 +--- a/arch/riscv/kvm/vcpu_timer.c ++++ b/arch/riscv/kvm/vcpu_timer.c +@@ -15,6 +15,10 @@ + #include + #include + ++#ifdef CONFIG_SOPHGO_MULTI_CHIP_CLOCK_SYNC ++extern void dw_cs_get_mult_shift(u32 *mult, u32 *shift); ++#endif ++ + static u64 kvm_riscv_current_cycles(struct kvm_guest_timer *gt) + { + return get_cycles64() + gt->time_delta; +@@ -358,6 +362,10 @@ void kvm_riscv_guest_timer_init(struct kvm *kvm) + { + struct kvm_guest_timer *gt = &kvm->arch.timer; + ++#ifdef CONFIG_SOPHGO_MULTI_CHIP_CLOCK_SYNC ++ dw_cs_get_mult_shift(>->nsec_mult, >->nsec_shift); ++#else + riscv_cs_get_mult_shift(>->nsec_mult, >->nsec_shift); ++#endif + gt->time_delta = -get_cycles64(); + } +diff --git a/arch/riscv/mm/init.c b/arch/riscv/mm/init.c +index ec02ea86aa39..bab2654aae48 100644 +--- a/arch/riscv/mm/init.c ++++ b/arch/riscv/mm/init.c +@@ -36,6 +36,11 @@ + + #include "../kernel/head.h" + ++#ifdef CONFIG_HIGHMEM ++#include ++extern phys_addr_t __init_memblock find_max_low_addr(phys_addr_t limit); ++#endif ++ + struct kernel_mapping kernel_map __ro_after_init; + EXPORT_SYMBOL(kernel_map); + #ifdef CONFIG_XIP_KERNEL +@@ -75,6 +80,9 @@ static void __init zone_sizes_init(void) + max_zone_pfns[ZONE_DMA32] = PFN_DOWN(dma32_phys_limit); + #endif + max_zone_pfns[ZONE_NORMAL] = max_low_pfn; ++#ifdef CONFIG_HIGHMEM ++ max_zone_pfns[ZONE_HIGHMEM] = max_pfn; ++#endif + + free_area_init(max_zone_pfns); + } +@@ -131,6 +139,10 @@ static inline void print_ml(char *name, unsigned long b, unsigned long t) + static void __init print_vm_layout(void) + { + pr_notice("Virtual kernel memory layout:\n"); ++#ifdef CONFIG_HIGHMEM ++ print_ml("pkmap", (unsigned long)PKMAP_BASE, ++ (unsigned long)FIXADDR_START); ++#endif + print_ml("fixmap", (unsigned long)FIXADDR_START, + (unsigned long)FIXADDR_TOP); + print_ml("pci io", (unsigned long)PCI_IO_START, +@@ -158,6 +170,106 @@ static void __init print_vm_layout(void) + static void print_vm_layout(void) { } + #endif /* CONFIG_DEBUG_VM */ + ++#ifdef CONFIG_HIGHMEM ++ ++#ifdef CONFIG_DEBUG_VM ++#error Please unset CONFIG_DEBUG_VM when CONFIG_HIGHMEM is set, \ ++because CONFIG_DEBUG_VM will trigger VM_BUG_ON_PAGE in __free_pages()->put_page_testzero(). ++#endif ++#if defined(CONFIG_SPARSEMEM_VMEMMAP) && defined(CONFIG_NUMA) ++#error Please unset CONFIG_SPARSEMEM_VMEMMAP when CONFIG_HIGHMEM and CONFIG_NUMA are set, \ ++because vmemmap_verify will report warning that [xxx-xxx] potential offnode page_structs. ++#endif ++ ++/* free order size pages for optimize system boot time. */ ++#define OPTIMIZE_FREE_PAGES ++ ++#ifdef OPTIMIZE_FREE_PAGES ++#define ORDER_SIZE(order) (1UL << order) ++#define ORDER_MASK(order) (~(ORDER_SIZE(order) - 1)) ++#define PFN_ALIGN_ORDER(pfn, order) \ ++ (((u64)(pfn) + (ORDER_SIZE(order) - 1)) & ORDER_MASK(order)) ++ ++/* Free the reserved page into the buddy system, so it gets managed. */ ++static void __init free_highmem_pages(u64 start, u64 order) ++{ ++ struct page *page; ++ u64 i, pfn; ++ ++ for (i = 0, pfn = start; i < ORDER_SIZE(order); i++, pfn++) { ++ page = pfn_to_page(pfn); ++ ClearPageReserved(page); ++ set_page_count(page, 0); ++ } ++ ++ page = pfn_to_page(start); ++ __free_pages(page, order); ++ adjust_managed_page_count(page, ORDER_SIZE(order)); ++} ++ ++static void __init free_highpages(void) ++{ ++ phys_addr_t range_start, range_end; ++ u64 max_low = max_low_pfn; ++ u64 i, order; ++ ++ /* set highmem page free */ ++ for_each_free_mem_range(i, NUMA_NO_NODE, MEMBLOCK_NONE, ++ &range_start, &range_end, NULL) { ++ u64 start = PFN_UP(range_start), start_align; ++ u64 end = PFN_DOWN(range_end); ++ ++ /* Ignore complete lowmem entries */ ++ if (end <= max_low) ++ continue; ++ ++ /* Truncate partial highmem entries */ ++ if (start < max_low) ++ start = max_low; ++ ++ order = MAX_ORDER; ++ start_align = PFN_ALIGN_ORDER(start, order); ++ ++ for (; start < start_align; start++) ++ free_highmem_page(pfn_to_page(start)); ++ ++ //step by order size ++ for (; start < end; start += ORDER_SIZE(order)) ++ free_highmem_pages(start, order); ++ ++ for (; start < end; start++) ++ free_highmem_page(pfn_to_page(start)); ++ } ++} ++#else ++static void __init free_highpages(void) ++{ ++ unsigned long max_low = max_low_pfn; ++ phys_addr_t range_start, range_end; ++ u64 i; ++ ++ /* set highmem page free */ ++ for_each_free_mem_range(i, NUMA_NO_NODE, MEMBLOCK_NONE, ++ &range_start, &range_end, NULL) { ++ unsigned long start = PFN_UP(range_start); ++ unsigned long end = PFN_DOWN(range_end); ++ ++ ++ /* Ignore complete lowmem entries */ ++ if (end <= max_low) ++ continue; ++ ++ /* Truncate partial highmem entries */ ++ if (start < max_low) ++ start = max_low; ++ ++ for (; start < end; start++) ++ free_highmem_page(pfn_to_page(start)); ++ } ++} ++#endif ++#endif ++ + void __init mem_init(void) + { + #ifdef CONFIG_FLATMEM +@@ -166,6 +278,9 @@ void __init mem_init(void) + + swiotlb_init(max_pfn > PFN_DOWN(dma32_phys_limit), SWIOTLB_VERBOSE); + memblock_free_all(); ++#ifdef CONFIG_HIGHMEM ++ free_highpages(); ++#endif + + print_vm_layout(); + } +@@ -197,13 +312,18 @@ static void __init setup_bootmem(void) + phys_addr_t vmlinux_end = __pa_symbol(&_end); + phys_addr_t max_mapped_addr; + phys_addr_t phys_ram_end, vmlinux_start; ++#ifdef CONFIG_HIGHMEM ++ phys_addr_t max_low_addr; ++#endif + + if (IS_ENABLED(CONFIG_XIP_KERNEL)) + vmlinux_start = __pa_symbol(&_sdata); + else + vmlinux_start = __pa_symbol(&_start); + ++#ifndef CONFIG_HIGHMEM + memblock_enforce_memory_limit(memory_limit); ++#endif + + /* + * Make sure we align the reservation on PMD_SIZE since we will +@@ -249,12 +369,22 @@ static void __init setup_bootmem(void) + } + + min_low_pfn = PFN_UP(phys_ram_base); ++#ifdef CONFIG_HIGHMEM ++ max_low_addr = find_max_low_addr(memory_limit); ++ max_low_pfn = PFN_DOWN(max_low_addr); ++ max_pfn = PFN_DOWN(phys_ram_end); ++ memblock_set_current_limit(max_low_addr); ++#else + max_low_pfn = max_pfn = PFN_DOWN(phys_ram_end); ++#endif + high_memory = (void *)(__va(PFN_PHYS(max_low_pfn))); + + dma32_phys_limit = min(4UL * SZ_1G, (unsigned long)PFN_PHYS(max_low_pfn)); ++#ifdef CONFIG_HIGHMEM ++ set_max_mapnr(max_pfn - ARCH_PFN_OFFSET); ++#else + set_max_mapnr(max_low_pfn - ARCH_PFN_OFFSET); +- ++#endif + reserve_initrd_mem(); + + /* +@@ -283,8 +413,14 @@ struct pt_alloc_ops pt_ops __initdata; + + pgd_t swapper_pg_dir[PTRS_PER_PGD] __page_aligned_bss; + pgd_t trampoline_pg_dir[PTRS_PER_PGD] __page_aligned_bss; ++#ifdef CONFIG_HIGHMEM ++static pte_t fixmap_pte[PTRS_PER_PTE * FIXADDR_PMD_NUM] __page_aligned_bss; ++#else + static pte_t fixmap_pte[PTRS_PER_PTE] __page_aligned_bss; +- ++#endif ++#ifdef CONFIG_HIGHMEM ++static pte_t pkmap_pte[PTRS_PER_PTE] __page_aligned_bss; ++#endif + pgd_t early_pg_dir[PTRS_PER_PGD] __initdata __aligned(PAGE_SIZE); + + #ifdef CONFIG_XIP_KERNEL +@@ -318,10 +454,17 @@ void __set_fixmap(enum fixed_addresses idx, phys_addr_t phys, pgprot_t prot) + { + unsigned long addr = __fix_to_virt(idx); + pte_t *ptep; ++#ifdef CONFIG_HIGHMEM ++ unsigned long pte_idx = (addr - FIXADDR_START) >> PAGE_SHIFT; ++#endif + + BUG_ON(idx <= FIX_HOLE || idx >= __end_of_fixed_addresses); + ++#ifdef CONFIG_HIGHMEM ++ ptep = &fixmap_pte[pte_idx]; ++#else + ptep = &fixmap_pte[pte_index(addr)]; ++#endif + + if (pgprot_val(prot)) + set_pte(ptep, pfn_pte(phys >> PAGE_SHIFT, prot)); +@@ -1144,8 +1287,26 @@ asmlinkage void __init setup_vm(uintptr_t dtb_pa) + if (pgtable_l4_enabled) + create_pud_mapping(fixmap_pud, FIXADDR_START, + (uintptr_t)fixmap_pmd, PUD_SIZE, PAGE_TABLE); ++#ifdef CONFIG_HIGHMEM ++ { ++ int i; ++ for (i = 0; i < FIXADDR_PMD_NUM; i++) ++ create_pmd_mapping(fixmap_pmd, ++ (FIXADDR_START + i * PMD_SIZE), ++ (uintptr_t)&(fixmap_pte[i * PTRS_PER_PTE]), ++ PMD_SIZE, ++ PAGE_TABLE); ++ } ++#else + create_pmd_mapping(fixmap_pmd, FIXADDR_START, + (uintptr_t)fixmap_pte, PMD_SIZE, PAGE_TABLE); ++#endif ++#ifdef CONFIG_HIGHMEM ++ /* Setup pkmap PMD */ ++ create_pmd_mapping(fixmap_pmd, PKMAP_BASE, ++ (uintptr_t)pkmap_pte, PMD_SIZE, PAGE_TABLE); ++#endif ++ + /* Setup trampoline PGD and PMD */ + create_pgd_mapping(trampoline_pg_dir, kernel_map.virt_addr, + trampoline_pgd_next, PGDIR_SIZE, PAGE_TABLE); +@@ -1268,7 +1429,7 @@ static void __init create_linear_mapping_page_table(void) + if (end >= __pa(PAGE_OFFSET) + memory_limit) + end = __pa(PAGE_OFFSET) + memory_limit; + +- create_linear_mapping_range(start, end, 0); ++ create_linear_mapping_range(start, end, PMD_SIZE); + } + + #ifdef CONFIG_STRICT_KERNEL_RWX +@@ -1488,6 +1649,13 @@ static void __init reserve_crashkernel(void) + crashk_res.end = crash_base + crash_size - 1; + } + ++#ifdef CONFIG_HIGHMEM ++static void __init pkmap_init(void) ++{ ++ pkmap_page_table = &pkmap_pte[pte_index(PKMAP_BASE)]; ++} ++#endif ++ + void __init paging_init(void) + { + setup_bootmem(); +@@ -1507,6 +1675,9 @@ void __init misc_mem_init(void) + local_flush_tlb_kernel_range(VMEMMAP_START, VMEMMAP_END); + #endif + zone_sizes_init(); ++#ifdef CONFIG_HIGHMEM ++ pkmap_init(); ++#endif + reserve_crashkernel(); + memblock_dump_all(); + } +diff --git a/arch/riscv/mm/pageattr.c b/arch/riscv/mm/pageattr.c +index 01398fee5cf8..161d0b34c2cb 100644 +--- a/arch/riscv/mm/pageattr.c ++++ b/arch/riscv/mm/pageattr.c +@@ -5,7 +5,6 @@ + + #include + #include +-#include + #include + #include + #include +@@ -26,6 +25,19 @@ static unsigned long set_pageattr_masks(unsigned long val, struct mm_walk *walk) + return new_val; + } + ++static int pageattr_pgd_entry(pgd_t *pgd, unsigned long addr, ++ unsigned long next, struct mm_walk *walk) ++{ ++ pgd_t val = READ_ONCE(*pgd); ++ ++ if (pgd_leaf(val)) { ++ val = __pgd(set_pageattr_masks(pgd_val(val), walk)); ++ set_pgd(pgd, val); ++ } ++ ++ return 0; ++} ++ + static int pageattr_p4d_entry(p4d_t *p4d, unsigned long addr, + unsigned long next, struct mm_walk *walk) + { +@@ -84,6 +96,7 @@ static int pageattr_pte_hole(unsigned long addr, unsigned long next, + } + + static const struct mm_walk_ops pageattr_ops = { ++ .pgd_entry = pageattr_pgd_entry, + .p4d_entry = pageattr_p4d_entry, + .pud_entry = pageattr_pud_entry, + .pmd_entry = pageattr_pmd_entry, +@@ -92,181 +105,12 @@ static const struct mm_walk_ops pageattr_ops = { + .walk_lock = PGWALK_RDLOCK, + }; + +-#ifdef CONFIG_64BIT +-static int __split_linear_mapping_pmd(pud_t *pudp, +- unsigned long vaddr, unsigned long end) +-{ +- pmd_t *pmdp; +- unsigned long next; +- +- pmdp = pmd_offset(pudp, vaddr); +- +- do { +- next = pmd_addr_end(vaddr, end); +- +- if (next - vaddr >= PMD_SIZE && +- vaddr <= (vaddr & PMD_MASK) && end >= next) +- continue; +- +- if (pmd_leaf(*pmdp)) { +- struct page *pte_page; +- unsigned long pfn = _pmd_pfn(*pmdp); +- pgprot_t prot = __pgprot(pmd_val(*pmdp) & ~_PAGE_PFN_MASK); +- pte_t *ptep_new; +- int i; +- +- pte_page = alloc_page(GFP_KERNEL); +- if (!pte_page) +- return -ENOMEM; +- +- ptep_new = (pte_t *)page_address(pte_page); +- for (i = 0; i < PTRS_PER_PTE; ++i, ++ptep_new) +- set_pte(ptep_new, pfn_pte(pfn + i, prot)); +- +- smp_wmb(); +- +- set_pmd(pmdp, pfn_pmd(page_to_pfn(pte_page), PAGE_TABLE)); +- } +- } while (pmdp++, vaddr = next, vaddr != end); +- +- return 0; +-} +- +-static int __split_linear_mapping_pud(p4d_t *p4dp, +- unsigned long vaddr, unsigned long end) +-{ +- pud_t *pudp; +- unsigned long next; +- int ret; +- +- pudp = pud_offset(p4dp, vaddr); +- +- do { +- next = pud_addr_end(vaddr, end); +- +- if (next - vaddr >= PUD_SIZE && +- vaddr <= (vaddr & PUD_MASK) && end >= next) +- continue; +- +- if (pud_leaf(*pudp)) { +- struct page *pmd_page; +- unsigned long pfn = _pud_pfn(*pudp); +- pgprot_t prot = __pgprot(pud_val(*pudp) & ~_PAGE_PFN_MASK); +- pmd_t *pmdp_new; +- int i; +- +- pmd_page = alloc_page(GFP_KERNEL); +- if (!pmd_page) +- return -ENOMEM; +- +- pmdp_new = (pmd_t *)page_address(pmd_page); +- for (i = 0; i < PTRS_PER_PMD; ++i, ++pmdp_new) +- set_pmd(pmdp_new, +- pfn_pmd(pfn + ((i * PMD_SIZE) >> PAGE_SHIFT), prot)); +- +- smp_wmb(); +- +- set_pud(pudp, pfn_pud(page_to_pfn(pmd_page), PAGE_TABLE)); +- } +- +- ret = __split_linear_mapping_pmd(pudp, vaddr, next); +- if (ret) +- return ret; +- } while (pudp++, vaddr = next, vaddr != end); +- +- return 0; +-} +- +-static int __split_linear_mapping_p4d(pgd_t *pgdp, +- unsigned long vaddr, unsigned long end) +-{ +- p4d_t *p4dp; +- unsigned long next; +- int ret; +- +- p4dp = p4d_offset(pgdp, vaddr); +- +- do { +- next = p4d_addr_end(vaddr, end); +- +- /* +- * If [vaddr; end] contains [vaddr & P4D_MASK; next], we don't +- * need to split, we'll change the protections on the whole P4D. +- */ +- if (next - vaddr >= P4D_SIZE && +- vaddr <= (vaddr & P4D_MASK) && end >= next) +- continue; +- +- if (p4d_leaf(*p4dp)) { +- struct page *pud_page; +- unsigned long pfn = _p4d_pfn(*p4dp); +- pgprot_t prot = __pgprot(p4d_val(*p4dp) & ~_PAGE_PFN_MASK); +- pud_t *pudp_new; +- int i; +- +- pud_page = alloc_page(GFP_KERNEL); +- if (!pud_page) +- return -ENOMEM; +- +- /* +- * Fill the pud level with leaf puds that have the same +- * protections as the leaf p4d. +- */ +- pudp_new = (pud_t *)page_address(pud_page); +- for (i = 0; i < PTRS_PER_PUD; ++i, ++pudp_new) +- set_pud(pudp_new, +- pfn_pud(pfn + ((i * PUD_SIZE) >> PAGE_SHIFT), prot)); +- +- /* +- * Make sure the pud filling is not reordered with the +- * p4d store which could result in seeing a partially +- * filled pud level. +- */ +- smp_wmb(); +- +- set_p4d(p4dp, pfn_p4d(page_to_pfn(pud_page), PAGE_TABLE)); +- } +- +- ret = __split_linear_mapping_pud(p4dp, vaddr, next); +- if (ret) +- return ret; +- } while (p4dp++, vaddr = next, vaddr != end); +- +- return 0; +-} +- +-static int __split_linear_mapping_pgd(pgd_t *pgdp, +- unsigned long vaddr, +- unsigned long end) +-{ +- unsigned long next; +- int ret; +- +- do { +- next = pgd_addr_end(vaddr, end); +- /* We never use PGD mappings for the linear mapping */ +- ret = __split_linear_mapping_p4d(pgdp, vaddr, next); +- if (ret) +- return ret; +- } while (pgdp++, vaddr = next, vaddr != end); +- +- return 0; +-} +- +-static int split_linear_mapping(unsigned long start, unsigned long end) +-{ +- return __split_linear_mapping_pgd(pgd_offset_k(start), start, end); +-} +-#endif /* CONFIG_64BIT */ +- + static int __set_memory(unsigned long addr, int numpages, pgprot_t set_mask, + pgprot_t clear_mask) + { + int ret; + unsigned long start = addr; + unsigned long end = start + PAGE_SIZE * numpages; +- unsigned long __maybe_unused lm_start; +- unsigned long __maybe_unused lm_end; + struct pageattr_masks masks = { + .set_mask = set_mask, + .clear_mask = clear_mask +@@ -276,72 +120,11 @@ static int __set_memory(unsigned long addr, int numpages, pgprot_t set_mask, + return 0; + + mmap_write_lock(&init_mm); +- +-#ifdef CONFIG_64BIT +- /* +- * We are about to change the permissions of a kernel mapping, we must +- * apply the same changes to its linear mapping alias, which may imply +- * splitting a huge mapping. +- */ +- +- if (is_vmalloc_or_module_addr((void *)start)) { +- struct vm_struct *area = NULL; +- int i, page_start; +- +- area = find_vm_area((void *)start); +- page_start = (start - (unsigned long)area->addr) >> PAGE_SHIFT; +- +- for (i = page_start; i < page_start + numpages; ++i) { +- lm_start = (unsigned long)page_address(area->pages[i]); +- lm_end = lm_start + PAGE_SIZE; +- +- ret = split_linear_mapping(lm_start, lm_end); +- if (ret) +- goto unlock; +- +- ret = walk_page_range_novma(&init_mm, lm_start, lm_end, +- &pageattr_ops, NULL, &masks); +- if (ret) +- goto unlock; +- } +- } else if (is_kernel_mapping(start) || is_linear_mapping(start)) { +- if (is_kernel_mapping(start)) { +- lm_start = (unsigned long)lm_alias(start); +- lm_end = (unsigned long)lm_alias(end); +- } else { +- lm_start = start; +- lm_end = end; +- } +- +- ret = split_linear_mapping(lm_start, lm_end); +- if (ret) +- goto unlock; +- +- ret = walk_page_range_novma(&init_mm, lm_start, lm_end, +- &pageattr_ops, NULL, &masks); +- if (ret) +- goto unlock; +- } +- + ret = walk_page_range_novma(&init_mm, start, end, &pageattr_ops, NULL, + &masks); +- +-unlock: +- mmap_write_unlock(&init_mm); +- +- /* +- * We can't use flush_tlb_kernel_range() here as we may have split a +- * hugepage that is larger than that, so let's flush everything. +- */ +- flush_tlb_all(); +-#else +- ret = walk_page_range_novma(&init_mm, start, end, &pageattr_ops, NULL, +- &masks); +- + mmap_write_unlock(&init_mm); + + flush_tlb_kernel_range(start, end); +-#endif + + return ret; + } +@@ -376,14 +159,36 @@ int set_memory_nx(unsigned long addr, int numpages) + + int set_direct_map_invalid_noflush(struct page *page) + { +- return __set_memory((unsigned long)page_address(page), 1, +- __pgprot(0), __pgprot(_PAGE_PRESENT)); ++ int ret; ++ unsigned long start = (unsigned long)page_address(page); ++ unsigned long end = start + PAGE_SIZE; ++ struct pageattr_masks masks = { ++ .set_mask = __pgprot(0), ++ .clear_mask = __pgprot(_PAGE_PRESENT) ++ }; ++ ++ mmap_read_lock(&init_mm); ++ ret = walk_page_range(&init_mm, start, end, &pageattr_ops, &masks); ++ mmap_read_unlock(&init_mm); ++ ++ return ret; + } + + int set_direct_map_default_noflush(struct page *page) + { +- return __set_memory((unsigned long)page_address(page), 1, +- PAGE_KERNEL, __pgprot(_PAGE_EXEC)); ++ int ret; ++ unsigned long start = (unsigned long)page_address(page); ++ unsigned long end = start + PAGE_SIZE; ++ struct pageattr_masks masks = { ++ .set_mask = PAGE_KERNEL, ++ .clear_mask = __pgprot(0) ++ }; ++ ++ mmap_read_lock(&init_mm); ++ ret = walk_page_range(&init_mm, start, end, &pageattr_ops, &masks); ++ mmap_read_unlock(&init_mm); ++ ++ return ret; + } + + #ifdef CONFIG_DEBUG_PAGEALLOC +diff --git a/drivers/base/arch_numa.c b/drivers/base/arch_numa.c +index 96281de7010d..4b0b582bfc1a 100644 +--- a/drivers/base/arch_numa.c ++++ b/drivers/base/arch_numa.c +@@ -359,7 +359,11 @@ static int __init numa_alloc_distance(void) + int i, j; + + size = nr_node_ids * nr_node_ids * sizeof(numa_distance[0]); ++#ifdef CONFIG_HIGHMEM ++ numa_distance = memblock_alloc_low(size, PAGE_SIZE); ++#else + numa_distance = memblock_alloc(size, PAGE_SIZE); ++#endif + if (WARN_ON(!numa_distance)) + return -ENOMEM; + +diff --git a/drivers/char/ipmi/ipmi_si_hardcode.c b/drivers/char/ipmi/ipmi_si_hardcode.c +index ed5e91b1e040..210644f3d863 100644 +--- a/drivers/char/ipmi/ipmi_si_hardcode.c ++++ b/drivers/char/ipmi/ipmi_si_hardcode.c +@@ -6,7 +6,7 @@ + #include + #include "ipmi_si.h" + #include "ipmi_plat_data.h" +- ++#include + /* + * There can be 4 IO ports passed in (with or without IRQs), 4 addresses, + * a default IO port, and 1 ACPI/SPMI address. That sets SI_MAX_DRIVERS. +@@ -90,6 +90,24 @@ static void __init ipmi_hardcode_init_one(const char *si_type_str, + ipmi_platform_add("hardcode-ipmi-si", i, &p); + } + ++#ifdef CONFIG_ARCH_SOPHGO ++static void variable_init(struct pci_dev *pdev) ++{ ++ unsigned long addr_data = pci_resource_start(pdev, 1) + 0x0e80; ++ // printk("addr_data=0x%lx\n", addr_data); ++ strcpy(si_type_str, "kcs"); ++ addrs[0] = addr_data; ++ num_addrs = 1; ++ regspacings[0] = 4; ++ num_regspacings = 1; ++ regsizes[0] = 4; ++ num_regsizes = 1; ++ irqs[0] = 0; ++ num_irqs = 1; ++ slave_addrs[0] = 0; ++ num_slave_addrs = 1; ++} ++#endif + void __init ipmi_hardcode_init(void) + { + unsigned int i; +@@ -97,7 +115,11 @@ void __init ipmi_hardcode_init(void) + char *si_type[SI_MAX_PARMS]; + + memset(si_type, 0, sizeof(si_type)); +- ++#ifdef CONFIG_ARCH_SOPHGO ++ struct pci_dev *pdev = pci_get_device(0x1A03, 0x2402, NULL); ++ if (pdev != NULL) ++ variable_init(pdev); ++#endif + /* Parse out the si_type string into its components. */ + str = si_type_str; + if (*str != '\0') { +diff --git a/drivers/char/ipmi/ipmi_si_intf.c b/drivers/char/ipmi/ipmi_si_intf.c +index 373ee71811e3..8e316d49bce1 100644 +--- a/drivers/char/ipmi/ipmi_si_intf.c ++++ b/drivers/char/ipmi/ipmi_si_intf.c +@@ -2158,7 +2158,8 @@ static int __init init_ipmi_si(void) + return 0; + } + } +-module_init(init_ipmi_si); ++// module_init(init_ipmi_si); ++late_initcall(init_ipmi_si); + + static void wait_msg_processed(struct smi_info *smi_info) + { +diff --git a/drivers/char/ipmi/ipmi_si_pci.c b/drivers/char/ipmi/ipmi_si_pci.c +index 74fa2055868b..6a935100e1ae 100644 +--- a/drivers/char/ipmi/ipmi_si_pci.c ++++ b/drivers/char/ipmi/ipmi_si_pci.c +@@ -111,6 +111,12 @@ static int ipmi_pci_probe(struct pci_dev *pdev, + io.regsize = DEFAULT_REGSIZE; + io.regshift = 0; + ++#ifdef CONFIG_ARCH_SOPHGO ++ io.addr_data = pci_resource_start(pdev, 1) + 0x0e80; ++ io.slave_addr = 0x20; ++ io.regspacing = 4; ++ io.regsize = 4; ++#endif + io.irq = pdev->irq; + if (io.irq) + io.irq_setup = ipmi_std_irq_setup; diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index c30099866174..1578cc32432d 100644 --- a/drivers/clk/Kconfig @@ -11110,7 +13041,7 @@ index 000000000000..99af0e6dae6a +} diff --git a/drivers/clk/sophgo/clk-mango.c b/drivers/clk/sophgo/clk-mango.c new file mode 100644 -index 000000000000..70e17f65c6fb +index 000000000000..894f2f177db8 --- /dev/null +++ b/drivers/clk/sophgo/clk-mango.c @@ -0,0 +1,977 @@ @@ -11349,7 +13280,7 @@ index 000000000000..70e17f65c6fb + { GATE_CLK_APB_GPIO, "clk_gate_apb_gpio", "clk_gate_top_axi0", + 0, 0x2000, 22, 0 }, + { GATE_CLK_APB_GPIO_INTR, "clk_gate_apb_gpio_intr", "clk_gate_top_axi0", -+ 0, 0x2000, 23, 0 }, ++ CLK_IS_CRITICAL, 0x2000, 23, 0 }, + { GATE_CLK_APB_I2C, "clk_gate_apb_i2c", "clk_gate_top_axi0", + 0, 0x2000, 26, 0 }, + { GATE_CLK_APB_WDT, "clk_gate_apb_wdt", "clk_gate_top_axi0", @@ -11373,21 +13304,21 @@ index 000000000000..70e17f65c6fb + { GATE_CLK_AXI_SD, "clk_gate_axi_sd", "clk_gate_top_axi_hsperi", + CLK_SET_RATE_PARENT, 0x2004, 5, 0 }, + { GATE_CLK_TIMER1, "clk_gate_timer1", "clk_div_timer1", -+ CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x2000, 12, 0 }, ++ CLK_SET_RATE_PARENT, 0x2000, 12, 0 }, + { GATE_CLK_TIMER2, "clk_gate_timer2", "clk_div_timer2", -+ CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x2000, 13, 0 }, ++ CLK_SET_RATE_PARENT, 0x2000, 13, 0 }, + { GATE_CLK_TIMER3, "clk_gate_timer3", "clk_div_timer3", -+ CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x2000, 14, 0 }, ++ CLK_SET_RATE_PARENT, 0x2000, 14, 0 }, + { GATE_CLK_TIMER4, "clk_gate_timer4", "clk_div_timer4", -+ CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x2000, 15, 0 }, ++ CLK_SET_RATE_PARENT, 0x2000, 15, 0 }, + { GATE_CLK_TIMER5, "clk_gate_timer5", "clk_div_timer5", -+ CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x2000, 16, 0 }, ++ CLK_SET_RATE_PARENT, 0x2000, 16, 0 }, + { GATE_CLK_TIMER6, "clk_gate_timer6", "clk_div_timer6", -+ CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x2000, 17, 0 }, ++ CLK_SET_RATE_PARENT, 0x2000, 17, 0 }, + { GATE_CLK_TIMER7, "clk_gate_timer7", "clk_div_timer7", -+ CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x2000, 18, 0 }, ++ CLK_SET_RATE_PARENT, 0x2000, 18, 0 }, + { GATE_CLK_TIMER8, "clk_gate_timer8", "clk_div_timer8", -+ CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x2000, 19, 0 }, ++ CLK_SET_RATE_PARENT, 0x2000, 19, 0 }, + { GATE_CLK_100K_EMMC, "clk_gate_100k_emmc", "clk_div_100k_emmc", + CLK_SET_RATE_PARENT, 0x2004, 4, 0 }, + { GATE_CLK_100K_SD, "clk_gate_100k_sd", "clk_div_100k_sd", @@ -11655,7 +13586,7 @@ index 000000000000..70e17f65c6fb + { GATE_CLK_APB_GPIO, "s1_clk_gate_apb_gpio", "s1_clk_gate_top_axi0", + 0, 0x2000, 22, 0 }, + { GATE_CLK_APB_GPIO_INTR, "s1_clk_gate_apb_gpio_intr", "s1_clk_gate_top_axi0", -+ 0, 0x2000, 23, 0 }, ++ CLK_IS_CRITICAL, 0x2000, 23, 0 }, + { GATE_CLK_APB_I2C, "s1_clk_gate_apb_i2c", "s1_clk_gate_top_axi0", + 0, 0x2000, 26, 0 }, + { GATE_CLK_APB_WDT, "s1_clk_gate_apb_wdt", "s1_clk_gate_top_axi0", @@ -11679,21 +13610,21 @@ index 000000000000..70e17f65c6fb + { GATE_CLK_AXI_SD, "s1_clk_gate_axi_sd", "s1_clk_gate_top_axi_hsperi", + CLK_SET_RATE_PARENT, 0x2004, 5, 0 }, + { GATE_CLK_TIMER1, "s1_clk_gate_timer1", "s1_clk_div_timer1", -+ CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x2000, 12, 0 }, ++ CLK_SET_RATE_PARENT, 0x2000, 12, 0 }, + { GATE_CLK_TIMER2, "s1_clk_gate_timer2", "s1_clk_div_timer2", -+ CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x2000, 13, 0 }, ++ CLK_SET_RATE_PARENT, 0x2000, 13, 0 }, + { GATE_CLK_TIMER3, "s1_clk_gate_timer3", "s1_clk_div_timer3", -+ CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x2000, 14, 0 }, ++ CLK_SET_RATE_PARENT, 0x2000, 14, 0 }, + { GATE_CLK_TIMER4, "s1_clk_gate_timer4", "s1_clk_div_timer4", -+ CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x2000, 15, 0 }, ++ CLK_SET_RATE_PARENT, 0x2000, 15, 0 }, + { GATE_CLK_TIMER5, "s1_clk_gate_timer5", "s1_clk_div_timer5", -+ CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x2000, 16, 0 }, ++ CLK_SET_RATE_PARENT, 0x2000, 16, 0 }, + { GATE_CLK_TIMER6, "s1_clk_gate_timer6", "s1_clk_div_timer6", -+ CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x2000, 17, 0 }, ++ CLK_SET_RATE_PARENT, 0x2000, 17, 0 }, + { GATE_CLK_TIMER7, "s1_clk_gate_timer7", "s1_clk_div_timer7", -+ CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x2000, 18, 0 }, ++ CLK_SET_RATE_PARENT, 0x2000, 18, 0 }, + { GATE_CLK_TIMER8, "s1_clk_gate_timer8", "s1_clk_div_timer8", -+ CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x2000, 19, 0 }, ++ CLK_SET_RATE_PARENT, 0x2000, 19, 0 }, + { GATE_CLK_100K_EMMC, "s1_clk_gate_100k_emmc", "s1_clk_div_100k_emmc", + CLK_SET_RATE_PARENT, 0x2004, 4, 0 }, + { GATE_CLK_100K_SD, "s1_clk_gate_100k_sd", "s1_clk_div_100k_sd", @@ -15847,6 +17778,51 @@ index 000000000000..78613188da70 +MODULE_AUTHOR("wei.liu "); +MODULE_DESCRIPTION("Thead Light Fullmask vpsys clock gate provider"); +MODULE_LICENSE("GPL v2"); +diff --git a/drivers/clocksource/dw_apb_timer_of.c b/drivers/clocksource/dw_apb_timer_of.c +index 3245eb0c602d..1ef476b80044 100644 +--- a/drivers/clocksource/dw_apb_timer_of.c ++++ b/drivers/clocksource/dw_apb_timer_of.c +@@ -107,9 +107,30 @@ static int __init add_clockevent(struct device_node *event_timer) + return 0; + } + ++#ifdef CONFIG_SOPHGO_MULTI_CHIP_CLOCK_SYNC ++void __iomem *sched_io_base; ++EXPORT_SYMBOL_GPL(sched_io_base); ++static struct dw_apb_clocksource *cs_g; ++#else + static void __iomem *sched_io_base; ++#endif + static u32 sched_rate; + ++#ifdef CONFIG_SOPHGO_MULTI_CHIP_CLOCK_SYNC ++u64 dw_timer_read_counter(void) ++{ ++ return ~readl_relaxed(sched_io_base); ++} ++EXPORT_SYMBOL_GPL(dw_timer_read_counter); ++ ++void dw_cs_get_mult_shift(u32 *mult, u32 *shift) ++{ ++ *mult = cs_g->cs.mult; ++ *shift = cs_g->cs.shift; ++} ++EXPORT_SYMBOL_GPL(dw_cs_get_mult_shift); ++#endif ++ + static int __init add_clocksource(struct device_node *source_timer) + { + void __iomem *iobase; +@@ -135,6 +156,9 @@ static int __init add_clocksource(struct device_node *source_timer) + */ + sched_io_base = iobase + 0x04; + sched_rate = rate; ++#ifdef CONFIG_SOPHGO_MULTI_CHIP_CLOCK_SYNC ++ cs_g = cs; ++#endif + + return 0; + } diff --git a/drivers/cpufreq/Kconfig b/drivers/cpufreq/Kconfig index d1fdea27eb0d..4c67dd5991d1 100644 --- a/drivers/cpufreq/Kconfig @@ -17416,6 +19392,66 @@ index 062d78818da1..57fc15a0d2df 100644 if (!IS_ENABLED(CONFIG_PHYS_ADDR_T_64BIT)) return 0; +diff --git a/drivers/gpu/drm/amd/display/Kconfig b/drivers/gpu/drm/amd/display/Kconfig +index 901d1961b739..90489b55efa7 100644 +--- a/drivers/gpu/drm/amd/display/Kconfig ++++ b/drivers/gpu/drm/amd/display/Kconfig +@@ -9,6 +9,7 @@ config DRM_AMD_DC + select SND_HDA_COMPONENT if SND_HDA_CORE + # !CC_IS_CLANG: https://github.com/ClangBuiltLinux/linux/issues/1752 + select DRM_AMD_DC_FP if (X86 || LOONGARCH || (PPC64 && ALTIVEC) || (ARM64 && KERNEL_MODE_NEON && !CC_IS_CLANG)) ++ select DRM_AMD_DC_DCN if RISCV && FPU + help + Choose this option if you want to use the new display engine + support for AMDGPU. This adds required support for Vega and +diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/dc_fpu.c b/drivers/gpu/drm/amd/display/amdgpu_dm/dc_fpu.c +index 172aa10a8800..53a7122ba98d 100644 +--- a/drivers/gpu/drm/amd/display/amdgpu_dm/dc_fpu.c ++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/dc_fpu.c +@@ -35,6 +35,8 @@ + #include + #elif defined(CONFIG_LOONGARCH) + #include ++#elif defined(CONFIG_RISCV) ++#include + #endif + + /** +@@ -90,7 +92,7 @@ void dc_fpu_begin(const char *function_name, const int line) + *pcpu += 1; + + if (*pcpu == 1) { +-#if defined(CONFIG_X86) || defined(CONFIG_LOONGARCH) ++#if defined(CONFIG_X86) || defined(CONFIG_LOONGARCH) || defined(CONFIG_RISCV) + migrate_disable(); + kernel_fpu_begin(); + #elif defined(CONFIG_PPC64) +@@ -130,7 +132,7 @@ void dc_fpu_end(const char *function_name, const int line) + pcpu = get_cpu_ptr(&fpu_recursion_depth); + *pcpu -= 1; + if (*pcpu <= 0) { +-#if defined(CONFIG_X86) || defined(CONFIG_LOONGARCH) ++#if defined(CONFIG_X86) || defined(CONFIG_LOONGARCH) || defined(CONFIG_RISCV) + kernel_fpu_end(); + migrate_enable(); + #elif defined(CONFIG_PPC64) +diff --git a/drivers/gpu/drm/amd/display/dc/dml/Makefile b/drivers/gpu/drm/amd/display/dc/dml/Makefile +index 0ba9a7997d56..abd04d13997d 100644 +--- a/drivers/gpu/drm/amd/display/dc/dml/Makefile ++++ b/drivers/gpu/drm/amd/display/dc/dml/Makefile +@@ -43,6 +43,12 @@ dml_ccflags := -mfpu=64 + dml_rcflags := -msoft-float + endif + ++ifdef CONFIG_RISCV ++include $(srctree)/arch/riscv/Makefile.isa ++# Remove V from the ISA string, like in arch/riscv/Makefile, but keep F and D. ++dml_ccflags := -march=$(subst v0p7,,$(riscv-march-y)) ++endif ++ + ifdef CONFIG_CC_IS_GCC + ifneq ($(call gcc-min-version, 70100),y) + IS_OLD_GCC = 1 diff --git a/drivers/gpu/drm/drm_gem_vram_helper.c b/drivers/gpu/drm/drm_gem_vram_helper.c index b67eafa55715..5ebe418bd383 100644 --- a/drivers/gpu/drm/drm_gem_vram_helper.c @@ -17429,6 +19465,32 @@ index b67eafa55715..5ebe418bd383 100644 if (ret < 0) goto err_ttm_tt_init; +diff --git a/drivers/gpu/drm/radeon/radeon_drv.c b/drivers/gpu/drm/radeon/radeon_drv.c +index 7bf08164140e..b0476feba79c 100644 +--- a/drivers/gpu/drm/radeon/radeon_drv.c ++++ b/drivers/gpu/drm/radeon/radeon_drv.c +@@ -36,6 +36,7 @@ + #include + #include + #include ++#include + + #include + #include +@@ -336,10 +337,10 @@ radeon_pci_remove(struct pci_dev *pdev) + static void + radeon_pci_shutdown(struct pci_dev *pdev) + { +- /* if we are running in a VM, make sure the device +- * torn down properly on reboot/shutdown ++ /* if we are running in a VM or kexec another kernel, ++ * make sure the device torn down properly on reboot/shutdown + */ +- if (radeon_device_is_virtual()) ++ if (radeon_device_is_virtual() || kexec_in_progress) + radeon_pci_remove(pdev); + + #if defined(CONFIG_PPC64) || defined(CONFIG_MACH_LOONGSON64) diff --git a/drivers/gpu/drm/radeon/radeon_irq_kms.c b/drivers/gpu/drm/radeon/radeon_irq_kms.c index c4dda908666c..33b56ca7af6f 100644 --- a/drivers/gpu/drm/radeon/radeon_irq_kms.c @@ -19615,6 +21677,544 @@ index f219bdea8f28..149e699aac92 100644 +#endif #endif /* __SDHCI_HW_H */ +diff --git a/drivers/mtd/spi-nor/controllers/Kconfig b/drivers/mtd/spi-nor/controllers/Kconfig +index ca45dcd3ffe8..d2138370f1fc 100644 +--- a/drivers/mtd/spi-nor/controllers/Kconfig ++++ b/drivers/mtd/spi-nor/controllers/Kconfig +@@ -16,3 +16,14 @@ config SPI_NXP_SPIFI + SPIFI is a specialized controller for connecting serial SPI + Flash. Enable this option if you have a device with a SPIFI + controller and want to access the Flash as a mtd device. ++ ++config SPI_SOPHGO_SPIFMC ++ tristate "Sophgo SPI Flash Master Controller (SPIFMC)" ++ depends on ARCH_SOPHGO || COMPILE_TEST ++ depends on HAS_IOMEM ++ help ++ Enable support for the Sophgo SPI Flash Master controller. ++ ++ SPIFMC is a master controller to control serial SPI Flash. ++ Enable this option if you have a device with a SPIFMC controller ++ and want to access the Flash as a mtd device. +diff --git a/drivers/mtd/spi-nor/controllers/Makefile b/drivers/mtd/spi-nor/controllers/Makefile +index 0b8e1d530913..627ac8850ab1 100644 +--- a/drivers/mtd/spi-nor/controllers/Makefile ++++ b/drivers/mtd/spi-nor/controllers/Makefile +@@ -1,3 +1,4 @@ + # SPDX-License-Identifier: GPL-2.0 + obj-$(CONFIG_SPI_HISI_SFC) += hisi-sfc.o + obj-$(CONFIG_SPI_NXP_SPIFI) += nxp-spifi.o ++obj-$(CONFIG_SPI_SOPHGO_SPIFMC) += sophgo-spifmc.o +diff --git a/drivers/mtd/spi-nor/controllers/sophgo-spifmc.c b/drivers/mtd/spi-nor/controllers/sophgo-spifmc.c +new file mode 100644 +index 000000000000..f7d85cc03137 +--- /dev/null ++++ b/drivers/mtd/spi-nor/controllers/sophgo-spifmc.c +@@ -0,0 +1,445 @@ ++// SPDX-License-Identifier: GPL-2.0-or-later ++/* ++ * SPI Flash Master Controller (SPIFMC) ++ * ++ * Copyright (c) 2023 Sophgo. ++ */ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++/* Hardware register definitions */ ++#define SPIFMC_CTRL 0x00 ++#define SPIFMC_CTRL_CPHA BIT(12) ++#define SPIFMC_CTRL_CPOL BIT(13) ++#define SPIFMC_CTRL_HOLD_OL BIT(14) ++#define SPIFMC_CTRL_WP_OL BIT(15) ++#define SPIFMC_CTRL_LSBF BIT(20) ++#define SPIFMC_CTRL_SRST BIT(21) ++#define SPIFMC_CTRL_SCK_DIV_SHIFT 0 ++#define SPIFMC_CTRL_FRAME_LEN_SHIFT 16 ++ ++#define SPIFMC_CE_CTRL 0x04 ++#define SPIFMC_CE_CTRL_CEMANUAL BIT(0) ++#define SPIFMC_CE_CTRL_CEMANUAL_EN BIT(1) ++ ++#define SPIFMC_DLY_CTRL 0x08 ++#define SPIFMC_CTRL_FM_INTVL_MASK 0x000f ++#define SPIFMC_CTRL_FM_INTVL BIT(0) ++#define SPIFMC_CTRL_CET_MASK 0x0f00 ++#define SPIFMC_CTRL_CET BIT(8) ++ ++#define SPIFMC_DMMR 0x0c ++ ++#define SPIFMC_TRAN_CSR 0x10 ++#define SPIFMC_TRAN_CSR_TRAN_MODE_MASK 0x0003 ++#define SPIFMC_TRAN_CSR_TRAN_MODE_RX BIT(0) ++#define SPIFMC_TRAN_CSR_TRAN_MODE_TX BIT(1) ++#define SPIFMC_TRAN_CSR_CNTNS_READ BIT(2) ++#define SPIFMC_TRAN_CSR_FAST_MODE BIT(3) ++#define SPIFMC_TRAN_CSR_BUS_WIDTH_1_BIT (0x00 << 4) ++#define SPIFMC_TRAN_CSR_BUS_WIDTH_2_BIT (0x01 << 4) ++#define SPIFMC_TRAN_CSR_BUS_WIDTH_4_BIT (0x02 << 4) ++#define SPIFMC_TRAN_CSR_DMA_EN BIT(6) ++#define SPIFMC_TRAN_CSR_MISO_LEVEL BIT(7) ++#define SPIFMC_TRAN_CSR_ADDR_BYTES_MASK 0x0700 ++#define SPIFMC_TRAN_CSR_ADDR_BYTES_SHIFT 8 ++#define SPIFMC_TRAN_CSR_WITH_CMD BIT(11) ++#define SPIFMC_TRAN_CSR_FIFO_TRG_LVL_MASK 0x3000 ++#define SPIFMC_TRAN_CSR_FIFO_TRG_LVL_1_BYTE (0x00 << 12) ++#define SPIFMC_TRAN_CSR_FIFO_TRG_LVL_2_BYTE (0x01 << 12) ++#define SPIFMC_TRAN_CSR_FIFO_TRG_LVL_4_BYTE (0x02 << 12) ++#define SPIFMC_TRAN_CSR_FIFO_TRG_LVL_8_BYTE (0x03 << 12) ++#define SPIFMC_TRAN_CSR_GO_BUSY BIT(15) ++ ++#define SPIFMC_TRAN_NUM 0x14 ++#define SPIFMC_FIFO_PORT 0x18 ++#define SPIFMC_FIFO_PT 0x20 ++ ++#define SPIFMC_INT_STS 0x28 ++#define SPIFMC_INT_TRAN_DONE BIT(0) ++#define SPIFMC_INT_RD_FIFO BIT(2) ++#define SPIFMC_INT_WR_FIFO BIT(3) ++#define SPIFMC_INT_RX_FRAME BIT(4) ++#define SPIFMC_INT_TX_FRAME BIT(5) ++ ++#define SPIFMC_INT_EN 0x2c ++#define SPIFMC_INT_TRAN_DONE_EN BIT(0) ++#define SPIFMC_INT_RD_FIFO_EN BIT(2) ++#define SPIFMC_INT_WR_FIFO_EN BIT(3) ++#define SPIFMC_INT_RX_FRAME_EN BIT(4) ++#define SPIFMC_INT_TX_FRAME_EN BIT(5) ++ ++#define SPIFMC_MAX_FIFO_DEPTH 8 ++ ++struct sophgo_spifmc { ++ struct device *dev; ++ struct clk *clk; ++ void __iomem *io_base; ++ struct spi_nor nor; ++}; ++ ++static inline int sophgo_spifmc_wait_int(struct sophgo_spifmc *spifmc, ++ u8 int_type) ++{ ++ u32 stat; ++ ++ return readl_poll_timeout(spifmc->io_base + SPIFMC_INT_STS, stat, ++ (stat & int_type), 0, 0); ++} ++ ++static inline u32 sophgo_spifmc_init_reg(struct sophgo_spifmc *spifmc) ++{ ++ u32 reg; ++ ++ reg = readl(spifmc->io_base + SPIFMC_TRAN_CSR); ++ reg &= ~(SPIFMC_TRAN_CSR_TRAN_MODE_MASK ++ | SPIFMC_TRAN_CSR_CNTNS_READ ++ | SPIFMC_TRAN_CSR_FAST_MODE ++ | SPIFMC_TRAN_CSR_BUS_WIDTH_2_BIT ++ | SPIFMC_TRAN_CSR_BUS_WIDTH_4_BIT ++ | SPIFMC_TRAN_CSR_DMA_EN ++ | SPIFMC_TRAN_CSR_ADDR_BYTES_MASK ++ | SPIFMC_TRAN_CSR_WITH_CMD ++ | SPIFMC_TRAN_CSR_FIFO_TRG_LVL_MASK); ++ ++ return reg; ++} ++ ++/* ++ * sophgo_spifmc_read_reg is a workaround function: ++ * AHB bus could only do 32-bit access to SPIFMC fifo, ++ * so cmd without 3-byte addr will leave 3-byte data in fifo. ++ * Set TX to mark that these 3-byte data would be sent out. ++ */ ++static int sophgo_spifmc_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf, ++ size_t len) ++{ ++ struct sophgo_spifmc *spifmc = nor->priv; ++ u32 reg; ++ int ret, i; ++ ++ reg = sophgo_spifmc_init_reg(spifmc); ++ reg |= SPIFMC_TRAN_CSR_BUS_WIDTH_1_BIT; ++ reg |= SPIFMC_TRAN_CSR_FIFO_TRG_LVL_1_BYTE; ++ reg |= SPIFMC_TRAN_CSR_WITH_CMD; ++ reg |= SPIFMC_TRAN_CSR_TRAN_MODE_RX | SPIFMC_TRAN_CSR_TRAN_MODE_TX; ++ writel(0, spifmc->io_base + SPIFMC_FIFO_PT); ++ writeb(opcode, spifmc->io_base + SPIFMC_FIFO_PORT); ++ ++ for (i = 0; i < len; i++) ++ writeb(0, spifmc->io_base + SPIFMC_FIFO_PORT); ++ ++ writel(0, spifmc->io_base + SPIFMC_INT_STS); ++ writel(len, spifmc->io_base + SPIFMC_TRAN_NUM); ++ reg |= SPIFMC_TRAN_CSR_GO_BUSY; ++ writel(reg, spifmc->io_base + SPIFMC_TRAN_CSR); ++ ++ ret = sophgo_spifmc_wait_int(spifmc, SPIFMC_INT_TRAN_DONE); ++ if (ret) ++ return ret; ++ ++ while (len--) ++ *buf++ = readb(spifmc->io_base + SPIFMC_FIFO_PORT); ++ ++ writel(0, spifmc->io_base + SPIFMC_FIFO_PT); ++ ++ return 0; ++} ++ ++static int sophgo_spifmc_write_reg(struct spi_nor *nor, u8 opcode, ++ const u8 *buf, size_t len) ++{ ++ struct sophgo_spifmc *spifmc = nor->priv; ++ u32 reg; ++ int i; ++ ++ reg = sophgo_spifmc_init_reg(spifmc); ++ reg |= SPIFMC_TRAN_CSR_FIFO_TRG_LVL_1_BYTE; ++ reg |= SPIFMC_TRAN_CSR_WITH_CMD; ++ ++ /* ++ * If write values to the Status Register, ++ * configure TRAN_CSR register as the same as sophgo_spifmc_read_reg. ++ */ ++ if (opcode == SPINOR_OP_WRSR) { ++ reg |= SPIFMC_TRAN_CSR_TRAN_MODE_RX | SPIFMC_TRAN_CSR_TRAN_MODE_TX; ++ writel(len, spifmc->io_base + SPIFMC_TRAN_NUM); ++ } ++ ++ writel(0, spifmc->io_base + SPIFMC_FIFO_PT); ++ writeb(opcode, spifmc->io_base + SPIFMC_FIFO_PORT); ++ ++ for (i = 0; i < len; i++) ++ writeb(buf[i], spifmc->io_base + SPIFMC_FIFO_PORT); ++ ++ writel(0, spifmc->io_base + SPIFMC_INT_STS); ++ reg |= SPIFMC_TRAN_CSR_GO_BUSY; ++ writel(reg, spifmc->io_base + SPIFMC_TRAN_CSR); ++ sophgo_spifmc_wait_int(spifmc, SPIFMC_INT_TRAN_DONE); ++ writel(0, spifmc->io_base + SPIFMC_FIFO_PT); ++ ++ return 0; ++} ++ ++static ssize_t sophgo_spifmc_read(struct spi_nor *nor, loff_t from, ++ size_t len, u_char *buf) ++{ ++ struct sophgo_spifmc *spifmc = nor->priv; ++ u32 reg; ++ int xfer_size, offset; ++ int i; ++ ++ reg = sophgo_spifmc_init_reg(spifmc); ++ reg |= (nor->addr_nbytes) << SPIFMC_TRAN_CSR_ADDR_BYTES_SHIFT; ++ reg |= SPIFMC_TRAN_CSR_FIFO_TRG_LVL_8_BYTE; ++ reg |= SPIFMC_TRAN_CSR_WITH_CMD; ++ reg |= SPIFMC_TRAN_CSR_TRAN_MODE_RX; ++ writel(0, spifmc->io_base + SPIFMC_FIFO_PT); ++ writeb(nor->read_opcode, spifmc->io_base + SPIFMC_FIFO_PORT); ++ ++ for (i = nor->addr_nbytes - 1; i >= 0; i--) ++ writeb((from >> i * 8) & 0xff, spifmc->io_base + SPIFMC_FIFO_PORT); ++ ++ writel(0, spifmc->io_base + SPIFMC_INT_STS); ++ writel(len, spifmc->io_base + SPIFMC_TRAN_NUM); ++ reg |= SPIFMC_TRAN_CSR_GO_BUSY; ++ writel(reg, spifmc->io_base + SPIFMC_TRAN_CSR); ++ sophgo_spifmc_wait_int(spifmc, SPIFMC_INT_RD_FIFO); ++ ++ offset = 0; ++ while (offset < len) { ++ xfer_size = min_t(size_t, SPIFMC_MAX_FIFO_DEPTH, len - offset); ++ ++ while ((readl(spifmc->io_base + SPIFMC_FIFO_PT) & 0xf) != xfer_size) ++ ; ++ ++ for (i = 0; i < xfer_size; i++) ++ buf[i + offset] = readb(spifmc->io_base + SPIFMC_FIFO_PORT); ++ ++ offset += xfer_size; ++ } ++ ++ sophgo_spifmc_wait_int(spifmc, SPIFMC_INT_TRAN_DONE); ++ writel(0, spifmc->io_base + SPIFMC_FIFO_PT); ++ ++ return len; ++} ++ ++static ssize_t sophgo_spifmc_write(struct spi_nor *nor, loff_t to, ++ size_t len, const u_char *buf) ++{ ++ struct sophgo_spifmc *spifmc = nor->priv; ++ u32 reg; ++ int i, offset; ++ int xfer_size, wait; ++ ++ reg = sophgo_spifmc_init_reg(spifmc); ++ reg |= nor->addr_nbytes << SPIFMC_TRAN_CSR_ADDR_BYTES_SHIFT; ++ reg |= SPIFMC_TRAN_CSR_FIFO_TRG_LVL_8_BYTE; ++ reg |= SPIFMC_TRAN_CSR_WITH_CMD; ++ reg |= SPIFMC_TRAN_CSR_TRAN_MODE_TX; ++ writel(0, spifmc->io_base + SPIFMC_FIFO_PT); ++ writeb(nor->program_opcode, spifmc->io_base + SPIFMC_FIFO_PORT); ++ ++ for (i = nor->addr_nbytes - 1; i >= 0; i--) ++ writeb((to >> i * 8) & 0xff, spifmc->io_base + SPIFMC_FIFO_PORT); ++ ++ writel(0, spifmc->io_base + SPIFMC_INT_STS); ++ writel(len, spifmc->io_base + SPIFMC_TRAN_NUM); ++ reg |= SPIFMC_TRAN_CSR_GO_BUSY; ++ writel(reg, spifmc->io_base + SPIFMC_TRAN_CSR); ++ ++ while ((readl(spifmc->io_base + SPIFMC_FIFO_PT) & 0xf) != 0) ++ ; ++ ++ writel(0, spifmc->io_base + SPIFMC_FIFO_PT); ++ ++ offset = 0; ++ while (offset < len) { ++ xfer_size = min_t(size_t, SPIFMC_MAX_FIFO_DEPTH, len - offset); ++ ++ wait = 0; ++ while ((readl(spifmc->io_base + SPIFMC_FIFO_PT) & 0xf) != 0) { ++ wait++; ++ udelay(10); ++ if (wait > 30000) { ++ dev_warn(spifmc->dev, "Wait to write FIFO timeout.\n"); ++ return -1; ++ } ++ } ++ ++ for (i = 0; i < xfer_size; i++) ++ writeb(buf[i + offset], spifmc->io_base + SPIFMC_FIFO_PORT); ++ ++ offset += xfer_size; ++ } ++ ++ sophgo_spifmc_wait_int(spifmc, SPIFMC_INT_TRAN_DONE); ++ writel(0, spifmc->io_base + SPIFMC_FIFO_PT); ++ ++ return len; ++} ++ ++static int sophgo_spifmc_erase(struct spi_nor *nor, loff_t offs) ++{ ++ struct sophgo_spifmc *spifmc = nor->priv; ++ u32 reg; ++ int i; ++ ++ reg = sophgo_spifmc_init_reg(spifmc); ++ reg |= nor->addr_nbytes << SPIFMC_TRAN_CSR_ADDR_BYTES_SHIFT; ++ reg |= SPIFMC_TRAN_CSR_FIFO_TRG_LVL_1_BYTE; ++ reg |= SPIFMC_TRAN_CSR_WITH_CMD; ++ writel(0, spifmc->io_base + SPIFMC_FIFO_PT); ++ writeb(nor->erase_opcode, spifmc->io_base + SPIFMC_FIFO_PORT); ++ ++ for (i = nor->addr_nbytes - 1; i >= 0; i--) ++ writeb((offs >> i * 8) & 0xff, spifmc->io_base + SPIFMC_FIFO_PORT); ++ ++ writel(0, spifmc->io_base + SPIFMC_INT_STS); ++ reg |= SPIFMC_TRAN_CSR_GO_BUSY; ++ writel(reg, spifmc->io_base + SPIFMC_TRAN_CSR); ++ sophgo_spifmc_wait_int(spifmc, SPIFMC_INT_TRAN_DONE); ++ writel(0, spifmc->io_base + SPIFMC_FIFO_PT); ++ ++ return 0; ++} ++ ++static const struct spi_nor_controller_ops sophgo_spifmc_controller_ops = { ++ .read_reg = sophgo_spifmc_read_reg, ++ .write_reg = sophgo_spifmc_write_reg, ++ .read = sophgo_spifmc_read, ++ .write = sophgo_spifmc_write, ++ .erase = sophgo_spifmc_erase, ++}; ++ ++static void sophgo_spifmc_init(struct sophgo_spifmc *spifmc) ++{ ++ u32 reg; ++ ++ /* disable DMMR (Direct Memory Mapping Read) */ ++ writel(0, spifmc->io_base + SPIFMC_DMMR); ++ /* soft reset */ ++ writel(readl(spifmc->io_base + SPIFMC_CTRL) | SPIFMC_CTRL_SRST | 0x3, ++ spifmc->io_base + SPIFMC_CTRL); ++ /* hardware CE contrl, soft reset cannot change the register */ ++ writel(0, spifmc->io_base + SPIFMC_CE_CTRL); ++ reg = spifmc->nor.addr_nbytes << SPIFMC_TRAN_CSR_ADDR_BYTES_SHIFT; ++ reg |= SPIFMC_TRAN_CSR_FIFO_TRG_LVL_4_BYTE; ++ reg |= SPIFMC_TRAN_CSR_WITH_CMD; ++ writel(reg, spifmc->io_base + SPIFMC_TRAN_CSR); ++} ++ ++static int sophgo_spifmc_register(struct device_node *np, ++ struct sophgo_spifmc *spifmc) ++{ ++ /* TODO: support DUAL and QUAD operations */ ++ const struct spi_nor_hwcaps hwcaps = { ++ .mask = SNOR_HWCAPS_READ | ++ SNOR_HWCAPS_PP, ++ }; ++ int ret; ++ ++ spifmc->nor.dev = spifmc->dev; ++ spi_nor_set_flash_node(&spifmc->nor, np); ++ spifmc->nor.priv = spifmc; ++ spifmc->nor.controller_ops = &sophgo_spifmc_controller_ops; ++ ++ ret = spi_nor_scan(&spifmc->nor, NULL, &hwcaps); ++ if (ret) { ++ dev_err(spifmc->dev, "Device scan failed.\n"); ++ return ret; ++ } ++ ++ ret = mtd_device_register(&spifmc->nor.mtd, NULL, 0); ++ if (ret) { ++ dev_err(spifmc->dev, "mtd device parse failed.\n"); ++ return ret; ++ } ++ ++ return 0; ++} ++ ++static int sophgo_spifmc_probe(struct platform_device *pdev) ++{ ++ struct device_node *np; ++ struct sophgo_spifmc *spifmc; ++ int ret; ++ ++ spifmc = devm_kzalloc(&pdev->dev, sizeof(*spifmc), GFP_KERNEL); ++ if (!spifmc) ++ return -ENOMEM; ++ ++ spifmc->io_base = devm_platform_ioremap_resource_byname(pdev, "memory"); ++ if (IS_ERR(spifmc->io_base)) ++ return PTR_ERR(spifmc->io_base); ++ ++ spifmc->clk = devm_clk_get(&pdev->dev, NULL); ++ if (IS_ERR(spifmc->clk)) { ++ dev_err(&pdev->dev, "AHB clock not found.\n"); ++ return PTR_ERR(spifmc->clk); ++ } ++ ++ ret = clk_prepare_enable(spifmc->clk); ++ if (ret) { ++ dev_err(&pdev->dev, "Unable to enable AHB clock.\n"); ++ return ret; ++ } ++ ++ spifmc->dev = &pdev->dev; ++ platform_set_drvdata(pdev, spifmc); ++ sophgo_spifmc_init(spifmc); ++ ++ np = of_get_next_available_child(pdev->dev.of_node, NULL); ++ if (!np) { ++ dev_err(&pdev->dev, "No SPI flash device to configure.\n"); ++ ret = -ENODEV; ++ goto fail; ++ } ++ ++ ret = sophgo_spifmc_register(np, spifmc); ++ of_node_put(np); ++ if (ret) { ++ dev_err(&pdev->dev, "Unable to register spifmc.\n"); ++ goto fail; ++ } ++ ++ return ret; ++fail: ++ clk_disable_unprepare(spifmc->clk); ++ return ret; ++} ++ ++static int sophgo_spifmc_remove(struct platform_device *pdev) ++{ ++ struct sophgo_spifmc *spifmc = platform_get_drvdata(pdev); ++ ++ mtd_device_unregister(&spifmc->nor.mtd); ++ clk_disable_unprepare(spifmc->clk); ++ ++ return 0; ++} ++ ++static const struct of_device_id sophgo_spifmc_match[] = { ++ {.compatible = "sophgo,spifmc"}, ++ { /* sentinel */ } ++}; ++MODULE_DEVICE_TABLE(of, sophgo_spifmc_match); ++ ++static struct platform_driver sophgo_spifmc_driver = { ++ .probe = sophgo_spifmc_probe, ++ .remove = sophgo_spifmc_remove, ++ .driver = { ++ .name = "sophgo-spifmc", ++ .of_match_table = sophgo_spifmc_match, ++ }, ++}; ++module_platform_driver(sophgo_spifmc_driver); ++ ++MODULE_DESCRIPTION("Sophgo SPI Flash Master Controller Driver"); ++MODULE_LICENSE("GPL v2"); +diff --git a/drivers/mtd/spi-nor/gigadevice.c b/drivers/mtd/spi-nor/gigadevice.c +index d57ddaf1525b..c60656702063 100644 +--- a/drivers/mtd/spi-nor/gigadevice.c ++++ b/drivers/mtd/spi-nor/gigadevice.c +@@ -33,6 +33,15 @@ static const struct spi_nor_fixups gd25q256_fixups = { + .post_bfpt = gd25q256_post_bfpt, + }; + ++static void gd25lb512me_default_init(struct spi_nor *nor) ++{ ++ nor->params->quad_enable = spi_nor_sr1_bit6_quad_enable; ++} ++ ++static const struct spi_nor_fixups gd25lb512me_fixups = { ++ .default_init = gd25lb512me_default_init, ++}; ++ + static const struct flash_info gigadevice_nor_parts[] = { + { "gd25q16", INFO(0xc84015, 0, 64 * 1024, 32) + FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) +@@ -67,6 +76,11 @@ static const struct flash_info gigadevice_nor_parts[] = { + FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_TB_SR_BIT6) + FIXUP_FLAGS(SPI_NOR_4B_OPCODES) + .fixups = &gd25q256_fixups }, ++ { "gd25lb512me", INFO(0xc8671a, 0, 64 * 1024, 1024) ++ FLAGS(SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) ++ NO_SFDP_FLAGS(SECT_4K | SPI_NOR_QUAD_READ) ++ FIXUP_FLAGS(SPI_NOR_4B_OPCODES) ++ .fixups = &gd25lb512me_fixups }, + }; + + const struct spi_nor_manufacturer spi_nor_gigadevice = { +diff --git a/drivers/net/ethernet/intel/i40e/i40e_common.c b/drivers/net/ethernet/intel/i40e/i40e_common.c +index 4d7caa119971..0a9efd8c6471 100644 +--- a/drivers/net/ethernet/intel/i40e/i40e_common.c ++++ b/drivers/net/ethernet/intel/i40e/i40e_common.c +@@ -3213,7 +3213,8 @@ static void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff, + p->base_queue = phys_id; + break; + case I40E_AQ_CAP_ID_MSIX: +- p->num_msix_vectors = number; ++ //p->num_msix_vectors = number; ++ p->num_msix_vectors = 8; + i40e_debug(hw, I40E_DEBUG_INIT, + "HW Capability: MSIX vector count = %d\n", + p->num_msix_vectors); +diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_type.h b/drivers/net/ethernet/intel/ixgbe/ixgbe_type.h +index 61b9774b3d31..1b18fa4eb082 100644 +--- a/drivers/net/ethernet/intel/ixgbe/ixgbe_type.h ++++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_type.h +@@ -2069,7 +2069,7 @@ enum { + #define IXGBE_DEVICE_CAPS 0x2C + #define IXGBE_SERIAL_NUMBER_MAC_ADDR 0x11 + #define IXGBE_PCIE_MSIX_82599_CAPS 0x72 +-#define IXGBE_MAX_MSIX_VECTORS_82599 0x40 ++#define IXGBE_MAX_MSIX_VECTORS_82599 0x09 + #define IXGBE_PCIE_MSIX_82598_CAPS 0x62 + #define IXGBE_MAX_MSIX_VECTORS_82598 0x13 + diff --git a/drivers/net/ethernet/stmicro/stmmac/Kconfig b/drivers/net/ethernet/stmicro/stmmac/Kconfig index 92d7d5a00b84..d86875c039a2 100644 --- a/drivers/net/ethernet/stmicro/stmmac/Kconfig @@ -19638,14 +22238,19 @@ index 92d7d5a00b84..d86875c039a2 100644 tristate "NXP IMX8 DWMAC support" default ARCH_MXC diff --git a/drivers/net/ethernet/stmicro/stmmac/Makefile b/drivers/net/ethernet/stmicro/stmmac/Makefile -index 5b57aee19267..3d8221783e57 100644 +index 5b57aee19267..a071e84272e3 100644 --- a/drivers/net/ethernet/stmicro/stmmac/Makefile +++ b/drivers/net/ethernet/stmicro/stmmac/Makefile -@@ -27,6 +27,8 @@ obj-$(CONFIG_DWMAC_STI) += dwmac-sti.o +@@ -22,11 +22,13 @@ obj-$(CONFIG_DWMAC_MESON) += dwmac-meson.o dwmac-meson8b.o + obj-$(CONFIG_DWMAC_QCOM_ETHQOS) += dwmac-qcom-ethqos.o + obj-$(CONFIG_DWMAC_ROCKCHIP) += dwmac-rk.o + obj-$(CONFIG_DWMAC_SOCFPGA) += dwmac-altr-socfpga.o ++obj-$(CONFIG_ARCH_SOPHGO) += dwmac-sophgo.o + obj-$(CONFIG_DWMAC_STARFIVE) += dwmac-starfive.o + obj-$(CONFIG_DWMAC_STI) += dwmac-sti.o obj-$(CONFIG_DWMAC_STM32) += dwmac-stm32.o obj-$(CONFIG_DWMAC_SUNXI) += dwmac-sunxi.o obj-$(CONFIG_DWMAC_SUN8I) += dwmac-sun8i.o -+obj-$(CONFIG_ARCH_SOPHGO) += dwmac-sophgo.o +obj-$(CONFIG_DWMAC_THEAD) += dwmac-thead.o obj-$(CONFIG_DWMAC_DWC_QOS_ETH) += dwmac-dwc-qos-eth.o obj-$(CONFIG_DWMAC_INTEL_PLAT) += dwmac-intel-plat.o @@ -20252,10 +22857,10 @@ index 9bac5fb2f13d..edac7c5e94a3 100644 +obj-$(CONFIG_PCIE_CADENCE_SOPHGO) += pcie-cadence-sophgo.o diff --git a/drivers/pci/controller/cadence/pcie-cadence-sophgo.c b/drivers/pci/controller/cadence/pcie-cadence-sophgo.c new file mode 100644 -index 000000000000..feb9bfdc7e75 +index 000000000000..c0dd61e31adc --- /dev/null +++ b/drivers/pci/controller/cadence/pcie-cadence-sophgo.c -@@ -0,0 +1,963 @@ +@@ -0,0 +1,972 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2017 Cadence +// Cadence PCIe host controller driver. @@ -20720,8 +23325,9 @@ index 000000000000..feb9bfdc7e75 + +struct vendor_id_list vendor_id_list[] = { + {"Inter X520", 0x8086, 0x10fb}, -+ //{"WangXun RP1000", 0x8088}, -+ {"Switchtec", 0x11f8,4052}, ++ {"Inter I40E", 0x8086, 0x1572}, ++ //{"WangXun RP1000", 0x8088}, ++ {"Switchtec", 0x11f8,0x4052}, +}; + +size_t vendor_id_list_num = ARRAY_SIZE(vendor_id_list); @@ -21050,6 +23656,11 @@ index 000000000000..feb9bfdc7e75 + return ret; +} + ++static int cdns_pcie_irq_parse_and_map_pci(const struct pci_dev *dev, u8 slot, u8 pin) ++{ ++ return 0; /* Proper return code 0 == NO_IRQ */ ++} ++ +static int cdns_pcie_host_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; @@ -21156,7 +23767,10 @@ index 000000000000..feb9bfdc7e75 + + bridge->dev.parent = dev; + bridge->ops = &cdns_pcie_host_ops; -+ bridge->map_irq = of_irq_parse_and_map_pci; ++ if (rc->top_intc_used == 1) ++ bridge->map_irq = of_irq_parse_and_map_pci; ++ else ++ bridge->map_irq = cdns_pcie_irq_parse_and_map_pci; + bridge->swizzle_irq = pci_common_swizzle; + if (rc->top_intc_used == 0) + bridge->sysdata = rc; @@ -21242,6 +23856,135 @@ index 000000000000..ef46c46678ed +int check_vendor_id(struct pci_dev *dev, struct vendor_id_list vendor_id_list[], + size_t vendor_id_list_num); +#endif +diff --git a/drivers/pci/msi/msi.c b/drivers/pci/msi/msi.c +index cde8c4e264b7..e5db5b1b81ac 100644 +--- a/drivers/pci/msi/msi.c ++++ b/drivers/pci/msi/msi.c +@@ -12,6 +12,7 @@ + + #include "../pci.h" + #include "msi.h" ++#include "../controller/cadence/pcie-cadence-sophgo.h" + + int pci_msi_enable = 1; + int pci_msi_ignore_mask; +@@ -814,66 +815,70 @@ int __pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries, int + nvec = pci_irq_numbers; + #endif + +- if (maxvec < minvec) +- return -ERANGE; ++ if (check_vendor_id(dev, vendor_id_list, vendor_id_list_num)) { ++ if (maxvec < minvec) ++ return -ERANGE; + +- if (dev->msi_enabled) { +- pci_info(dev, "can't enable MSI-X (MSI already enabled)\n"); +- return -EINVAL; +- } ++ if (dev->msi_enabled) { ++ pci_info(dev, "can't enable MSI-X (MSI already enabled)\n"); ++ return -EINVAL; ++ } + +- if (WARN_ON_ONCE(dev->msix_enabled)) +- return -EINVAL; ++ if (WARN_ON_ONCE(dev->msix_enabled)) ++ return -EINVAL; + +- /* Check MSI-X early on irq domain enabled architectures */ +- if (!pci_msi_domain_supports(dev, MSI_FLAG_PCI_MSIX, ALLOW_LEGACY)) +- return -ENOTSUPP; ++ /* Check MSI-X early on irq domain enabled architectures */ ++ if (!pci_msi_domain_supports(dev, MSI_FLAG_PCI_MSIX, ALLOW_LEGACY)) ++ return -ENOTSUPP; + +- if (!pci_msi_supported(dev, nvec) || dev->current_state != PCI_D0) +- return -EINVAL; ++ if (!pci_msi_supported(dev, nvec) || dev->current_state != PCI_D0) ++ return -EINVAL; + +- hwsize = pci_msix_vec_count(dev); +- if (hwsize < 0) +- return hwsize; ++ hwsize = pci_msix_vec_count(dev); ++ if (hwsize < 0) ++ return hwsize; + +- if (!pci_msix_validate_entries(dev, entries, nvec)) +- return -EINVAL; ++ if (!pci_msix_validate_entries(dev, entries, nvec)) ++ return -EINVAL; + +- if (hwsize < nvec) { +- /* Keep the IRQ virtual hackery working */ +- if (flags & PCI_IRQ_VIRTUAL) +- hwsize = nvec; +- else +- nvec = hwsize; +- } ++ if (hwsize < nvec) { ++ /* Keep the IRQ virtual hackery working */ ++ if (flags & PCI_IRQ_VIRTUAL) ++ hwsize = nvec; ++ else ++ nvec = hwsize; ++ } + +- if (nvec < minvec) +- return -ENOSPC; ++ if (nvec < minvec) ++ return -ENOSPC; + +- rc = pci_setup_msi_context(dev); +- if (rc) +- return rc; ++ rc = pci_setup_msi_context(dev); ++ if (rc) ++ return rc; + +- if (!pci_setup_msix_device_domain(dev, hwsize)) +- return -ENODEV; ++ if (!pci_setup_msix_device_domain(dev, hwsize)) ++ return -ENODEV; + +- for (;;) { +- if (affd) { +- nvec = irq_calc_affinity_vectors(minvec, nvec, affd); +- if (nvec < minvec) +- return -ENOSPC; +- } ++ for (;;) { ++ if (affd) { ++ nvec = irq_calc_affinity_vectors(minvec, nvec, affd); ++ if (nvec < minvec) ++ return -ENOSPC; ++ } + +- rc = msix_capability_init(dev, entries, nvec, affd); +- if (rc == 0) +- return nvec; ++ rc = msix_capability_init(dev, entries, nvec, affd); ++ if (rc == 0) ++ return nvec; + +- if (rc < 0) +- return rc; +- if (rc < minvec) +- return -ENOSPC; ++ if (rc < 0) ++ return rc; ++ if (rc < minvec) ++ return -ENOSPC; + +- nvec = rc; ++ nvec = rc; ++ } ++ } else { ++ return -1; + } + } + diff --git a/drivers/pci/pcie/portdrv.c b/drivers/pci/pcie/portdrv.c index 46fad0d813b2..560b3a236d84 100644 --- a/drivers/pci/pcie/portdrv.c @@ -25745,6 +28488,571 @@ index 000000000000..cecda6e251a9 +MODULE_AUTHOR("Alibaba Group Holding Limited"); +MODULE_DESCRIPTION("Thead Light mailbox IPC client driver"); +MODULE_LICENSE("GPL v2"); +diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig +index 6f270577df86..f5e30f724f74 100644 +--- a/drivers/rtc/Kconfig ++++ b/drivers/rtc/Kconfig +@@ -1992,4 +1992,10 @@ config RTC_DRV_POLARFIRE_SOC + This driver can also be built as a module, if so, the module + will be called "rtc-mpfs". + ++config RTC_DRV_ASTBMC ++ tristate "SG2042 server get rtc time from bmc via pci bus" ++ help ++ This driver can also be built as a module, if so, the module ++ will be called "rtc-astbmc". ++ + endif # RTC_CLASS +diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile +index 7711f79787ac..441b27e2d8fd 100644 +--- a/drivers/rtc/Makefile ++++ b/drivers/rtc/Makefile +@@ -189,3 +189,4 @@ obj-$(CONFIG_RTC_DRV_WM8350) += rtc-wm8350.o + obj-$(CONFIG_RTC_DRV_X1205) += rtc-x1205.o + obj-$(CONFIG_RTC_DRV_XGENE) += rtc-xgene.o + obj-$(CONFIG_RTC_DRV_ZYNQMP) += rtc-zynqmp.o ++obj-$(CONFIG_RTC_DRV_ASTBMC) += rtc-astbmc.o +diff --git a/drivers/rtc/rtc-astbmc.c b/drivers/rtc/rtc-astbmc.c +new file mode 100644 +index 000000000000..8b56090cf0f8 +--- /dev/null ++++ b/drivers/rtc/rtc-astbmc.c +@@ -0,0 +1,535 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++/* rtc-astbmc.c ++ * ++ * Driver for Dallas Semiconductor astbmcrtc Low Current, PCI Compatible ++ * Real Time Clock ++ * ++ * Author : Raghavendra Chandra Ganiga ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++/* Registers in astbmcrtc rtc */ ++ ++#define ASPEED_PCI_BMC_HOST2BMC_Q1 0x30000 ++#define ASPEED_PCI_BMC_HOST2BMC_Q2 0x30010 ++#define ASPEED_PCI_BMC_BMC2HOST_Q1 0x30020 ++#define ASPEED_PCI_BMC_BMC2HOST_Q2 0x30030 ++#define ASPEED_PCI_BMC_BMC2HOST_STS 0x30040 ++#define BMC2HOST_INT_STS_DOORBELL BIT(31) ++#define BMC2HOST_ENABLE_INTB BIT(30) ++/* */ ++#define BMC2HOST_Q1_FULL BIT(27) ++#define BMC2HOST_Q1_EMPTY BIT(26) ++#define BMC2HOST_Q2_FULL BIT(25) ++#define BMC2HOST_Q2_EMPTY BIT(24) ++#define BMC2HOST_Q1_FULL_UNMASK BIT(23) ++#define BMC2HOST_Q1_EMPTY_UNMASK BIT(22) ++#define BMC2HOST_Q2_FULL_UNMASK BIT(21) ++#define BMC2HOST_Q2_EMPTY_UNMASK BIT(20) ++ ++#define ASPEED_PCI_BMC_HOST2BMC_STS 0x30044 ++#define HOST2BMC_INT_STS_DOORBELL BIT(31) ++#define HOST2BMC_ENABLE_INTB BIT(30) ++/* */ ++#define HOST2BMC_Q1_FULL BIT(27) ++#define HOST2BMC_Q1_EMPTY BIT(26) ++#define HOST2BMC_Q2_FULL BIT(25) ++#define HOST2BMC_Q2_EMPTY BIT(24) ++#define HOST2BMC_Q1_FULL_UNMASK BIT(23) ++#define HOST2BMC_Q1_EMPTY_UNMASK BIT(22) ++#define HOST2BMC_Q2_FULL_UNMASK BIT(21) ++#define HOST2BMC_Q2_EMPTY_UNMASK BIT(20) ++ ++struct aspeed_pci_bmc_dev { ++ struct device *dev; ++ struct miscdevice miscdev; ++ ++ unsigned long mem_bar_base; ++ unsigned long mem_bar_size; ++ void __iomem *mem_bar_reg; ++ ++ unsigned long message_bar_base; ++ unsigned long message_bar_size; ++ void __iomem *msg_bar_reg; ++ ++ struct bin_attribute bin0; ++ struct bin_attribute bin1; ++ ++ struct kernfs_node *kn0; ++ struct kernfs_node *kn1; ++ ++ /* Queue waiters for idle engine */ ++ wait_queue_head_t tx_wait0; ++ wait_queue_head_t tx_wait1; ++ wait_queue_head_t rx_wait0; ++ wait_queue_head_t rx_wait1; ++ ++ void __iomem *sio_mbox_reg; ++ int sio_mbox_irq; ++ ++ u8 IntLine; ++ int legency_irq; ++}; ++ ++#define HOST_BMC_QUEUE_SIZE (16 * 4) ++#define PCIE_DEVICE_SIO_ADDR (0x2E * 4) ++#define BMC_MULTI_MSI 32 ++ ++#define DRIVER_NAME "ASPEED BMC DEVICE" ++ ++static struct rtc_device *rtc; ++static int time64_flag = 1; ++module_param(time64_flag, int, 0644); ++ ++static struct aspeed_pci_bmc_dev *file_aspeed_bmc_device(struct file *file) ++{ ++ return container_of(file->private_data, struct aspeed_pci_bmc_dev, ++ miscdev); ++} ++ ++static int aspeed_pci_bmc_dev_mmap(struct file *file, struct vm_area_struct *vma) ++{ ++ struct aspeed_pci_bmc_dev *pci_bmc_dev = file_aspeed_bmc_device(file); ++ unsigned long vsize = vma->vm_end - vma->vm_start; ++ pgprot_t prot = vma->vm_page_prot; ++ ++ if (vma->vm_pgoff + vsize > pci_bmc_dev->mem_bar_base + 0x100000) ++ return -EINVAL; ++ ++ prot = pgprot_noncached(prot); ++ ++ if (remap_pfn_range(vma, vma->vm_start, ++ (pci_bmc_dev->mem_bar_base >> PAGE_SHIFT) + vma->vm_pgoff, ++ vsize, prot)) ++ return -EAGAIN; ++ ++ return 0; ++} ++ ++static const struct file_operations aspeed_pci_bmc_dev_fops = { ++ .owner = THIS_MODULE, ++ .mmap = aspeed_pci_bmc_dev_mmap, ++}; ++ ++ ++static irqreturn_t aspeed_pci_host_bmc_device_interrupt(int irq, void *dev_id) ++{ ++ struct aspeed_pci_bmc_dev *pci_bmc_device = dev_id; ++ u32 bmc2host_q_sts = readl(pci_bmc_device->msg_bar_reg + ASPEED_PCI_BMC_BMC2HOST_STS); ++ ++ if (bmc2host_q_sts & BMC2HOST_INT_STS_DOORBELL) ++ writel(BMC2HOST_INT_STS_DOORBELL, pci_bmc_device->msg_bar_reg + ASPEED_PCI_BMC_BMC2HOST_STS); ++ ++ if (bmc2host_q_sts & BMC2HOST_ENABLE_INTB) ++ writel(BMC2HOST_ENABLE_INTB, pci_bmc_device->msg_bar_reg + ASPEED_PCI_BMC_BMC2HOST_STS); ++ ++ if (bmc2host_q_sts & BMC2HOST_Q1_FULL) ++ dev_info(pci_bmc_device->dev, "Q1 Full\n"); ++ ++ if (bmc2host_q_sts & BMC2HOST_Q2_FULL) ++ dev_info(pci_bmc_device->dev, "Q2 Full\n"); ++ ++ ++ //check q1 ++ if (!(readl(pci_bmc_device->msg_bar_reg + ASPEED_PCI_BMC_HOST2BMC_STS) & HOST2BMC_Q1_FULL)) ++ wake_up_interruptible(&pci_bmc_device->tx_wait0); ++ ++ if (!(readl(pci_bmc_device->msg_bar_reg + ASPEED_PCI_BMC_BMC2HOST_STS) & BMC2HOST_Q1_EMPTY)) ++ wake_up_interruptible(&pci_bmc_device->rx_wait0); ++ //chech q2 ++ if (!(readl(pci_bmc_device->msg_bar_reg + ASPEED_PCI_BMC_HOST2BMC_STS) & HOST2BMC_Q2_FULL)) ++ wake_up_interruptible(&pci_bmc_device->tx_wait1); ++ ++ if (!(readl(pci_bmc_device->msg_bar_reg + ASPEED_PCI_BMC_BMC2HOST_STS) & BMC2HOST_Q2_EMPTY)) ++ wake_up_interruptible(&pci_bmc_device->rx_wait1); ++ ++ return IRQ_HANDLED; ++ ++} ++ ++ ++static int clear_r_queue1(struct device *dev, int timeout) ++{ ++ u32 value; ++ unsigned long tick_end = jiffies + timeout * HZ; ++ struct aspeed_pci_bmc_dev *pci_bmc_device = dev_get_drvdata(dev); ++ while (!(readl(pci_bmc_device->msg_bar_reg + ASPEED_PCI_BMC_BMC2HOST_STS) & BMC2HOST_Q1_EMPTY)) { ++ value = readl(pci_bmc_device->msg_bar_reg + ASPEED_PCI_BMC_BMC2HOST_Q1); ++ writel(HOST2BMC_INT_STS_DOORBELL | HOST2BMC_ENABLE_INTB, pci_bmc_device->msg_bar_reg + ASPEED_PCI_BMC_HOST2BMC_STS); ++ ++ if (time_after(jiffies, tick_end)) { ++ return 0; ++ } ++ } ++ return 1; ++} ++ ++ ++ ++static ssize_t read_8bytes_from_queue1(struct device *dev, time64_t * time_stamp, int timeout) ++{ ++ int i = 0; ++ u32 * time_buf = (u32*)time_stamp; ++ struct aspeed_pci_bmc_dev *pci_bmc_device = dev_get_drvdata(dev); ++ unsigned long tick_end = jiffies + timeout * HZ; ++ ++ while (i < 2) { ++ if (!(readl(pci_bmc_device->msg_bar_reg + ASPEED_PCI_BMC_BMC2HOST_STS) & BMC2HOST_Q1_EMPTY)) { ++ time_buf[i++] = readl(pci_bmc_device->msg_bar_reg + ASPEED_PCI_BMC_BMC2HOST_Q1); ++ writel(HOST2BMC_INT_STS_DOORBELL | HOST2BMC_ENABLE_INTB, pci_bmc_device->msg_bar_reg + ASPEED_PCI_BMC_HOST2BMC_STS); ++ } ++ ++ if (time_after(jiffies, tick_end)) { ++ return 0; ++ } ++ } ++ return sizeof(time64_t); ++} ++ ++static ssize_t read_queue1(struct device *dev, u32 * data) ++{ ++ struct aspeed_pci_bmc_dev *pci_bmc_device = dev_get_drvdata(dev); ++ int ret; ++ ++ ret = wait_event_interruptible(pci_bmc_device->rx_wait0, ++ !(readl(pci_bmc_device->msg_bar_reg + ASPEED_PCI_BMC_BMC2HOST_STS) & BMC2HOST_Q1_EMPTY)); ++ if (ret) ++ return -EINTR; ++ ++ * data = readl(pci_bmc_device->msg_bar_reg + ASPEED_PCI_BMC_BMC2HOST_Q1); ++ writel(HOST2BMC_INT_STS_DOORBELL | HOST2BMC_ENABLE_INTB, pci_bmc_device->msg_bar_reg + ASPEED_PCI_BMC_HOST2BMC_STS); ++ return sizeof(u32); ++} ++static ssize_t write_queue1(struct device *dev, u32 data) ++{ ++ struct aspeed_pci_bmc_dev *pci_bmc_device = dev_get_drvdata(dev); ++ int ret; ++ ++ ret = wait_event_interruptible(pci_bmc_device->tx_wait0, ++ !(readl(pci_bmc_device->msg_bar_reg + ASPEED_PCI_BMC_HOST2BMC_STS) & HOST2BMC_Q1_FULL)); ++ if (ret) ++ return -EINTR; ++ ++ writel(data, pci_bmc_device->msg_bar_reg + ASPEED_PCI_BMC_HOST2BMC_Q1); ++ //trigger to host ++ writel(HOST2BMC_INT_STS_DOORBELL | HOST2BMC_ENABLE_INTB, pci_bmc_device->msg_bar_reg + ASPEED_PCI_BMC_HOST2BMC_STS); ++ ++ return sizeof(u32); ++} ++ ++static ssize_t read_queue2(struct device *dev, u32 * timestamp) ++{ ++ struct aspeed_pci_bmc_dev *pci_bmc_device = dev_get_drvdata(dev); ++ int ret; ++ ++ ret = wait_event_interruptible(pci_bmc_device->rx_wait1, ++ !(readl(pci_bmc_device->msg_bar_reg + ASPEED_PCI_BMC_BMC2HOST_STS) & BMC2HOST_Q2_EMPTY)); ++ if (ret) ++ return -EINTR; ++ ++ * timestamp = readl(pci_bmc_device->msg_bar_reg + ASPEED_PCI_BMC_BMC2HOST_Q2); ++ writel(HOST2BMC_INT_STS_DOORBELL | HOST2BMC_ENABLE_INTB, pci_bmc_device->msg_bar_reg + ASPEED_PCI_BMC_HOST2BMC_STS); ++ return sizeof(u32); ++} ++static ssize_t write_queue2(struct device *dev, u32 data) ++{ ++ struct aspeed_pci_bmc_dev *pci_bmc_device = dev_get_drvdata(dev); ++ int ret; ++ ++ ret = wait_event_interruptible(pci_bmc_device->tx_wait1, ++ !(readl(pci_bmc_device->msg_bar_reg + ASPEED_PCI_BMC_HOST2BMC_STS) & HOST2BMC_Q2_FULL)); ++ if (ret) ++ return -EINTR; ++ ++ writel(data, pci_bmc_device->msg_bar_reg + ASPEED_PCI_BMC_HOST2BMC_Q2); ++ //trigger to host ++ writel(HOST2BMC_INT_STS_DOORBELL | HOST2BMC_ENABLE_INTB, pci_bmc_device->msg_bar_reg + ASPEED_PCI_BMC_HOST2BMC_STS); ++ ++ ++ return sizeof(u32); ++} ++ ++static ssize_t write_8bytes_to_queue2(struct device *dev, time64_t * time_stamp) ++{ ++ int i = 0; ++ u32 * time_buf = (u32*)time_stamp; ++ struct aspeed_pci_bmc_dev *pci_bmc_device = dev_get_drvdata(dev); ++ ++ while (i < 2) { ++ if (!(readl(pci_bmc_device->msg_bar_reg + ASPEED_PCI_BMC_HOST2BMC_STS) & HOST2BMC_Q2_FULL)) { ++ writel(time_buf[i++], pci_bmc_device->msg_bar_reg + ASPEED_PCI_BMC_HOST2BMC_Q2); ++ writel(HOST2BMC_INT_STS_DOORBELL | HOST2BMC_ENABLE_INTB, pci_bmc_device->msg_bar_reg + ASPEED_PCI_BMC_HOST2BMC_STS); ++ ++ } ++ } ++ return sizeof(time64_t); ++} ++ ++ ++ ++static int astbmc_read_time(struct device *dev, struct rtc_time *dt) ++{ ++ time64_t time_stamp = 0; ++ u32 tx_cmd = 0x55555555; ++ ++ clear_r_queue1(dev, 5); ++ ++ write_queue1(dev, tx_cmd); ++ ++ read_8bytes_from_queue1(dev, &time_stamp, 5); ++ ++ rtc_time64_to_tm(time_stamp, dt); ++ ++ return 0; ++} ++ ++static int astbmc_set_time(struct device *dev, struct rtc_time *dt) ++{ ++ time64_t time_stamp = 0; ++ u32 tx_cmd = 0xaaaaaaaa; ++ ++ write_queue2(dev, tx_cmd); ++ ++ time_stamp = rtc_tm_to_time64(dt); ++ ++ write_8bytes_to_queue2(dev, &time_stamp); ++ ++ return 0; ++} ++ ++static const struct rtc_class_ops astbmc_rtc_ops = { ++ .read_time = astbmc_read_time, ++ .set_time = astbmc_set_time, ++}; ++ ++ ++//0-unenabled 1-enabled ++static int is_bmc_rtc_device_func_enable(struct device *dev) ++{ ++ time64_t time_stamp = 0; ++ u32 tx_cmd = 0x55555555; ++ ++ clear_r_queue1(dev, 5); ++ ++ write_queue1(dev, tx_cmd); ++ ++ if (read_8bytes_from_queue1(dev, &time_stamp, 5) == 0) { ++ pr_info("BMC has not enabled rtc device func!\n"); ++ return 0; ++ } ++ ++ pr_info("BMC has enabled rtc device func!\n"); ++ return 1; ++ ++} ++ ++ ++#define BMC_MSI_IDX_BASE 0 ++static int aspeed_pci_host_bmc_device_probe(struct pci_dev *pdev, const struct pci_device_id *ent) ++{ ++ struct aspeed_pci_bmc_dev *pci_bmc_dev; ++ struct device *dev = &pdev->dev; ++ u16 config_cmd_val; ++ int nr_entries; ++ int rc = 0; ++ ++ pr_info("ASPEED BMC PCI ID %04x:%04x, IRQ=%u\n", pdev->vendor, pdev->device, pdev->irq); ++ ++ pci_bmc_dev = kzalloc(sizeof(*pci_bmc_dev), GFP_KERNEL); ++ if (!pci_bmc_dev) { ++ rc = -ENOMEM; ++ dev_err(&pdev->dev, "kmalloc() returned NULL memory.\n"); ++ goto out_err; ++ } ++ ++ rc = pci_enable_device(pdev); ++ if (rc != 0) { ++ dev_err(&pdev->dev, "pci_enable_device() returned error %d\n", rc); ++ goto out_err; ++ } ++ ++ /* set PCI host mastering */ ++ pci_set_master(pdev); ++ ++ nr_entries = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI); ++ if (nr_entries < 0) { ++ pci_bmc_dev->legency_irq = 1; ++ pci_read_config_word(pdev, PCI_COMMAND, &config_cmd_val); ++ config_cmd_val &= ~PCI_COMMAND_INTX_DISABLE; ++ pci_write_config_word((struct pci_dev *)pdev, PCI_COMMAND, config_cmd_val); ++ ++ } else { ++ pci_bmc_dev->legency_irq = 0; ++ pci_read_config_word(pdev, PCI_COMMAND, &config_cmd_val); ++ config_cmd_val |= PCI_COMMAND_INTX_DISABLE; ++ pci_write_config_word((struct pci_dev *)pdev, PCI_COMMAND, config_cmd_val); ++ pdev->irq = pci_irq_vector(pdev, BMC_MSI_IDX_BASE); ++ } ++ ++ pr_info("ASPEED BMC PCI ID %04x:%04x, IRQ=%u\n", pdev->vendor, pdev->device, pdev->irq); ++ ++ init_waitqueue_head(&pci_bmc_dev->tx_wait0); ++ init_waitqueue_head(&pci_bmc_dev->tx_wait1); ++ init_waitqueue_head(&pci_bmc_dev->rx_wait0); ++ init_waitqueue_head(&pci_bmc_dev->rx_wait1); ++ ++ //Get MEM bar ++ pci_bmc_dev->mem_bar_base = pci_resource_start(pdev, 0); ++ pci_bmc_dev->mem_bar_size = pci_resource_len(pdev, 0); ++ ++ pr_info("BAR0 I/O Mapped Base Address is: %08lx End %08lx\n", pci_bmc_dev->mem_bar_base, pci_bmc_dev->mem_bar_size); ++ ++ pci_bmc_dev->mem_bar_reg = pci_ioremap_bar(pdev, 0); ++ if (!pci_bmc_dev->mem_bar_reg) { ++ rc = -ENOMEM; ++ goto out_free0; ++ } ++ ++ //Get MSG BAR info ++ pci_bmc_dev->message_bar_base = pci_resource_start(pdev, 1); ++ pci_bmc_dev->message_bar_size = pci_resource_len(pdev, 1); ++ ++ pr_info("MSG BAR1 Memory Mapped Base Address is: %08lx End %08lx\n", pci_bmc_dev->message_bar_base, pci_bmc_dev->message_bar_size); ++ ++ pci_bmc_dev->msg_bar_reg = pci_ioremap_bar(pdev, 1); ++ if (!pci_bmc_dev->msg_bar_reg) { ++ rc = -ENOMEM; ++ goto out_free1; ++ } ++ ++ /* ERRTA40: dummy read */ ++ (void)__raw_readl((void __iomem *)pci_bmc_dev->msg_bar_reg); ++ ++ ++ pci_bmc_dev->miscdev.minor = MISC_DYNAMIC_MINOR; ++ pci_bmc_dev->miscdev.name = DRIVER_NAME; ++ pci_bmc_dev->miscdev.fops = &aspeed_pci_bmc_dev_fops; ++ pci_bmc_dev->miscdev.parent = dev; ++ ++ rc = misc_register(&pci_bmc_dev->miscdev); ++ if (rc) { ++ pr_err("host bmc register fail %d\n", rc); ++ goto out_free; ++ } ++ ++ pci_set_drvdata(pdev, pci_bmc_dev); ++ ++ rc = request_irq(pdev->irq, aspeed_pci_host_bmc_device_interrupt, IRQF_SHARED, "ASPEED BMC DEVICE", pci_bmc_dev); ++ if (rc) { ++ pr_err("host bmc device Unable to get IRQ %d\n", rc); ++ goto out_unreg; ++ } ++ ++ return 0; ++ ++ if (!is_bmc_rtc_device_func_enable(dev)) ++ return 0; ++ ++ //register rtc device ++ rtc = devm_rtc_allocate_device(dev); ++ if (IS_ERR(rtc)) ++ return PTR_ERR(rtc); ++ ++ rtc->ops = &astbmc_rtc_ops; ++ rtc->range_min = RTC_TIMESTAMP_BEGIN_0000; ++ rtc->range_max = RTC_TIMESTAMP_END_9999; ++ ++ devm_rtc_register_device(rtc); ++ ++ return 0; ++ ++out_unreg: ++ misc_deregister(&pci_bmc_dev->miscdev); ++out_free1: ++ pci_release_region(pdev, 1); ++out_free0: ++ pci_release_region(pdev, 0); ++out_free: ++ kfree(pci_bmc_dev); ++out_err: ++ pci_disable_device(pdev); ++ ++ return rc; ++ ++} ++ ++ ++ ++static void aspeed_pci_host_bmc_device_remove(struct pci_dev *pdev) ++{ ++ struct aspeed_pci_bmc_dev *pci_bmc_dev = pci_get_drvdata(pdev); ++ ++ free_irq(pdev->irq, pdev); ++ misc_deregister(&pci_bmc_dev->miscdev); ++ pci_release_regions(pdev); ++ kfree(pci_bmc_dev); ++ pci_disable_device(pdev); ++} ++ ++/** ++ * This table holds the list of (VendorID,DeviceID) supported by this driver ++ * ++ */ ++static struct pci_device_id aspeed_host_bmc_dev_pci_ids[] = { ++ { PCI_DEVICE(0x1A03, 0x2402), }, ++ { 0, } ++}; ++ ++MODULE_DEVICE_TABLE(pci, aspeed_host_bmc_dev_pci_ids); ++ ++static struct pci_driver aspeed_host_bmc_dev_driver = { ++ .name = DRIVER_NAME, ++ .id_table = aspeed_host_bmc_dev_pci_ids, ++ .probe = aspeed_pci_host_bmc_device_probe, ++ .remove = aspeed_pci_host_bmc_device_remove, ++}; ++ ++static int __init aspeed_host_bmc_device_init(void) ++{ ++ int ret; ++ ++ /* register pci driver */ ++ ret = pci_register_driver(&aspeed_host_bmc_dev_driver); ++ if (ret < 0) { ++ pr_err("pci-driver: can't register pci driver\n"); ++ return ret; ++ } ++ ++ return 0; ++ ++} ++ ++static void aspeed_host_bmc_device_exit(void) ++{ ++ /* unregister pci driver */ ++ pci_unregister_driver(&aspeed_host_bmc_dev_driver); ++} ++ ++// late_initcall(aspeed_host_bmc_device_init); ++module_init(aspeed_host_bmc_device_init); ++module_exit(aspeed_host_bmc_device_exit); ++ ++MODULE_AUTHOR("Ryan Chen "); ++MODULE_DESCRIPTION("ASPEED Host BMC DEVICE Driver"); ++MODULE_LICENSE("GPL"); diff --git a/drivers/soc/Kconfig b/drivers/soc/Kconfig index d21e75d69294..6ce6f6300055 100644 --- a/drivers/soc/Kconfig @@ -25757,14 +29065,15 @@ index d21e75d69294..6ce6f6300055 100644 endmenu diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile -index 0706a27d13be..f34415578e9e 100644 +index 0706a27d13be..f19f053b5404 100644 --- a/drivers/soc/Makefile +++ b/drivers/soc/Makefile -@@ -30,8 +30,10 @@ obj-y += rockchip/ +@@ -29,9 +29,11 @@ obj-y += renesas/ + obj-y += rockchip/ obj-$(CONFIG_SOC_SAMSUNG) += samsung/ obj-y += sifive/ ++obj-$(CONFIG_ARCH_SOPHGO) += sophgo/ obj-y += sunxi/ -+obj-$(CONFIG_ARCH_SOPHGO) += sophgo/ obj-$(CONFIG_ARCH_TEGRA) += tegra/ obj-y += ti/ obj-$(CONFIG_ARCH_U8500) += ux500/ @@ -30035,6 +33344,19 @@ index 000000000000..8930845604a0 + +#endif /* __LINUX_LIGHT_RPMSG_H__*/ + +diff --git a/kernel/kexec_core.c b/kernel/kexec_core.c +index b7246b7171b7..52de73abd9fc 100644 +--- a/kernel/kexec_core.c ++++ b/kernel/kexec_core.c +@@ -51,7 +51,7 @@ atomic_t __kexec_lock = ATOMIC_INIT(0); + + /* Flag to indicate we are going to kexec a new kernel */ + bool kexec_in_progress = false; +- ++EXPORT_SYMBOL(kexec_in_progress); + + /* Location of the reserved area for the crash kernel */ + struct resource crashk_res = { diff --git a/kernel/panic.c b/kernel/panic.c index ef9f9a4e928d..0506d3ceb06c 100644 --- a/kernel/panic.c @@ -30059,8 +33381,35 @@ index ef9f9a4e928d..0506d3ceb06c 100644 if (panic_on_warn) { /* +diff --git a/kernel/sched/fair.c b/kernel/sched/fair.c +index 3dcbf50b677f..7eb1e8087469 100644 +--- a/kernel/sched/fair.c ++++ b/kernel/sched/fair.c +@@ -10497,6 +10497,9 @@ int can_migrate_task(struct task_struct *p, struct lb_env *env) + if (kthread_is_per_cpu(p)) + return 0; + ++ if (is_migration_disabled(p)) ++ return 0; ++ + #ifdef CONFIG_QOS_SCHED_DYNAMIC_AFFINITY + set_task_select_cpus(p, NULL, 0); + if (!cpumask_test_cpu(env->dst_cpu, p->select_cpus)) { +diff --git a/kernel/time/tick-oneshot.c b/kernel/time/tick-oneshot.c +index 5e2c2c26b3cc..368c8fc21b1f 100644 +--- a/kernel/time/tick-oneshot.c ++++ b/kernel/time/tick-oneshot.c +@@ -78,7 +78,7 @@ int tick_switch_to_oneshot(void (*handler)(struct clock_event_device *)) + if (!dev || !(dev->features & CLOCK_EVT_FEAT_ONESHOT) || + !tick_device_is_functional(dev)) { + +- pr_info("Clockevents: could not switch to one-shot mode:"); ++ pr_debug("Clockevents: could not switch to one-shot mode:"); + if (!dev) { + pr_cont(" no tick device\n"); + } else { diff --git a/mm/memblock.c b/mm/memblock.c -index b46bcb931a2e..7ebe8620bb6f 100644 +index b46bcb931a2e..285bc9757ec7 100644 --- a/mm/memblock.c +++ b/mm/memblock.c @@ -1780,6 +1780,7 @@ phys_addr_t __init_memblock memblock_end_of_DRAM(void) @@ -30071,7 +33420,7 @@ index b46bcb931a2e..7ebe8620bb6f 100644 phys_addr_t max_addr = PHYS_ADDR_MAX; struct memblock_region *r; -@@ -1789,11 +1790,10 @@ static phys_addr_t __init_memblock __find_max_addr(phys_addr_t limit) +@@ -1789,16 +1790,37 @@ static phys_addr_t __init_memblock __find_max_addr(phys_addr_t limit) * of those regions, max_addr will keep original value PHYS_ADDR_MAX */ for_each_mem_region(r) { @@ -30085,6 +33434,33 @@ index b46bcb931a2e..7ebe8620bb6f 100644 } return max_addr; + } + ++#ifdef CONFIG_HIGHMEM ++phys_addr_t __init_memblock find_max_low_addr(phys_addr_t limit) ++{ ++ phys_addr_t max_low_addr = PHYS_ADDR_MAX; ++ phys_addr_t max_low_addr_limit; ++ struct memblock_region *r; ++ ++ max_low_addr_limit = memblock_start_of_DRAM() + limit; ++ ++ for_each_mem_region(r) { ++ if ((r->base+r->size) <= max_low_addr_limit) ++ max_low_addr = r->base + r->size; ++ else if (r->base < max_low_addr_limit) ++ max_low_addr = max_low_addr_limit; ++ else ++ continue; ++ } ++ ++ return max_low_addr; ++} ++#endif ++ + void __init memblock_enforce_memory_limit(phys_addr_t limit) + { + phys_addr_t max_addr; diff --git a/scripts/package/builddeb b/scripts/package/builddeb index d7dd0d04c70c..259668daea63 100755 --- a/scripts/package/builddeb @@ -30121,6 +33497,43 @@ index ef6d06fe0f5b..a6863ba97d00 100644 AZX_DCAPS_SNOOP_TYPE(NVIDIA)) #define AZX_DCAPS_PRESET_CTHDA \ +diff --git a/tools/lib/perf/cpumap.c b/tools/lib/perf/cpumap.c +index 2a5a29217374..b53c22b909b8 100644 +--- a/tools/lib/perf/cpumap.c ++++ b/tools/lib/perf/cpumap.c +@@ -405,8 +405,8 @@ struct perf_cpu_map *perf_cpu_map__merge(struct perf_cpu_map *orig, + struct perf_cpu_map *other) + { + struct perf_cpu *tmp_cpus; +- int tmp_len; +- int i, j, k; ++ unsigned int tmp_len; ++ unsigned int i, j, k; + struct perf_cpu_map *merged; + + if (perf_cpu_map__is_subset(orig, other)) +@@ -423,7 +423,7 @@ struct perf_cpu_map *perf_cpu_map__merge(struct perf_cpu_map *orig, + + /* Standard merge algorithm from wikipedia */ + i = j = k = 0; +- while (i < __perf_cpu_map__nr(orig) && j < __perf_cpu_map__nr(other)) { ++ while (i < (unsigned int)(__perf_cpu_map__nr(orig)) && j < (unsigned int)(__perf_cpu_map__nr(other))) { + if (__perf_cpu_map__cpu(orig, i).cpu <= __perf_cpu_map__cpu(other, j).cpu) { + if (__perf_cpu_map__cpu(orig, i).cpu == __perf_cpu_map__cpu(other, j).cpu) + j++; +@@ -432,10 +432,10 @@ struct perf_cpu_map *perf_cpu_map__merge(struct perf_cpu_map *orig, + tmp_cpus[k++] = __perf_cpu_map__cpu(other, j++); + } + +- while (i < __perf_cpu_map__nr(orig)) ++ while (i < (unsigned int)(__perf_cpu_map__nr(orig))) + tmp_cpus[k++] = __perf_cpu_map__cpu(orig, i++); + +- while (j < __perf_cpu_map__nr(other)) ++ while (j < (unsigned int)(__perf_cpu_map__nr(other))) + tmp_cpus[k++] = __perf_cpu_map__cpu(other, j++); + assert(k <= tmp_len); + diff --git a/tools/perf/pmu-events/arch/riscv/mapfile.csv b/tools/perf/pmu-events/arch/riscv/mapfile.csv index c61b3d6ef616..b42b65d09c36 100644 --- a/tools/perf/pmu-events/arch/riscv/mapfile.csv diff --git a/kernel.spec b/kernel.spec index 20d4b4c..6a0fb10 100644 --- a/kernel.spec +++ b/kernel.spec @@ -42,7 +42,7 @@ rm -f test_openEuler_sign.ko test_openEuler_sign.ko.sig %global upstream_sublevel 0 %global devel_release 27 %global maintenance_release .0.0 -%global pkg_release .31 +%global pkg_release .32 %global openeuler_lts 1 %global openeuler_major 2403 @@ -1079,6 +1079,139 @@ fi %endif %changelog +* Fri May 24 2024 Mingzheng Xing - 6.6.0-27.0.0.32 +- Update the riscv-kernel patch for sg2042, rebase 6.6.0-27.0.0 and add features: + - SPI Flash driver + - kexec file raw image + - HIGHMEM +- This patch only applies to the RISC-V architecture, the related commit list: +- +- sg2042: Update sg2042 openeuler_defconfig +- th1520: riscv: config: Enable th1520 support +- riscv: thead: Use the wback_inv instead of wback_only +- riscv: errata: thead: use pa based instructions for CMO +- riscv: errata: thead: use riscv_nonstd_cache_ops for CMO +- Revert "riscv: use VA+PA variant of CMO macros for DMA page preparation" +- Revert "riscv: use VA+PA variant of CMO macros for DMA synchorization" +- Revert "riscv: errata: cmo: add CMO macro variant with both VA and PA" +- Revert "riscv: errata: Replace thead cache clean with flush" +- Revert "riscv: errata: thead: use riscv_nonstd_cache_ops for CMO" +- Revert "riscv: errata: thead: use pa based instructions for CMO" +- riscv: mm: fix NOCACHE_THEAD does not set bit[61] correctly +- riscv: mm: update T-Head memory type definitions +- Revert "sg2042: riscv: changing T-Head PBMT attributes" +- riscv: remove compression for riscv Image +- th1520: cpufreq: correct typo in config name +- th1520: riscv: dts: thead: Add Milk-V Meles board +- th1520: cpufreq: light-mpw-cpufreq: fix -Wunused-variable in panic_cpufreq_notifier_call +- th1520: cpufreq: light-mpw-cpufreq: fix cpu_pll1 already disabled warning +- riscv: Add th1520-lichee-cluster-4a dts support (8G/16G) +- riscv: dts: th1520-beaglev-ahead: add alias for emmc & sd +- riscv: dts: th1520-lichee-pi-4a: add alias for emmc & sd +- riscv: dts: lpi4a 16g support +- th1520: perf vendor events riscv: add T-HEAD C9xx JSON file +- th1520: riscv: dts: thead: Add PMU event node +- riscv: pinctrl: th1520: fix build +- riscv: dts: th1520: lpi4a: add rpmsg node +- riscv: dts: th1520: add mbox client node +- riscv: rpmsg: mailbox-client: sync thead sdk 1.4.2 +- riscv: panic: add thead sdk quirks +- riscv: dts: add watchdog node +- th1520: riscv: dts: Add th1520 reset device tree +- th1520: reset: Add th1520 reset driver support +- th1520: dt-bindings: reset: Document th1520 reset control +- riscv: light_wdt: update sdk 1.4.2 +- th1520_light_event: update sdk 1.4.2 +- th1520_aon: update sdk 1.4.2 +- th1520: fix compile th1520-beaglev-ahead error +- th1520: add TH1520 cpu frequency driver +- th1520: riscv: errata: thead: use pa based instructions for CMO +- th1520: riscv: errata: thead: use riscv_nonstd_cache_ops for CMO +- riscv: dts: thead: Add TH1520 CPU reset node +- th1520: riscv: dts: thead: Enable Lichee Pi 4A USB +- th1520: riscv: dts: thead: Add Lichee Pi 4A IO expansions +- th1520: riscv: dts: thead: Add TH1520 USB nodes +- th1520: riscv: dts: thead: Add TH1520 I2C nodes +- th1520: usb: dwc3: add T-HEAD TH1520 usb driver +- th1520: dt-bindings: usb: Add T-HEAD TH1520 USB controller +- th1520: riscv: dts: thead: Add BeagleV Ahead SDIO0 pins +- th1520: riscv: dts: thead: Add Lichee Pi 4A SDIO0 pins +- th1520: riscv: dts: thead: Add TH1520 ethernet nodes +- th1520: net: stmmac: add glue layer for T-HEAD TH1520 SoC +- th1520: dt-bindings: net: add T-HEAD dwmac support +- th1520: dt-bindings: net: snps,dwmac: allow dwmac-3.70a to set pbl properties +- th1520: riscv: dts: thead: Enable Lichee Pi 4A PWM fan +- th1520: riscv: dts: thead: Add TH1520 PVT node +- th1520: riscv: dts: thead: Add TH1520 PWM node +- th1520: pwm: add T-HEAD PWM driver +- th1520: dt-bindings: pwm: Add T-HEAD PWM controller +- th1520: gpio: dwapb: Use generic request, free and set_config +- riscv: dts: thead: Enable LicheePi 4A eMMC and microSD +- riscv: dts: thead: Enable BeagleV Ahead eMMC and microSD +- riscv: dts: thead: Add TH1520 mmc controllers and sdhci clock +- riscv: defconfig: Enable mmc and dma drivers for T-Head TH1520 +- mmc: sdhci-of-dwcmshc: Add support for T-Head TH1520 +- mmc: sdhci: add __sdhci_execute_tuning() to header +- dt-bindings: mmc: sdhci-of-dwcmhsc: Add T-Head TH1520 support +- th1520: riscv: dtb: thead: Add BeagleV Ahead LEDs +- th1520: riscv: dts: thead: Add TH1520 pinctrl settings for UART0 +- th1520: riscv: dts: thead: Adjust TH1520 GPIO labels +- th1520: riscv: dts: thead: Add TH1520 GPIO ranges +- th1520: riscv: dts: thead: Add TH1520 pin control nodes +- th1520: pinctrl: Add driver for the T-Head TH1520 SoC +- th1520: dt-bindings: pinctrl: Add thead,th1520-pinctrl bindings +- th1520: dt-bindings: gpio: dwapb: allow gpio-ranges +- sg2042: riscv: config: Enable sg2042 support +- sg2042: drivers: rtc: disable BMC RTC device +- sg2042: dts: add i2c-rtc ds1307 device node for single chip +- sg2042: riscv:dts:modify dw gpio clock name +- sg2042: drivers:pci:remove the err log of parsing pci +- sg2042: driver: ipmi: support KVM and IPMI SI for BMC +- sg2042: perf cpumap: Make counter as unsigned ints +- sg2042: driver: radeon: deinit device during kexec +- sg2042: kernel: schedule: Fix set_task_cpu() bug +- sg2042: mm: Modify __find_max_addr for memory hole +- sg2042: riscv: kernel: Optimize apply_relocate_add() +- sg2042: riscv: mm: Clear compilation warning about last_cpupid +- sg2042: kernel: tick: filter unnecessary printing +- sg2042: kernel: Adjust the log level of the tick_switch_to_oneshot function +- sg2042: driver: clk: Modify the timer clock is turned off defaultly +- sg2042: drivers: clock: Add sophgo sg2042 multi-chip clock synchronous support +- Revert "riscv: Fix set_memory_XX() and set_direct_map_XX() by splitting huge linear mappings" +- Revert "riscv: Fix set_direct_map_default_noflush() to reset _PAGE_EXEC" +- Revert "riscv: Fix wrong usage of lm_alias() when splitting a huge linear mapping" +- sg2042: riscv: mm: Add high memory on riscv64 using sv39 +- sg2042: riscv/kexec: handle R_RISCV_ADD16 and R_RISCV_SUB16 relocation types +- sg2042: riscv: kexec: Add image loader for kexec file +- sg2042: drm/amd/display: Support DRM_AMD_DC_FP on RISC-V +- sg2042: riscv: Factor out riscv-march-y to a separate Makefile +- sg2042: riscv: Add support for kernel-mode FPU +- sg2042: mango pci hack:broadcast when no MSI source known +- sg2042: nvidia hda: force msi +- sg2042: radeon hack: force 64-bit msi to fit top intc +- sg2042: amdgpu: disable rebar +- sg2042: ttm: disallow cached mapping +- sg2042: driver: soc: Add sophgo sg2042 soc support +- sg2042: drivers: pcie: Create msi-x whitelist,turn on msi-x for top intr +- sg2042: driver: pcie: Add sophgo sg2042 soc support +- sg2042: driver: net: Add sophgo sg2042 soc support +- sg2042: driver: mtd: Add sophgo sg2042 soc support +- sg2042: driver: mmc: Add sophgo sg2042 soc support +- sg2042: driver: reset: Add sophgo sg2042 soc support +- sg2042: driver: pinctrl: Add sophgo sg2042 soc support +- sg2042: driver: clk: Add sophgo sg2042 soc support +- sg2042: riscv: spinlock: Fix deadlock issue +- sg2042: riscv: add smp_cond_load_acquire() +- sg2042: riscv: add ioremap_wc for gpu +- sg2042: riscv: changing T-Head PBMT attributes +- sg2042: riscv: errata: thead: Make cache clean to flush +- sg2042: riscv: use VA+PA variant of CMO macros for DMA page preparation +- sg2042: riscv: use VA+PA variant of CMO macros for DMA synchorization +- sg2042: riscv: errata: cmo: add CMO macro variant with both VA and PA +- sg2042: riscv: errata: Replace thead cache clean with flush +- sg2042: riscv: Kconfig: Set vector as default no +- sg2042: riscv: Add sophgo sg2042 soc support + * Sat May 18 2024 ZhangPeng - 6.6.0-27.0.0.31 - !7527 ext4 iomap performance optimize - ext4: fallback to generic_perform_write once iov_iter_count <= PAGE_SIZE