9ce8b26b85
sync code: fix PCIe and serdes, roh module problem Signed-off-by: veega2022 <zhuweijia@huawei.com>
126 lines
4.8 KiB
Diff
126 lines
4.8 KiB
Diff
From 104dce7743c31c73a54095844d704272fa14de69 Mon Sep 17 00:00:00 2001
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From: veega2022 <zhuweijia@huawei.com>
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Date: Wed, 10 May 2023 18:20:58 +0800
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Subject: [PATCH 06/18] fix the number of PCS lane registers in the PCIe
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dumpreg
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Traverse the PCS registers of all lanes under the current core.
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Signed-off-by: hesiyuan <hesiyuan4@huawei.com>
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---
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pcie/func_lib/pcie_func/pcie_reg_dump.c | 36 +++++++++++-------------
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pcie/func_lib/pcie_func/pcie_reg_dump.h | 10 +++++++
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pcie/usr_cmd/interface/pcie_common_api.h | 4 +++
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3 files changed, 31 insertions(+), 19 deletions(-)
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diff --git a/pcie/func_lib/pcie_func/pcie_reg_dump.c b/pcie/func_lib/pcie_func/pcie_reg_dump.c
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index 7d91969..e10ff7e 100644
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--- a/pcie/func_lib/pcie_func/pcie_reg_dump.c
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+++ b/pcie/func_lib/pcie_func/pcie_reg_dump.c
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@@ -108,13 +108,13 @@ struct pcie_dumpreg_info g_reg_table_mac[] = {
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};
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struct pcie_dumpreg_info g_reg_table_pcs[] = {
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- {0, "SERDES_STATUS_RPT"},
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- {0, "EBUF_STATUS"},
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- {0, "GEN3_DEC_ENC_STATUS"},
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- {0, "WAKE_STATUS"},
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- {0, "RECV_DET_OR_PWR_CHAGE"},
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- {0, "EQEVAL_STATUS"},
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- {0, "LANE_INTR_STATUS"},
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+ HIKP_PCIE_PCS_LANE_TBL_ENTRY(SERDES_STATUS_RPT),
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+ HIKP_PCIE_PCS_LANE_TBL_ENTRY(EBUF_STATUS),
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+ HIKP_PCIE_PCS_LANE_TBL_ENTRY(GEN3_DEC_ENC_STATUS),
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+ HIKP_PCIE_PCS_LANE_TBL_ENTRY(WAKE_STATUS),
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+ HIKP_PCIE_PCS_LANE_TBL_ENTRY(RECV_DET_OR_PWR_CHAGE),
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+ HIKP_PCIE_PCS_LANE_TBL_ENTRY(EQEVAL_STATUS),
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+ HIKP_PCIE_PCS_LANE_TBL_ENTRY(LANE_INTR_STATUS),
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};
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struct pcie_dumpreg_info g_reg_table_iob_tx[] = {
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@@ -348,6 +348,13 @@ static void pcie_dumpreg_save_glb_analysis_log(const uint32_t *data, uint32_t da
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pcie_dumpreg_write_value_to_file(g_reg_table_core_glb[item_i].name,
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g_reg_table_core_glb[item_i].val);
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}
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+ /* PCS REG */
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+ for (item_i = 0; item_i < HIKP_ARRAY_SIZE(g_reg_table_pcs) &&
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+ data_i < data_num; item_i++, data_i++) {
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+ g_reg_table_pcs[item_i].val = data[data_i];
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+ pcie_dumpreg_write_value_to_file(g_reg_table_pcs[item_i].name,
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+ g_reg_table_pcs[item_i].val);
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+ }
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}
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static void pcie_dumpreg_save_port_analysis_log(uint32_t *data, uint32_t data_num)
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@@ -376,13 +383,6 @@ static void pcie_dumpreg_save_port_analysis_log(uint32_t *data, uint32_t data_nu
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pcie_dumpreg_write_value_to_file(g_reg_table_mac[item_i].name,
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g_reg_table_mac[item_i].val);
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}
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- /* PCS REG */
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- for (item_i = 0; item_i < HIKP_ARRAY_SIZE(g_reg_table_pcs) &&
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- data_i < data_num; item_i++, data_i++) {
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- g_reg_table_pcs[item_i].val = data[data_i];
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- pcie_dumpreg_write_value_to_file(g_reg_table_pcs[item_i].name,
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- g_reg_table_pcs[item_i].val);
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- }
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}
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static int pcie_dumpreg_write_header_to_file(uint32_t version,
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@@ -421,14 +421,12 @@ static int pcie_dumpreg_save_log(uint32_t *data, uint32_t data_num,
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switch (req_data->level) {
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case DUMP_GLOBAL_LEVEL:
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expect_data_num = HIKP_ARRAY_SIZE(g_reg_table_iob_tx) +
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- HIKP_ARRAY_SIZE(g_reg_table_iob_rx) + HIKP_ARRAY_SIZE(g_reg_table_ap_glb) +
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- HIKP_ARRAY_SIZE(g_reg_table_core_glb);
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+ HIKP_ARRAY_SIZE(g_reg_table_iob_rx) + HIKP_ARRAY_SIZE(g_reg_table_ap_glb) +
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+ HIKP_ARRAY_SIZE(g_reg_table_core_glb) + HIKP_ARRAY_SIZE(g_reg_table_pcs);
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break;
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case DUMP_PORT_LEVEL:
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expect_data_num = HIKP_ARRAY_SIZE(g_reg_table_tl) +
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- HIKP_ARRAY_SIZE(g_reg_table_dl) +
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- HIKP_ARRAY_SIZE(g_reg_table_mac) +
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- HIKP_ARRAY_SIZE(g_reg_table_pcs);
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+ HIKP_ARRAY_SIZE(g_reg_table_dl) + HIKP_ARRAY_SIZE(g_reg_table_mac);
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break;
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default:
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Err("PCIe DUMPREG", "check dump level failed.\n");
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diff --git a/pcie/func_lib/pcie_func/pcie_reg_dump.h b/pcie/func_lib/pcie_func/pcie_reg_dump.h
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index 1993c1f..4ec1909 100644
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--- a/pcie/func_lib/pcie_func/pcie_reg_dump.h
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+++ b/pcie/func_lib/pcie_func/pcie_reg_dump.h
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@@ -20,6 +20,16 @@
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#define MAX_STR_LEN 80
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#define PCIE_DUMPREG_LOGFILE_NAME "pcie_dumpreg"
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+#define HIKP_PCIE_PCS_LANE_TBL_ENTRY(name) \
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+ {0, STR(CONTACT(name, _00))}, {0, STR(CONTACT(name, _01))}, \
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+ {0, STR(CONTACT(name, _02))}, {0, STR(CONTACT(name, _03))}, \
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+ {0, STR(CONTACT(name, _04))}, {0, STR(CONTACT(name, _05))}, \
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+ {0, STR(CONTACT(name, _06))}, {0, STR(CONTACT(name, _07))}, \
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+ {0, STR(CONTACT(name, _08))}, {0, STR(CONTACT(name, _09))}, \
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+ {0, STR(CONTACT(name, _10))}, {0, STR(CONTACT(name, _11))}, \
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+ {0, STR(CONTACT(name, _12))}, {0, STR(CONTACT(name, _13))}, \
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+ {0, STR(CONTACT(name, _14))}, {0, STR(CONTACT(name, _15))}
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+
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enum pcie_dump_level {
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DUMP_GLOBAL_LEVEL = 1,
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DUMP_PORT_LEVEL = 2,
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diff --git a/pcie/usr_cmd/interface/pcie_common_api.h b/pcie/usr_cmd/interface/pcie_common_api.h
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index f6541bd..9809575 100644
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--- a/pcie/usr_cmd/interface/pcie_common_api.h
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+++ b/pcie/usr_cmd/interface/pcie_common_api.h
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@@ -17,6 +17,10 @@
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#include <stdint.h>
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#include <stdio.h>
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+#define CONTACT(x, y) x##y
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+#define STR_INTER(x) #x
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+#define STR(x) STR_INTER(x)
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+
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struct print_info {
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char *buff;
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size_t buff_size;
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--
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2.25.1
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