9ce8b26b85
sync code: fix PCIe and serdes, roh module problem Signed-off-by: veega2022 <zhuweijia@huawei.com>
38 lines
1.4 KiB
Diff
38 lines
1.4 KiB
Diff
From befc663ba761c1b334b50de138e57e2a00be4f32 Mon Sep 17 00:00:00 2001
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From: veega2022 <zhuweijia@huawei.com>
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Date: Wed, 10 May 2023 17:54:59 +0800
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Subject: [PATCH 02/18] fix pcie_info cmd print display problem
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The spelling of WITDH is incorrect. Change it to WIDTH.
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Signed-off-by: hesiyuan <hesiyuan4@huawei.com>
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---
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pcie/func_lib/pcie_func/pcie_statistics.c | 4 ++--
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1 file changed, 2 insertions(+), 2 deletions(-)
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diff --git a/pcie/func_lib/pcie_func/pcie_statistics.c b/pcie/func_lib/pcie_func/pcie_statistics.c
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index f12660d..308a142 100644
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--- a/pcie/func_lib/pcie_func/pcie_statistics.c
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+++ b/pcie/func_lib/pcie_func/pcie_statistics.c
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@@ -22,7 +22,7 @@
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#include "pcie_statistics.h"
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static const char *g_global_width_name[GLOBAL_WIDTH_TABLE_SIZE] = {
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- "PCIE_WITDH_X1", "PCIE_WITDH_X2", "PCIE_WITDH_X4", "PCIE_WITDH_X8", "PCIE_WITDH_X16"
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+ "PCIE_WIDTH_X1", "PCIE_WIDTH_X2", "PCIE_WIDTH_X4", "PCIE_WIDTH_X8", "PCIE_WIDTH_X16"
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};
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static int port_distribution_rsp_data_check(const struct hikp_cmd_ret *cmd_ret, uint32_t *port_num)
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@@ -81,7 +81,7 @@ int pcie_port_distribution_get(uint32_t chip_id)
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for (i = 0; i < pair_num; i++) {
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if (port_info->info_pair[i].port_width >= HIKP_ARRAY_SIZE(g_global_width_name)) {
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Info("PCIe Base", "port_id[%u] %s\n", port_info->info_pair[i].port_id,
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- "UNKNOWN_WITDH");
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+ "UNKNOWN_WIDTH");
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continue;
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}
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Info("PCIe Base", "port_id[%u] %s\n", port_info->info_pair[i].port_id,
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--
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2.25.1
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