3225aed4dd
Signed-off-by: May <mayshao-oc@zhaoxin.com> (cherry picked from commit c4f135bfbc5d7fc8b2471ce71997067e4441662e)
78 lines
2.7 KiB
Diff
78 lines
2.7 KiB
Diff
From 59b19d50bd70c08e5c9f5db1742600b7b76df94a Mon Sep 17 00:00:00 2001
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From: May <mayshao-oc@zhaoxin.com>
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Date: Wed, 15 Jan 2025 10:32:17 +0800
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Subject: [PATCH 2/3] x86_64: Optimize large size copy in memmove-ssse3
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This patch optimizes large size copy using normal store when src > dst
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and overlap. Make it the same as the logic in memmove-vec-unaligned-erms.S.
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Current memmove-ssse3 use '__x86_shared_cache_size_half' as the non-
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temporal threshold, this patch updates that value to
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'__x86_shared_non_temporal_threshold'. Currently, the
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__x86_shared_non_temporal_threshold is cpu-specific, and different CPUs
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will have different values based on the related nt-benchmark results.
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However, in memmove-ssse3, the nontemporal threshold uses
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'__x86_shared_cache_size_half', which sounds unreasonable.
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The performance is not changed drastically although shows overall
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improvements without any major regressions or gains.
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Results on Zhaoxin KX-7000:
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bench-memcpy geometric_mean(N=20) New / Original: 0.999
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bench-memcpy-random geometric_mean(N=20) New / Original: 0.999
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bench-memcpy-large geometric_mean(N=20) New / Original: 0.978
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bench-memmove geometric_mean(N=20) New / Original: 1.000
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bench-memmmove-large geometric_mean(N=20) New / Original: 0.962
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Results on Intel Core i5-6600K:
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bench-memcpy geometric_mean(N=20) New / Original: 1.001
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bench-memcpy-random geometric_mean(N=20) New / Original: 0.999
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bench-memcpy-large geometric_mean(N=20) New / Original: 1.001
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bench-memmove geometric_mean(N=20) New / Original: 0.995
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bench-memmmove-large geometric_mean(N=20) New / Original: 0.936
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Signed-off-by: May <mayshao-oc@zhaoxin.com>
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---
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sysdeps/x86_64/multiarch/memmove-ssse3.S | 14 +++++++++-----
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1 file changed, 9 insertions(+), 5 deletions(-)
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diff --git a/sysdeps/x86_64/multiarch/memmove-ssse3.S b/sysdeps/x86_64/multiarch/memmove-ssse3.S
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index 460b0ec0..69561628 100644
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--- a/sysdeps/x86_64/multiarch/memmove-ssse3.S
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+++ b/sysdeps/x86_64/multiarch/memmove-ssse3.S
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@@ -151,13 +151,10 @@ L(more_2x_vec):
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loop. */
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movups %xmm0, (%rdi)
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-# ifdef SHARED_CACHE_SIZE_HALF
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- cmp $SHARED_CACHE_SIZE_HALF, %RDX_LP
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-# else
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- cmp __x86_shared_cache_size_half(%rip), %rdx
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-# endif
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+ cmp __x86_shared_non_temporal_threshold(%rip), %rdx
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ja L(large_memcpy)
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+L(loop_fwd):
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leaq -64(%rdi, %rdx), %r8
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andq $-16, %rdi
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movl $48, %edx
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@@ -199,6 +196,13 @@ L(large_memcpy):
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movups -64(%r9, %rdx), %xmm10
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movups -80(%r9, %rdx), %xmm11
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+ /* Check if src and dst overlap. If they do use cacheable
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+ writes to potentially gain positive interference between
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+ the loads during the memmove. */
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+ subq %rdi, %r9
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+ cmpq %rdx, %r9
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+ jb L(loop_fwd)
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+
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sall $5, %ecx
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leal (%rcx, %rcx, 2), %r8d
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leaq -96(%rdi, %rdx), %rcx
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--
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2.27.0
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