cb3e0b2e06
Signed-off-by: Xie jiamei <xiejiamei@hygon.cn> (cherry picked from commit 9cf451dd6fdd13ec64780b1f56c84778f99449fb)
98 lines
3.3 KiB
Diff
98 lines
3.3 KiB
Diff
From daa15a5bffc436cf7b943b306c85c90ce8bb369e Mon Sep 17 00:00:00 2001
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From: Feifei Wang <wangfeifei@hygon.cn>
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Date: Mon, 19 Aug 2024 14:57:54 +0800
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Subject: [PATCH 02/10] x86: Add cache information support for Hygon processors
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Add hygon branch in dl_init_cacheinfo function to initialize
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cache size variables for hygon processors. In the meanwhile,
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add handle_hygon() function to get cache information.
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Signed-off-by: Feifei Wang <wangfeifei@hygon.cn>
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Reviewed-by: Jing Li <lijing@hygon.cn>
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Reviewed-by: H.J. Lu <hjl.tools@gmail.com>
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---
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sysdeps/x86/dl-cacheinfo.h | 60 ++++++++++++++++++++++++++++++++++++++
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1 file changed, 60 insertions(+)
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diff --git a/sysdeps/x86/dl-cacheinfo.h b/sysdeps/x86/dl-cacheinfo.h
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index 7b5ed210ca..85c404dd26 100644
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--- a/sysdeps/x86/dl-cacheinfo.h
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+++ b/sysdeps/x86/dl-cacheinfo.h
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@@ -567,6 +567,48 @@ handle_zhaoxin (int name)
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return 0;
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}
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+static long int __attribute__ ((noinline))
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+handle_hygon (int name)
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+{
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+ unsigned int eax;
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+ unsigned int ebx;
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+ unsigned int ecx;
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+ unsigned int edx;
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+ unsigned int count = 0x1;
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+
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+ if (name >= _SC_LEVEL3_CACHE_SIZE)
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+ count = 0x3;
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+ else if (name >= _SC_LEVEL2_CACHE_SIZE)
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+ count = 0x2;
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+ else if (name >= _SC_LEVEL1_DCACHE_SIZE)
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+ count = 0x0;
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+
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+ /* Use __cpuid__ '0x8000_001D' to compute cache details. */
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+ __cpuid_count (0x8000001D, count, eax, ebx, ecx, edx);
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+
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+ switch (name)
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+ {
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+ case _SC_LEVEL1_ICACHE_ASSOC:
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+ case _SC_LEVEL1_DCACHE_ASSOC:
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+ case _SC_LEVEL2_CACHE_ASSOC:
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+ case _SC_LEVEL3_CACHE_ASSOC:
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+ return ((ebx >> 22) & 0x3ff) + 1;
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+ case _SC_LEVEL1_ICACHE_LINESIZE:
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+ case _SC_LEVEL1_DCACHE_LINESIZE:
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+ case _SC_LEVEL2_CACHE_LINESIZE:
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+ case _SC_LEVEL3_CACHE_LINESIZE:
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+ return (ebx & 0xfff) + 1;
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+ case _SC_LEVEL1_ICACHE_SIZE:
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+ case _SC_LEVEL1_DCACHE_SIZE:
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+ case _SC_LEVEL2_CACHE_SIZE:
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+ case _SC_LEVEL3_CACHE_SIZE:
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+ return (((ebx >> 22) & 0x3ff) + 1) * ((ebx & 0xfff) + 1) * (ecx + 1);
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+ default:
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+ __builtin_unreachable ();
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+ }
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+ return -1;
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+}
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+
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static void
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get_common_cache_info (long int *shared_ptr, long int * shared_per_thread_ptr, unsigned int *threads_ptr,
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long int core)
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@@ -890,6 +932,24 @@ dl_init_cacheinfo (struct cpu_features *cpu_features)
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shared_per_thread = shared;
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}
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+ else if (cpu_features->basic.kind == arch_kind_hygon)
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+ {
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+ data = handle_hygon (_SC_LEVEL1_DCACHE_SIZE);
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+ shared = handle_hygon (_SC_LEVEL3_CACHE_SIZE);
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+ shared_per_thread = shared;
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+
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+ level1_icache_size = handle_hygon (_SC_LEVEL1_ICACHE_SIZE);
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+ level1_icache_linesize = handle_hygon (_SC_LEVEL1_ICACHE_LINESIZE);
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+ level1_dcache_size = data;
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+ level1_dcache_assoc = handle_hygon (_SC_LEVEL1_DCACHE_ASSOC);
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+ level1_dcache_linesize = handle_hygon (_SC_LEVEL1_DCACHE_LINESIZE);
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+ level2_cache_size = handle_hygon (_SC_LEVEL2_CACHE_SIZE);;
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+ level2_cache_assoc = handle_hygon (_SC_LEVEL2_CACHE_ASSOC);
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+ level2_cache_linesize = handle_hygon (_SC_LEVEL2_CACHE_LINESIZE);
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+ level3_cache_size = shared;
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+ level3_cache_assoc = handle_hygon (_SC_LEVEL3_CACHE_ASSOC);
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+ level3_cache_linesize = handle_hygon (_SC_LEVEL3_CACHE_LINESIZE);
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+ }
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cpu_features->level1_icache_size = level1_icache_size;
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cpu_features->level1_icache_linesize = level1_icache_linesize;
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--
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2.17.1
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