349 lines
9.2 KiB
Diff
349 lines
9.2 KiB
Diff
From 1521237c3211bb0b1a8f7a9c5793d382789b2b68 Mon Sep 17 00:00:00 2001
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From: Wilco Dijkstra <wilco.dijkstra@arm.com>
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Date: Thu, 26 Oct 2023 16:34:47 +0100
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Subject: [PATCH 07/26] AArch64: Cleanup emag memset
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Cleanup emag memset - merge the memset_base64.S file, remove
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the unused ZVA code (since it is disabled on emag).
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Reviewed-by: Adhemerval Zanella <adhemerval.zanella@linaro.org>
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(cherry picked from commit 9627ab99b50d250c6dd3001a3355aa03692f7fe5)
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---
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sysdeps/aarch64/multiarch/ifunc-impl-list.c | 2 +-
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sysdeps/aarch64/multiarch/memset.c | 2 +-
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sysdeps/aarch64/multiarch/memset_base64.S | 185 --------------------
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sysdeps/aarch64/multiarch/memset_emag.S | 98 +++++++++--
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4 files changed, 90 insertions(+), 197 deletions(-)
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delete mode 100644 sysdeps/aarch64/multiarch/memset_base64.S
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diff --git a/sysdeps/aarch64/multiarch/ifunc-impl-list.c b/sysdeps/aarch64/multiarch/ifunc-impl-list.c
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index 836e8317a5..3596d3c8d3 100644
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--- a/sysdeps/aarch64/multiarch/ifunc-impl-list.c
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+++ b/sysdeps/aarch64/multiarch/ifunc-impl-list.c
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@@ -57,7 +57,7 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array,
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/* Enable this on non-falkor processors too so that other cores
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can do a comparative analysis with __memset_generic. */
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IFUNC_IMPL_ADD (array, i, memset, (zva_size == 64), __memset_falkor)
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- IFUNC_IMPL_ADD (array, i, memset, (zva_size == 64), __memset_emag)
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+ IFUNC_IMPL_ADD (array, i, memset, 1, __memset_emag)
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IFUNC_IMPL_ADD (array, i, memset, 1, __memset_kunpeng)
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#if HAVE_AARCH64_SVE_ASM
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IFUNC_IMPL_ADD (array, i, memset, sve && zva_size == 256, __memset_a64fx)
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diff --git a/sysdeps/aarch64/multiarch/memset.c b/sysdeps/aarch64/multiarch/memset.c
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index 23fc66e158..9193b197dd 100644
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--- a/sysdeps/aarch64/multiarch/memset.c
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+++ b/sysdeps/aarch64/multiarch/memset.c
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@@ -56,7 +56,7 @@ select_memset_ifunc (void)
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if ((IS_FALKOR (midr) || IS_PHECDA (midr)) && zva_size == 64)
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return __memset_falkor;
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- if (IS_EMAG (midr) && zva_size == 64)
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+ if (IS_EMAG (midr))
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return __memset_emag;
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return __memset_generic;
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diff --git a/sysdeps/aarch64/multiarch/memset_base64.S b/sysdeps/aarch64/multiarch/memset_base64.S
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deleted file mode 100644
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index 0e8f709fa5..0000000000
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--- a/sysdeps/aarch64/multiarch/memset_base64.S
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+++ /dev/null
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@@ -1,185 +0,0 @@
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-/* Copyright (C) 2018-2023 Free Software Foundation, Inc.
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-
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- This file is part of the GNU C Library.
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-
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- The GNU C Library is free software; you can redistribute it and/or
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- modify it under the terms of the GNU Lesser General Public
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- License as published by the Free Software Foundation; either
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- version 2.1 of the License, or (at your option) any later version.
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-
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- The GNU C Library is distributed in the hope that it will be useful,
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- but WITHOUT ANY WARRANTY; without even the implied warranty of
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- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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- Lesser General Public License for more details.
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-
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- You should have received a copy of the GNU Lesser General Public
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- License along with the GNU C Library. If not, see
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- <https://www.gnu.org/licenses/>. */
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-
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-#include <sysdep.h>
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-#include "memset-reg.h"
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-
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-#ifndef MEMSET
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-# define MEMSET __memset_base64
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-#endif
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-
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-/* To disable DC ZVA, set this threshold to 0. */
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-#ifndef DC_ZVA_THRESHOLD
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-# define DC_ZVA_THRESHOLD 512
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-#endif
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-
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-/* Assumptions:
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- *
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- * ARMv8-a, AArch64, unaligned accesses
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- *
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- */
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-
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-ENTRY (MEMSET)
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-
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- PTR_ARG (0)
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- SIZE_ARG (2)
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-
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- bfi valw, valw, 8, 8
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- bfi valw, valw, 16, 16
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- bfi val, val, 32, 32
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-
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- add dstend, dstin, count
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-
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- cmp count, 96
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- b.hi L(set_long)
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- cmp count, 16
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- b.hs L(set_medium)
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-
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- /* Set 0..15 bytes. */
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- tbz count, 3, 1f
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- str val, [dstin]
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- str val, [dstend, -8]
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- ret
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-
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- .p2align 3
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-1: tbz count, 2, 2f
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- str valw, [dstin]
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- str valw, [dstend, -4]
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- ret
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-2: cbz count, 3f
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- strb valw, [dstin]
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- tbz count, 1, 3f
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- strh valw, [dstend, -2]
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-3: ret
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-
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- .p2align 3
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- /* Set 16..96 bytes. */
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-L(set_medium):
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- stp val, val, [dstin]
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- tbnz count, 6, L(set96)
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- stp val, val, [dstend, -16]
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- tbz count, 5, 1f
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- stp val, val, [dstin, 16]
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- stp val, val, [dstend, -32]
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-1: ret
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-
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- .p2align 4
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- /* Set 64..96 bytes. Write 64 bytes from the start and
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- 32 bytes from the end. */
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-L(set96):
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- stp val, val, [dstin, 16]
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- stp val, val, [dstin, 32]
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- stp val, val, [dstin, 48]
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- stp val, val, [dstend, -32]
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- stp val, val, [dstend, -16]
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- ret
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-
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- .p2align 4
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-L(set_long):
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- stp val, val, [dstin]
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- bic dst, dstin, 15
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-#if DC_ZVA_THRESHOLD
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- cmp count, DC_ZVA_THRESHOLD
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- ccmp val, 0, 0, cs
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- b.eq L(zva_64)
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-#endif
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- /* Small-size or non-zero memset does not use DC ZVA. */
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- sub count, dstend, dst
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-
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- /*
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- * Adjust count and bias for loop. By subtracting extra 1 from count,
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- * it is easy to use tbz instruction to check whether loop tailing
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- * count is less than 33 bytes, so as to bypass 2 unnecessary stps.
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- */
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- sub count, count, 64+16+1
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-
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-#if DC_ZVA_THRESHOLD
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- /* Align loop on 16-byte boundary, this might be friendly to i-cache. */
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- nop
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-#endif
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-
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-1: stp val, val, [dst, 16]
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- stp val, val, [dst, 32]
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- stp val, val, [dst, 48]
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- stp val, val, [dst, 64]!
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- subs count, count, 64
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- b.hs 1b
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-
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- tbz count, 5, 1f /* Remaining count is less than 33 bytes? */
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- stp val, val, [dst, 16]
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- stp val, val, [dst, 32]
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-1: stp val, val, [dstend, -32]
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- stp val, val, [dstend, -16]
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- ret
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-
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-#if DC_ZVA_THRESHOLD
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- .p2align 3
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-L(zva_64):
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- stp val, val, [dst, 16]
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- stp val, val, [dst, 32]
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- stp val, val, [dst, 48]
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- bic dst, dst, 63
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-
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- /*
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- * Previous memory writes might cross cache line boundary, and cause
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- * cache line partially dirty. Zeroing this kind of cache line using
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- * DC ZVA will incur extra cost, for it requires loading untouched
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- * part of the line from memory before zeoring.
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- *
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- * So, write the first 64 byte aligned block using stp to force
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- * fully dirty cache line.
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- */
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- stp val, val, [dst, 64]
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- stp val, val, [dst, 80]
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- stp val, val, [dst, 96]
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- stp val, val, [dst, 112]
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-
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- sub count, dstend, dst
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- /*
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- * Adjust count and bias for loop. By subtracting extra 1 from count,
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- * it is easy to use tbz instruction to check whether loop tailing
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- * count is less than 33 bytes, so as to bypass 2 unnecessary stps.
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- */
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- sub count, count, 128+64+64+1
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- add dst, dst, 128
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- nop
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-
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- /* DC ZVA sets 64 bytes each time. */
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-1: dc zva, dst
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- add dst, dst, 64
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- subs count, count, 64
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- b.hs 1b
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-
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- /*
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- * Write the last 64 byte aligned block using stp to force fully
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- * dirty cache line.
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- */
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- stp val, val, [dst, 0]
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- stp val, val, [dst, 16]
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- stp val, val, [dst, 32]
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- stp val, val, [dst, 48]
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-
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- tbz count, 5, 1f /* Remaining count is less than 33 bytes? */
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- stp val, val, [dst, 64]
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- stp val, val, [dst, 80]
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-1: stp val, val, [dstend, -32]
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- stp val, val, [dstend, -16]
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- ret
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-#endif
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-
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-END (MEMSET)
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diff --git a/sysdeps/aarch64/multiarch/memset_emag.S b/sysdeps/aarch64/multiarch/memset_emag.S
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index 6fecad4fae..bbfa815925 100644
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--- a/sysdeps/aarch64/multiarch/memset_emag.S
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+++ b/sysdeps/aarch64/multiarch/memset_emag.S
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@@ -18,17 +18,95 @@
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<https://www.gnu.org/licenses/>. */
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#include <sysdep.h>
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+#include "memset-reg.h"
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-#define MEMSET __memset_emag
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-
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-/*
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- * Using DC ZVA to zero memory does not produce better performance if
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- * memory size is not very large, especially when there are multiple
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- * processes/threads contending memory/cache. Here we set threshold to
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- * zero to disable using DC ZVA, which is good for multi-process/thread
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- * workloads.
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+/* Assumptions:
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+ *
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+ * ARMv8-a, AArch64, unaligned accesses
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+ *
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*/
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-#define DC_ZVA_THRESHOLD 0
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+ENTRY (__memset_emag)
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+
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+ PTR_ARG (0)
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+ SIZE_ARG (2)
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+
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+ bfi valw, valw, 8, 8
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+ bfi valw, valw, 16, 16
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+ bfi val, val, 32, 32
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+
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+ add dstend, dstin, count
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+
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+ cmp count, 96
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+ b.hi L(set_long)
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+ cmp count, 16
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+ b.hs L(set_medium)
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+
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+ /* Set 0..15 bytes. */
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+ tbz count, 3, 1f
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+ str val, [dstin]
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+ str val, [dstend, -8]
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+ ret
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+
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+ .p2align 3
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+1: tbz count, 2, 2f
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+ str valw, [dstin]
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+ str valw, [dstend, -4]
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+ ret
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+2: cbz count, 3f
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+ strb valw, [dstin]
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+ tbz count, 1, 3f
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+ strh valw, [dstend, -2]
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+3: ret
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+
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+ .p2align 3
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+ /* Set 16..96 bytes. */
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+L(set_medium):
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+ stp val, val, [dstin]
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+ tbnz count, 6, L(set96)
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+ stp val, val, [dstend, -16]
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+ tbz count, 5, 1f
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+ stp val, val, [dstin, 16]
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+ stp val, val, [dstend, -32]
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+1: ret
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+
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+ .p2align 4
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+ /* Set 64..96 bytes. Write 64 bytes from the start and
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+ 32 bytes from the end. */
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+L(set96):
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+ stp val, val, [dstin, 16]
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+ stp val, val, [dstin, 32]
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+ stp val, val, [dstin, 48]
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+ stp val, val, [dstend, -32]
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+ stp val, val, [dstend, -16]
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+ ret
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+
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+ .p2align 4
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+L(set_long):
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+ stp val, val, [dstin]
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+ bic dst, dstin, 15
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+ /* Small-size or non-zero memset does not use DC ZVA. */
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+ sub count, dstend, dst
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+
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+ /*
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+ * Adjust count and bias for loop. By subtracting extra 1 from count,
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+ * it is easy to use tbz instruction to check whether loop tailing
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+ * count is less than 33 bytes, so as to bypass 2 unnecessary stps.
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+ */
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+ sub count, count, 64+16+1
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+
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+1: stp val, val, [dst, 16]
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+ stp val, val, [dst, 32]
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+ stp val, val, [dst, 48]
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+ stp val, val, [dst, 64]!
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+ subs count, count, 64
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+ b.hs 1b
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+
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+ tbz count, 5, 1f /* Remaining count is less than 33 bytes? */
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+ stp val, val, [dst, 16]
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+ stp val, val, [dst, 32]
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+1: stp val, val, [dstend, -32]
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+ stp val, val, [dstend, -16]
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+ ret
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-#include "./memset_base64.S"
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+END (__memset_emag)
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--
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2.33.0
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