77 lines
2.3 KiB
Diff
77 lines
2.3 KiB
Diff
From 8fac691bbaaf60690902e585290bb88e060cc85a Mon Sep 17 00:00:00 2001
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From: Xi Ruoyao <xry111@xry111.site>
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Date: Thu, 13 Jun 2024 19:04:05 +0800
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Subject: [PATCH 07/15] LoongArch: Ensure sp 16-byte aligned for tlsdesc
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"ADDI sp, sp, 24" and "ADDI sp, sp, SZFCSREG" (SZFCSREG = 4) are
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misaligning the stack: the ABI mandates a 16-byte alignment. Fix it
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by changing the first one to "ADDI sp, sp, 32", and reuse the spare 4th
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slot for saving fcsr.
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Reported-by: Jinyang He <hejinyang@loongson.cn>
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Signed-off-by: Xi Ruoyao <xry111@xry111.site>
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---
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sysdeps/loongarch/dl-tlsdesc.S | 10 ++++------
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sysdeps/loongarch/sys/asm.h | 1 -
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2 files changed, 4 insertions(+), 7 deletions(-)
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diff --git a/sysdeps/loongarch/dl-tlsdesc.S b/sysdeps/loongarch/dl-tlsdesc.S
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index 15d5fa1c..346b80f2 100644
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--- a/sysdeps/loongarch/dl-tlsdesc.S
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+++ b/sysdeps/loongarch/dl-tlsdesc.S
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@@ -100,7 +100,7 @@ _dl_tlsdesc_undefweak:
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_dl_tlsdesc_dynamic:
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/* Save just enough registers to support fast path, if we fall
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into slow path we will save additional registers. */
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- ADDI sp, sp, -24
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+ ADDI sp, sp, -32
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REG_S t0, sp, 0
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REG_S t1, sp, 8
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REG_S t2, sp, 16
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@@ -141,7 +141,7 @@ Hign address dynamic_block1 <----- dtv5 */
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REG_L t0, sp, 0
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REG_L t1, sp, 8
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REG_L t2, sp, 16
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- ADDI sp, sp, 24
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+ ADDI sp, sp, 32
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RET
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.Lslow:
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@@ -171,9 +171,8 @@ Hign address dynamic_block1 <----- dtv5 */
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/* Save fcsr0 register.
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Only one physical fcsr0 register, fcsr1-fcsr3 are aliases
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of some fields in fcsr0. */
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- ADDI sp, sp, -SZFCSREG
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movfcsr2gr t0, fcsr0
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- st.w t0, sp, 0
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+ st.w t0, sp, FRAME_SIZE + 24 /* Use the spare slot above t2 */
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/* Whether support LASX. */
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la.global t0, _rtld_global_ro
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@@ -406,9 +405,8 @@ Hign address dynamic_block1 <----- dtv5 */
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.Lfcsr:
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/* Restore fcsr0 register. */
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- ld.w t0, sp, 0
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+ ld.w t0, sp, FRAME_SIZE + 24
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movgr2fcsr fcsr0, t0
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- ADDI sp, sp, SZFCSREG
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#endif /* #ifndef __loongarch_soft_float */
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diff --git a/sysdeps/loongarch/sys/asm.h b/sysdeps/loongarch/sys/asm.h
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index dbee93ee..c5eb8afa 100644
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--- a/sysdeps/loongarch/sys/asm.h
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+++ b/sysdeps/loongarch/sys/asm.h
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@@ -25,7 +25,6 @@
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/* Macros to handle different pointer/register sizes for 32/64-bit code. */
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#define SZREG 8
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#define SZFREG 8
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-#define SZFCSREG 4
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#define SZVREG 16
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#define SZXREG 32
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#define REG_L ld.d
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--
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2.43.0
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