3225aed4dd
Signed-off-by: May <mayshao-oc@zhaoxin.com> (cherry picked from commit c4f135bfbc5d7fc8b2471ce71997067e4441662e)
51 lines
2.2 KiB
Diff
51 lines
2.2 KiB
Diff
From 6374dceef2bf72456144184cb70bdd216a744d61 Mon Sep 17 00:00:00 2001
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From: May <mayshao-oc@zhaoxin.com>
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Date: Wed, 15 Jan 2025 10:42:33 +0800
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Subject: [PATCH 3/3] x86: Set default non_temporal_threshold for Zhaoxin
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processors
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Current 'non_temporal_threshold' set to 'non_temporal_threshold_lowbound'
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on Zhaoxin processors without ERMS. The default
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'non_temporal_threshold_lowbound' is too small for the KH-40000 and KX-7000
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Zhaoxin processors, this patch updates the value to
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'shared / cachesize_non_temporal_divisor'.
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Signed-off-by: May <mayshao-oc@zhaoxin.com>
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---
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sysdeps/x86/cpu-features.c | 1 +
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sysdeps/x86/dl-cacheinfo.h | 6 ++++--
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2 files changed, 5 insertions(+), 2 deletions(-)
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diff --git a/sysdeps/x86/cpu-features.c b/sysdeps/x86/cpu-features.c
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index 43b5f562..f752ebd2 100644
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--- a/sysdeps/x86/cpu-features.c
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+++ b/sysdeps/x86/cpu-features.c
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@@ -949,6 +949,7 @@ https://www.intel.com/content/www/us/en/support/articles/000059422/processors.ht
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/* Yongfeng and Shijidadao mircoarch tuning. */
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case 0x5b:
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+ cpu_features->cachesize_non_temporal_divisor = 2;
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case 0x6b:
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cpu_features->preferred[index_arch_AVX_Fast_Unaligned_Load]
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&= ~bit_arch_AVX_Fast_Unaligned_Load;
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diff --git a/sysdeps/x86/dl-cacheinfo.h b/sysdeps/x86/dl-cacheinfo.h
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index 6c774042..bd2a9122 100644
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--- a/sysdeps/x86/dl-cacheinfo.h
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+++ b/sysdeps/x86/dl-cacheinfo.h
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@@ -940,8 +940,10 @@ dl_init_cacheinfo (struct cpu_features *cpu_features)
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/* If no ERMS, we use the per-thread L3 chunking. Normal cacheable stores run
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a higher risk of actually thrashing the cache as they don't have a HW LRU
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hint. As well, their performance in highly parallel situations is
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- noticeably worse. */
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- if (!CPU_FEATURE_USABLE_P (cpu_features, ERMS))
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+ noticeably worse. Zhaoxin processors are an exception, the lowbound is not
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+ suitable for them based on actual test data. */
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+ if (!CPU_FEATURE_USABLE_P (cpu_features, ERMS)
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+ && cpu_features->basic.kind != arch_kind_zhaoxin)
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non_temporal_threshold = non_temporal_threshold_lowbound;
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/* SIZE_MAX >> 4 because memmove-vec-unaligned-erms right-shifts the value of
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'x86_non_temporal_threshold' by `LOG_4X_MEMCPY_THRESH` (4) and it is best
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--
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2.27.0
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