cb3e0b2e06
Signed-off-by: Xie jiamei <xiejiamei@hygon.cn> (cherry picked from commit 9cf451dd6fdd13ec64780b1f56c84778f99449fb)
96 lines
3.9 KiB
Diff
96 lines
3.9 KiB
Diff
From 01b5cac929a3be361dd575bed6673c40a25a6d61 Mon Sep 17 00:00:00 2001
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From: Noah Goldstein <goldstein.w.n@gmail.com>
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Date: Wed, 14 Aug 2024 14:37:30 +0800
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Subject: [PATCH 08/10] x86: Use `Avoid_Non_Temporal_Memset` to control
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non-temporal path
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This is just a refactor and there should be no behavioral change from
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this commit.
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The goal is to make `Avoid_Non_Temporal_Memset` a more universal knob
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for controlling whether we use non-temporal memset rather than having
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extra logic based on vendor.
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Reviewed-by: H.J. Lu <hjl.tools@gmail.com>
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---
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sysdeps/x86/cpu-features.c | 16 ++++++++++++++++
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sysdeps/x86/dl-cacheinfo.h | 15 +++++++--------
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2 files changed, 23 insertions(+), 8 deletions(-)
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diff --git a/sysdeps/x86/cpu-features.c b/sysdeps/x86/cpu-features.c
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index b4030776a7..c9f2297524 100644
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--- a/sysdeps/x86/cpu-features.c
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+++ b/sysdeps/x86/cpu-features.c
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@@ -640,6 +640,12 @@ init_cpu_features (struct cpu_features *cpu_features)
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unsigned int stepping = 0;
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enum cpu_features_kind kind;
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+ /* Default is avoid non-temporal memset for non Intel/AMD hardware. This is,
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+ as of writing this, we only have benchmarks indicatings it profitability
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+ on Intel/AMD. */
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+ cpu_features->preferred[index_arch_Avoid_Non_Temporal_Memset]
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+ |= bit_arch_Avoid_Non_Temporal_Memset;
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+
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cpu_features->cachesize_non_temporal_divisor = 4;
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#if !HAS_CPUID
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if (__get_cpuid_max (0, 0) == 0)
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@@ -665,6 +671,11 @@ init_cpu_features (struct cpu_features *cpu_features)
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update_active (cpu_features);
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+ /* Benchmarks indicate non-temporal memset can be profitable on Intel
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+ hardware. */
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+ cpu_features->preferred[index_arch_Avoid_Non_Temporal_Memset]
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+ &= ~bit_arch_Avoid_Non_Temporal_Memset;
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+
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if (family == 0x06)
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{
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model += extended_model;
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@@ -874,6 +885,11 @@ https://www.intel.com/content/www/us/en/support/articles/000059422/processors.ht
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ecx = cpu_features->features[CPUID_INDEX_1].cpuid.ecx;
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+ /* Benchmarks indicate non-temporal memset can be profitable on AMD
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+ hardware. */
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+ cpu_features->preferred[index_arch_Avoid_Non_Temporal_Memset]
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+ &= ~bit_arch_Avoid_Non_Temporal_Memset;
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+
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if (CPU_FEATURE_USABLE_P (cpu_features, AVX))
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{
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/* Since the FMA4 bit is in CPUID_INDEX_80000001 and
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diff --git a/sysdeps/x86/dl-cacheinfo.h b/sysdeps/x86/dl-cacheinfo.h
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index de4584116f..d8288f0b0c 100644
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--- a/sysdeps/x86/dl-cacheinfo.h
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+++ b/sysdeps/x86/dl-cacheinfo.h
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@@ -1048,14 +1048,6 @@ dl_init_cacheinfo (struct cpu_features *cpu_features)
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if (CPU_FEATURE_USABLE_P (cpu_features, FSRM))
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rep_movsb_threshold = 2112;
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- /* Non-temporal stores are more performant on Intel and AMD hardware above
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- non_temporal_threshold. Enable this for both Intel and AMD hardware. */
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- unsigned long int memset_non_temporal_threshold = SIZE_MAX;
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- if (!CPU_FEATURES_ARCH_P (cpu_features, Avoid_Non_Temporal_Memset)
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- && (cpu_features->basic.kind == arch_kind_intel
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- || cpu_features->basic.kind == arch_kind_amd))
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- memset_non_temporal_threshold = non_temporal_threshold;
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-
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/* For AMD CPUs that support ERMS (Zen3+), REP MOVSB is in a lot of
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cases slower than the vectorized path (and for some alignments,
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it is really slow, check BZ #30994). */
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@@ -1077,6 +1069,13 @@ dl_init_cacheinfo (struct cpu_features *cpu_features)
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if (tunable_size != 0)
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shared = tunable_size;
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+ /* Non-temporal stores are more performant on some hardware above
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+ non_temporal_threshold. Currently Prefer_Non_Temporal is set for for both
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+ Intel and AMD hardware. */
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+ unsigned long int memset_non_temporal_threshold = SIZE_MAX;
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+ if (!CPU_FEATURES_ARCH_P (cpu_features, Avoid_Non_Temporal_Memset))
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+ memset_non_temporal_threshold = non_temporal_threshold;
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+
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tunable_size = TUNABLE_GET (x86_non_temporal_threshold, long int, NULL);
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if (tunable_size > minimum_non_temporal_threshold
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&& tunable_size <= maximum_non_temporal_threshold)
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--
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2.17.1
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