From 2abad8896fef244c5513d266184a1bfa32a5f509 Mon Sep 17 00:00:00 2001 From: swcompiler Date: Fri, 29 Nov 2024 13:39:58 +0800 Subject: [PATCH 02/23] Sw64: Add relocations and ELF flags to elf.h and script/glibcelf.py --- elf/elf.h | 79 +++++++++++++++++++++++++++++++++++++++++++++ scripts/glibcelf.py | 10 ++++++ 2 files changed, 89 insertions(+) diff --git a/elf/elf.h b/elf/elf.h index 89fc8021..33a5e97b 100644 --- a/elf/elf.h +++ b/elf/elf.h @@ -371,6 +372,10 @@ typedef struct chances of collision with official or non-GNU unofficial values. */ #define EM_ALPHA 0x9026 +#define EM_SW_64 0x9916 + + + /* Legal values for e_version (version). */ @@ -2426,6 +2431,80 @@ enum /* Legal values for d_tag of Elf64_Dyn. */ #define DT_ALPHA_PLTRO (DT_LOPROC + 0) #define DT_ALPHA_NUM 1 +/* SW_64 specific definitions. */ + +/* Legal values for e_flags field of Elf64_Ehdr. */ + +#define EF_SW_64_32BIT 1 /* All addresses must be < 2GB. */ +#define EF_SW_64_CANRELAX 2 /* Relocations for relaxing exist. */ + +/* Legal values for sh_type field of Elf64_Shdr. */ + +/* These two are primerily concerned with ECOFF debugging info. */ +#define SHT_SW_64_DEBUG 0x70000001 +#define SHT_SW_64_REGINFO 0x70000002 + +/* Legal values for sh_flags field of Elf64_Shdr. */ + +#define SHF_SW_64_GPREL 0x10000000 + +/* Legal values for st_other field of Elf64_Sym. */ +#define STO_SW_64_NOPV 0x80 /* No PV required. */ +#define STO_SW_64_STD_GPLOAD 0x88 /* PV only used for initial ldgp. */ + +/* SW_64 relocs. */ + +#define R_SW_64_NONE 0 /* No reloc */ +#define R_SW_64_REFLONG 1 /* Direct 32 bit */ +#define R_SW_64_REFQUAD 2 /* Direct 64 bit */ +#define R_SW_64_GPREL32 3 /* GP relative 32 bit */ +#define R_SW_64_LITERAL 4 /* GP relative 16 bit w/optimization */ +#define R_SW_64_LITUSE 5 /* Optimization hint for LITERAL */ +#define R_SW_64_GPDISP 6 /* Add displacement to GP */ +#define R_SW_64_BRADDR 7 /* PC+4 relative 23 bit shifted */ +#define R_SW_64_HINT 8 /* PC+4 relative 16 bit shifted */ +#define R_SW_64_SREL16 9 /* PC relative 16 bit */ +#define R_SW_64_SREL32 10 /* PC relative 32 bit */ +#define R_SW_64_SREL64 11 /* PC relative 64 bit */ +#define R_SW_64_GPRELHIGH 17 /* GP relative 32 bit, high 16 bits */ +#define R_SW_64_GPRELLOW 18 /* GP relative 32 bit, low 16 bits */ +#define R_SW_64_GPREL16 19 /* GP relative 16 bit */ +#define R_SW_64_COPY 24 /* Copy symbol at runtime */ +#define R_SW_64_GLOB_DAT 25 /* Create GOT entry */ +#define R_SW_64_JMP_SLOT 26 /* Create PLT entry */ +#define R_SW_64_RELATIVE 27 /* Adjust by program base */ +#define R_SW_64_TLS_GD_HI 28 +#define R_SW_64_TLSGD 29 +#define R_SW_64_TLS_LDM 30 +#define R_SW_64_DTPMOD64 31 +#define R_SW_64_GOTDTPREL 32 +#define R_SW_64_DTPREL64 33 +#define R_SW_64_DTPRELHI 34 +#define R_SW_64_DTPRELLO 35 +#define R_SW_64_DTPREL16 36 +#define R_SW_64_GOTTPREL 37 +#define R_SW_64_TPREL64 38 +#define R_SW_64_TPRELHI 39 +#define R_SW_64_TPRELLO 40 +#define R_SW_64_TPREL16 41 +/* Keep this the last entry. */ +#define R_SW_64_NUM 46 + +/* Magic values of the LITUSE relocation addend. */ +#define LITUSE_SW_64_ADDR 0 +#define LITUSE_SW_64_BASE 1 +#define LITUSE_SW_64_BYTOFF 2 +#define LITUSE_SW_64_JSR 3 +#define LITUSE_SW_64_TLS_GD 4 +#define LITUSE_SW_64_TLS_LDM 5 + +/* Legal values for d_tag of Elf64_Dyn. */ +#define DT_SW_64_PLTRO (DT_LOPROC + 0) +#define DT_SW_64_NUM 1 + + + + /* PowerPC specific declarations */ diff --git a/scripts/glibcelf.py b/scripts/glibcelf.py index b52e83d6..2c191afa 100644 --- a/scripts/glibcelf.py +++ b/scripts/glibcelf.py @@ -304,6 +304,8 @@ class Sht(_TypedConstant): prefix = 'SHT_' class ShtALPHA(Sht): """Supplemental SHT_* constants for EM_ALPHA.""" +class ShtSW_64(Sht): + """Supplemental SHT_* constants for EM_SW_64.""" class ShtARC(Sht): """Supplemental SHT_* constants for EM_ARC.""" class ShtARM(Sht): @@ -319,6 +321,7 @@ class ShtPARISC(Sht): class ShtRISCV(Sht): """Supplemental SHT_* constants for EM_RISCV.""" _register_elf_h(ShtALPHA, prefix='SHT_ALPHA_', parent=Sht) +_register_elf_h(ShtSW_64, prefix='SHT_SW_64_', parent=Sht) _register_elf_h(ShtARC, prefix='SHT_ARC_', parent=Sht) _register_elf_h(ShtARM, prefix='SHT_ARM_', parent=Sht) _register_elf_h(ShtCSKY, prefix='SHT_CSKY_', parent=Sht) @@ -354,6 +357,8 @@ class Shf(_FlagConstant): prefix = 'SHF_' class ShfALPHA(Shf): """Supplemental SHF_* constants for EM_ALPHA.""" +class ShfSW_64(Shf): + """Supplemental SHF_* constants for EM_SW_64.""" class ShfARM(Shf): """Supplemental SHF_* constants for EM_ARM.""" class ShfIA_64(Shf): @@ -363,6 +368,7 @@ class ShfMIPS(Shf): class ShfPARISC(Shf): """Supplemental SHF_* constants for EM_PARISC.""" _register_elf_h(ShfALPHA, prefix='SHF_ALPHA_', parent=Shf) +_register_elf_h(ShfSW_64, prefix='SHF_SW_64_', parent=Shf) _register_elf_h(ShfARM, prefix='SHF_ARM_', parent=Shf) _register_elf_h(ShfIA_64, prefix='SHF_IA_64_', parent=Shf) _register_elf_h(ShfMIPS, prefix='SHF_MIPS_', parent=Shf) @@ -425,6 +431,8 @@ class DtAARCH64(Dt): """Supplemental DT_* constants for EM_AARCH64.""" class DtALPHA(Dt): """Supplemental DT_* constants for EM_ALPHA.""" +class DtSW_64(Dt): + """Supplemental DT_* constants for EM_SW_64.""" class DtALTERA_NIOS2(Dt): """Supplemental DT_* constants for EM_ALTERA_NIOS2.""" class DtIA_64(Dt): @@ -446,6 +454,7 @@ DT_VALRNGLO DT_VALRNGHI DT_VALNUM DT_VERSIONTAGNUM DT_EXTRANUM DT_AARCH64_NUM DT_ALPHA_NUM +DT_SW_64_NUM DT_IA_64_NUM DT_MIPS_NUM DT_PPC_NUM @@ -454,6 +463,7 @@ DT_SPARC_NUM '''.strip().split() _register_elf_h(DtAARCH64, prefix='DT_AARCH64_', skip=_dt_skip, parent=Dt) _register_elf_h(DtALPHA, prefix='DT_ALPHA_', skip=_dt_skip, parent=Dt) +_register_elf_h(DtSW_64, prefix='DT_SW_64_', skip=_dt_skip, parent=Dt) _register_elf_h(DtALTERA_NIOS2, prefix='DT_NIOS2_', skip=_dt_skip, parent=Dt) _register_elf_h(DtIA_64, prefix='DT_IA_64_', skip=_dt_skip, parent=Dt) _register_elf_h(DtMIPS, prefix='DT_MIPS_', skip=_dt_skip, parent=Dt) -- 2.25.1