48 lines
1.9 KiB
Diff
48 lines
1.9 KiB
Diff
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From 54e99a96ec3b97f53ee018bfa8dbbef2dd13f1e8 Mon Sep 17 00:00:00 2001
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From: Joe Damato <jdamato@fastly.com>
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Date: Fri, 7 Jun 2024 23:04:47 +0000
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Subject: [PATCH 05/10] x86: Enable non-temporal memset tunable for AMD
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In commit 46b5e98ef6f1 ("x86: Add seperate non-temporal tunable for
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memset") a tunable threshold for enabling non-temporal memset was added,
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but only for Intel hardware.
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Since that commit, new benchmark results suggest that non-temporal
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memset is beneficial on AMD, as well, so allow this tunable to be set
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for AMD.
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See:
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https://docs.google.com/spreadsheets/d/1opzukzvum4n6-RUVHTGddV6RjAEil4P2uMjjQGLbLcU/edit?usp=sharing
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which has been updated to include data using different stategies for
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large memset on AMD Zen2, Zen3, and Zen4.
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Signed-off-by: Joe Damato <jdamato@fastly.com>
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Reviewed-by: Noah Goldstein <goldstein.w.n@gmail.com>
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---
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sysdeps/x86/dl-cacheinfo.h | 8 ++++----
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1 file changed, 4 insertions(+), 4 deletions(-)
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diff --git a/sysdeps/x86/dl-cacheinfo.h b/sysdeps/x86/dl-cacheinfo.h
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index 9f27da21ce..dfdb4069c7 100644
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--- a/sysdeps/x86/dl-cacheinfo.h
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+++ b/sysdeps/x86/dl-cacheinfo.h
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@@ -1048,11 +1048,11 @@ dl_init_cacheinfo (struct cpu_features *cpu_features)
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if (CPU_FEATURE_USABLE_P (cpu_features, FSRM))
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rep_movsb_threshold = 2112;
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- /* Non-temporal stores in memset have only been tested on Intel hardware.
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- Until we benchmark data on other x86 processor, disable non-temporal
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- stores in memset. */
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+ /* Non-temporal stores are more performant on Intel and AMD hardware above
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+ non_temporal_threshold. Enable this for both Intel and AMD hardware. */
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unsigned long int memset_non_temporal_threshold = SIZE_MAX;
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- if (cpu_features->basic.kind == arch_kind_intel)
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+ if (cpu_features->basic.kind == arch_kind_intel
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+ || cpu_features->basic.kind == arch_kind_amd)
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memset_non_temporal_threshold = non_temporal_threshold;
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/* For AMD CPUs that support ERMS (Zen3+), REP MOVSB is in a lot of
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--
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2.17.1
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