35 lines
1.2 KiB
Diff
35 lines
1.2 KiB
Diff
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From 5a64f933655384477d85122c6855dc6d84061810 Mon Sep 17 00:00:00 2001
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From: Noah Goldstein <goldstein.w.n@gmail.com>
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Date: Wed, 1 Nov 2023 15:30:26 -0500
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Subject: [PATCH] x86: Only align destination to 1x VEC_SIZE in memset 4x
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loop
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Current code aligns to 2x VEC_SIZE. Aligning to 2x has no affect on
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performance other than potentially resulting in an additional
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iteration of the loop.
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1x maintains aligned stores (the only reason to align in this case)
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and doesn't incur any unnecessary loop iterations.
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Reviewed-by: Sunil K Pandey <skpgkp2@gmail.com>
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(cherry picked from commit 9469261cf1924d350feeec64d2c80cafbbdcdd4d)
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---
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sysdeps/x86_64/multiarch/memset-vec-unaligned-erms.S | 2 +-
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1 file changed, 1 insertion(+), 1 deletion(-)
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diff --git a/sysdeps/x86_64/multiarch/memset-vec-unaligned-erms.S b/sysdeps/x86_64/multiarch/memset-vec-unaligned-erms.S
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index 3d9ad49cb9..0f0636b90f 100644
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--- a/sysdeps/x86_64/multiarch/memset-vec-unaligned-erms.S
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+++ b/sysdeps/x86_64/multiarch/memset-vec-unaligned-erms.S
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@@ -293,7 +293,7 @@ L(more_2x_vec):
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leaq (VEC_SIZE * 4)(%rax), %LOOP_REG
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#endif
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/* Align dst for loop. */
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- andq $(VEC_SIZE * -2), %LOOP_REG
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+ andq $(VEC_SIZE * -1), %LOOP_REG
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.p2align 4
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L(loop):
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VMOVA %VMM(0), LOOP_4X_OFFSET(%LOOP_REG)
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--
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2.27.0
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