159 lines
5.5 KiB
Diff
159 lines
5.5 KiB
Diff
From 52a41006c2e8141a42de93ffcc2c040e034244b2 Mon Sep 17 00:00:00 2001
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From: Lulu Cheng <chenglulu@loongson.cn>
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Date: Wed, 16 Nov 2022 09:25:14 +0800
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Subject: [PATCH 031/124] LoongArch: Add prefetch instructions.
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Enable sw prefetching at -O3 and higher.
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Co-Authored-By: xujiahao <xujiahao@loongson.cn>
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gcc/ChangeLog:
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* config/loongarch/constraints.md (ZD): New constraint.
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* config/loongarch/loongarch-def.c: Initial number of parallel prefetch.
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* config/loongarch/loongarch-tune.h (struct loongarch_cache):
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Define number of parallel prefetch.
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* config/loongarch/loongarch.cc (loongarch_option_override_internal):
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Set up parameters to be used in prefetching algorithm.
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* config/loongarch/loongarch.md (prefetch): New template.
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Signed-off-by: Peng Fan <fanpeng@loongson.cn>
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Signed-off-by: ticat_fp <fanpeng@loongson.cn>
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---
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gcc/config/loongarch/constraints.md | 10 ++++++++++
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gcc/config/loongarch/loongarch-def.c | 2 ++
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gcc/config/loongarch/loongarch-tune.h | 1 +
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gcc/config/loongarch/loongarch.cc | 28 +++++++++++++++++++++++++++
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gcc/config/loongarch/loongarch.md | 14 ++++++++++++++
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5 files changed, 55 insertions(+)
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diff --git a/gcc/config/loongarch/constraints.md b/gcc/config/loongarch/constraints.md
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index 43cb7b5f0..46f7f63ae 100644
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--- a/gcc/config/loongarch/constraints.md
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+++ b/gcc/config/loongarch/constraints.md
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@@ -86,6 +86,10 @@
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;; "ZB"
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;; "An address that is held in a general-purpose register.
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;; The offset is zero"
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+;; "ZD"
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+;; "An address operand whose address is formed by a base register
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+;; and offset that is suitable for use in instructions with the same
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+;; addressing mode as @code{preld}."
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;; "<" "Matches a pre-dec or post-dec operand." (Global non-architectural)
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;; ">" "Matches a pre-inc or post-inc operand." (Global non-architectural)
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@@ -190,3 +194,9 @@
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The offset is zero"
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(and (match_code "mem")
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(match_test "REG_P (XEXP (op, 0))")))
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+
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+(define_address_constraint "ZD"
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+ "An address operand whose address is formed by a base register
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+ and offset that is suitable for use in instructions with the same
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+ addressing mode as @code{preld}."
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+ (match_test "loongarch_12bit_offset_address_p (op, mode)"))
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diff --git a/gcc/config/loongarch/loongarch-def.c b/gcc/config/loongarch/loongarch-def.c
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index cbf995d81..80ab10a52 100644
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--- a/gcc/config/loongarch/loongarch-def.c
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+++ b/gcc/config/loongarch/loongarch-def.c
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@@ -62,11 +62,13 @@ loongarch_cpu_cache[N_TUNE_TYPES] = {
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.l1d_line_size = 64,
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.l1d_size = 64,
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.l2d_size = 256,
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+ .simultaneous_prefetches = 4,
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},
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[CPU_LA464] = {
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.l1d_line_size = 64,
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.l1d_size = 64,
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.l2d_size = 256,
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+ .simultaneous_prefetches = 4,
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},
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};
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diff --git a/gcc/config/loongarch/loongarch-tune.h b/gcc/config/loongarch/loongarch-tune.h
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index 6f3530f5c..8e3eb2947 100644
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--- a/gcc/config/loongarch/loongarch-tune.h
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+++ b/gcc/config/loongarch/loongarch-tune.h
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@@ -45,6 +45,7 @@ struct loongarch_cache {
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int l1d_line_size; /* bytes */
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int l1d_size; /* KiB */
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int l2d_size; /* kiB */
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+ int simultaneous_prefetches; /* number of parallel prefetch */
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};
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#endif /* LOONGARCH_TUNE_H */
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diff --git a/gcc/config/loongarch/loongarch.cc b/gcc/config/loongarch/loongarch.cc
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index d552b162a..622c9435b 100644
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--- a/gcc/config/loongarch/loongarch.cc
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+++ b/gcc/config/loongarch/loongarch.cc
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@@ -63,6 +63,7 @@ along with GCC; see the file COPYING3. If not see
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#include "context.h"
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#include "builtins.h"
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#include "rtl-iter.h"
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+#include "opts.h"
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/* This file should be included last. */
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#include "target-def.h"
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@@ -6099,6 +6100,33 @@ loongarch_option_override_internal (struct gcc_options *opts)
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if (loongarch_branch_cost == 0)
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loongarch_branch_cost = loongarch_cost->branch_cost;
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+ /* Set up parameters to be used in prefetching algorithm. */
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+ int simultaneous_prefetches
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+ = loongarch_cpu_cache[LARCH_ACTUAL_TUNE].simultaneous_prefetches;
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+
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+ SET_OPTION_IF_UNSET (opts, &global_options_set,
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+ param_simultaneous_prefetches,
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+ simultaneous_prefetches);
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+
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+ SET_OPTION_IF_UNSET (opts, &global_options_set,
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+ param_l1_cache_line_size,
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+ loongarch_cpu_cache[LARCH_ACTUAL_TUNE].l1d_line_size);
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+
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+ SET_OPTION_IF_UNSET (opts, &global_options_set,
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+ param_l1_cache_size,
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+ loongarch_cpu_cache[LARCH_ACTUAL_TUNE].l1d_size);
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+
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+ SET_OPTION_IF_UNSET (opts, &global_options_set,
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+ param_l2_cache_size,
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+ loongarch_cpu_cache[LARCH_ACTUAL_TUNE].l2d_size);
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+
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+
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+ /* Enable sw prefetching at -O3 and higher. */
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+ if (opts->x_flag_prefetch_loop_arrays < 0
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+ && (opts->x_optimize >= 3 || opts->x_flag_profile_use)
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+ && !opts->x_optimize_size)
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+ opts->x_flag_prefetch_loop_arrays = 1;
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+
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if (TARGET_DIRECT_EXTERN_ACCESS && flag_shlib)
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error ("%qs cannot be used for compiling a shared library",
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"-mdirect-extern-access");
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diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loongarch.md
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index 682ab9617..2fda53819 100644
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--- a/gcc/config/loongarch/loongarch.md
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+++ b/gcc/config/loongarch/loongarch.md
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@@ -3282,6 +3282,20 @@
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;; ....................
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;;
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+(define_insn "prefetch"
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+ [(prefetch (match_operand 0 "address_operand" "ZD")
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+ (match_operand 1 "const_int_operand" "n")
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+ (match_operand 2 "const_int_operand" "n"))]
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+ ""
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+{
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+ switch (INTVAL (operands[1]))
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+ {
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+ case 0: return "preld\t0,%a0";
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+ case 1: return "preld\t8,%a0";
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+ default: gcc_unreachable ();
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+ }
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+})
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+
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(define_insn "nop"
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[(const_int 0)]
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""
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--
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2.33.0
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