103 lines
3.4 KiB
Diff
103 lines
3.4 KiB
Diff
From f69237e2e7d129e680fc0bd6a79c53aa193f2ef0 Mon Sep 17 00:00:00 2001
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From: Xi Ruoyao <xry111@xry111.site>
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Date: Wed, 6 Jul 2022 23:22:29 +0800
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Subject: [PATCH 002/124] loongarch: avoid unnecessary sign-extend after 32-bit
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division
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Like add.w/sub.w/mul.w, div.w/mod.w/div.wu/mod.wu also sign-extend the
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output on LA64. But, LoongArch v1.00 mandates that the inputs of 32-bit
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division to be sign-extended so we have to expand 32-bit division into
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RTL sequences.
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We defined div.w/mod.w/div.wu/mod.wu as a (DI, DI) -> SI instruction.
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This definition does not indicate the fact that these instructions will
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store the result as sign-extended value in a 64-bit GR. Then the
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compiler would emit unnecessary sign-extend operations. For example:
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int div(int a, int b) { return a / b; }
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was compiled to:
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div.w $r4, $r4, $r5
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slli.w $r4, $r4, 0 # this is unnecessary
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jr $r1
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To remove this unnecessary operation, we change the division
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instructions to (DI, DI) -> DI and describe the sign-extend behavior
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explicitly in the RTL template. In the expander for 32-bit division we
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then use simplify_gen_subreg to extract the lower 32 bits.
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gcc/ChangeLog:
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* config/loongarch/loongarch.md (<any_div>di3_fake): Describe
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the sign-extend of result in the RTL template.
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(<any_div><mode>3): Adjust for <any_div>di3_fake change.
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gcc/testsuite/ChangeLog:
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* gcc.target/loongarch/div-4.c: New test.
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Signed-off-by: Peng Fan <fanpeng@loongson.cn>
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Signed-off-by: ticat_fp <fanpeng@loongson.cn>
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---
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gcc/config/loongarch/loongarch.md | 12 ++++++++----
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gcc/testsuite/gcc.target/loongarch/div-4.c | 9 +++++++++
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2 files changed, 17 insertions(+), 4 deletions(-)
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create mode 100644 gcc/testsuite/gcc.target/loongarch/div-4.c
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diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loongarch.md
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index 6bca2ed39..5c0445dd8 100644
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--- a/gcc/config/loongarch/loongarch.md
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+++ b/gcc/config/loongarch/loongarch.md
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@@ -752,6 +752,7 @@
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{
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rtx reg1 = gen_reg_rtx (DImode);
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rtx reg2 = gen_reg_rtx (DImode);
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+ rtx rd = gen_reg_rtx (DImode);
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operands[1] = gen_rtx_SIGN_EXTEND (word_mode, operands[1]);
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operands[2] = gen_rtx_SIGN_EXTEND (word_mode, operands[2]);
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@@ -759,7 +760,9 @@
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emit_insn (gen_rtx_SET (reg1, operands[1]));
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emit_insn (gen_rtx_SET (reg2, operands[2]));
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- emit_insn (gen_<optab>di3_fake (operands[0], reg1, reg2));
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+ emit_insn (gen_<optab>di3_fake (rd, reg1, reg2));
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+ emit_insn (gen_rtx_SET (operands[0],
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+ simplify_gen_subreg (SImode, rd, DImode, 0)));
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DONE;
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}
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})
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@@ -781,9 +784,10 @@
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(const_string "no")))])
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(define_insn "<optab>di3_fake"
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- [(set (match_operand:SI 0 "register_operand" "=r,&r,&r")
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- (any_div:SI (match_operand:DI 1 "register_operand" "r,r,0")
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- (match_operand:DI 2 "register_operand" "r,r,r")))]
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+ [(set (match_operand:DI 0 "register_operand" "=r,&r,&r")
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+ (sign_extend:DI
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+ (any_div:SI (match_operand:DI 1 "register_operand" "r,r,0")
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+ (match_operand:DI 2 "register_operand" "r,r,r"))))]
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""
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{
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return loongarch_output_division ("<insn>.w<u>\t%0,%1,%2", operands);
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diff --git a/gcc/testsuite/gcc.target/loongarch/div-4.c b/gcc/testsuite/gcc.target/loongarch/div-4.c
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new file mode 100644
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index 000000000..a52f87d6c
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--- /dev/null
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+++ b/gcc/testsuite/gcc.target/loongarch/div-4.c
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@@ -0,0 +1,9 @@
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+/* { dg-do compile } */
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+/* { dg-options "-O2" } */
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+/* { dg-final { scan-assembler-not "slli" } } */
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+
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+int
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+div(int a, int b)
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+{
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+ return a / b;
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+}
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--
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2.33.0
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