446 lines
17 KiB
Diff
446 lines
17 KiB
Diff
From a31baa1e437fa4acedfaf03db91c1d6e5ce78013 Mon Sep 17 00:00:00 2001
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From: Xi Ruoyao <xry111@xry111.site>
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Date: Sun, 2 Apr 2023 21:37:49 +0800
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Subject: [PATCH 041/124] LoongArch: Optimize additions with immediates
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1. Use addu16i.d for TARGET_64BIT and suitable immediates.
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2. Split one addition with immediate into two addu16i.d or addi.{d/w}
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instructions if possible. This can avoid using a temp register w/o
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increase the count of instructions.
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Inspired by https://reviews.llvm.org/D143710 and
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https://reviews.llvm.org/D147222.
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Bootstrapped and regtested on loongarch64-linux-gnu. Ok for GCC 14?
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gcc/ChangeLog:
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* config/loongarch/loongarch-protos.h
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(loongarch_addu16i_imm12_operand_p): New function prototype.
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(loongarch_split_plus_constant): Likewise.
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* config/loongarch/loongarch.cc
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(loongarch_addu16i_imm12_operand_p): New function.
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(loongarch_split_plus_constant): Likewise.
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* config/loongarch/loongarch.h (ADDU16I_OPERAND): New macro.
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(DUAL_IMM12_OPERAND): Likewise.
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(DUAL_ADDU16I_OPERAND): Likewise.
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* config/loongarch/constraints.md (La, Lb, Lc, Ld, Le): New
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constraint.
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* config/loongarch/predicates.md (const_dual_imm12_operand): New
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predicate.
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(const_addu16i_operand): Likewise.
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(const_addu16i_imm12_di_operand): Likewise.
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(const_addu16i_imm12_si_operand): Likewise.
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(plus_di_operand): Likewise.
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(plus_si_operand): Likewise.
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(plus_si_extend_operand): Likewise.
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* config/loongarch/loongarch.md (add<mode>3): Convert to
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define_insn_and_split. Use plus_<mode>_operand predicate
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instead of arith_operand. Add alternatives for La, Lb, Lc, Ld,
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and Le constraints.
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(*addsi3_extended): Convert to define_insn_and_split. Use
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plus_si_extend_operand instead of arith_operand. Add
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alternatives for La and Le alternatives.
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gcc/testsuite/ChangeLog:
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* gcc.target/loongarch/add-const.c: New test.
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* gcc.target/loongarch/stack-check-cfa-1.c: Adjust for stack
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frame size change.
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* gcc.target/loongarch/stack-check-cfa-2.c: Likewise.
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Signed-off-by: Peng Fan <fanpeng@loongson.cn>
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Signed-off-by: ticat_fp <fanpeng@loongson.cn>
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---
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gcc/config/loongarch/constraints.md | 46 ++++++++++++-
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gcc/config/loongarch/loongarch-protos.h | 2 +
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gcc/config/loongarch/loongarch.cc | 44 +++++++++++++
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gcc/config/loongarch/loongarch.h | 19 ++++++
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gcc/config/loongarch/loongarch.md | 66 +++++++++++++++----
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gcc/config/loongarch/predicates.md | 36 ++++++++++
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.../gcc.target/loongarch/add-const.c | 45 +++++++++++++
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.../gcc.target/loongarch/stack-check-cfa-1.c | 2 +-
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.../gcc.target/loongarch/stack-check-cfa-2.c | 2 +-
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9 files changed, 246 insertions(+), 16 deletions(-)
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create mode 100644 gcc/testsuite/gcc.target/loongarch/add-const.c
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diff --git a/gcc/config/loongarch/constraints.md b/gcc/config/loongarch/constraints.md
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index 46f7f63ae..25f3cda35 100644
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--- a/gcc/config/loongarch/constraints.md
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+++ b/gcc/config/loongarch/constraints.md
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@@ -60,7 +60,22 @@
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;; "I" "A signed 12-bit constant (for arithmetic instructions)."
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;; "J" "Integer zero."
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;; "K" "An unsigned 12-bit constant (for logic instructions)."
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-;; "L" <-----unused
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+;; "L" -
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+;; "La"
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+;; "A signed constant in [-4096, 2048) or (2047, 4094]."
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+;; "Lb"
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+;; "A signed 32-bit constant and low 16-bit is zero, which can be
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+;; added onto a register with addu16i.d. It matches nothing if
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+;; the addu16i.d instruction is not available."
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+;; "Lc"
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+;; "A signed 64-bit constant can be expressed as Lb + I, but not a
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+;; single Lb or I."
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+;; "Ld"
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+;; "A signed 64-bit constant can be expressed as Lb + Lb, but not a
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+;; single Lb."
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+;; "Le"
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+;; "A signed 32-bit constant can be expressed as Lb + I, but not a
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+;; single Lb or I."
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;; "M" <-----unused
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;; "N" <-----unused
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;; "O" <-----unused
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@@ -170,6 +185,35 @@
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(and (match_code "const_int")
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(match_test "IMM12_OPERAND_UNSIGNED (ival)")))
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+(define_constraint "La"
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+ "A signed constant in [-4096, 2048) or (2047, 4094]."
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+ (and (match_code "const_int")
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+ (match_test "DUAL_IMM12_OPERAND (ival)")))
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+
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+(define_constraint "Lb"
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+ "A signed 32-bit constant and low 16-bit is zero, which can be added
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+ onto a register with addu16i.d."
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+ (and (match_code "const_int")
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+ (match_test "ADDU16I_OPERAND (ival)")))
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+
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+(define_constraint "Lc"
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+ "A signed 64-bit constant can be expressed as Lb + I, but not a single Lb
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+ or I."
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+ (and (match_code "const_int")
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+ (match_test "loongarch_addu16i_imm12_operand_p (ival, DImode)")))
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+
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+(define_constraint "Ld"
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+ "A signed 64-bit constant can be expressed as Lb + Lb, but not a single
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+ Lb."
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+ (and (match_code "const_int")
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+ (match_test "DUAL_ADDU16I_OPERAND (ival)")))
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+
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+(define_constraint "Le"
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+ "A signed 32-bit constant can be expressed as Lb + I, but not a single Lb
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+ or I."
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+ (and (match_code "const_int")
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+ (match_test "loongarch_addu16i_imm12_operand_p (ival, SImode)")))
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+
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(define_constraint "Yd"
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"@internal
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A constant @code{move_operand} that can be safely loaded using
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diff --git a/gcc/config/loongarch/loongarch-protos.h b/gcc/config/loongarch/loongarch-protos.h
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index 77b221724..0a9b47722 100644
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--- a/gcc/config/loongarch/loongarch-protos.h
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+++ b/gcc/config/loongarch/loongarch-protos.h
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@@ -83,6 +83,8 @@ extern rtx loongarch_legitimize_call_address (rtx);
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extern rtx loongarch_subword (rtx, bool);
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extern bool loongarch_split_move_p (rtx, rtx);
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extern void loongarch_split_move (rtx, rtx, rtx);
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+extern bool loongarch_addu16i_imm12_operand_p (HOST_WIDE_INT, machine_mode);
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+extern void loongarch_split_plus_constant (rtx *, machine_mode);
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extern const char *loongarch_output_move (rtx, rtx);
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extern bool loongarch_cfun_has_cprestore_slot_p (void);
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#ifdef RTX_CODE
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diff --git a/gcc/config/loongarch/loongarch.cc b/gcc/config/loongarch/loongarch.cc
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index 1a4686f03..233dddbac 100644
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--- a/gcc/config/loongarch/loongarch.cc
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+++ b/gcc/config/loongarch/loongarch.cc
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@@ -3753,6 +3753,50 @@ loongarch_split_move (rtx dest, rtx src, rtx insn_)
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}
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}
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+/* Check if adding an integer constant value for a specific mode can be
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+ performed with an addu16i.d instruction and an addi.{w/d}
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+ instruction. */
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+
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+bool
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+loongarch_addu16i_imm12_operand_p (HOST_WIDE_INT value, machine_mode mode)
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+{
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+ /* Not necessary, but avoid unnecessary calculation if !TARGET_64BIT. */
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+ if (!TARGET_64BIT)
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+ return false;
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+
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+ if ((value & 0xffff) == 0)
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+ return false;
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+
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+ if (IMM12_OPERAND (value))
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+ return false;
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+
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+ value = (value & ~HWIT_UC_0xFFF) + ((value & 0x800) << 1);
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+ return ADDU16I_OPERAND (trunc_int_for_mode (value, mode));
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+}
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+
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+/* Split one integer constant op[0] into two (op[1] and op[2]) for constant
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+ plus operation in a specific mode. The splitted constants can be added
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+ onto a register with a single instruction (addi.{d/w} or addu16i.d). */
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+
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+void
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+loongarch_split_plus_constant (rtx *op, machine_mode mode)
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+{
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+ HOST_WIDE_INT v = INTVAL (op[0]), a;
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+
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+ if (DUAL_IMM12_OPERAND (v))
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+ a = (v > 0 ? 2047 : -2048);
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+ else if (loongarch_addu16i_imm12_operand_p (v, mode))
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+ a = (v & ~HWIT_UC_0xFFF) + ((v & 0x800) << 1);
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+ else if (mode == DImode && DUAL_ADDU16I_OPERAND (v))
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+ a = (v > 0 ? 0x7fff : -0x8000) << 16;
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+ else
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+ gcc_unreachable ();
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+
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+ op[1] = gen_int_mode (a, mode);
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+ v = v - (unsigned HOST_WIDE_INT) a;
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+ op[2] = gen_int_mode (v, mode);
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+}
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+
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/* Return true if a move from SRC to DEST in INSN should be split. */
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static bool
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diff --git a/gcc/config/loongarch/loongarch.h b/gcc/config/loongarch/loongarch.h
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index c6e37b1b4..9d3cd9ca0 100644
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--- a/gcc/config/loongarch/loongarch.h
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+++ b/gcc/config/loongarch/loongarch.h
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@@ -612,6 +612,25 @@ enum reg_class
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#define CONST_LOW_PART(VALUE) ((VALUE) - CONST_HIGH_PART (VALUE))
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+/* True if VALUE can be added onto a register with one addu16i.d
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+ instruction. */
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+
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+#define ADDU16I_OPERAND(VALUE) \
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+ (TARGET_64BIT && (((VALUE) & 0xffff) == 0 \
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+ && IMM16_OPERAND ((HOST_WIDE_INT) (VALUE) / 65536)))
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+
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+/* True if VALUE can be added onto a register with two addi.{d/w}
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+ instructions, but not one addi.{d/w} instruction. */
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+#define DUAL_IMM12_OPERAND(VALUE) \
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+ (IN_RANGE ((VALUE), -4096, 4094) && !IMM12_OPERAND (VALUE))
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+
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+/* True if VALUE can be added onto a register with two addu16i.d
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+ instruction, but not one addu16i.d instruction. */
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+#define DUAL_ADDU16I_OPERAND(VALUE) \
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+ (TARGET_64BIT && (((VALUE) & 0xffff) == 0 \
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+ && !ADDU16I_OPERAND (VALUE) \
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+ && IN_RANGE ((VALUE) / 65536, -0x10000, 0xfffe)))
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+
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#define IMM12_INT(X) IMM12_OPERAND (INTVAL (X))
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#define IMM12_INT_UNSIGNED(X) IMM12_OPERAND_UNSIGNED (INTVAL (X))
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#define LU12I_INT(X) LU12I_OPERAND (INTVAL (X))
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diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loongarch.md
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index 833b94753..b2f7c7f78 100644
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--- a/gcc/config/loongarch/loongarch.md
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+++ b/gcc/config/loongarch/loongarch.md
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@@ -598,24 +598,64 @@
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[(set_attr "type" "fadd")
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(set_attr "mode" "<UNITMODE>")])
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-(define_insn "add<mode>3"
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- [(set (match_operand:GPR 0 "register_operand" "=r,r")
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- (plus:GPR (match_operand:GPR 1 "register_operand" "r,r")
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- (match_operand:GPR 2 "arith_operand" "r,I")))]
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+(define_insn_and_split "add<mode>3"
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+ [(set (match_operand:GPR 0 "register_operand" "=r,r,r,r,r,r,r")
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+ (plus:GPR (match_operand:GPR 1 "register_operand" "r,r,r,r,r,r,r")
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+ (match_operand:GPR 2 "plus_<mode>_operand"
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+ "r,I,La,Lb,Lc,Ld,Le")))]
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""
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- "add%i2.<d>\t%0,%1,%2";
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+ "@
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+ add.<d>\t%0,%1,%2
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+ addi.<d>\t%0,%1,%2
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+ #
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+ * operands[2] = GEN_INT (INTVAL (operands[2]) / 65536); \
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+ return \"addu16i.d\t%0,%1,%2\";
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+ #
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+ #
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+ #"
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+ "CONST_INT_P (operands[2]) && !IMM12_INT (operands[2]) \
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+ && !ADDU16I_OPERAND (INTVAL (operands[2]))"
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+ [(set (match_dup 0) (plus:GPR (match_dup 1) (match_dup 3)))
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+ (set (match_dup 0) (plus:GPR (match_dup 0) (match_dup 4)))]
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+ {
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+ loongarch_split_plus_constant (&operands[2], <MODE>mode);
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+ }
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[(set_attr "alu_type" "add")
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- (set_attr "mode" "<MODE>")])
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-
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-(define_insn "*addsi3_extended"
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- [(set (match_operand:DI 0 "register_operand" "=r,r")
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+ (set_attr "mode" "<MODE>")
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+ (set_attr "insn_count" "1,1,2,1,2,2,2")
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+ (set (attr "enabled")
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+ (cond
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+ [(match_test "<MODE>mode != DImode && which_alternative == 4")
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+ (const_string "no")
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+ (match_test "<MODE>mode != DImode && which_alternative == 5")
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+ (const_string "no")
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+ (match_test "<MODE>mode != SImode && which_alternative == 6")
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+ (const_string "no")]
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+ (const_string "yes")))])
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+
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+(define_insn_and_split "*addsi3_extended"
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+ [(set (match_operand:DI 0 "register_operand" "=r,r,r,r")
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(sign_extend:DI
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- (plus:SI (match_operand:SI 1 "register_operand" "r,r")
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- (match_operand:SI 2 "arith_operand" "r,I"))))]
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+ (plus:SI (match_operand:SI 1 "register_operand" "r,r,r,r")
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+ (match_operand:SI 2 "plus_si_extend_operand"
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+ "r,I,La,Le"))))]
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"TARGET_64BIT"
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- "add%i2.w\t%0,%1,%2"
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+ "@
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+ add.w\t%0,%1,%2
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+ addi.w\t%0,%1,%2
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+ #
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+ #"
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+ "CONST_INT_P (operands[2]) && !IMM12_INT (operands[2])"
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+ [(set (subreg:SI (match_dup 0) 0) (plus:SI (match_dup 1) (match_dup 3)))
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+ (set (match_dup 0)
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+ (sign_extend:DI (plus:SI (subreg:SI (match_dup 0) 0)
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+ (match_dup 4))))]
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+ {
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+ loongarch_split_plus_constant (&operands[2], SImode);
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+ }
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[(set_attr "alu_type" "add")
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- (set_attr "mode" "SI")])
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+ (set_attr "mode" "SI")
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+ (set_attr "insn_count" "1,1,2,2")])
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;;
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diff --git a/gcc/config/loongarch/predicates.md b/gcc/config/loongarch/predicates.md
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index 3c32b2987..4966d5569 100644
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--- a/gcc/config/loongarch/predicates.md
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+++ b/gcc/config/loongarch/predicates.md
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@@ -39,14 +39,50 @@
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(and (match_code "const_int")
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(match_test "IMM12_OPERAND (INTVAL (op))")))
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+(define_predicate "const_dual_imm12_operand"
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+ (and (match_code "const_int")
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+ (match_test "DUAL_IMM12_OPERAND (INTVAL (op))")))
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+
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(define_predicate "const_imm16_operand"
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(and (match_code "const_int")
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(match_test "IMM16_OPERAND (INTVAL (op))")))
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+(define_predicate "const_addu16i_operand"
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+ (and (match_code "const_int")
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+ (match_test "ADDU16I_OPERAND (INTVAL (op))")))
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+
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+(define_predicate "const_addu16i_imm12_di_operand"
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+ (and (match_code "const_int")
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+ (match_test "loongarch_addu16i_imm12_operand_p (INTVAL (op), DImode)")))
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+
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+(define_predicate "const_addu16i_imm12_si_operand"
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+ (and (match_code "const_int")
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+ (match_test "loongarch_addu16i_imm12_operand_p (INTVAL (op), SImode)")))
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+
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+(define_predicate "const_dual_addu16i_operand"
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+ (and (match_code "const_int")
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+ (match_test "DUAL_ADDU16I_OPERAND (INTVAL (op))")))
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+
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(define_predicate "arith_operand"
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(ior (match_operand 0 "const_arith_operand")
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(match_operand 0 "register_operand")))
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+(define_predicate "plus_di_operand"
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+ (ior (match_operand 0 "arith_operand")
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+ (match_operand 0 "const_dual_imm12_operand")
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+ (match_operand 0 "const_addu16i_operand")
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+ (match_operand 0 "const_addu16i_imm12_di_operand")
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+ (match_operand 0 "const_dual_addu16i_operand")))
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+
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+(define_predicate "plus_si_extend_operand"
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+ (ior (match_operand 0 "arith_operand")
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+ (match_operand 0 "const_dual_imm12_operand")
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+ (match_operand 0 "const_addu16i_imm12_si_operand")))
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+
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+(define_predicate "plus_si_operand"
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+ (ior (match_operand 0 "plus_si_extend_operand")
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+ (match_operand 0 "const_addu16i_operand")))
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+
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(define_predicate "const_immalsl_operand"
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(and (match_code "const_int")
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(match_test "IN_RANGE (INTVAL (op), 1, 4)")))
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diff --git a/gcc/testsuite/gcc.target/loongarch/add-const.c b/gcc/testsuite/gcc.target/loongarch/add-const.c
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new file mode 100644
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index 000000000..7b6a7cb92
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--- /dev/null
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+++ b/gcc/testsuite/gcc.target/loongarch/add-const.c
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@@ -0,0 +1,45 @@
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+/* { dg-do compile } */
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+/* { dg-options "-O -mabi=lp64d" } */
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+
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+/* None of these functions should load the const operand into a temp
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+ register. */
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+
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+/* { dg-final { scan-assembler-not "add\\.[dw]" } } */
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+
|
||
+unsigned long f01 (unsigned long x) { return x + 1; }
|
||
+unsigned long f02 (unsigned long x) { return x - 1; }
|
||
+unsigned long f03 (unsigned long x) { return x + 2047; }
|
||
+unsigned long f04 (unsigned long x) { return x + 4094; }
|
||
+unsigned long f05 (unsigned long x) { return x - 2048; }
|
||
+unsigned long f06 (unsigned long x) { return x - 4096; }
|
||
+unsigned long f07 (unsigned long x) { return x + 0x7fff0000; }
|
||
+unsigned long f08 (unsigned long x) { return x - 0x80000000l; }
|
||
+unsigned long f09 (unsigned long x) { return x + 0x7fff0000l * 2; }
|
||
+unsigned long f10 (unsigned long x) { return x - 0x80000000l * 2; }
|
||
+unsigned long f11 (unsigned long x) { return x + 0x7fff0000 + 0x1; }
|
||
+unsigned long f12 (unsigned long x) { return x + 0x7fff0000 - 0x1; }
|
||
+unsigned long f13 (unsigned long x) { return x + 0x7fff0000 + 0x7ff; }
|
||
+unsigned long f14 (unsigned long x) { return x + 0x7fff0000 - 0x800; }
|
||
+unsigned long f15 (unsigned long x) { return x - 0x80000000l - 1; }
|
||
+unsigned long f16 (unsigned long x) { return x - 0x80000000l + 1; }
|
||
+unsigned long f17 (unsigned long x) { return x - 0x80000000l - 0x800; }
|
||
+unsigned long f18 (unsigned long x) { return x - 0x80000000l + 0x7ff; }
|
||
+
|
||
+unsigned int g01 (unsigned int x) { return x + 1; }
|
||
+unsigned int g02 (unsigned int x) { return x - 1; }
|
||
+unsigned int g03 (unsigned int x) { return x + 2047; }
|
||
+unsigned int g04 (unsigned int x) { return x + 4094; }
|
||
+unsigned int g05 (unsigned int x) { return x - 2048; }
|
||
+unsigned int g06 (unsigned int x) { return x - 4096; }
|
||
+unsigned int g07 (unsigned int x) { return x + 0x7fff0000; }
|
||
+unsigned int g08 (unsigned int x) { return x - 0x80000000l; }
|
||
+unsigned int g09 (unsigned int x) { return x + 0x7fff0000l * 2; }
|
||
+unsigned int g10 (unsigned int x) { return x - 0x80000000l * 2; }
|
||
+unsigned int g11 (unsigned int x) { return x + 0x7fff0000 + 0x1; }
|
||
+unsigned int g12 (unsigned int x) { return x + 0x7fff0000 - 0x1; }
|
||
+unsigned int g13 (unsigned int x) { return x + 0x7fff0000 + 0x7ff; }
|
||
+unsigned int g14 (unsigned int x) { return x + 0x7fff0000 - 0x800; }
|
||
+unsigned int g15 (unsigned int x) { return x - 0x80000000l - 1; }
|
||
+unsigned int g16 (unsigned int x) { return x - 0x80000000l + 1; }
|
||
+unsigned int g17 (unsigned int x) { return x - 0x80000000l - 0x800; }
|
||
+unsigned int g18 (unsigned int x) { return x - 0x80000000l + 0x7ff; }
|
||
diff --git a/gcc/testsuite/gcc.target/loongarch/stack-check-cfa-1.c b/gcc/testsuite/gcc.target/loongarch/stack-check-cfa-1.c
|
||
index 3533fe7b6..cd72154f4 100644
|
||
--- a/gcc/testsuite/gcc.target/loongarch/stack-check-cfa-1.c
|
||
+++ b/gcc/testsuite/gcc.target/loongarch/stack-check-cfa-1.c
|
||
@@ -6,7 +6,7 @@
|
||
#define SIZE 128*1024
|
||
#include "stack-check-prologue.h"
|
||
|
||
-/* { dg-final { scan-assembler-times {\.cfi_def_cfa_offset 131088} 1 } } */
|
||
+/* { dg-final { scan-assembler-times {\.cfi_def_cfa_offset 131072} 1 } } */
|
||
/* { dg-final { scan-assembler-times {\.cfi_def_cfa_offset 0} 1 } } */
|
||
|
||
/* Checks that the CFA notes are correct for every sp adjustment. */
|
||
diff --git a/gcc/testsuite/gcc.target/loongarch/stack-check-cfa-2.c b/gcc/testsuite/gcc.target/loongarch/stack-check-cfa-2.c
|
||
index e5e711105..3e5ca05b2 100644
|
||
--- a/gcc/testsuite/gcc.target/loongarch/stack-check-cfa-2.c
|
||
+++ b/gcc/testsuite/gcc.target/loongarch/stack-check-cfa-2.c
|
||
@@ -6,7 +6,7 @@
|
||
#define SIZE 1280*1024 + 512
|
||
#include "stack-check-prologue.h"
|
||
|
||
-/* { dg-final { scan-assembler-times {\.cfi_def_cfa_offset 1311248} 1 } } */
|
||
+/* { dg-final { scan-assembler-times {\.cfi_def_cfa_offset 1311232} 1 } } */
|
||
/* { dg-final { scan-assembler-times {\.cfi_def_cfa_offset 0} 1 } } */
|
||
|
||
/* Checks that the CFA notes are correct for every sp adjustment. */
|
||
--
|
||
2.33.0
|
||
|