01e0ec8ea6
- avoid-cycling-on-vertain-subreg-reloads.patch: Add patch source comment - change-gcc-BASE-VER.patch: Likewise - dont-generate-IF_THEN_ELSE.patch: Likewise - fix-ICE-in-compute_live_loop_exits.patch: Likewise - fix-ICE-in-eliminate_stmt.patch: Likewise - fix-ICE-in-vect_create_epilog_for_reduction.patch: Likewise - fix-ICE-in-vect_stmt_to_vectorize.patch: Likewise - fix-ICE-in-verify_ssa.patch: Likewise - fix-ICE-when-vectorizing-nested-cycles.patch: Likewise - fix-cost-of-plus.patch: Likewise - ipa-const-prop-self-recursion-bugfix.patch: Likewise - simplify-removing-subregs.patch: Likewise - medium-code-mode.patch: Bugfix - fix-when-peeling-for-alignment.patch: Move to ... - fix-PR-92351-When-peeling-for-alignment.patch: ... this - AArch64-Fix-constraints-for-CPY-M.patch: New file - Apply-maximum-nunits-for-BB-SLP.patch: New file - Fix-EXTRACT_LAST_REDUCTION-segfault.patch: New file - Fix-up-push_partial_def-little-endian-bitfield.patch: New file - Fix-zero-masking-for-vcvtps2ph.patch: New file - IRA-Handle-fully-tied-destinations.patch: New file - SLP-VECT-Add-check-to-fix-96837.patch: New file - aarch64-Fix-ash-lr-lshr-mode-3-expanders.patch: New file - aarch64-Fix-bf16-and-matrix-g++-gfortran.patch: New file - aarch64-Fix-mismatched-SVE-predicate-modes.patch: New file - aarch64-fix-sve-acle-error.patch: New file - adjust-vector-cost-and-move-EXTRACT_LAST_REDUCTION-costing.patch: New file - bf16-and-matrix-characteristic.patch: New file - fix-ICE-IPA-compare-VRP-types.patch: New file - fix-ICE-in-affine-combination.patch: New file - fix-ICE-in-pass-vect.patch: New file - fix-ICE-in-vect_update_misalignment_for_peel.patch: New file - fix-addlosymdi-ICE-in-pass-reload.patch: New file - fix-an-ICE-in-vect_recog_mask_conversion_pattern.patch: New file - fix-avx512vl-vcvttpd2dq-2-fail.patch: New file - fix-issue499-add-nop-convert.patch: New file - fix-issue604-ldist-dependency-fixup.patch: New file - modulo-sched-Carefully-process-loop-counter-initiali.patch: New file - re-PR-target-91124-gcc.target-i386-avx512vl-vpshldvd.patch: New file - reduction-paths-with-unhandled-live-stmt.patch: New file - redundant-loop-elimination.patch: New file - sccvn-Improve-handling-of-load-masked-with-integer.patch: New file - speed-up-DDG-analysis-and-fix-bootstrap-compare-debug.patch: New file - store-merging-Consider-also-overlapping-stores-earlier.patch: New file - tree-optimization-96920-another-ICE-when-vectorizing.patch: New file - tree-optimization-97812-fix-range-query-in-VRP-asser.patch: New file - vectorizable-comparison-Swap-operands-only-once.patch: New file - x86-Fix-bf16-and-matrix.patch: New file
322 lines
12 KiB
Diff
322 lines
12 KiB
Diff
This backport contains 4 patchs from gcc main stream tree.
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The commit id of these patchs list as following in the order of time.
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0001-re-PR-target-90424-memcpy-into-vector-builtin-not-op.patch
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1bf2a0b90f2457f6d9301535560eb5e05978261b
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0002-testsuite-aarch64-arm-Add-missing-quotes-to-expected.patch
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0ec537f3500924f29505977aa89c2a1d4671c584
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0003-x86-Tweak-testcases-for-PR82361.patch
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ad4644f378fe2f731cd987a4aff14b935f530b88
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0004-x86-Robustify-vzeroupper-handling-across-calls.patch
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2a2e3a0dfcbe0861915f421d11b828f0c35023f0
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diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
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index 9282a8fb6..ba72da1ec 100644
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--- a/gcc/config/i386/i386.c
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+++ b/gcc/config/i386/i386.c
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@@ -95,6 +95,7 @@ along with GCC; see the file COPYING3. If not see
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#include "i386-builtins.h"
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#include "i386-expand.h"
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#include "i386-features.h"
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+#include "function-abi.h"
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/* This file should be included last. */
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#include "target-def.h"
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@@ -13529,6 +13530,15 @@ ix86_avx_u128_mode_needed (rtx_insn *insn)
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}
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}
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+ /* If the function is known to preserve some SSE registers,
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+ RA and previous passes can legitimately rely on that for
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+ modes wider than 256 bits. It's only safe to issue a
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+ vzeroupper if all SSE registers are clobbered. */
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+ const function_abi &abi = insn_callee_abi (insn);
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+ if (!hard_reg_set_subset_p (reg_class_contents[ALL_SSE_REGS],
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+ abi.mode_clobbers (V4DImode)))
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+ return AVX_U128_ANY;
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+
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return AVX_U128_CLEAN;
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}
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diff --git a/gcc/testsuite/g++.target/i386/pr90424-1.C b/gcc/testsuite/g++.target/i386/pr90424-1.C
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new file mode 100644
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index 000000000..9df8c089b
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--- /dev/null
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+++ b/gcc/testsuite/g++.target/i386/pr90424-1.C
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@@ -0,0 +1,32 @@
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+/* { dg-do compile { target c++11 } } */
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+/* { dg-options "-O2 -msse2 -fdump-tree-optimized" } */
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+
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+template <class T>
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+using V [[gnu::vector_size(16)]] = T;
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+
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+template <class T, unsigned M = sizeof(V<T>)>
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+V<T> load(const void *p) {
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+ using W = V<T>;
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+ W r;
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+ __builtin_memcpy(&r, p, M);
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+ return r;
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+}
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+
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+// movq or movsd
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+template V<char> load<char, 8>(const void *); // bad
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+template V<short> load<short, 8>(const void *); // bad
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+template V<int> load<int, 8>(const void *); // bad
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+template V<long> load<long, 8>(const void *); // good
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+// the following is disabled because V2SF isn't a supported mode
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+// template V<float> load<float, 8>(const void *); // bad
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+template V<double> load<double, 8>(const void *); // good (movsd?)
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+
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+// movd or movss
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+template V<char> load<char, 4>(const void *); // bad
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+template V<short> load<short, 4>(const void *); // bad
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+template V<int> load<int, 4>(const void *); // good
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+template V<float> load<float, 4>(const void *); // good
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+
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+/* We should end up with one load and one insert for each function. */
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+/* { dg-final { scan-tree-dump-times "BIT_INSERT_EXPR" 9 "optimized" } } */
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+/* { dg-final { scan-tree-dump-times "MEM" 9 "optimized" } } */
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diff --git a/gcc/testsuite/g++.target/i386/pr90424-2.C b/gcc/testsuite/g++.target/i386/pr90424-2.C
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new file mode 100644
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index 000000000..3abb65f45
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--- /dev/null
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+++ b/gcc/testsuite/g++.target/i386/pr90424-2.C
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@@ -0,0 +1,31 @@
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+/* { dg-do compile { target c++11 } } */
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+/* { dg-options "-O2 -msse2 -fdump-tree-optimized" } */
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+
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+template <class T>
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+using V [[gnu::vector_size(16)]] = T;
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+
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+template <class T, unsigned M = sizeof(V<T>)>
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+V<T> load(const void *p) {
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+ V<T> r = {};
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+ __builtin_memcpy(&r, p, M);
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+ return r;
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+}
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+
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+// movq or movsd
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+template V<char> load<char, 8>(const void *); // bad
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+template V<short> load<short, 8>(const void *); // bad
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+template V<int> load<int, 8>(const void *); // bad
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+template V<long> load<long, 8>(const void *); // good
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+// the following is disabled because V2SF isn't a supported mode
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+// template V<float> load<float, 8>(const void *); // bad
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+template V<double> load<double, 8>(const void *); // good (movsd?)
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+
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+// movd or movss
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+template V<char> load<char, 4>(const void *); // bad
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+template V<short> load<short, 4>(const void *); // bad
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+template V<int> load<int, 4>(const void *); // good
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+template V<float> load<float, 4>(const void *); // good
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+
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+/* We should end up with one load and one insert for each function. */
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+/* { dg-final { scan-tree-dump-times "BIT_INSERT_EXPR" 9 "optimized" } } */
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+/* { dg-final { scan-tree-dump-times "MEM" 9 "optimized" } } */
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diff --git a/gcc/testsuite/gcc.target/aarch64/target_attr_10.c b/gcc/testsuite/gcc.target/aarch64/target_attr_10.c
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index 184990471..d96a8733a 100644
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--- a/gcc/testsuite/gcc.target/aarch64/target_attr_10.c
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+++ b/gcc/testsuite/gcc.target/aarch64/target_attr_10.c
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@@ -13,4 +13,4 @@ foo (uint8x16_t a, uint8x16_t b, uint8x16_t c)
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return vbslq_u8 (a, b, c); /* { dg-message "called from here" } */
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}
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-/* { dg-error "inlining failed in call to always_inline" "" { target *-*-* } 0 } */
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+/* { dg-error "inlining failed in call to 'always_inline'" "" { target *-*-* } 0 } */
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diff --git a/gcc/testsuite/gcc.target/arm/attr-neon-builtin-fail.c b/gcc/testsuite/gcc.target/arm/attr-neon-builtin-fail.c
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index 05dc579f2..fb6e0b9cd 100644
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--- a/gcc/testsuite/gcc.target/arm/attr-neon-builtin-fail.c
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+++ b/gcc/testsuite/gcc.target/arm/attr-neon-builtin-fail.c
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@@ -14,5 +14,5 @@ foo (uint8x16_t *p)
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*p = vmovq_n_u8 (3); /* { dg-message "called from here" } */
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}
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-/* { dg-error "inlining failed in call to always_inline" "" { target *-*-* } 0 } */
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+/* { dg-error "inlining failed in call to 'always_inline'" "" { target *-*-* } 0 } */
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diff --git a/gcc/testsuite/gcc.target/i386/pr82361-1.c b/gcc/testsuite/gcc.target/i386/pr82361-1.c
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index e7c356557..dec1792ae 100644
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--- a/gcc/testsuite/gcc.target/i386/pr82361-1.c
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+++ b/gcc/testsuite/gcc.target/i386/pr82361-1.c
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@@ -4,50 +4,50 @@
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/* We should be able to optimize all %eax to %rax zero extensions, because
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div and idiv instructions with 32-bit operands zero-extend both results. */
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/* { dg-final { scan-assembler-not "movl\t%eax, %eax" } } */
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-/* FIXME: We are still not able to optimize the modulo in f1/f2, only manage
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- one. */
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+/* FIXME: The compiler does not merge zero-extension to the modulo part
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+ of f1 and f2. */
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/* { dg-final { scan-assembler-times "movl\t%edx" 2 } } */
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void
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f1 (unsigned int a, unsigned int b)
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{
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- unsigned long long c = a / b;
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- unsigned long long d = a % b;
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+ register unsigned long long c asm ("rax") = a / b;
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+ register unsigned long long d asm ("rdx") = a % b;
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asm volatile ("" : : "r" (c), "r" (d));
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}
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void
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f2 (int a, int b)
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{
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- unsigned long long c = (unsigned int) (a / b);
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- unsigned long long d = (unsigned int) (a % b);
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+ register unsigned long long c asm ("rax") = (unsigned int) (a / b);
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+ register unsigned long long d asm ("rdx") = (unsigned int) (a % b);
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asm volatile ("" : : "r" (c), "r" (d));
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}
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void
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f3 (unsigned int a, unsigned int b)
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{
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- unsigned long long c = a / b;
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+ register unsigned long long c asm ("rax") = a / b;
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asm volatile ("" : : "r" (c));
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}
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void
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f4 (int a, int b)
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{
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- unsigned long long c = (unsigned int) (a / b);
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+ register unsigned long long c asm ("rax") = (unsigned int) (a / b);
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asm volatile ("" : : "r" (c));
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}
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void
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f5 (unsigned int a, unsigned int b)
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{
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- unsigned long long d = a % b;
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+ register unsigned long long d asm ("rdx") = a % b;
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asm volatile ("" : : "r" (d));
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}
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void
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f6 (int a, int b)
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{
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- unsigned long long d = (unsigned int) (a % b);
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+ register unsigned long long d asm ("rdx") = (unsigned int) (a % b);
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asm volatile ("" : : "r" (d));
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}
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diff --git a/gcc/testsuite/gcc.target/i386/pr82361-2.c b/gcc/testsuite/gcc.target/i386/pr82361-2.c
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index c1e484d6e..2d87de182 100644
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--- a/gcc/testsuite/gcc.target/i386/pr82361-2.c
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+++ b/gcc/testsuite/gcc.target/i386/pr82361-2.c
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@@ -4,7 +4,8 @@
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/* We should be able to optimize all %eax to %rax zero extensions, because
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div and idiv instructions with 32-bit operands zero-extend both results. */
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/* { dg-final { scan-assembler-not "movl\t%eax, %eax" } } */
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-/* Ditto %edx to %rdx zero extensions. */
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-/* { dg-final { scan-assembler-not "movl\t%edx, %edx" } } */
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+/* FIXME: The compiler does not merge zero-extension to the modulo part
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+ of f1 and f2. */
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+/* { dg-final { scan-assembler-times "movl\t%edx" 4 } } */
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#include "pr82361-1.c"
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diff --git a/gcc/tree-cfg.c b/gcc/tree-cfg.c
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index 527deffe4..be47519bc 100644
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--- a/gcc/tree-cfg.c
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+++ b/gcc/tree-cfg.c
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@@ -4297,8 +4297,17 @@ verify_gimple_assign_ternary (gassign *stmt)
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}
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if (! ((INTEGRAL_TYPE_P (rhs1_type)
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&& INTEGRAL_TYPE_P (rhs2_type))
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+ /* Vector element insert. */
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|| (VECTOR_TYPE_P (rhs1_type)
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- && types_compatible_p (TREE_TYPE (rhs1_type), rhs2_type))))
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+ && types_compatible_p (TREE_TYPE (rhs1_type), rhs2_type))
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+ /* Aligned sub-vector insert. */
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+ || (VECTOR_TYPE_P (rhs1_type)
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+ && VECTOR_TYPE_P (rhs2_type)
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+ && types_compatible_p (TREE_TYPE (rhs1_type),
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+ TREE_TYPE (rhs2_type))
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+ && multiple_p (TYPE_VECTOR_SUBPARTS (rhs1_type),
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+ TYPE_VECTOR_SUBPARTS (rhs2_type))
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+ && multiple_of_p (bitsizetype, rhs3, TYPE_SIZE (rhs2_type)))))
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{
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error ("not allowed type combination in BIT_INSERT_EXPR");
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debug_generic_expr (rhs1_type);
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diff --git a/gcc/tree-ssa.c b/gcc/tree-ssa.c
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index 1dc544b6d..a149f5e79 100644
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--- a/gcc/tree-ssa.c
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+++ b/gcc/tree-ssa.c
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@@ -1522,8 +1522,6 @@ non_rewritable_lvalue_p (tree lhs)
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if (DECL_P (decl)
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&& VECTOR_TYPE_P (TREE_TYPE (decl))
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&& TYPE_MODE (TREE_TYPE (decl)) != BLKmode
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- && operand_equal_p (TYPE_SIZE_UNIT (TREE_TYPE (lhs)),
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- TYPE_SIZE_UNIT (TREE_TYPE (TREE_TYPE (decl))), 0)
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&& known_ge (mem_ref_offset (lhs), 0)
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&& known_gt (wi::to_poly_offset (TYPE_SIZE_UNIT (TREE_TYPE (decl))),
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mem_ref_offset (lhs))
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@@ -1531,7 +1529,24 @@ non_rewritable_lvalue_p (tree lhs)
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TYPE_SIZE_UNIT (TREE_TYPE (lhs)))
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&& known_ge (wi::to_poly_offset (TYPE_SIZE (TREE_TYPE (decl))),
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wi::to_poly_offset (TYPE_SIZE (TREE_TYPE (lhs)))))
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- return false;
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+ {
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+ poly_uint64 lhs_bits, nelts;
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+ if (poly_int_tree_p (TYPE_SIZE (TREE_TYPE (lhs)), &lhs_bits)
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+ && multiple_p (lhs_bits,
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+ tree_to_uhwi
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+ (TYPE_SIZE (TREE_TYPE (TREE_TYPE (decl)))),
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+ &nelts))
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+ {
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+ if (known_eq (nelts, 1u))
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+ return false;
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+ /* For sub-vector inserts the insert vector mode has to be
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+ supported. */
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+ tree vtype = build_vector_type (TREE_TYPE (TREE_TYPE (decl)),
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+ nelts);
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+ if (TYPE_MODE (vtype) != BLKmode)
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+ return false;
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+ }
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+ }
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}
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/* A vector-insert using a BIT_FIELD_REF is rewritable using
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@@ -1869,20 +1884,30 @@ execute_update_addresses_taken (void)
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&& bitmap_bit_p (suitable_for_renaming, DECL_UID (sym))
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&& VECTOR_TYPE_P (TREE_TYPE (sym))
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&& TYPE_MODE (TREE_TYPE (sym)) != BLKmode
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- && operand_equal_p (TYPE_SIZE_UNIT (TREE_TYPE (lhs)),
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- TYPE_SIZE_UNIT
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- (TREE_TYPE (TREE_TYPE (sym))), 0)
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- && tree_fits_uhwi_p (TREE_OPERAND (lhs, 1))
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- && tree_int_cst_lt (TREE_OPERAND (lhs, 1),
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- TYPE_SIZE_UNIT (TREE_TYPE (sym)))
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- && (tree_to_uhwi (TREE_OPERAND (lhs, 1))
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- % tree_to_uhwi (TYPE_SIZE_UNIT (TREE_TYPE (lhs)))) == 0)
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+ && known_ge (mem_ref_offset (lhs), 0)
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+ && known_gt (wi::to_poly_offset
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+ (TYPE_SIZE_UNIT (TREE_TYPE (sym))),
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+ mem_ref_offset (lhs))
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+ && multiple_of_p (sizetype,
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+ TREE_OPERAND (lhs, 1),
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+ TYPE_SIZE_UNIT (TREE_TYPE (lhs))))
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{
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tree val = gimple_assign_rhs1 (stmt);
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if (! types_compatible_p (TREE_TYPE (val),
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TREE_TYPE (TREE_TYPE (sym))))
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{
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- tree tem = make_ssa_name (TREE_TYPE (TREE_TYPE (sym)));
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+ poly_uint64 lhs_bits, nelts;
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+ tree temtype = TREE_TYPE (TREE_TYPE (sym));
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+ if (poly_int_tree_p (TYPE_SIZE (TREE_TYPE (lhs)),
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+ &lhs_bits)
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+ && multiple_p (lhs_bits,
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+ tree_to_uhwi
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+ (TYPE_SIZE (TREE_TYPE
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+ (TREE_TYPE (sym)))),
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+ &nelts)
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+ && maybe_ne (nelts, 1u))
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+ temtype = build_vector_type (temtype, nelts);
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+ tree tem = make_ssa_name (temtype);
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gimple *pun
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= gimple_build_assign (tem,
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build1 (VIEW_CONVERT_EXPR,
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