- Add add-checks-to-avoid-spoiling-if-conversion.patch - Add add-option-fallow-store-data-races.patch - Add complete-struct-reorg.patch - Add cse-in-vectorization.patch - Add enable-simd-math.patch - Add fix-ICE-avoid-issueing-loads-in-SM-when-possible.patch - Add fix-ICE-in-compute_live_loop_exits.patch - Add fix-ICE-in-copy_reference_ops_from_ref.patch - Add fix-ICE-in-declare-return-variable.patch - Add fix-ICE-in-exact_div.patch - Add fix-ICE-in-gimple_op.patch - Add fix-ICE-in-model_update_limit_points_in_group.patch - Add fix-ICE-in-reload.patch - Add fix-ICE-in-store_constructor.patch - Add fix-ICE-in-vec.patch - Add fix-ICE-in-vect_create_epilog_for_reduction.patch - Add fix-ICE-in-vect_create_epilog_for_reduction_2.patch - Add fix-ICE-in-vect_create_epilog_for_reduction_3.patch - Add fix-ICE-in-vect_get_vec_def_for_stmt_copy.patch - Add fix-ICE-in-vect_slp_analyze_node_operations.patch - Add fix-ICE-in-vect_stmt_to_vectorize.patch - Add fix-ICE-in-vect_transform_stmt.patch - Add fix-ICE-in-vectorizable_condition.patch - Add fix-ICE-in-verify_ssa.patch - Add fix-ICE-statement-uses-released-SSA-name.patch - Add fix-ICE-when-vectorizing-nested-cycles.patch - Add fix-SSA-update-for-vectorizer-epilogue.patch - Add fix-do-not-build-op.patch - Add fix-load-eliding-in-SM.patch - Add fix-wrong-vectorizer-code.patch - Add generate-csel-for-arrayref.patch - Add ipa-const-prop-self-recursion-bugfix.patch - Add ipa-const-prop.patch - Add ipa-struct-reorg-bugfix.patch - Add ipa-struct-reorg.patch - Add medium-code-mode.patch - Add reduction-chain-slp-option.patch - Add reductions-slp-enhancement.patch - Add simplify-removing-subregs.patch - Add tighten-range-for-generating-csel.patch - Add vectorization-enhancement.patch - Add add-checks-to-avoid-spoiling-if-conversion.patch - Add add-option-fallow-store-data-races.patch - Add complete-struct-reorg.patch - Add cse-in-vectorization.patch - Add enable-simd-math.patch - Add fix-ICE-avoid-issueing-loads-in-SM-when-possible.patch - Add fix-ICE-in-compute_live_loop_exits.patch - Add fix-ICE-in-copy_reference_ops_from_ref.patch - Add fix-ICE-in-declare-return-variable.patch - Add fix-ICE-in-exact_div.patch - Add fix-ICE-in-gimple_op.patch - Add fix-ICE-in-model_update_limit_points_in_group.patch - Add fix-ICE-in-reload.patch - Add fix-ICE-in-store_constructor.patch - Add fix-ICE-in-vec.patch - Add fix-ICE-in-vect_create_epilog_for_reduction.patch - Add fix-ICE-in-vect_create_epilog_for_reduction_2.patch - Add fix-ICE-in-vect_create_epilog_for_reduction_3.patch - Add fix-ICE-in-vect_get_vec_def_for_stmt_copy.patch - Add fix-ICE-in-vect_slp_analyze_node_operations.patch - Add fix-ICE-in-vect_stmt_to_vectorize.patch - Add fix-ICE-in-vect_transform_stmt.patch - Add fix-ICE-in-vectorizable_condition.patch - Add fix-ICE-in-verify_ssa.patch - Add fix-ICE-statement-uses-released-SSA-name.patch - Add fix-ICE-when-vectorizing-nested-cycles.patch - Add fix-SSA-update-for-vectorizer-epilogue.patch - Add fix-do-not-build-op.patch - Add fix-load-eliding-in-SM.patch - Add fix-wrong-vectorizer-code.patch - Add generate-csel-for-arrayref.patch - Add ipa-const-prop-self-recursion-bugfix.patch - Add ipa-const-prop.patch - Add ipa-struct-reorg-bugfix.patch - Add ipa-struct-reorg.patch - Add medium-code-mode.patch - Add reduction-chain-slp-option.patch - Add reductions-slp-enhancement.patch - Add simplify-removing-subregs.patch - Add tighten-range-for-generating-csel.patch - Add vectorization-enhancement.patch
299 lines
14 KiB
Diff
299 lines
14 KiB
Diff
This backport contains 1 patch from gcc main stream tree.
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The commit id of these patchs list as following in the order of time.
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0001-re-PR-middle-end-92046-Command-line-options-that-are.patch
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e622a32db78300821fc1327637ec6413febc2c66
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diff -uprN a/gcc/common.opt b/gcc/common.opt
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--- a/gcc/common.opt 2020-05-28 16:12:58.815511599 +0800
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+++ b/gcc/common.opt 2020-05-28 15:54:33.797511589 +0800
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@@ -993,6 +993,10 @@ Align the start of loops.
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falign-loops=
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Common RejectNegative Joined Var(str_align_loops) Optimization
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+fallow-store-data-races
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+Common Report Var(flag_store_data_races) Optimization
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+Allow the compiler to introduce new data races on stores.
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+
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fargument-alias
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Common Ignore
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Does nothing. Preserved for backward compatibility.
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diff -uprN a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
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--- a/gcc/doc/invoke.texi 2020-05-28 16:12:56.875511599 +0800
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+++ b/gcc/doc/invoke.texi 2020-05-28 15:54:33.757511589 +0800
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@@ -400,6 +400,7 @@ Objective-C and Objective-C++ Dialects}.
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-falign-jumps[=@var{n}[:@var{m}:[@var{n2}[:@var{m2}]]]] @gol
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-falign-labels[=@var{n}[:@var{m}:[@var{n2}[:@var{m2}]]]] @gol
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-falign-loops[=@var{n}[:@var{m}:[@var{n2}[:@var{m2}]]]] @gol
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+-fallow-store-data-races @gol
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-fassociative-math -fauto-profile -fauto-profile[=@var{path}] @gol
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-fauto-inc-dec -fbranch-probabilities @gol
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-fbranch-target-load-optimize -fbranch-target-load-optimize2 @gol
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@@ -8365,9 +8366,9 @@ designed to reduce code size.
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Disregard strict standards compliance. @option{-Ofast} enables all
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@option{-O3} optimizations. It also enables optimizations that are not
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valid for all standard-compliant programs.
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-It turns on @option{-ffast-math} and the Fortran-specific
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-@option{-fstack-arrays}, unless @option{-fmax-stack-var-size} is
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-specified, and @option{-fno-protect-parens}.
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+It turns on @option{-ffast-math}, @option{-fallow-store-data-races}
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+and the Fortran-specific @option{-fstack-arrays}, unless
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+@option{-fmax-stack-var-size} is specified, and @option{-fno-protect-parens}.
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@item -Og
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@opindex Og
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@@ -10120,6 +10121,12 @@ The maximum allowed @var{n} option value
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Enabled at levels @option{-O2}, @option{-O3}.
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+@item -fallow-store-data-races
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+@opindex fallow-store-data-races
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+Allow the compiler to introduce new data races on stores.
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+
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+Enabled at level @option{-Ofast}.
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+
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@item -funit-at-a-time
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@opindex funit-at-a-time
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This option is left for compatibility reasons. @option{-funit-at-a-time}
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@@ -11902,10 +11909,6 @@ The maximum number of conditional store
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if either vectorization (@option{-ftree-vectorize}) or if-conversion
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(@option{-ftree-loop-if-convert}) is disabled.
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-@item allow-store-data-races
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-Allow optimizers to introduce new data races on stores.
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-Set to 1 to allow, otherwise to 0.
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-
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@item case-values-threshold
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The smallest number of different values for which it is best to use a
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jump-table instead of a tree of conditional branches. If the value is
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diff -uprN a/gcc/opts.c b/gcc/opts.c
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--- a/gcc/opts.c 2020-05-28 16:12:58.847511599 +0800
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+++ b/gcc/opts.c 2020-05-28 15:54:35.713511589 +0800
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@@ -560,6 +560,7 @@ static const struct default_options defa
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/* -Ofast adds optimizations to -O3. */
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{ OPT_LEVELS_FAST, OPT_ffast_math, NULL, 1 },
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+ { OPT_LEVELS_FAST, OPT_fallow_store_data_races, NULL, 1 },
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{ OPT_LEVELS_NONE, 0, NULL, 0 }
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};
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@@ -682,13 +683,6 @@ default_options_optimization (struct gcc
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: default_param_value (PARAM_MAX_DSE_ACTIVE_LOCAL_STORES) / 10,
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opts->x_param_values, opts_set->x_param_values);
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- /* At -Ofast, allow store motion to introduce potential race conditions. */
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- maybe_set_param_value
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- (PARAM_ALLOW_STORE_DATA_RACES,
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- opts->x_optimize_fast ? 1
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- : default_param_value (PARAM_ALLOW_STORE_DATA_RACES),
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- opts->x_param_values, opts_set->x_param_values);
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-
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if (opts->x_optimize_size)
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/* We want to crossjump as much as possible. */
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maybe_set_param_value (PARAM_MIN_CROSSJUMP_INSNS, 1,
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diff -uprN a/gcc/params.def b/gcc/params.def
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--- a/gcc/params.def 2020-05-28 16:12:58.831511599 +0800
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+++ b/gcc/params.def 2020-05-28 15:54:35.725511589 +0800
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@@ -1199,12 +1199,6 @@ DEFPARAM (PARAM_CASE_VALUES_THRESHOLD,
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"if 0, use the default for the machine.",
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0, 0, 0)
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-/* Data race flags for C++0x memory model compliance. */
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-DEFPARAM (PARAM_ALLOW_STORE_DATA_RACES,
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- "allow-store-data-races",
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- "Allow new data races on stores to be introduced.",
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- 0, 0, 1)
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-
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/* Reassociation width to be used by tree reassoc optimization. */
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DEFPARAM (PARAM_TREE_REASSOC_WIDTH,
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"tree-reassoc-width",
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diff -uprN a/gcc/params.h b/gcc/params.h
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--- a/gcc/params.h 2020-05-28 16:12:58.843511599 +0800
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+++ b/gcc/params.h 2020-05-28 15:54:35.725511589 +0800
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@@ -228,8 +228,6 @@ extern void init_param_values (int *para
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PARAM_VALUE (PARAM_MAX_STORES_TO_SINK)
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#define ALLOW_LOAD_DATA_RACES \
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PARAM_VALUE (PARAM_ALLOW_LOAD_DATA_RACES)
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-#define ALLOW_STORE_DATA_RACES \
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- PARAM_VALUE (PARAM_ALLOW_STORE_DATA_RACES)
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#define ALLOW_PACKED_LOAD_DATA_RACES \
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PARAM_VALUE (PARAM_ALLOW_PACKED_LOAD_DATA_RACES)
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#define ALLOW_PACKED_STORE_DATA_RACES \
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diff -uprN a/gcc/testsuite/c-c++-common/cxxbitfields-3.c b/gcc/testsuite/c-c++-common/cxxbitfields-3.c
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--- a/gcc/testsuite/c-c++-common/cxxbitfields-3.c 2020-05-28 16:12:56.959511599 +0800
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+++ b/gcc/testsuite/c-c++-common/cxxbitfields-3.c 2020-05-28 15:54:33.853511589 +0800
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@@ -1,5 +1,5 @@
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/* { dg-do compile { target i?86-*-* x86_64-*-* } } */
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-/* { dg-options "-O2 --param allow-store-data-races=0" } */
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+/* { dg-options "-O2 -fno-allow-store-data-races" } */
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/* Make sure we don't narrow down to a QI or HI to store into VAR.J,
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but instead use an SI. */
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diff -uprN a/gcc/testsuite/c-c++-common/cxxbitfields-6.c b/gcc/testsuite/c-c++-common/cxxbitfields-6.c
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--- a/gcc/testsuite/c-c++-common/cxxbitfields-6.c 2020-05-28 16:12:56.935511599 +0800
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+++ b/gcc/testsuite/c-c++-common/cxxbitfields-6.c 2020-05-28 15:54:33.845511589 +0800
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@@ -1,6 +1,6 @@
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/* PR middle-end/50141 */
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/* { dg-do compile } */
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-/* { dg-options "-O2 --param allow-store-data-races=0" } */
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+/* { dg-options "-O2 -fno-allow-store-data-races" } */
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struct S
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{
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diff -uprN a/gcc/testsuite/c-c++-common/simulate-thread/bitfields-1.c b/gcc/testsuite/c-c++-common/simulate-thread/bitfields-1.c
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--- a/gcc/testsuite/c-c++-common/simulate-thread/bitfields-1.c 2020-05-28 16:12:56.939511599 +0800
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+++ b/gcc/testsuite/c-c++-common/simulate-thread/bitfields-1.c 2020-05-28 15:54:33.821511589 +0800
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@@ -1,5 +1,5 @@
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/* { dg-do link } */
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-/* { dg-options "--param allow-store-data-races=0" } */
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+/* { dg-options "-fno-allow-store-data-races" } */
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/* { dg-final { simulate-thread } } */
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#include <stdio.h>
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diff -uprN a/gcc/testsuite/c-c++-common/simulate-thread/bitfields-2.c b/gcc/testsuite/c-c++-common/simulate-thread/bitfields-2.c
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--- a/gcc/testsuite/c-c++-common/simulate-thread/bitfields-2.c 2020-05-28 16:12:56.939511599 +0800
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+++ b/gcc/testsuite/c-c++-common/simulate-thread/bitfields-2.c 2020-05-28 15:54:33.821511589 +0800
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@@ -1,5 +1,5 @@
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/* { dg-do link { target { ! int16 } } } */
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-/* { dg-options "--param allow-store-data-races=0" } */
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+/* { dg-options "-fno-allow-store-data-races" } */
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/* { dg-final { simulate-thread } } */
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#include <stdio.h>
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diff -uprN a/gcc/testsuite/c-c++-common/simulate-thread/bitfields-3.c b/gcc/testsuite/c-c++-common/simulate-thread/bitfields-3.c
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--- a/gcc/testsuite/c-c++-common/simulate-thread/bitfields-3.c 2020-05-28 16:12:56.939511599 +0800
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+++ b/gcc/testsuite/c-c++-common/simulate-thread/bitfields-3.c 2020-05-28 15:54:33.821511589 +0800
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@@ -1,5 +1,5 @@
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/* { dg-do link } */
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-/* { dg-options "--param allow-store-data-races=0" } */
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+/* { dg-options "-fno-allow-store-data-races" } */
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/* { dg-final { simulate-thread } } */
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#include <stdio.h>
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diff -uprN a/gcc/testsuite/c-c++-common/simulate-thread/bitfields-4.c b/gcc/testsuite/c-c++-common/simulate-thread/bitfields-4.c
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--- a/gcc/testsuite/c-c++-common/simulate-thread/bitfields-4.c 2020-05-28 16:12:56.939511599 +0800
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+++ b/gcc/testsuite/c-c++-common/simulate-thread/bitfields-4.c 2020-05-28 15:54:33.821511589 +0800
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@@ -1,5 +1,5 @@
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/* { dg-do link } */
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-/* { dg-options "--param allow-store-data-races=0" } */
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+/* { dg-options "-fno-allow-store-data-races" } */
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/* { dg-final { simulate-thread } } */
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#include <stdio.h>
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diff -uprN a/gcc/testsuite/gcc.dg/lto/pr52097_0.c b/gcc/testsuite/gcc.dg/lto/pr52097_0.c
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--- a/gcc/testsuite/gcc.dg/lto/pr52097_0.c 2020-05-28 16:12:57.803511599 +0800
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+++ b/gcc/testsuite/gcc.dg/lto/pr52097_0.c 2020-05-28 15:54:34.777511589 +0800
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@@ -1,5 +1,5 @@
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/* { dg-lto-do link } */
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-/* { dg-lto-options { { -O -flto -fexceptions -fnon-call-exceptions --param allow-store-data-races=0 } } } */
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+/* { dg-lto-options { { -O -flto -fexceptions -fnon-call-exceptions -fno-allow-store-data-races } } } */
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/* { dg-require-effective-target exceptions } */
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typedef struct { unsigned int e0 : 16; } s1;
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diff -uprN a/gcc/testsuite/gcc.dg/simulate-thread/speculative-store-2.c b/gcc/testsuite/gcc.dg/simulate-thread/speculative-store-2.c
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--- a/gcc/testsuite/gcc.dg/simulate-thread/speculative-store-2.c 2020-05-28 16:12:57.815511599 +0800
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+++ b/gcc/testsuite/gcc.dg/simulate-thread/speculative-store-2.c 2020-05-28 15:54:34.781511589 +0800
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@@ -1,5 +1,5 @@
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/* { dg-do link } */
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-/* { dg-options "--param allow-store-data-races=0 -O2" } */
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+/* { dg-options "-fno-allow-store-data-races -O2" } */
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/* { dg-final { simulate-thread } } */
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#include <stdio.h>
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diff -uprN a/gcc/testsuite/gcc.dg/simulate-thread/speculative-store-3.c b/gcc/testsuite/gcc.dg/simulate-thread/speculative-store-3.c
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--- a/gcc/testsuite/gcc.dg/simulate-thread/speculative-store-3.c 2020-05-28 16:12:57.815511599 +0800
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+++ b/gcc/testsuite/gcc.dg/simulate-thread/speculative-store-3.c 2020-05-28 15:54:34.781511589 +0800
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@@ -1,5 +1,5 @@
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/* { dg-do link } */
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-/* { dg-options "--param allow-store-data-races=0 -O2" } */
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+/* { dg-options "-fno-allow-store-data-races -O2" } */
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/* { dg-final { simulate-thread } } */
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#include <stdio.h>
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diff -uprN a/gcc/testsuite/gcc.dg/simulate-thread/speculative-store-4.c b/gcc/testsuite/gcc.dg/simulate-thread/speculative-store-4.c
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--- a/gcc/testsuite/gcc.dg/simulate-thread/speculative-store-4.c 2020-05-28 16:12:57.815511599 +0800
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+++ b/gcc/testsuite/gcc.dg/simulate-thread/speculative-store-4.c 2020-05-28 15:54:34.781511589 +0800
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@@ -1,5 +1,5 @@
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/* { dg-do link } */
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-/* { dg-options "--param allow-store-data-races=0" } */
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+/* { dg-options "-fno-allow-store-data-races" } */
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/* { dg-final { simulate-thread } } */
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#include <stdio.h>
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diff -uprN a/gcc/testsuite/gcc.dg/simulate-thread/speculative-store.c b/gcc/testsuite/gcc.dg/simulate-thread/speculative-store.c
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--- a/gcc/testsuite/gcc.dg/simulate-thread/speculative-store.c 2020-05-28 16:12:57.815511599 +0800
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+++ b/gcc/testsuite/gcc.dg/simulate-thread/speculative-store.c 2020-05-28 15:54:34.781511589 +0800
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@@ -1,12 +1,12 @@
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/* { dg-do link } */
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-/* { dg-options "--param allow-store-data-races=0" } */
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+/* { dg-options "-fno-allow-store-data-races" } */
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/* { dg-final { simulate-thread } } */
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#include <stdio.h>
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#include "simulate-thread.h"
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/* This file tests that speculative store movement out of a loop doesn't
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- happen. This is disallowed when --param allow-store-data-races is 0. */
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+ happen. This is disallowed when -fno-allow-store-data-races. */
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int global = 100;
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diff -uprN a/gcc/testsuite/gcc.dg/tree-ssa/20050314-1.c b/gcc/testsuite/gcc.dg/tree-ssa/20050314-1.c
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--- a/gcc/testsuite/gcc.dg/tree-ssa/20050314-1.c 2020-05-28 16:12:58.027511599 +0800
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+++ b/gcc/testsuite/gcc.dg/tree-ssa/20050314-1.c 2020-05-28 15:54:34.997511589 +0800
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@@ -1,5 +1,5 @@
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/* { dg-do compile } */
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-/* { dg-options "-O1 -fdump-tree-lim2-details --param allow-store-data-races=1" } */
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+/* { dg-options "-O1 -fdump-tree-lim2-details -fallow-store-data-races" } */
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float a[100];
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diff -uprN a/gcc/testsuite/g++.dg/simulate-thread/bitfields-2.C b/gcc/testsuite/g++.dg/simulate-thread/bitfields-2.C
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--- a/gcc/testsuite/g++.dg/simulate-thread/bitfields-2.C 2020-05-28 16:12:57.015511599 +0800
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+++ b/gcc/testsuite/g++.dg/simulate-thread/bitfields-2.C 2020-05-28 15:54:33.885511589 +0800
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@@ -1,5 +1,5 @@
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/* { dg-do link } */
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-/* { dg-options "--param allow-store-data-races=0" } */
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+/* { dg-options "-fno-allow-store-data-races" } */
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/* { dg-final { simulate-thread } } */
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/* Test that setting <var.a> does not touch either <var.b> or <var.c>.
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diff -uprN a/gcc/testsuite/g++.dg/simulate-thread/bitfields.C b/gcc/testsuite/g++.dg/simulate-thread/bitfields.C
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--- a/gcc/testsuite/g++.dg/simulate-thread/bitfields.C 2020-05-28 16:12:57.015511599 +0800
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+++ b/gcc/testsuite/g++.dg/simulate-thread/bitfields.C 2020-05-28 15:54:33.885511589 +0800
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@@ -1,5 +1,5 @@
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/* { dg-do link } */
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-/* { dg-options "--param allow-store-data-races=0" } */
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+/* { dg-options "-fno-allow-store-data-races" } */
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/* { dg-final { simulate-thread } } */
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/* Test that setting <var.a> does not touch either <var.b> or <var.c>.
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diff -uprN a/gcc/tree-if-conv.c b/gcc/tree-if-conv.c
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--- a/gcc/tree-if-conv.c 2020-05-28 16:12:58.831511599 +0800
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+++ b/gcc/tree-if-conv.c 2020-05-28 15:54:35.641511589 +0800
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@@ -913,10 +913,10 @@ ifcvt_memrefs_wont_trap (gimple *stmt, v
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to unconditionally. */
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if (base_master_dr
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&& DR_BASE_W_UNCONDITIONALLY (*base_master_dr))
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- return PARAM_VALUE (PARAM_ALLOW_STORE_DATA_RACES);
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+ return flag_store_data_races;
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/* or the base is known to be not readonly. */
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else if (base_object_writable (DR_REF (a)))
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- return PARAM_VALUE (PARAM_ALLOW_STORE_DATA_RACES);
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+ return flag_store_data_races;
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}
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return false;
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diff -uprN a/gcc/tree-ssa-loop-im.c b/gcc/tree-ssa-loop-im.c
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--- a/gcc/tree-ssa-loop-im.c 2020-05-28 16:12:58.779511599 +0800
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+++ b/gcc/tree-ssa-loop-im.c 2020-05-28 15:54:35.729511589 +0800
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@@ -2088,7 +2088,7 @@ execute_sm (struct loop *loop, vec<edge>
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for_each_index (&ref->mem.ref, force_move_till, &fmt_data);
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if (bb_in_transaction (loop_preheader_edge (loop)->src)
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- || (! PARAM_VALUE (PARAM_ALLOW_STORE_DATA_RACES)
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+ || (! flag_store_data_races
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&& ! ref_always_accessed_p (loop, ref, true)))
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multi_threaded_model_p = true;
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