185 lines
6.3 KiB
Diff
185 lines
6.3 KiB
Diff
From 03a6da5290c60437a0fc97347bb84c120c26cc58 Mon Sep 17 00:00:00 2001
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From: Xi Ruoyao <xry111@xry111.site>
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Date: Wed, 6 Jul 2022 13:45:55 +0800
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Subject: [PATCH 001/124] loongarch: add alternatives for idiv insns to improve
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code generation
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Currently in the description of LoongArch integer division instructions,
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the output is marked as earlyclobbered ('&'). It's necessary when
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loongarch_check_zero_div_p() because clobbering operand 2 (divisor) will
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make the checking for zero divisor impossible.
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But, for -mno-check-zero-division (the default of GCC >= 12.2 for
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optimized code), the output is not earlyclobbered at all. And, the
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read of operand 1 only occurs before clobbering the output. So we make
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three alternatives for an idiv instruction:
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* (=r,r,r): For -mno-check-zero-division.
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* (=&r,r,r): For -mcheck-zero-division.
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* (=&r,0,r): For -mcheck-zero-division, to explicitly allow patterns
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like "div.d $a0, $a0, $a1".
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gcc/ChangeLog:
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* config/loongarch/loongarch.cc (loongarch_check_zero_div_p):
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Remove static, for use in the machine description file.
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* config/loongarch/loongarch-protos.h:
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(loongarch_check_zero_div_p): Add prototype.
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* config/loongarch/loongarch.md (enabled): New attr.
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(*<optab><mode>3): Add (=r,r,r) and (=&r,0,r) alternatives for
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idiv. Conditionally enable the alternatives using
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loongarch_check_zero_div_p.
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(<optab>di3_fake): Likewise.
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gcc/testsuite/ChangeLog:
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* gcc.target/loongarch/div-1.c: New test.
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* gcc.target/loongarch/div-2.c: New test.
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* gcc.target/loongarch/div-3.c: New test.
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Signed-off-by: Peng Fan <fanpeng@loongson.cn>
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Signed-off-by: ticat_fp <fanpeng@loongson.cn>
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---
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gcc/config/loongarch/loongarch-protos.h | 1 +
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gcc/config/loongarch/loongarch.cc | 2 +-
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gcc/config/loongarch/loongarch.md | 28 +++++++++++++++-------
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gcc/testsuite/gcc.target/loongarch/div-1.c | 9 +++++++
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gcc/testsuite/gcc.target/loongarch/div-2.c | 9 +++++++
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gcc/testsuite/gcc.target/loongarch/div-3.c | 9 +++++++
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6 files changed, 49 insertions(+), 9 deletions(-)
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create mode 100644 gcc/testsuite/gcc.target/loongarch/div-1.c
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create mode 100644 gcc/testsuite/gcc.target/loongarch/div-2.c
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create mode 100644 gcc/testsuite/gcc.target/loongarch/div-3.c
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diff --git a/gcc/config/loongarch/loongarch-protos.h b/gcc/config/loongarch/loongarch-protos.h
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index 2144c2421..2287fd376 100644
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--- a/gcc/config/loongarch/loongarch-protos.h
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+++ b/gcc/config/loongarch/loongarch-protos.h
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@@ -130,6 +130,7 @@ extern bool loongarch_symbol_binds_local_p (const_rtx);
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extern const char *current_section_name (void);
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extern unsigned int current_section_flags (void);
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extern bool loongarch_use_ins_ext_p (rtx, HOST_WIDE_INT, HOST_WIDE_INT);
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+extern bool loongarch_check_zero_div_p (void);
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union loongarch_gen_fn_ptrs
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{
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diff --git a/gcc/config/loongarch/loongarch.cc b/gcc/config/loongarch/loongarch.cc
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index 22901cb61..750d53bbe 100644
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--- a/gcc/config/loongarch/loongarch.cc
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+++ b/gcc/config/loongarch/loongarch.cc
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@@ -2110,7 +2110,7 @@ loongarch_load_store_insns (rtx mem, rtx_insn *insn)
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/* Return true if we need to trap on division by zero. */
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-static bool
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+bool
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loongarch_check_zero_div_p (void)
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{
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/* if -m[no-]check-zero-division is given explicitly. */
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diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loongarch.md
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index 8f8412fba..6bca2ed39 100644
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--- a/gcc/config/loongarch/loongarch.md
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+++ b/gcc/config/loongarch/loongarch.md
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@@ -110,6 +110,8 @@
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;;
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;; ....................
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+(define_attr "enabled" "no,yes" (const_string "yes"))
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+
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(define_attr "got" "unset,load"
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(const_string "unset"))
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@@ -763,26 +765,36 @@
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})
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(define_insn "*<optab><mode>3"
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- [(set (match_operand:GPR 0 "register_operand" "=&r")
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- (any_div:GPR (match_operand:GPR 1 "register_operand" "r")
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- (match_operand:GPR 2 "register_operand" "r")))]
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+ [(set (match_operand:GPR 0 "register_operand" "=r,&r,&r")
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+ (any_div:GPR (match_operand:GPR 1 "register_operand" "r,r,0")
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+ (match_operand:GPR 2 "register_operand" "r,r,r")))]
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""
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{
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return loongarch_output_division ("<insn>.<d><u>\t%0,%1,%2", operands);
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}
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[(set_attr "type" "idiv")
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- (set_attr "mode" "<MODE>")])
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+ (set_attr "mode" "<MODE>")
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+ (set (attr "enabled")
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+ (if_then_else
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+ (match_test "!!which_alternative == loongarch_check_zero_div_p()")
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+ (const_string "yes")
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+ (const_string "no")))])
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(define_insn "<optab>di3_fake"
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- [(set (match_operand:SI 0 "register_operand" "=&r")
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- (any_div:SI (match_operand:DI 1 "register_operand" "r")
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- (match_operand:DI 2 "register_operand" "r")))]
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+ [(set (match_operand:SI 0 "register_operand" "=r,&r,&r")
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+ (any_div:SI (match_operand:DI 1 "register_operand" "r,r,0")
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+ (match_operand:DI 2 "register_operand" "r,r,r")))]
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""
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{
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return loongarch_output_division ("<insn>.w<u>\t%0,%1,%2", operands);
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}
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[(set_attr "type" "idiv")
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- (set_attr "mode" "SI")])
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+ (set_attr "mode" "SI")
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+ (set (attr "enabled")
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+ (if_then_else
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+ (match_test "!!which_alternative == loongarch_check_zero_div_p()")
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+ (const_string "yes")
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+ (const_string "no")))])
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;; Floating point multiply accumulate instructions.
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diff --git a/gcc/testsuite/gcc.target/loongarch/div-1.c b/gcc/testsuite/gcc.target/loongarch/div-1.c
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new file mode 100644
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index 000000000..b1683f853
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--- /dev/null
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+++ b/gcc/testsuite/gcc.target/loongarch/div-1.c
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@@ -0,0 +1,9 @@
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+/* { dg-do compile } */
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+/* { dg-options "-O2 -mcheck-zero-division" } */
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+/* { dg-final { scan-assembler "div.\[wd\]\t\\\$r4,\\\$r4,\\\$r5" } } */
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+
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+long
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+div(long a, long b)
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+{
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+ return a / b;
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+}
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diff --git a/gcc/testsuite/gcc.target/loongarch/div-2.c b/gcc/testsuite/gcc.target/loongarch/div-2.c
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new file mode 100644
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index 000000000..4c2beb5b9
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--- /dev/null
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+++ b/gcc/testsuite/gcc.target/loongarch/div-2.c
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@@ -0,0 +1,9 @@
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+/* { dg-do compile } */
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+/* { dg-options "-O2 -mno-check-zero-division" } */
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+/* { dg-final { scan-assembler "div.\[wd\]\t\\\$r4,\\\$r5,\\\$r4" } } */
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+
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+long
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+div(long a, long b)
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+{
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+ return b / a;
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+}
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diff --git a/gcc/testsuite/gcc.target/loongarch/div-3.c b/gcc/testsuite/gcc.target/loongarch/div-3.c
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new file mode 100644
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index 000000000..d25969263
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--- /dev/null
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+++ b/gcc/testsuite/gcc.target/loongarch/div-3.c
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@@ -0,0 +1,9 @@
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+/* { dg-do compile } */
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+/* { dg-options "-O2 -mcheck-zero-division" } */
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+/* { dg-final { scan-assembler-not "div.\[wd\]\t\\\$r4,\\\$r5,\\\$r4" } } */
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+
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+long
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+div(long a, long b)
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+{
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+ return b / a;
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+}
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--
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2.33.0
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