gcc/fix-cost-of-plus.patch
jdkboy db8a90ff34 Add several enhancement patches
- Add add-checks-to-avoid-spoiling-if-conversion.patch
 - Add add-option-fallow-store-data-races.patch
 - Add complete-struct-reorg.patch
 - Add cse-in-vectorization.patch
 - Add enable-simd-math.patch
 - Add fix-ICE-avoid-issueing-loads-in-SM-when-possible.patch
 - Add fix-ICE-in-compute_live_loop_exits.patch
 - Add fix-ICE-in-copy_reference_ops_from_ref.patch
 - Add fix-ICE-in-declare-return-variable.patch
 - Add fix-ICE-in-exact_div.patch
 - Add fix-ICE-in-gimple_op.patch
 - Add fix-ICE-in-model_update_limit_points_in_group.patch
 - Add fix-ICE-in-reload.patch
 - Add fix-ICE-in-store_constructor.patch
 - Add fix-ICE-in-vec.patch
 - Add fix-ICE-in-vect_create_epilog_for_reduction.patch
 - Add fix-ICE-in-vect_create_epilog_for_reduction_2.patch
 - Add fix-ICE-in-vect_create_epilog_for_reduction_3.patch
 - Add fix-ICE-in-vect_get_vec_def_for_stmt_copy.patch
 - Add fix-ICE-in-vect_slp_analyze_node_operations.patch
 - Add fix-ICE-in-vect_stmt_to_vectorize.patch
 - Add fix-ICE-in-vect_transform_stmt.patch
 - Add fix-ICE-in-vectorizable_condition.patch
 - Add fix-ICE-in-verify_ssa.patch
 - Add fix-ICE-statement-uses-released-SSA-name.patch
 - Add fix-ICE-when-vectorizing-nested-cycles.patch
 - Add fix-SSA-update-for-vectorizer-epilogue.patch
 - Add fix-do-not-build-op.patch
 - Add fix-load-eliding-in-SM.patch
 - Add fix-wrong-vectorizer-code.patch
 - Add generate-csel-for-arrayref.patch
 - Add ipa-const-prop-self-recursion-bugfix.patch
 - Add ipa-const-prop.patch
 - Add ipa-struct-reorg-bugfix.patch
 - Add ipa-struct-reorg.patch
 - Add medium-code-mode.patch
 - Add reduction-chain-slp-option.patch
 - Add reductions-slp-enhancement.patch
 - Add simplify-removing-subregs.patch
 - Add tighten-range-for-generating-csel.patch
 - Add vectorization-enhancement.patch
 - Add add-checks-to-avoid-spoiling-if-conversion.patch
 - Add add-option-fallow-store-data-races.patch
 - Add complete-struct-reorg.patch
 - Add cse-in-vectorization.patch
 - Add enable-simd-math.patch
 - Add fix-ICE-avoid-issueing-loads-in-SM-when-possible.patch
 - Add fix-ICE-in-compute_live_loop_exits.patch
 - Add fix-ICE-in-copy_reference_ops_from_ref.patch
 - Add fix-ICE-in-declare-return-variable.patch
 - Add fix-ICE-in-exact_div.patch
 - Add fix-ICE-in-gimple_op.patch
 - Add fix-ICE-in-model_update_limit_points_in_group.patch
 - Add fix-ICE-in-reload.patch
 - Add fix-ICE-in-store_constructor.patch
 - Add fix-ICE-in-vec.patch
 - Add fix-ICE-in-vect_create_epilog_for_reduction.patch
 - Add fix-ICE-in-vect_create_epilog_for_reduction_2.patch
 - Add fix-ICE-in-vect_create_epilog_for_reduction_3.patch
 - Add fix-ICE-in-vect_get_vec_def_for_stmt_copy.patch
 - Add fix-ICE-in-vect_slp_analyze_node_operations.patch
 - Add fix-ICE-in-vect_stmt_to_vectorize.patch
 - Add fix-ICE-in-vect_transform_stmt.patch
 - Add fix-ICE-in-vectorizable_condition.patch
 - Add fix-ICE-in-verify_ssa.patch
 - Add fix-ICE-statement-uses-released-SSA-name.patch
 - Add fix-ICE-when-vectorizing-nested-cycles.patch
 - Add fix-SSA-update-for-vectorizer-epilogue.patch
 - Add fix-do-not-build-op.patch
 - Add fix-load-eliding-in-SM.patch
 - Add fix-wrong-vectorizer-code.patch
 - Add generate-csel-for-arrayref.patch
 - Add ipa-const-prop-self-recursion-bugfix.patch
 - Add ipa-const-prop.patch
 - Add ipa-struct-reorg-bugfix.patch
 - Add ipa-struct-reorg.patch
 - Add medium-code-mode.patch
 - Add reduction-chain-slp-option.patch
 - Add reductions-slp-enhancement.patch
 - Add simplify-removing-subregs.patch
 - Add tighten-range-for-generating-csel.patch
 - Add vectorization-enhancement.patch
2020-08-29 15:26:30 +08:00

17 lines
586 B
Diff

AArch64-Fix-cost-of-plus-.-const_int-C.patch:
commit 835d50c66aa5bde2f354a6e63a2afa7d2f76a05a
diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index 56a4a47db73..71d44de1d0a 100644
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -10753,7 +10753,7 @@ cost_plus:
}
if (GET_MODE_CLASS (mode) == MODE_INT
- && ((CONST_INT_P (op1) && aarch64_uimm12_shift (INTVAL (op1)))
+ && (aarch64_plus_immediate (op1, mode)
|| aarch64_sve_addvl_addpl_immediate (op1, mode)))
{
*cost += rtx_cost (op0, mode, PLUS, 0, speed);