- Add add-checks-to-avoid-spoiling-if-conversion.patch - Add add-option-fallow-store-data-races.patch - Add complete-struct-reorg.patch - Add cse-in-vectorization.patch - Add enable-simd-math.patch - Add fix-ICE-avoid-issueing-loads-in-SM-when-possible.patch - Add fix-ICE-in-compute_live_loop_exits.patch - Add fix-ICE-in-copy_reference_ops_from_ref.patch - Add fix-ICE-in-declare-return-variable.patch - Add fix-ICE-in-exact_div.patch - Add fix-ICE-in-gimple_op.patch - Add fix-ICE-in-model_update_limit_points_in_group.patch - Add fix-ICE-in-reload.patch - Add fix-ICE-in-store_constructor.patch - Add fix-ICE-in-vec.patch - Add fix-ICE-in-vect_create_epilog_for_reduction.patch - Add fix-ICE-in-vect_create_epilog_for_reduction_2.patch - Add fix-ICE-in-vect_create_epilog_for_reduction_3.patch - Add fix-ICE-in-vect_get_vec_def_for_stmt_copy.patch - Add fix-ICE-in-vect_slp_analyze_node_operations.patch - Add fix-ICE-in-vect_stmt_to_vectorize.patch - Add fix-ICE-in-vect_transform_stmt.patch - Add fix-ICE-in-vectorizable_condition.patch - Add fix-ICE-in-verify_ssa.patch - Add fix-ICE-statement-uses-released-SSA-name.patch - Add fix-ICE-when-vectorizing-nested-cycles.patch - Add fix-SSA-update-for-vectorizer-epilogue.patch - Add fix-do-not-build-op.patch - Add fix-load-eliding-in-SM.patch - Add fix-wrong-vectorizer-code.patch - Add generate-csel-for-arrayref.patch - Add ipa-const-prop-self-recursion-bugfix.patch - Add ipa-const-prop.patch - Add ipa-struct-reorg-bugfix.patch - Add ipa-struct-reorg.patch - Add medium-code-mode.patch - Add reduction-chain-slp-option.patch - Add reductions-slp-enhancement.patch - Add simplify-removing-subregs.patch - Add tighten-range-for-generating-csel.patch - Add vectorization-enhancement.patch - Add add-checks-to-avoid-spoiling-if-conversion.patch - Add add-option-fallow-store-data-races.patch - Add complete-struct-reorg.patch - Add cse-in-vectorization.patch - Add enable-simd-math.patch - Add fix-ICE-avoid-issueing-loads-in-SM-when-possible.patch - Add fix-ICE-in-compute_live_loop_exits.patch - Add fix-ICE-in-copy_reference_ops_from_ref.patch - Add fix-ICE-in-declare-return-variable.patch - Add fix-ICE-in-exact_div.patch - Add fix-ICE-in-gimple_op.patch - Add fix-ICE-in-model_update_limit_points_in_group.patch - Add fix-ICE-in-reload.patch - Add fix-ICE-in-store_constructor.patch - Add fix-ICE-in-vec.patch - Add fix-ICE-in-vect_create_epilog_for_reduction.patch - Add fix-ICE-in-vect_create_epilog_for_reduction_2.patch - Add fix-ICE-in-vect_create_epilog_for_reduction_3.patch - Add fix-ICE-in-vect_get_vec_def_for_stmt_copy.patch - Add fix-ICE-in-vect_slp_analyze_node_operations.patch - Add fix-ICE-in-vect_stmt_to_vectorize.patch - Add fix-ICE-in-vect_transform_stmt.patch - Add fix-ICE-in-vectorizable_condition.patch - Add fix-ICE-in-verify_ssa.patch - Add fix-ICE-statement-uses-released-SSA-name.patch - Add fix-ICE-when-vectorizing-nested-cycles.patch - Add fix-SSA-update-for-vectorizer-epilogue.patch - Add fix-do-not-build-op.patch - Add fix-load-eliding-in-SM.patch - Add fix-wrong-vectorizer-code.patch - Add generate-csel-for-arrayref.patch - Add ipa-const-prop-self-recursion-bugfix.patch - Add ipa-const-prop.patch - Add ipa-struct-reorg-bugfix.patch - Add ipa-struct-reorg.patch - Add medium-code-mode.patch - Add reduction-chain-slp-option.patch - Add reductions-slp-enhancement.patch - Add simplify-removing-subregs.patch - Add tighten-range-for-generating-csel.patch - Add vectorization-enhancement.patch
75 lines
3.0 KiB
Diff
75 lines
3.0 KiB
Diff
This backport contains 1 patch from gcc main stream tree.
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The commit id of these patchs list as following in the order of time.
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0001-widening_mul-restrict-ops-to-be-defined-in-the-same-.patch:
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d21dff5b4fee51ae432143065bededfc763dc344
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diff -Nurp a/gcc/testsuite/gcc.dg/pr94269.c b/gcc/testsuite/gcc.dg/pr94269.c
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--- a/gcc/testsuite/gcc.dg/pr94269.c 1970-01-01 08:00:00.000000000 +0800
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+++ b/gcc/testsuite/gcc.dg/pr94269.c 2020-04-17 17:04:50.608000000 +0800
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@@ -0,0 +1,26 @@
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+/* { dg-do compile { target aarch64*-*-* } } */
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+/* { dg-options "-O2 -ftree-loop-vectorize -funsafe-math-optimizations -march=armv8.2-a+sve -msve-vector-bits=256" } */
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+
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+float
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+foo(long n, float *x, int inc_x,
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+ float *y, int inc_y)
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+{
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+ float dot = 0.0;
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+ int ix = 0, iy = 0;
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+
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+ if (n < 0) {
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+ return dot;
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+ }
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+
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+ int i = 0;
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+ while (i < n) {
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+ dot += y[iy] * x[ix];
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+ ix += inc_x;
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+ iy += inc_y;
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+ i++;
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+ }
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+
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+ return dot;
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+}
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+
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+/* { dg-final { scan-assembler-not "smaddl" { target aarch64*-*-* } } } */
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diff -Nurp a/gcc/tree-ssa-math-opts.c b/gcc/tree-ssa-math-opts.c
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--- a/gcc/tree-ssa-math-opts.c 2020-04-17 16:43:59.540000000 +0800
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+++ b/gcc/tree-ssa-math-opts.c 2020-04-17 16:48:34.072036000 +0800
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@@ -2721,11 +2721,14 @@ convert_plusminus_to_widen (gimple_stmt_
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multiply-and-accumulate instructions.
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If the widened-multiplication result has more than one uses, it is
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- probably wiser not to do the conversion. */
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+ probably wiser not to do the conversion. Also restrict this operation
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+ to single basic block to avoid moving the multiply to a different block
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+ with a higher execution frequency. */
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if (code == PLUS_EXPR
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&& (rhs1_code == MULT_EXPR || rhs1_code == WIDEN_MULT_EXPR))
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{
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if (!has_single_use (rhs1)
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+ || gimple_bb (rhs1_stmt) != gimple_bb (stmt)
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|| !is_widening_mult_p (rhs1_stmt, &type1, &mult_rhs1,
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&type2, &mult_rhs2))
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return false;
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@@ -2735,6 +2738,7 @@ convert_plusminus_to_widen (gimple_stmt_
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else if (rhs2_code == MULT_EXPR || rhs2_code == WIDEN_MULT_EXPR)
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{
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if (!has_single_use (rhs2)
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+ || gimple_bb (rhs2_stmt) != gimple_bb (stmt)
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|| !is_widening_mult_p (rhs2_stmt, &type1, &mult_rhs1,
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&type2, &mult_rhs2))
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return false;
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diff -Nurp a/gcc/testsuite/gcc.target/aarch64/sve/var_stride_1.c b/gcc/testsuite/gcc.target/aarch64/sve/var_stride_1.c
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--- a/gcc/testsuite/gcc.target/aarch64/sve/var_stride_1.c 2020-03-31 09:51:36.000000000 +0800
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+++ b/gcc/testsuite/gcc.target/aarch64/sve/var_stride_1.c 2020-04-29 10:55:44.937471475 +0800
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@@ -17,7 +17,6 @@ f (TYPE *x, TYPE *y, unsigned short n, l
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/* { dg-final { scan-assembler {\tstr\tw[0-9]+} } } */
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/* Should multiply by (VF-1)*4 rather than (257-1)*4. */
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/* { dg-final { scan-assembler-not {, 1024} } } */
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-/* { dg-final { scan-assembler-not {\t.bfiz\t} } } */
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/* { dg-final { scan-assembler-not {lsl[^\n]*[, ]10} } } */
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/* { dg-final { scan-assembler-not {\tcmp\tx[0-9]+, 0} } } */
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/* { dg-final { scan-assembler-not {\tcmp\tw[0-9]+, 0} } } */
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