- avoid-cycling-on-vertain-subreg-reloads.patch: Add patch source comment - change-gcc-BASE-VER.patch: Likewise - dont-generate-IF_THEN_ELSE.patch: Likewise - fix-ICE-in-compute_live_loop_exits.patch: Likewise - fix-ICE-in-eliminate_stmt.patch: Likewise - fix-ICE-in-vect_create_epilog_for_reduction.patch: Likewise - fix-ICE-in-vect_stmt_to_vectorize.patch: Likewise - fix-ICE-in-verify_ssa.patch: Likewise - fix-ICE-when-vectorizing-nested-cycles.patch: Likewise - fix-cost-of-plus.patch: Likewise - ipa-const-prop-self-recursion-bugfix.patch: Likewise - simplify-removing-subregs.patch: Likewise - medium-code-mode.patch: Bugfix - fix-when-peeling-for-alignment.patch: Move to ... - fix-PR-92351-When-peeling-for-alignment.patch: ... this - AArch64-Fix-constraints-for-CPY-M.patch: New file - Apply-maximum-nunits-for-BB-SLP.patch: New file - Fix-EXTRACT_LAST_REDUCTION-segfault.patch: New file - Fix-up-push_partial_def-little-endian-bitfield.patch: New file - Fix-zero-masking-for-vcvtps2ph.patch: New file - IRA-Handle-fully-tied-destinations.patch: New file - SLP-VECT-Add-check-to-fix-96837.patch: New file - aarch64-Fix-ash-lr-lshr-mode-3-expanders.patch: New file - aarch64-Fix-bf16-and-matrix-g++-gfortran.patch: New file - aarch64-Fix-mismatched-SVE-predicate-modes.patch: New file - aarch64-fix-sve-acle-error.patch: New file - adjust-vector-cost-and-move-EXTRACT_LAST_REDUCTION-costing.patch: New file - bf16-and-matrix-characteristic.patch: New file - fix-ICE-IPA-compare-VRP-types.patch: New file - fix-ICE-in-affine-combination.patch: New file - fix-ICE-in-pass-vect.patch: New file - fix-ICE-in-vect_update_misalignment_for_peel.patch: New file - fix-addlosymdi-ICE-in-pass-reload.patch: New file - fix-an-ICE-in-vect_recog_mask_conversion_pattern.patch: New file - fix-avx512vl-vcvttpd2dq-2-fail.patch: New file - fix-issue499-add-nop-convert.patch: New file - fix-issue604-ldist-dependency-fixup.patch: New file - modulo-sched-Carefully-process-loop-counter-initiali.patch: New file - re-PR-target-91124-gcc.target-i386-avx512vl-vpshldvd.patch: New file - reduction-paths-with-unhandled-live-stmt.patch: New file - redundant-loop-elimination.patch: New file - sccvn-Improve-handling-of-load-masked-with-integer.patch: New file - speed-up-DDG-analysis-and-fix-bootstrap-compare-debug.patch: New file - store-merging-Consider-also-overlapping-stores-earlier.patch: New file - tree-optimization-96920-another-ICE-when-vectorizing.patch: New file - tree-optimization-97812-fix-range-query-in-VRP-asser.patch: New file - vectorizable-comparison-Swap-operands-only-once.patch: New file - x86-Fix-bf16-and-matrix.patch: New file
153 lines
3.9 KiB
Diff
153 lines
3.9 KiB
Diff
This backport contains 1 patch from gcc main stream tree.
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The commit id of these patchs list as following in the order of time.
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0001-vect-PR-92351-When-peeling-for-alignment-make-alignm.patch
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4e9d58d16767b1bc686f0c4b3bd2da25dc71e8f3
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diff --git a/gcc/testsuite/gcc.dg/vect/vect-peel-2-epilogues.c b/gcc/testsuite/gcc.dg/vect/vect-peel-2-epilogues.c
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new file mode 100644
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index 00000000000..c06fa442faf
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--- /dev/null
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+++ b/gcc/testsuite/gcc.dg/vect/vect-peel-2-epilogues.c
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@@ -0,0 +1,3 @@
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+/* { dg-require-effective-target vect_int } */
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+
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+#include "vect-peel-2-src.c"
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diff --git a/gcc/testsuite/gcc.dg/vect/vect-peel-2-src.c b/gcc/testsuite/gcc.dg/vect/vect-peel-2-src.c
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new file mode 100644
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index 00000000000..f6fc134c870
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--- /dev/null
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+++ b/gcc/testsuite/gcc.dg/vect/vect-peel-2-src.c
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@@ -0,0 +1,48 @@
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+#include <stdarg.h>
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+#include "tree-vect.h"
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+
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+#define N 128
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+
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+/* unaligned store. */
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+
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+int ib[N+7];
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+
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+__attribute__ ((noinline))
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+int main1 ()
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+{
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+ int i;
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+ int ia[N+1];
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+
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+ /* The store is aligned and the loads are misaligned with the same
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+ misalignment. Cost model is disabled. If misaligned stores are supported,
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+ we peel according to the loads to align them. */
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+ for (i = 0; i <= N; i++)
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+ {
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+ ia[i] = ib[i+2] + ib[i+6];
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+ }
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+
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+ /* check results: */
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+ for (i = 1; i <= N; i++)
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+ {
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+ if (ia[i] != ib[i+2] + ib[i+6])
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+ abort ();
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+ }
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+
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+ return 0;
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+}
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+
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+int main (void)
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+{
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+ int i;
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+
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+ check_vect ();
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+
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+ for (i = 0; i <= N+6; i++)
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+ {
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+ asm volatile ("" : "+r" (i));
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+ ib[i] = i;
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+ }
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+
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+ return main1 ();
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+}
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+
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diff --git a/gcc/testsuite/gcc.dg/vect/vect-peel-2.c b/gcc/testsuite/gcc.dg/vect/vect-peel-2.c
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index b6061c3b855..65e70bd4417 100644
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--- a/gcc/testsuite/gcc.dg/vect/vect-peel-2.c
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+++ b/gcc/testsuite/gcc.dg/vect/vect-peel-2.c
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@@ -1,52 +1,8 @@
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/* { dg-require-effective-target vect_int } */
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+/* Disabling epilogues until we find a better way to deal with scans. */
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+/* { dg-additional-options "--param vect-epilogues-nomask=0" } */
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-#include <stdarg.h>
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-#include "tree-vect.h"
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-
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-#define N 128
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-
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-/* unaligned store. */
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-
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-int ib[N+7];
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-
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-__attribute__ ((noinline))
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-int main1 ()
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-{
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- int i;
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- int ia[N+1];
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-
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- /* The store is aligned and the loads are misaligned with the same
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- misalignment. Cost model is disabled. If misaligned stores are supported,
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- we peel according to the loads to align them. */
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- for (i = 0; i <= N; i++)
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- {
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- ia[i] = ib[i+2] + ib[i+6];
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- }
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-
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- /* check results: */
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- for (i = 1; i <= N; i++)
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- {
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- if (ia[i] != ib[i+2] + ib[i+6])
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- abort ();
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- }
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-
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- return 0;
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-}
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-
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-int main (void)
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-{
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- int i;
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-
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- check_vect ();
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-
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- for (i = 0; i <= N+6; i++)
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- {
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- asm volatile ("" : "+r" (i));
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- ib[i] = i;
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- }
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-
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- return main1 ();
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-}
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+#include "vect-peel-2-src.c"
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/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */
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/* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 1 "vect" { target { { vect_element_align } && { vect_aligned_arrays } } } } } */
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diff --git a/gcc/tree-vect-data-refs.c b/gcc/tree-vect-data-refs.c
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index 36639b697f1..88f14e73d65 100644
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--- a/gcc/tree-vect-data-refs.c
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+++ b/gcc/tree-vect-data-refs.c
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@@ -938,6 +938,18 @@ vect_compute_data_ref_alignment (dr_vec_info *dr_info)
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= exact_div (vect_calculate_target_alignment (dr_info), BITS_PER_UNIT);
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DR_TARGET_ALIGNMENT (dr_info) = vector_alignment;
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+ /* If the main loop has peeled for alignment we have no way of knowing
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+ whether the data accesses in the epilogues are aligned. We can't at
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+ compile time answer the question whether we have entered the main loop or
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+ not. Fixes PR 92351. */
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+ if (loop_vinfo)
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+ {
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+ loop_vec_info orig_loop_vinfo = LOOP_VINFO_ORIG_LOOP_INFO (loop_vinfo);
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+ if (orig_loop_vinfo
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+ && LOOP_VINFO_PEELING_FOR_ALIGNMENT (orig_loop_vinfo) != 0)
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+ return;
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+ }
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+
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unsigned HOST_WIDE_INT vect_align_c;
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if (!vector_alignment.is_constant (&vect_align_c))
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return;
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