61 lines
2.1 KiB
Diff
61 lines
2.1 KiB
Diff
diff -urp a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
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--- a/gcc/config/arm/arm.c 2019-01-18 11:25:20.840179114 +0800
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+++ b/gcc/config/arm/arm.c 2019-01-18 11:25:47.548179817 +0800
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@@ -14306,18 +14306,36 @@ gen_movmem_ldrd_strd (rtx *operands)
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emit_move_insn (reg0, src);
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else
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{
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- emit_insn (gen_unaligned_loadsi (low_reg, src));
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- src = next_consecutive_mem (src);
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- emit_insn (gen_unaligned_loadsi (hi_reg, src));
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+ if (flag_lsrd_be_adjust && BYTES_BIG_ENDIAN && WORDS_BIG_ENDIAN)
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+ {
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+ emit_insn (gen_unaligned_loadsi (hi_reg, src));
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+ src = next_consecutive_mem (src);
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+ emit_insn (gen_unaligned_loadsi (low_reg, src));
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+ }
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+ else
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+ {
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+ emit_insn (gen_unaligned_loadsi (low_reg, src));
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+ src = next_consecutive_mem (src);
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+ emit_insn (gen_unaligned_loadsi (hi_reg, src));
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+ }
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}
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if (dst_aligned)
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emit_move_insn (dst, reg0);
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else
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{
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- emit_insn (gen_unaligned_storesi (dst, low_reg));
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- dst = next_consecutive_mem (dst);
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- emit_insn (gen_unaligned_storesi (dst, hi_reg));
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+ if (flag_lsrd_be_adjust && BYTES_BIG_ENDIAN && WORDS_BIG_ENDIAN)
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+ {
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+ emit_insn (gen_unaligned_storesi (dst, hi_reg));
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+ dst = next_consecutive_mem (dst);
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+ emit_insn (gen_unaligned_storesi (dst, low_reg));
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+ }
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+ else
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+ {
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+ emit_insn (gen_unaligned_storesi (dst, low_reg));
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+ dst = next_consecutive_mem (dst);
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+ emit_insn (gen_unaligned_storesi (dst, hi_reg));
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+ }
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}
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src = next_consecutive_mem (src);
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diff -urp a/gcc/config/arm/arm.opt b/gcc/config/arm/arm.opt
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--- a/gcc/config/arm/arm.opt 2019-01-18 11:25:20.840179114 +0800
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+++ b/gcc/config/arm/arm.opt 2019-01-18 11:28:51.744184666 +0800
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@@ -274,6 +274,10 @@ masm-syntax-unified
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Target Report Var(inline_asm_unified) Init(0) Save
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Assume unified syntax for inline assembly code.
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+mlsrd-be-adjust
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+Target Report Var(flag_lsrd_be_adjust) Init(1)
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+Adjust ldrd/strd splitting order when it's big-endian.
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+
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mpure-code
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Target Report Var(target_pure_code) Init(0)
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Do not allow constant data to be placed in code sections.
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