127 lines
4.4 KiB
Diff
127 lines
4.4 KiB
Diff
From 5ad28ef4010c1248b4d94396d03f863705f7b0db Mon Sep 17 00:00:00 2001
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From: liuhongt <hongtao.liu@intel.com>
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Date: Mon, 26 Jun 2023 21:07:09 +0800
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Subject: [PATCH 08/32] Refine maskstore patterns with UNSPEC_MASKMOV.
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Similar like r14-2070-gc79476da46728e
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If mem_addr points to a memory region with less than whole vector size
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bytes of accessible memory and k is a mask that would prevent reading
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the inaccessible bytes from mem_addr, add UNSPEC_MASKMOV to prevent
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it to be transformed to any other whole memory access instructions.
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gcc/ChangeLog:
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PR rtl-optimization/110237
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* config/i386/sse.md (<avx512>_store<mode>_mask): Refine with
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UNSPEC_MASKMOV.
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(maskstore<mode><avx512fmaskmodelower): Ditto.
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(*<avx512>_store<mode>_mask): New define_insn, it's renamed
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from original <avx512>_store<mode>_mask.
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---
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gcc/config/i386/sse.md | 69 ++++++++++++++++++++++++++++++++++--------
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1 file changed, 57 insertions(+), 12 deletions(-)
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diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
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index b30e96cb1..3af159896 100644
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--- a/gcc/config/i386/sse.md
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+++ b/gcc/config/i386/sse.md
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@@ -1554,7 +1554,7 @@
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(set_attr "prefix" "evex")
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(set_attr "mode" "<sseinsnmode>")])
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-(define_insn "<avx512>_store<mode>_mask"
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+(define_insn "*<avx512>_store<mode>_mask"
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[(set (match_operand:V48_AVX512VL 0 "memory_operand" "=m")
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(vec_merge:V48_AVX512VL
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(match_operand:V48_AVX512VL 1 "register_operand" "v")
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@@ -1582,7 +1582,7 @@
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(set_attr "memory" "store")
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(set_attr "mode" "<sseinsnmode>")])
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-(define_insn "<avx512>_store<mode>_mask"
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+(define_insn "*<avx512>_store<mode>_mask"
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[(set (match_operand:VI12HF_AVX512VL 0 "memory_operand" "=m")
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(vec_merge:VI12HF_AVX512VL
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(match_operand:VI12HF_AVX512VL 1 "register_operand" "v")
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@@ -26002,21 +26002,66 @@
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"TARGET_AVX")
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(define_expand "maskstore<mode><avx512fmaskmodelower>"
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- [(set (match_operand:V48H_AVX512VL 0 "memory_operand")
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- (vec_merge:V48H_AVX512VL
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- (match_operand:V48H_AVX512VL 1 "register_operand")
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- (match_dup 0)
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- (match_operand:<avx512fmaskmode> 2 "register_operand")))]
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+ [(set (match_operand:V48_AVX512VL 0 "memory_operand")
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+ (unspec:V48_AVX512VL
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+ [(match_operand:V48_AVX512VL 1 "register_operand")
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+ (match_dup 0)
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+ (match_operand:<avx512fmaskmode> 2 "register_operand")]
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+ UNSPEC_MASKMOV))]
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"TARGET_AVX512F")
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(define_expand "maskstore<mode><avx512fmaskmodelower>"
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- [(set (match_operand:VI12_AVX512VL 0 "memory_operand")
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- (vec_merge:VI12_AVX512VL
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- (match_operand:VI12_AVX512VL 1 "register_operand")
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- (match_dup 0)
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- (match_operand:<avx512fmaskmode> 2 "register_operand")))]
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+ [(set (match_operand:VI12HF_AVX512VL 0 "memory_operand")
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+ (unspec:VI12HF_AVX512VL
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+ [(match_operand:VI12HF_AVX512VL 1 "register_operand")
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+ (match_dup 0)
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+ (match_operand:<avx512fmaskmode> 2 "register_operand")]
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+ UNSPEC_MASKMOV))]
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"TARGET_AVX512BW")
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+(define_insn "<avx512>_store<mode>_mask"
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+ [(set (match_operand:V48_AVX512VL 0 "memory_operand" "=m")
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+ (unspec:V48_AVX512VL
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+ [(match_operand:V48_AVX512VL 1 "register_operand" "v")
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+ (match_dup 0)
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+ (match_operand:<avx512fmaskmode> 2 "register_operand" "Yk")]
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+ UNSPEC_MASKMOV))]
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+ "TARGET_AVX512F"
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+{
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+ if (FLOAT_MODE_P (GET_MODE_INNER (<MODE>mode)))
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+ {
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+ if (misaligned_operand (operands[0], <MODE>mode))
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+ return "vmovu<ssemodesuffix>\t{%1, %0%{%2%}|%0%{%2%}, %1}";
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+ else
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+ return "vmova<ssemodesuffix>\t{%1, %0%{%2%}|%0%{%2%}, %1}";
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+ }
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+ else
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+ {
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+ if (misaligned_operand (operands[0], <MODE>mode))
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+ return "vmovdqu<ssescalarsize>\t{%1, %0%{%2%}|%0%{%2%}, %1}";
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+ else
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+ return "vmovdqa<ssescalarsize>\t{%1, %0%{%2%}|%0%{%2%}, %1}";
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+ }
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+}
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+ [(set_attr "type" "ssemov")
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+ (set_attr "prefix" "evex")
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+ (set_attr "memory" "store")
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+ (set_attr "mode" "<sseinsnmode>")])
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+
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+(define_insn "<avx512>_store<mode>_mask"
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+ [(set (match_operand:VI12HF_AVX512VL 0 "memory_operand" "=m")
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+ (unspec:VI12HF_AVX512VL
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+ [(match_operand:VI12HF_AVX512VL 1 "register_operand" "v")
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+ (match_dup 0)
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+ (match_operand:<avx512fmaskmode> 2 "register_operand" "Yk")]
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+ UNSPEC_MASKMOV))]
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+ "TARGET_AVX512BW"
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+ "vmovdqu<ssescalarsize>\t{%1, %0%{%2%}|%0%{%2%}, %1}"
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+ [(set_attr "type" "ssemov")
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+ (set_attr "prefix" "evex")
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+ (set_attr "memory" "store")
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+ (set_attr "mode" "<sseinsnmode>")])
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+
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(define_expand "cbranch<mode>4"
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[(set (reg:CC FLAGS_REG)
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(compare:CC (match_operand:VI48_AVX 1 "register_operand")
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--
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2.28.0.windows.1
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