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gcc/LoongArch-Add-LA664-support.patch
ticat_fp eaea42573e LoongArch: add 3a6000 support 
Signed-off-by: ticat_fp <fanpeng@loongson.cn>
2024-04-23 09:07:30 +08:00

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From c68463abbab98aa7f5a9b91e71ed6f6834c723df Mon Sep 17 00:00:00 2001
From: Lulu Cheng <chenglulu@loongson.cn>
Date: Thu, 16 Nov 2023 20:43:53 +0800
Subject: [PATCH] LoongArch: Add LA664 support.
Define ISA_BASE_LA64V110, which represents the base instruction set defined in LoongArch1.1.
Support the configure setting --with-arch =la664, and support -march=la664,-mtune=la664.
gcc/ChangeLog:
* config.gcc: Support LA664.
* config/loongarch/genopts/loongarch-strings: Likewise.
* config/loongarch/genopts/loongarch.opt.in: Likewise.
* config/loongarch/loongarch-cpu.cc (fill_native_cpu_config): Likewise.
* config/loongarch/loongarch-def.c: Likewise.
* config/loongarch/loongarch-def.h (N_ISA_BASE_TYPES): Likewise.
(ISA_BASE_LA64V110): Define macro.
(N_ARCH_TYPES): Update value.
(N_TUNE_TYPES): Update value.
(CPU_LA664): New macro.
* config/loongarch/loongarch-opts.cc (isa_default_abi): Likewise.
(isa_base_compat_p): Likewise.
* config/loongarch/loongarch-opts.h (TARGET_64BIT): This parameter is enabled
when la_target.isa.base is equal to ISA_BASE_LA64V100 or ISA_BASE_LA64V110.
(TARGET_uARCH_LA664): Define macro.
* config/loongarch/loongarch-str.h (STR_CPU_LA664): Likewise.
* config/loongarch/loongarch.cc (loongarch_cpu_sched_reassociation_width):
Add LA664 support.
* config/loongarch/loongarch.opt: Regenerate.
Signed-off-by: ticat_fp <fanpeng@loongson.cn>
---
gcc/config.gcc | 10 ++++-----
.../loongarch/genopts/loongarch-strings | 1 +
gcc/config/loongarch/genopts/loongarch.opt.in | 3 +++
gcc/config/loongarch/loongarch-cpu.cc | 4 ++++
gcc/config/loongarch/loongarch-def.c | 21 +++++++++++++++++++
gcc/config/loongarch/loongarch-def.h | 8 ++++---
gcc/config/loongarch/loongarch-opts.cc | 8 +++----
gcc/config/loongarch/loongarch-opts.h | 4 +++-
gcc/config/loongarch/loongarch-str.h | 1 +
gcc/config/loongarch/loongarch.cc | 1 +
gcc/config/loongarch/loongarch.opt | 3 +++
11 files changed, 51 insertions(+), 13 deletions(-)
diff --git a/gcc/config.gcc b/gcc/config.gcc
index 6d51bd93f3f..b88591b6fd8 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -5039,7 +5039,7 @@ case "${target}" in
# Perform initial sanity checks on --with-* options.
case ${with_arch} in
- "" | abi-default | loongarch64 | la464) ;; # OK, append here.
+ "" | abi-default | loongarch64 | la[46]64) ;; # OK, append here.
native)
if test x${host} != x${target}; then
echo "--with-arch=native is illegal for cross-compiler." 1>&2
@@ -5088,7 +5088,7 @@ case "${target}" in
case ${abi_base}/${abi_ext} in
lp64*/base)
# architectures that support lp64* ABI
- arch_pattern="native|abi-default|loongarch64|la464"
+ arch_pattern="native|abi-default|loongarch64|la[46]64"
# default architecture for lp64* ABI
arch_default="abi-default"
;;
@@ -5163,7 +5163,7 @@ case "${target}" in
# Check default with_tune configuration using with_arch.
case ${with_arch} in
loongarch64)
- tune_pattern="native|abi-default|loongarch64|la464"
+ tune_pattern="native|abi-default|loongarch64|la[46]64"
;;
*)
# By default, $with_tune == $with_arch
@@ -5219,7 +5219,7 @@ case "${target}" in
# Fixed: use the default gcc configuration for all multilib
# builds by default.
with_multilib_default="" ;;
- arch,native|arch,loongarch64|arch,la464) # OK, append here.
+ arch,native|arch,loongarch64|arch,la[46]64) # OK, append here.
with_multilib_default="/march=${component}" ;;
arch,*)
with_multilib_default="/march=abi-default"
@@ -5307,7 +5307,7 @@ case "${target}" in
if test x${parse_state} = x"arch"; then
# -march option
case ${component} in
- native | abi-default | loongarch64 | la464) # OK, append here.
+ native | abi-default | loongarch64 | la[46]64) # OK, append here.
# Append -march spec for each multilib variant.
loongarch_multilib_list_make="${loongarch_multilib_list_make}/march=${component}"
parse_state="opts"
diff --git a/gcc/config/loongarch/genopts/loongarch-strings b/gcc/config/loongarch/genopts/loongarch-strings
index 8e412f7536e..7bc4824007e 100644
--- a/gcc/config/loongarch/genopts/loongarch-strings
+++ b/gcc/config/loongarch/genopts/loongarch-strings
@@ -26,6 +26,7 @@ STR_CPU_NATIVE native
STR_CPU_ABI_DEFAULT abi-default
STR_CPU_LOONGARCH64 loongarch64
STR_CPU_LA464 la464
+STR_CPU_LA664 la664
# Base architecture
STR_ISA_BASE_LA64V100 la64
diff --git a/gcc/config/loongarch/genopts/loongarch.opt.in b/gcc/config/loongarch/genopts/loongarch.opt.in
index 158701d327a..00b4733d75b 100644
--- a/gcc/config/loongarch/genopts/loongarch.opt.in
+++ b/gcc/config/loongarch/genopts/loongarch.opt.in
@@ -107,6 +107,9 @@ Enum(cpu_type) String(@@STR_CPU_LOONGARCH64@@) Value(CPU_LOONGARCH64)
EnumValue
Enum(cpu_type) String(@@STR_CPU_LA464@@) Value(CPU_LA464)
+EnumValue
+Enum(cpu_type) String(@@STR_CPU_LA664@@) Value(CPU_LA664)
+
m@@OPTSTR_ARCH@@=
Target RejectNegative Joined Enum(cpu_type) Var(la_opt_cpu_arch) Init(M_OPT_UNSET)
-m@@OPTSTR_ARCH@@=PROCESSOR Generate code for the given PROCESSOR ISA.
diff --git a/gcc/config/loongarch/loongarch-cpu.cc b/gcc/config/loongarch/loongarch-cpu.cc
index 7a2866f60f9..f3a13414143 100644
--- a/gcc/config/loongarch/loongarch-cpu.cc
+++ b/gcc/config/loongarch/loongarch-cpu.cc
@@ -106,6 +106,10 @@ fill_native_cpu_config (struct loongarch_target *tgt)
native_cpu_type = CPU_LA464;
break;
+ case 0x0014d000: /* LA664 */
+ native_cpu_type = CPU_LA664;
+ break;
+
default:
/* Unknown PRID. */
if (tune_native_p)
diff --git a/gcc/config/loongarch/loongarch-def.c b/gcc/config/loongarch/loongarch-def.c
index 430ef8b2d95..067629141b6 100644
--- a/gcc/config/loongarch/loongarch-def.c
+++ b/gcc/config/loongarch/loongarch-def.c
@@ -28,6 +28,7 @@ loongarch_cpu_strings[N_TUNE_TYPES] = {
[CPU_ABI_DEFAULT] = STR_CPU_ABI_DEFAULT,
[CPU_LOONGARCH64] = STR_CPU_LOONGARCH64,
[CPU_LA464] = STR_CPU_LA464,
+ [CPU_LA664] = STR_CPU_LA664,
};
struct loongarch_isa
@@ -42,6 +43,11 @@ loongarch_cpu_default_isa[N_ARCH_TYPES] = {
.fpu = ISA_EXT_FPU64,
.simd = ISA_EXT_SIMD_LASX,
},
+ [CPU_LA664] = {
+ .base = ISA_BASE_LA64V110,
+ .fpu = ISA_EXT_FPU64,
+ .simd = ISA_EXT_SIMD_LASX,
+ },
};
struct loongarch_cache
@@ -58,6 +64,12 @@ loongarch_cpu_cache[N_TUNE_TYPES] = {
.l2d_size = 256,
.simultaneous_prefetches = 4,
},
+ [CPU_LA664] = {
+ .l1d_line_size = 64,
+ .l1d_size = 64,
+ .l2d_size = 256,
+ .simultaneous_prefetches = 4,
+ },
};
struct loongarch_align
@@ -70,6 +82,10 @@ loongarch_cpu_align[N_TUNE_TYPES] = {
.function = "32",
.label = "16",
},
+ [CPU_LA664] = {
+ .function = "32",
+ .label = "16",
+ },
};
@@ -104,6 +120,9 @@ loongarch_cpu_rtx_cost_data[N_TUNE_TYPES] = {
[CPU_LA464] = {
DEFAULT_COSTS
},
+ [CPU_LA664] = {
+ DEFAULT_COSTS
+ },
};
/* RTX costs to use when optimizing for size. */
@@ -127,6 +146,7 @@ loongarch_cpu_issue_rate[N_TUNE_TYPES] = {
[CPU_NATIVE] = 4,
[CPU_LOONGARCH64] = 4,
[CPU_LA464] = 4,
+ [CPU_LA664] = 6,
};
int
@@ -134,6 +154,7 @@ loongarch_cpu_multipass_dfa_lookahead[N_TUNE_TYPES] = {
[CPU_NATIVE] = 4,
[CPU_LOONGARCH64] = 4,
[CPU_LA464] = 4,
+ [CPU_LA664] = 6,
};
/* Wiring string definitions from loongarch-str.h to global arrays
diff --git a/gcc/config/loongarch/loongarch-def.h b/gcc/config/loongarch/loongarch-def.h
index 6e2a6987910..db497f3ffe2 100644
--- a/gcc/config/loongarch/loongarch-def.h
+++ b/gcc/config/loongarch/loongarch-def.h
@@ -55,7 +55,8 @@ extern "C" {
/* enum isa_base */
extern const char* loongarch_isa_base_strings[];
#define ISA_BASE_LA64V100 0
-#define N_ISA_BASE_TYPES 1
+#define ISA_BASE_LA64V110 1
+#define N_ISA_BASE_TYPES 2
/* enum isa_ext_* */
extern const char* loongarch_isa_ext_strings[];
@@ -141,8 +142,9 @@ struct loongarch_target
#define CPU_ABI_DEFAULT 1
#define CPU_LOONGARCH64 2
#define CPU_LA464 3
-#define N_ARCH_TYPES 4
-#define N_TUNE_TYPES 4
+#define CPU_LA664 4
+#define N_ARCH_TYPES 5
+#define N_TUNE_TYPES 5
/* parallel tables. */
extern const char* loongarch_cpu_strings[];
diff --git a/gcc/config/loongarch/loongarch-opts.cc b/gcc/config/loongarch/loongarch-opts.cc
index e5921189a06..67a59152a01 100644
--- a/gcc/config/loongarch/loongarch-opts.cc
+++ b/gcc/config/loongarch/loongarch-opts.cc
@@ -552,17 +552,17 @@ isa_default_abi (const struct loongarch_isa *isa)
switch (isa->fpu)
{
case ISA_EXT_FPU64:
- if (isa->base == ISA_BASE_LA64V100)
+ if (isa->base >= ISA_BASE_LA64V100)
abi.base = ABI_BASE_LP64D;
break;
case ISA_EXT_FPU32:
- if (isa->base == ISA_BASE_LA64V100)
+ if (isa->base >= ISA_BASE_LA64V100)
abi.base = ABI_BASE_LP64F;
break;
case ISA_EXT_NONE:
- if (isa->base == ISA_BASE_LA64V100)
+ if (isa->base >= ISA_BASE_LA64V100)
abi.base = ABI_BASE_LP64S;
break;
@@ -582,7 +582,7 @@ isa_base_compat_p (const struct loongarch_isa *set1,
switch (set2->base)
{
case ISA_BASE_LA64V100:
- return (set1->base == ISA_BASE_LA64V100);
+ return (set1->base >= ISA_BASE_LA64V100);
default:
gcc_unreachable ();
diff --git a/gcc/config/loongarch/loongarch-opts.h b/gcc/config/loongarch/loongarch-opts.h
index 6dd309aad96..0e1b3e528a1 100644
--- a/gcc/config/loongarch/loongarch-opts.h
+++ b/gcc/config/loongarch/loongarch-opts.h
@@ -76,7 +76,8 @@ loongarch_update_gcc_opt_status (struct loongarch_target *target,
#define TARGET_DOUBLE_FLOAT (la_target.isa.fpu == ISA_EXT_FPU64)
#define TARGET_DOUBLE_FLOAT_ABI (la_target.abi.base == ABI_BASE_LP64D)
-#define TARGET_64BIT (la_target.isa.base == ISA_BASE_LA64V100)
+#define TARGET_64BIT (la_target.isa.base == ISA_BASE_LA64V100 \
+ || la_target.isa.base == ISA_BASE_LA64V110)
#define TARGET_ABI_LP64 (la_target.abi.base == ABI_BASE_LP64D \
|| la_target.abi.base == ABI_BASE_LP64F \
|| la_target.abi.base == ABI_BASE_LP64S)
@@ -88,6 +89,7 @@ loongarch_update_gcc_opt_status (struct loongarch_target *target,
/* TARGET_ macros for use in *.md template conditionals */
#define TARGET_uARCH_LA464 (la_target.cpu_tune == CPU_LA464)
+#define TARGET_uARCH_LA664 (la_target.cpu_tune == CPU_LA664)
/* Note: optimize_size may vary across functions,
while -m[no]-memcpy imposes a global constraint. */
diff --git a/gcc/config/loongarch/loongarch-str.h b/gcc/config/loongarch/loongarch-str.h
index 072558c28f1..fc4f41bfc1e 100644
--- a/gcc/config/loongarch/loongarch-str.h
+++ b/gcc/config/loongarch/loongarch-str.h
@@ -30,6 +30,7 @@ along with GCC; see the file COPYING3. If not see
#define STR_CPU_ABI_DEFAULT "abi-default"
#define STR_CPU_LOONGARCH64 "loongarch64"
#define STR_CPU_LA464 "la464"
+#define STR_CPU_LA664 "la664"
#define STR_ISA_BASE_LA64V100 "la64"
diff --git a/gcc/config/loongarch/loongarch.cc b/gcc/config/loongarch/loongarch.cc
index 22ca24a1878..4cd509f11c6 100644
--- a/gcc/config/loongarch/loongarch.cc
+++ b/gcc/config/loongarch/loongarch.cc
@@ -10177,6 +10177,7 @@ loongarch_cpu_sched_reassociation_width (struct loongarch_target *target,
{
case CPU_LOONGARCH64:
case CPU_LA464:
+ case CPU_LA664:
/* Vector part. */
if (LSX_SUPPORTED_MODE_P (mode) || LASX_SUPPORTED_MODE_P (mode))
{
diff --git a/gcc/config/loongarch/loongarch.opt b/gcc/config/loongarch/loongarch.opt
index a5988411fbb..7f129e53ba5 100644
--- a/gcc/config/loongarch/loongarch.opt
+++ b/gcc/config/loongarch/loongarch.opt
@@ -114,6 +114,9 @@ Enum(cpu_type) String(loongarch64) Value(CPU_LOONGARCH64)
EnumValue
Enum(cpu_type) String(la464) Value(CPU_LA464)
+EnumValue
+Enum(cpu_type) String(la664) Value(CPU_LA664)
+
march=
Target RejectNegative Joined Enum(cpu_type) Var(la_opt_cpu_arch) Init(M_OPT_UNSET)
-march=PROCESSOR Generate code for the given PROCESSOR ISA.
--
2.33.0
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