01e0ec8ea6
- avoid-cycling-on-vertain-subreg-reloads.patch: Add patch source comment - change-gcc-BASE-VER.patch: Likewise - dont-generate-IF_THEN_ELSE.patch: Likewise - fix-ICE-in-compute_live_loop_exits.patch: Likewise - fix-ICE-in-eliminate_stmt.patch: Likewise - fix-ICE-in-vect_create_epilog_for_reduction.patch: Likewise - fix-ICE-in-vect_stmt_to_vectorize.patch: Likewise - fix-ICE-in-verify_ssa.patch: Likewise - fix-ICE-when-vectorizing-nested-cycles.patch: Likewise - fix-cost-of-plus.patch: Likewise - ipa-const-prop-self-recursion-bugfix.patch: Likewise - simplify-removing-subregs.patch: Likewise - medium-code-mode.patch: Bugfix - fix-when-peeling-for-alignment.patch: Move to ... - fix-PR-92351-When-peeling-for-alignment.patch: ... this - AArch64-Fix-constraints-for-CPY-M.patch: New file - Apply-maximum-nunits-for-BB-SLP.patch: New file - Fix-EXTRACT_LAST_REDUCTION-segfault.patch: New file - Fix-up-push_partial_def-little-endian-bitfield.patch: New file - Fix-zero-masking-for-vcvtps2ph.patch: New file - IRA-Handle-fully-tied-destinations.patch: New file - SLP-VECT-Add-check-to-fix-96837.patch: New file - aarch64-Fix-ash-lr-lshr-mode-3-expanders.patch: New file - aarch64-Fix-bf16-and-matrix-g++-gfortran.patch: New file - aarch64-Fix-mismatched-SVE-predicate-modes.patch: New file - aarch64-fix-sve-acle-error.patch: New file - adjust-vector-cost-and-move-EXTRACT_LAST_REDUCTION-costing.patch: New file - bf16-and-matrix-characteristic.patch: New file - fix-ICE-IPA-compare-VRP-types.patch: New file - fix-ICE-in-affine-combination.patch: New file - fix-ICE-in-pass-vect.patch: New file - fix-ICE-in-vect_update_misalignment_for_peel.patch: New file - fix-addlosymdi-ICE-in-pass-reload.patch: New file - fix-an-ICE-in-vect_recog_mask_conversion_pattern.patch: New file - fix-avx512vl-vcvttpd2dq-2-fail.patch: New file - fix-issue499-add-nop-convert.patch: New file - fix-issue604-ldist-dependency-fixup.patch: New file - modulo-sched-Carefully-process-loop-counter-initiali.patch: New file - re-PR-target-91124-gcc.target-i386-avx512vl-vpshldvd.patch: New file - reduction-paths-with-unhandled-live-stmt.patch: New file - redundant-loop-elimination.patch: New file - sccvn-Improve-handling-of-load-masked-with-integer.patch: New file - speed-up-DDG-analysis-and-fix-bootstrap-compare-debug.patch: New file - store-merging-Consider-also-overlapping-stores-earlier.patch: New file - tree-optimization-96920-another-ICE-when-vectorizing.patch: New file - tree-optimization-97812-fix-range-query-in-VRP-asser.patch: New file - vectorizable-comparison-Swap-operands-only-once.patch: New file - x86-Fix-bf16-and-matrix.patch: New file
166 lines
4.2 KiB
Diff
166 lines
4.2 KiB
Diff
This backport contains 1 patch from gcc main stream tree.
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The commit id of these patchs list as following in the order of time.
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7a6588fe65432c0f1a8b5fdefba81700ebf88711
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0001-aarch64-Fix-ash-lr-lshr-mode-3-expanders-PR94488.patch
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diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
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index 24a11fb5040..9f0e2bd1e6f 100644
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--- a/gcc/config/aarch64/aarch64-simd.md
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+++ b/gcc/config/aarch64/aarch64-simd.md
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@@ -1105,31 +1105,17 @@
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tmp));
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DONE;
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}
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- else
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- {
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- operands[2] = force_reg (SImode, operands[2]);
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- }
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- }
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- else if (MEM_P (operands[2]))
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- {
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- operands[2] = force_reg (SImode, operands[2]);
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}
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- if (REG_P (operands[2]))
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- {
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- rtx tmp = gen_reg_rtx (<MODE>mode);
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- emit_insn (gen_aarch64_simd_dup<mode> (tmp,
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- convert_to_mode (<VEL>mode,
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- operands[2],
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- 0)));
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- emit_insn (gen_aarch64_simd_reg_sshl<mode> (operands[0], operands[1],
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- tmp));
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- DONE;
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- }
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- else
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- FAIL;
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-}
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-)
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+ operands[2] = force_reg (SImode, operands[2]);
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+
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+ rtx tmp = gen_reg_rtx (<MODE>mode);
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+ emit_insn (gen_aarch64_simd_dup<mode> (tmp, convert_to_mode (<VEL>mode,
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+ operands[2],
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+ 0)));
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+ emit_insn (gen_aarch64_simd_reg_sshl<mode> (operands[0], operands[1], tmp));
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+ DONE;
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+})
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(define_expand "lshr<mode>3"
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[(match_operand:VDQ_I 0 "register_operand")
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@@ -1152,31 +1138,19 @@
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tmp));
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DONE;
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}
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- else
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- operands[2] = force_reg (SImode, operands[2]);
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- }
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- else if (MEM_P (operands[2]))
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- {
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- operands[2] = force_reg (SImode, operands[2]);
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}
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- if (REG_P (operands[2]))
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- {
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- rtx tmp = gen_reg_rtx (SImode);
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- rtx tmp1 = gen_reg_rtx (<MODE>mode);
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- emit_insn (gen_negsi2 (tmp, operands[2]));
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- emit_insn (gen_aarch64_simd_dup<mode> (tmp1,
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- convert_to_mode (<VEL>mode,
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- tmp, 0)));
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- emit_insn (gen_aarch64_simd_reg_shl<mode>_unsigned (operands[0],
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- operands[1],
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- tmp1));
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- DONE;
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- }
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- else
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- FAIL;
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-}
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-)
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+ operands[2] = force_reg (SImode, operands[2]);
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+
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+ rtx tmp = gen_reg_rtx (SImode);
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+ rtx tmp1 = gen_reg_rtx (<MODE>mode);
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+ emit_insn (gen_negsi2 (tmp, operands[2]));
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+ emit_insn (gen_aarch64_simd_dup<mode> (tmp1,
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+ convert_to_mode (<VEL>mode, tmp, 0)));
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+ emit_insn (gen_aarch64_simd_reg_shl<mode>_unsigned (operands[0], operands[1],
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+ tmp1));
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+ DONE;
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+})
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(define_expand "ashr<mode>3"
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[(match_operand:VDQ_I 0 "register_operand")
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@@ -1199,31 +1173,19 @@
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tmp));
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DONE;
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}
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- else
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- operands[2] = force_reg (SImode, operands[2]);
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- }
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- else if (MEM_P (operands[2]))
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- {
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- operands[2] = force_reg (SImode, operands[2]);
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}
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- if (REG_P (operands[2]))
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- {
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- rtx tmp = gen_reg_rtx (SImode);
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- rtx tmp1 = gen_reg_rtx (<MODE>mode);
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- emit_insn (gen_negsi2 (tmp, operands[2]));
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- emit_insn (gen_aarch64_simd_dup<mode> (tmp1,
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- convert_to_mode (<VEL>mode,
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- tmp, 0)));
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- emit_insn (gen_aarch64_simd_reg_shl<mode>_signed (operands[0],
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- operands[1],
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- tmp1));
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- DONE;
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- }
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- else
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- FAIL;
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-}
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-)
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+ operands[2] = force_reg (SImode, operands[2]);
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+
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+ rtx tmp = gen_reg_rtx (SImode);
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+ rtx tmp1 = gen_reg_rtx (<MODE>mode);
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+ emit_insn (gen_negsi2 (tmp, operands[2]));
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+ emit_insn (gen_aarch64_simd_dup<mode> (tmp1, convert_to_mode (<VEL>mode,
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+ tmp, 0)));
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+ emit_insn (gen_aarch64_simd_reg_shl<mode>_signed (operands[0], operands[1],
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+ tmp1));
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+ DONE;
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+})
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(define_expand "vashl<mode>3"
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[(match_operand:VDQ_I 0 "register_operand")
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diff --git a/gcc/testsuite/gcc.c-torture/compile/pr94488.c b/gcc/testsuite/gcc.c-torture/compile/pr94488.c
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new file mode 100644
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index 00000000000..6e20a4168de
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--- /dev/null
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+++ b/gcc/testsuite/gcc.c-torture/compile/pr94488.c
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@@ -0,0 +1,22 @@
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+/* PR target/94488 */
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+
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+typedef unsigned long V __attribute__((__vector_size__(16)));
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+typedef long W __attribute__((__vector_size__(16)));
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+
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+void
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+foo (V *x, unsigned long y)
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+{
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+ *x = *x >> (unsigned int) y;
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+}
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+
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+void
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+bar (V *x, unsigned long y)
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+{
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+ *x = *x << (unsigned int) y;
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+}
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+
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+void
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+baz (W *x, unsigned long y)
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+{
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+ *x = *x >> (unsigned int) y;
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+}
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