diff -Nurp a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
--- a/gcc/config/aarch64/aarch64.c	2020-07-06 17:20:30.368000000 +0800
+++ b/gcc/config/aarch64/aarch64.c	2020-07-06 20:02:39.480000000 +0800
@@ -18860,8 +18860,12 @@ aarch64_simd_clone_compute_vecsize_and_s
   elt_bits = GET_MODE_BITSIZE (SCALAR_TYPE_MODE (base_type));
   if (clonei->simdlen == 0)
     {
-      count = 2;
-      vec_bits = (num == 0 ? 64 : 128);
+      /* Currently mathlib or sleef hasn't provide function for V2SF mode
+      simdclone of single precision functions. (e.g._ZCVnN2v_expf)
+      Therefore this mode is disabled by default to avoid link error.
+      Use -msimdmath-64 option to enable this mode.  */
+      count = flag_simdmath_64 ? 2 : 1;
+      vec_bits = ((num == 0 && flag_simdmath_64) ? 64 : 128);
       clonei->simdlen = vec_bits / elt_bits;
     }
   else
diff -Nurp a/gcc/config/aarch64/aarch64.opt b/gcc/config/aarch64/aarch64.opt
--- a/gcc/config/aarch64/aarch64.opt	2020-07-06 17:20:30.364000000 +0800
+++ b/gcc/config/aarch64/aarch64.opt	2020-07-06 20:02:39.480000000 +0800
@@ -186,6 +186,12 @@ precision of square root results to abou
 single precision and to 32 bits for double precision.
 If enabled, it implies -mlow-precision-recip-sqrt.
 
+msimdmath-64
+Target Var(flag_simdmath_64) Optimization
+Allow compiler to generate V2SF 64 bits simdclone of math functions,
+which is not currently supported in mathlib or sleef.
+Therefore this option is disabled by default.
+
 mlow-precision-div
 Target Var(flag_mlow_precision_div) Optimization
 Enable the division approximation.  Enabling this reduces