From 95d8a6545bef39f5deff376c60c38e4e3c13c8f5 Mon Sep 17 00:00:00 2001 From: zhaowenyu <804544223@qq.com> Date: Sat, 25 Jun 2022 00:45:24 +0800 Subject: [PATCH 10/12] [Backport] ira: Fix unnecessary register spill Reference: https://gcc.gnu.org/git/gitweb.cgi?p=gcc.git;h=edf95e51e53697f3050f076675c26a4cece17741 The variables first_moveable_pseudo and last_moveable_pseudo aren't reset after compiling a function, which means they leak into the first scheduler pass of the following function. In some cases, this can cause an extra spill during register location of the second function. --- gcc/ira.c | 2 ++ gcc/testsuite/gcc.target/aarch64/nospill.c | 35 ++++++++++++++++++++++ 2 files changed, 37 insertions(+) create mode 100644 gcc/testsuite/gcc.target/aarch64/nospill.c diff --git a/gcc/ira.c b/gcc/ira.c index 681ec2f46..77e4bb988 100644 --- a/gcc/ira.c +++ b/gcc/ira.c @@ -5130,6 +5130,8 @@ move_unallocated_pseudos (void) INSN_UID (newinsn), i); SET_REG_N_REFS (i, 0); } + + first_moveable_pseudo = last_moveable_pseudo = 0; } /* If the backend knows where to allocate pseudos for hard diff --git a/gcc/testsuite/gcc.target/aarch64/nospill.c b/gcc/testsuite/gcc.target/aarch64/nospill.c new file mode 100644 index 000000000..968a4267e --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/nospill.c @@ -0,0 +1,35 @@ +/* { dg-do compile } */ +/* { dg-options "-O3" } */ + +/* The pseudo for P is marked as moveable in the IRA pass. */ +float +func_0 (float a, float b, float c) +{ + float p = c / a; + + if (b > 1) + { + b /= p; + if (c > 2) + a /= 3; + } + + return b / c * a; +} + +/* If first_moveable_pseudo and last_moveable_pseudo are not reset correctly, + they will carry over and spill the pseudo for Q. */ +float +func_1 (float a, float b, float c) +{ + float q = a + b; + + c *= a / (b + b); + if (a > 0) + c *= q; + + return a * b * c; +} + +/* We have plenty of spare registers, so check nothing has been spilled. */ +/* { dg-final { scan-assembler-not "\tstr\t" } } */ -- 2.27.0.windows.1