This backport contains 1 patch from gcc main stream tree.
The commit id of these patchs list as following in the order of time.

0001-aarch64-Fix-mismatched-SVE-predicate-modes.patch
26bebf576ddcdcfb596f07e8c2896f17c48516e7

diff -urpN a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
--- a/gcc/config/aarch64/aarch64.c	2020-12-14 00:57:20.128000000 -0500
+++ b/gcc/config/aarch64/aarch64.c	2020-12-14 01:00:15.080000000 -0500
@@ -4328,6 +4328,7 @@ aarch64_expand_sve_const_pred_eor (rtx t
   /* EOR the result with an ELT_SIZE PTRUE.  */
   rtx mask = aarch64_ptrue_all (elt_size);
   mask = force_reg (VNx16BImode, mask);
+  inv = gen_lowpart (VNx16BImode, inv);
   target = aarch64_target_reg (target, VNx16BImode);
   emit_insn (gen_aarch64_pred_z (XOR, VNx16BImode, target, mask, inv, mask));
   return target;
diff -urpN a/gcc/testsuite/gcc.dg/vect/pr94606.c b/gcc/testsuite/gcc.dg/vect/pr94606.c
--- a/gcc/testsuite/gcc.dg/vect/pr94606.c	1969-12-31 19:00:00.000000000 -0500
+++ b/gcc/testsuite/gcc.dg/vect/pr94606.c	2020-12-14 01:00:15.080000000 -0500
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=armv8.2-a+sve -msve-vector-bits=256" { target aarch64*-*-* } } */
+
+const short mask[] = { 0, 0, 0, 0, 0, 0, 0, 0,
+		       0, 0, 0, 1, 1, 1, 1, 1 };
+
+int
+foo (short *restrict x, short *restrict y)
+{
+  for (int i = 0; i < 16; ++i)
+    if (mask[i])
+      x[i] += y[i];
+}