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[Revert] Remove 2 patches

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Remove 2 backport patches

(cherry picked from commit 55e6b3c41ff8ff81578079da330ae919f7a0b7fc)
This commit is contained in:
benniaobufeijiushiji 2022-08-16 21:29:45 +08:00 committed by openeuler-sync-bot
parent 0c24e155b2
commit b63e4c9f9a
3 changed files with 7 additions and 243 deletions
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165
0043-Backport-Extend-special_memory_constraint.patch
View File

@ -1,165 +0,0 @@
From b4770dd95fa342671d53c9de2077d77ee07b68dd Mon Sep 17 00:00:00 2001
From: zhaowenyu <804544223@qq.com>
Date: Sat, 25 Jun 2022 00:41:50 +0800
Subject: [PATCH 09/12] [Backport] Extend special_memory_constraint.
Reference: https://gcc.gnu.org/git/gitweb.cgi?p=gcc.git;h=4de7b010038933dd6ca96bf186ca49f243d0def6
For operand with special_memory_constraint, there could be a wrapper for memory_operand.
Extract mem for operand for conditional judgement like MEM_P, also for record_address_regs.
---
gcc/ira-costs.c | 12 +++++++-----
gcc/ira.c | 2 +-
gcc/lra-constraints.c | 28 +++++++++++++++++++++++-----
gcc/recog.c | 7 +++++--
gcc/rtl.h | 1 +
5 files changed, 37 insertions(+), 13 deletions(-)
diff --git a/gcc/ira-costs.c b/gcc/ira-costs.c
index 6891156b5..aeda6588b 100644
--- a/gcc/ira-costs.c
+++ b/gcc/ira-costs.c
@@ -781,7 +781,8 @@ record_reg_classes (int n_alts, int n_ops, rtx *ops,
case CT_SPECIAL_MEMORY:
insn_allows_mem[i] = allows_mem[i] = 1;
- if (MEM_P (op) && constraint_satisfied_p (op, cn))
+ if (MEM_P (extract_mem_from_operand (op))
+ && constraint_satisfied_p (op, cn))
win = 1;
break;
@@ -1397,15 +1398,16 @@ record_operand_costs (rtx_insn *insn, enum reg_class *pref)
commutative. */
for (i = 0; i < recog_data.n_operands; i++)
{
+ rtx op_mem = extract_mem_from_operand (recog_data.operand[i]);
memcpy (op_costs[i], init_cost, struct_costs_size);
if (GET_CODE (recog_data.operand[i]) == SUBREG)
recog_data.operand[i] = SUBREG_REG (recog_data.operand[i]);
- if (MEM_P (recog_data.operand[i]))
- record_address_regs (GET_MODE (recog_data.operand[i]),
- MEM_ADDR_SPACE (recog_data.operand[i]),
- XEXP (recog_data.operand[i], 0),
+ if (MEM_P (op_mem))
+ record_address_regs (GET_MODE (op_mem),
+ MEM_ADDR_SPACE (op_mem),
+ XEXP (op_mem, 0),
0, MEM, SCRATCH, frequency * 2);
else if (constraints[i][0] == 'p'
|| (insn_extra_address_constraint
diff --git a/gcc/ira.c b/gcc/ira.c
index 681ec2f46..c13650229 100644
--- a/gcc/ira.c
+++ b/gcc/ira.c
@@ -1868,7 +1868,7 @@ ira_setup_alts (rtx_insn *insn)
case CT_MEMORY:
case CT_SPECIAL_MEMORY:
- if (MEM_P (op))
+ if (MEM_P (extract_mem_from_operand (op)))
goto op_success;
win_p = true;
break;
diff --git a/gcc/lra-constraints.c b/gcc/lra-constraints.c
index 7cc479b30..df75c7b94 100644
--- a/gcc/lra-constraints.c
+++ b/gcc/lra-constraints.c
@@ -409,14 +409,34 @@ valid_address_p (rtx op, struct address_info *ad,
return valid_address_p (ad->mode, *ad->outer, ad->as);
}
+/* For special_memory_operand, it could be false for MEM_P (op),
+ i.e. bcst_mem_operand in i386 backend.
+ Extract and return real memory operand or op. */
+rtx
+extract_mem_from_operand (rtx op)
+{
+ for (rtx x = op;; x = XEXP (x, 0))
+ {
+ if (MEM_P (x))
+ return x;
+ if (GET_RTX_LENGTH (GET_CODE (x)) != 1
+ || GET_RTX_FORMAT (GET_CODE (x))[0] != 'e')
+ break;
+ }
+ return op;
+}
+
/* Return true if the eliminated form of memory reference OP satisfies
extra (special) memory constraint CONSTRAINT. */
static bool
satisfies_memory_constraint_p (rtx op, enum constraint_num constraint)
{
struct address_info ad;
+ rtx mem = extract_mem_from_operand (op);
+ if (!MEM_P (mem))
+ return false;
- decompose_mem_address (&ad, op);
+ decompose_mem_address (&ad, mem);
address_eliminator eliminator (&ad);
return constraint_satisfied_p (op, constraint);
}
@@ -2344,8 +2364,7 @@ process_alt_operands (int only_alternative)
break;
case CT_MEMORY:
- if (MEM_P (op)
- && satisfies_memory_constraint_p (op, cn))
+ if (satisfies_memory_constraint_p (op, cn))
win = true;
else if (spilled_pseudo_p (op))
win = true;
@@ -2386,8 +2405,7 @@ process_alt_operands (int only_alternative)
break;
case CT_SPECIAL_MEMORY:
- if (MEM_P (op)
- && satisfies_memory_constraint_p (op, cn))
+ if (satisfies_memory_constraint_p (op, cn))
win = true;
else if (spilled_pseudo_p (op))
win = true;
diff --git a/gcc/recog.c b/gcc/recog.c
index 2720aaaac..8674054b9 100644
--- a/gcc/recog.c
+++ b/gcc/recog.c
@@ -1798,7 +1798,8 @@ asm_operand_ok (rtx op, const char *constraint, const char **constraints)
case CT_MEMORY:
case CT_SPECIAL_MEMORY:
/* Every memory operand can be reloaded to fit. */
- result = result || memory_operand (op, VOIDmode);
+ result = result || memory_operand (extract_mem_from_operand (op),
+ VOIDmode);
break;
case CT_ADDRESS:
@@ -2584,7 +2585,9 @@ constrain_operands (int strict, alternative_mask alternatives)
/* A unary operator may be accepted by the predicate, but it
is irrelevant for matching constraints. */
- if (UNARY_P (op))
+ /* For special_memory_operand, there could be a memory operand inside,
+ and it would cause a mismatch for constraint_satisfied_p. */
+ if (UNARY_P (op) && op == extract_mem_from_operand (op))
op = XEXP (op, 0);
if (GET_CODE (op) == SUBREG)
diff --git a/gcc/rtl.h b/gcc/rtl.h
index b29afca8d..35fb6ba73 100644
--- a/gcc/rtl.h
+++ b/gcc/rtl.h
@@ -4323,6 +4323,7 @@ extern rtx gen_hard_reg_clobber (machine_mode, unsigned int);
extern rtx get_reg_known_value (unsigned int);
extern bool get_reg_known_equiv_p (unsigned int);
extern rtx get_reg_base_value (unsigned int);
+extern rtx extract_mem_from_operand (rtx);
#ifdef STACK_REGS
extern int stack_regs_mentioned (const_rtx insn);
--
2.27.0.windows.1

73
0044-Backport-ira-Fix-unnecessary-register-spill.patch
View File

@ -1,73 +0,0 @@
From 95d8a6545bef39f5deff376c60c38e4e3c13c8f5 Mon Sep 17 00:00:00 2001
From: zhaowenyu <804544223@qq.com>
Date: Sat, 25 Jun 2022 00:45:24 +0800
Subject: [PATCH 10/12] [Backport] ira: Fix unnecessary register spill
Reference: https://gcc.gnu.org/git/gitweb.cgi?p=gcc.git;h=edf95e51e53697f3050f076675c26a4cece17741
The variables first_moveable_pseudo and last_moveable_pseudo aren't reset after compiling a function,
which means they leak into the first scheduler pass of the following function. In some cases, this
can cause an extra spill during register location of the second function.
---
gcc/ira.c | 2 ++
gcc/testsuite/gcc.target/aarch64/nospill.c | 35 ++++++++++++++++++++++
2 files changed, 37 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/aarch64/nospill.c
diff --git a/gcc/ira.c b/gcc/ira.c
index 681ec2f46..77e4bb988 100644
--- a/gcc/ira.c
+++ b/gcc/ira.c
@@ -5130,6 +5130,8 @@ move_unallocated_pseudos (void)
INSN_UID (newinsn), i);
SET_REG_N_REFS (i, 0);
}
+
+ first_moveable_pseudo = last_moveable_pseudo = 0;
}
/* If the backend knows where to allocate pseudos for hard
diff --git a/gcc/testsuite/gcc.target/aarch64/nospill.c b/gcc/testsuite/gcc.target/aarch64/nospill.c
new file mode 100644
index 000000000..968a4267e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/nospill.c
@@ -0,0 +1,35 @@
+/* { dg-do compile } */
+/* { dg-options "-O3" } */
+
+/* The pseudo for P is marked as moveable in the IRA pass. */
+float
+func_0 (float a, float b, float c)
+{
+ float p = c / a;
+
+ if (b > 1)
+ {
+ b /= p;
+ if (c > 2)
+ a /= 3;
+ }
+
+ return b / c * a;
+}
+
+/* If first_moveable_pseudo and last_moveable_pseudo are not reset correctly,
+ they will carry over and spill the pseudo for Q. */
+float
+func_1 (float a, float b, float c)
+{
+ float q = a + b;
+
+ c *= a / (b + b);
+ if (a > 0)
+ c *= q;
+
+ return a * b * c;
+}
+
+/* We have plenty of spare registers, so check nothing has been spilled. */
+/* { dg-final { scan-assembler-not "\tstr\t" } } */
--
2.27.0.windows.1

12
gcc.spec
View File

@ -61,7 +61,7 @@
Summary: Various compilers (C, C++, Objective-C, ...) Summary: Various compilers (C, C++, Objective-C, ...)
Name: gcc Name: gcc
Version: %{gcc_version} Version: %{gcc_version}
Release: 13 Release: 14
License: GPLv3+ and GPLv3+ with exceptions and GPLv2+ with exceptions and LGPLv2+ and BSD License: GPLv3+ and GPLv3+ with exceptions and GPLv2+ with exceptions and LGPLv2+ and BSD
URL: https://gcc.gnu.org URL: https://gcc.gnu.org
@ -158,8 +158,6 @@ Patch39: 0039-Backport-ipa-sra-Fix-thinko-when-overriding-safe_to_.patch
Patch40: 0040-Backport-ifcvt-Allow-constants-for-noce_convert_mult.patch Patch40: 0040-Backport-ifcvt-Allow-constants-for-noce_convert_mult.patch
Patch41: 0041-Backport-Register-sysroot-in-the-driver-switches-tab.patch Patch41: 0041-Backport-Register-sysroot-in-the-driver-switches-tab.patch
Patch42: 0042-DFE-Fix-bugs.patch Patch42: 0042-DFE-Fix-bugs.patch
Patch43: 0043-Backport-Extend-special_memory_constraint.patch
Patch44: 0044-Backport-ira-Fix-unnecessary-register-spill.patch
Patch45: 0045-Transposed-SLP-Enable-Transposed-SLP.patch Patch45: 0045-Transposed-SLP-Enable-Transposed-SLP.patch
Patch46: 0046-ArrayWidenCompare-Add-a-new-optimization-for-array-c.patch Patch46: 0046-ArrayWidenCompare-Add-a-new-optimization-for-array-c.patch
@ -660,8 +658,6 @@ not stable, so plugins must be rebuilt any time GCC is updated.
%patch40 -p1 %patch40 -p1
%patch41 -p1 %patch41 -p1
%patch42 -p1 %patch42 -p1
%patch43 -p1
%patch44 -p1
%patch45 -p1 %patch45 -p1
%patch46 -p1 %patch46 -p1
@ -2684,6 +2680,12 @@ end
%doc rpm.doc/changelogs/libcc1/ChangeLog* %doc rpm.doc/changelogs/libcc1/ChangeLog*
%changelog %changelog
* Mon Aug 16 2022 benniaobufeijiushiji <linda7@huawei.com> - 10.3.1-14
- Type:Revert
- ID:NA
- SUG:NA
- DESC:Remove 2 unnecessary patches
* Mon Aug 8 2022 benniaobufeijiushiji <linda7@huawei.com> - 10.3.1-13 * Mon Aug 8 2022 benniaobufeijiushiji <linda7@huawei.com> - 10.3.1-13
- Type:Sync - Type:Sync
- ID:NA - ID:NA