!330 [sync] PR-327: [Sync] Sync patch from openeuler/gcc
From: @openeuler-sync-bot Reviewed-by: @huang-xiaoquan Signed-off-by: @huang-xiaoquan
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0025-AArch64-Rewrite-the-tsv110-option.patch
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114
0025-AArch64-Rewrite-the-tsv110-option.patch
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@ -0,0 +1,114 @@
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From 2f0d0b1298fb9c3266bb102796b027a5570ad833 Mon Sep 17 00:00:00 2001
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From: dingguangya <dingguangya1@huawei.com>
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Date: Mon, 4 Sep 2023 16:27:38 +0800
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Subject: [PATCH 1/2] [AArch64] Rewrite the tsv110 option
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Reset the more appropriate options for tsv110.
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---
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gcc/common/config/aarch64/aarch64-common.cc | 76 +++++++++++++++++++++
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1 file changed, 76 insertions(+)
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diff --git a/gcc/common/config/aarch64/aarch64-common.cc b/gcc/common/config/aarch64/aarch64-common.cc
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index dfda5b837..85ce8133b 100644
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--- a/gcc/common/config/aarch64/aarch64-common.cc
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+++ b/gcc/common/config/aarch64/aarch64-common.cc
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@@ -44,6 +44,8 @@
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#undef TARGET_OPTION_INIT_STRUCT
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#define TARGET_OPTION_INIT_STRUCT aarch64_option_init_struct
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+#define INVALID_IMP ((unsigned) -1)
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+
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/* Set default optimization options. */
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static const struct default_options aarch_option_optimization_table[] =
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{
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@@ -65,6 +67,77 @@ static const struct default_options aarch_option_optimization_table[] =
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{ OPT_LEVELS_NONE, 0, NULL, 0 }
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};
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+/* CPU vendor id. */
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+static unsigned vendor_id = INVALID_IMP;
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+
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+/* The part number of the CPU. */
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+static unsigned part_id = INVALID_IMP;
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+
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+/* Return the hex integer that is after ':' for the FIELD.
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+ Return -1 if there was problem parsing the integer. */
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+static unsigned
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+parse_cpuinfo (char *field)
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+{
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+ if (field == NULL)
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+ return INVALID_IMP;
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+ const char *rest = strchr (field, ':');
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+
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+ if (rest == NULL)
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+ return INVALID_IMP;
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+
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+ char *after;
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+ unsigned fint = strtol (rest + 1, &after, 16);
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+ if (after == rest + 1)
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+ return INVALID_IMP;
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+ return fint;
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+}
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+
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+/* Read CPU vendor_id and part_id. */
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+
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+static void
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+read_cpuinfo ()
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+{
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+ FILE *fp = fopen ("/proc/cpuinfo", "r");
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+ if (fp == NULL)
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+ return;
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+
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+ /* Read 1024-byte data from /proc/cpuinfo. */
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+ char cpuinfo[1024];
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+ fread(cpuinfo, sizeof(char), sizeof(cpuinfo) - 1, fp);
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+
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+ char *vendor = strstr(cpuinfo, "CPU implementer");
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+ vendor_id = parse_cpuinfo(vendor);
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+
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+ char *part = strstr(cpuinfo, "CPU part");
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+ part_id = parse_cpuinfo(part);
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+
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+ fclose(fp);
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+}
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+
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+/* Reset the tsv110 option. After checking the platform information,
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+ this function can reset the more appropriate options.
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+ TODO: Currently, this function is not applicable to the cross
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+ compilation scenario. */
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+
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+static void
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+reset_tsv110_option ()
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+{
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+ /* Read CPU Information. */
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+ if (vendor_id == INVALID_IMP)
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+ read_cpuinfo ();
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+
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+ if (vendor_id == 0x48 && part_id == 0xd01)
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+ {
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+ /* Outline-atomics is enabled by default and
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+ aarch64_flag_outline_atomics defaults to 2. Therefore, the current
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+ modification affects only the default scenario. When the option
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+ moutline-atomics is added, the value of aarch64_flag_outline_atomics is 1,
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+ that is, aarch64_flag_outline_atomics is not reset to 0. */
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+ if (aarch64_flag_outline_atomics == 2)
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+ aarch64_flag_outline_atomics = 0;
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+ }
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+}
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+
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/* Implement TARGET_HANDLE_OPTION.
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This function handles the target specific options for CPU/target selection.
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@@ -83,6 +156,9 @@ aarch64_handle_option (struct gcc_options *opts,
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const char *arg = decoded->arg;
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int val = decoded->value;
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+ /* Reset the tsv110 options. */
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+ reset_tsv110_option ();
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+
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switch (code)
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{
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case OPT_march_:
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--
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2.33.0
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@ -0,0 +1,37 @@
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From 7efae59159577657f22511aa3b2cebe85ca60d9d Mon Sep 17 00:00:00 2001
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From: dingguangya <dingguangya1@huawei.com>
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Date: Mon, 4 Sep 2023 16:30:58 +0800
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Subject: [PATCH 2/2] [GOMP] Enabling moutline-atomics improves libgomp
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performance in multi-thread scenarios
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Libgomp is used in multi-thread scenarios,
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Enabling moutline-atomics improves performance.
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---
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libgomp/configure.tgt | 11 +++++++++++
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1 file changed, 11 insertions(+)
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diff --git a/libgomp/configure.tgt b/libgomp/configure.tgt
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index 2cd7272fc..f924e9f98 100644
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--- a/libgomp/configure.tgt
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+++ b/libgomp/configure.tgt
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@@ -32,6 +32,17 @@ if test $gcc_cv_have_tls = yes ; then
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esac
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fi
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+# Enabling moutline-atomics improves libgomp performance in multi-thread scenarios.
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+case "${target_cpu}" in
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+ aarch64*)
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+ case "${target}" in
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+ aarch64*-*-linux*)
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+ XCFLAGS="${XCFLAGS} -moutline-atomics"
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+ ;;
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+ esac
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+ ;;
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+esac
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+
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tmake_file=
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# Since we require POSIX threads, assume a POSIX system by default.
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config_path="posix"
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--
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2.33.0
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10
gcc.spec
10
gcc.spec
@ -2,7 +2,7 @@
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%global gcc_major 12
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# Note, gcc_release must be integer, if you want to add suffixes to
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# %%{release}, append them after %%{gcc_release} on Release: line.
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%global gcc_release 9
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%global gcc_release 10
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%global _unpackaged_files_terminate_build 0
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%global _performance_build 1
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@ -159,6 +159,8 @@ Patch21: 0021-StructReorderFields-Structure-reorder-fields.patch
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Patch22: 0022-DFE-Add-Dead-Field-Elimination-in-Struct-Reorg.patch
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Patch23: 0023-PGO-kernel-Add-fkernel-pgo-option-to-support-PGO-ker.patch
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Patch24: 0024-Struct-Reorg-Refactoring-and-merge-reorder-fields-in.patch
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Patch25: 0025-AArch64-Rewrite-the-tsv110-option.patch
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Patch26: 0026-GOMP-Enabling-moutline-atomics-improves-libgomp-perf.patch
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# On ARM EABI systems, we do want -gnueabi to be part of the
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# target triple.
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@ -649,6 +651,8 @@ not stable, so plugins must be rebuilt any time GCC is updated.
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%patch22 -p1
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%patch23 -p1
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%patch24 -p1
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%patch25 -p1
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%patch26 -p1
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echo '%{_vendor} %{version}-%{release}' > gcc/DEV-PHASE
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@ -2752,6 +2756,10 @@ end
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%doc rpm.doc/changelogs/libcc1/ChangeLog*
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%changelog
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* Mon Sep 04 2023 dingguangya <dingguangya1@huawei.com> 12.3.1-10
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- Type: Sync
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- DESC: Sync patch from openeuler/gcc
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* Tue Aug 29 2023 huangxiaoquan <huangxiaoquan1@huawei.com> 12.3.1-9
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- Type: Sync
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- DESC: Sync patch from openeuler/gcc part 2
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