107 lines
3.7 KiB
Diff
107 lines
3.7 KiB
Diff
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From 56752a6bbfb3d3501d0899b23020c3e2eb58882c Mon Sep 17 00:00:00 2001
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From: Xi Ruoyao <xry111@xry111.site>
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Date: Fri, 17 Nov 2023 20:44:17 +0800
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Subject: [PATCH] LoongArch: Fix internal error running "gcc -march=native" on
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LA664
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On LA664, the PRID preset is ISA_BASE_LA64V110 but the base architecture
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is guessed ISA_BASE_LA64V100. This causes a warning to be outputed:
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cc1: warning: base architecture 'la64' differs from PRID preset '?'
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But we've not set the "?" above in loongarch_isa_base_strings, thus it's
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a nullptr and then an ICE is triggered.
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Add ISA_BASE_LA64V110 to genopts and initialize
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loongarch_isa_base_strings[ISA_BASE_LA64V110] correctly to fix the ICE.
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The warning itself will be fixed later.
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gcc/ChangeLog:
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* config/loongarch/genopts/loongarch-strings:
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(STR_ISA_BASE_LA64V110): Add.
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* config/loongarch/genopts/loongarch.opt.in:
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(ISA_BASE_LA64V110): Add.
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* config/loongarch/loongarch-def.c
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(loongarch_isa_base_strings): Initialize [ISA_BASE_LA64V110]
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to STR_ISA_BASE_LA64V110.
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* config/loongarch/loongarch.opt: Regenerate.
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* config/loongarch/loongarch-str.h: Regenerate.
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Signed-off-by: ticat_fp <fanpeng@loongson.cn>
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---
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gcc/config/loongarch/genopts/loongarch-strings | 1 +
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gcc/config/loongarch/genopts/loongarch.opt.in | 3 +++
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gcc/config/loongarch/loongarch-def.c | 1 +
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gcc/config/loongarch/loongarch-str.h | 1 +
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gcc/config/loongarch/loongarch.opt | 3 +++
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5 files changed, 9 insertions(+)
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diff --git a/gcc/config/loongarch/genopts/loongarch-strings b/gcc/config/loongarch/genopts/loongarch-strings
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index 7bc4824007e..b2070c83ed0 100644
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--- a/gcc/config/loongarch/genopts/loongarch-strings
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+++ b/gcc/config/loongarch/genopts/loongarch-strings
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@@ -30,6 +30,7 @@ STR_CPU_LA664 la664
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# Base architecture
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STR_ISA_BASE_LA64V100 la64
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+STR_ISA_BASE_LA64V110 la64v1.1
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# -mfpu
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OPTSTR_ISA_EXT_FPU fpu
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diff --git a/gcc/config/loongarch/genopts/loongarch.opt.in b/gcc/config/loongarch/genopts/loongarch.opt.in
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index 00b4733d75b..b274b3fb21e 100644
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--- a/gcc/config/loongarch/genopts/loongarch.opt.in
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+++ b/gcc/config/loongarch/genopts/loongarch.opt.in
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@@ -32,6 +32,9 @@ Basic ISAs of LoongArch:
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EnumValue
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Enum(isa_base) String(@@STR_ISA_BASE_LA64V100@@) Value(ISA_BASE_LA64V100)
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+EnumValue
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+Enum(isa_base) String(@@STR_ISA_BASE_LA64V110@@) Value(ISA_BASE_LA64V110)
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+
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;; ISA extensions / adjustments
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Enum
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Name(isa_ext_fpu) Type(int)
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diff --git a/gcc/config/loongarch/loongarch-def.c b/gcc/config/loongarch/loongarch-def.c
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index 067629141b6..f22d488acb2 100644
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--- a/gcc/config/loongarch/loongarch-def.c
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+++ b/gcc/config/loongarch/loongarch-def.c
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@@ -165,6 +165,7 @@ loongarch_cpu_multipass_dfa_lookahead[N_TUNE_TYPES] = {
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const char*
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loongarch_isa_base_strings[N_ISA_BASE_TYPES] = {
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[ISA_BASE_LA64V100] = STR_ISA_BASE_LA64V100,
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+ [ISA_BASE_LA64V110] = STR_ISA_BASE_LA64V110,
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};
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const char*
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diff --git a/gcc/config/loongarch/loongarch-str.h b/gcc/config/loongarch/loongarch-str.h
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index fc4f41bfc1e..114dbc692d7 100644
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--- a/gcc/config/loongarch/loongarch-str.h
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+++ b/gcc/config/loongarch/loongarch-str.h
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@@ -33,6 +33,7 @@ along with GCC; see the file COPYING3. If not see
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#define STR_CPU_LA664 "la664"
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#define STR_ISA_BASE_LA64V100 "la64"
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+#define STR_ISA_BASE_LA64V110 "la64v1.1"
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#define OPTSTR_ISA_EXT_FPU "fpu"
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#define STR_NONE "none"
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diff --git a/gcc/config/loongarch/loongarch.opt b/gcc/config/loongarch/loongarch.opt
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index 7f129e53ba5..350ca30d232 100644
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--- a/gcc/config/loongarch/loongarch.opt
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+++ b/gcc/config/loongarch/loongarch.opt
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@@ -39,6 +39,9 @@ Basic ISAs of LoongArch:
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EnumValue
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Enum(isa_base) String(la64) Value(ISA_BASE_LA64V100)
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+EnumValue
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+Enum(isa_base) String(la64v1.1) Value(ISA_BASE_LA64V110)
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+
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;; ISA extensions / adjustments
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Enum
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Name(isa_ext_fpu) Type(int)
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--
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2.33.0
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