gcc/revert-moutline-atomics.patch

This backport contains 1 patch from gcc main stream tree.
The commit id of these patchs list as following in the order of time.

0001-aarch64-Implement-moutline-atomics.patch
3950b229a5ed6710f30241c2ddc3c74909bf4740

diff -Nurp a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
--- a/gcc/config/aarch64/aarch64.c	2021-03-11 17:12:30.380000000 +0800
+++ b/gcc/config/aarch64/aarch64.c	2021-03-11 17:13:29.992000000 +0800
@@ -18150,82 +18150,6 @@ aarch64_emit_unlikely_jump (rtx insn)
   add_reg_br_prob_note (jump, profile_probability::very_unlikely ());
 }
 
-/* We store the names of the various atomic helpers in a 5x4 array.
-   Return the libcall function given MODE, MODEL and NAMES.  */
-
-rtx
-aarch64_atomic_ool_func(machine_mode mode, rtx model_rtx,
-			const atomic_ool_names *names)
-{
-  memmodel model = memmodel_base (INTVAL (model_rtx));
-  int mode_idx, model_idx;
-
-  switch (mode)
-    {
-    case E_QImode:
-      mode_idx = 0;
-      break;
-    case E_HImode:
-      mode_idx = 1;
-      break;
-    case E_SImode:
-      mode_idx = 2;
-      break;
-    case E_DImode:
-      mode_idx = 3;
-      break;
-    case E_TImode:
-      mode_idx = 4;
-      break;
-    default:
-      gcc_unreachable ();
-    }
-
-  switch (model)
-    {
-    case MEMMODEL_RELAXED:
-      model_idx = 0;
-      break;
-    case MEMMODEL_CONSUME:
-    case MEMMODEL_ACQUIRE:
-      model_idx = 1;
-      break;
-    case MEMMODEL_RELEASE:
-      model_idx = 2;
-      break;
-    case MEMMODEL_ACQ_REL:
-    case MEMMODEL_SEQ_CST:
-      model_idx = 3;
-      break;
-    default:
-      gcc_unreachable ();
-    }
-
-  return init_one_libfunc_visibility (names->str[mode_idx][model_idx],
-				      VISIBILITY_HIDDEN);
-}
-
-#define DEF0(B, N) \
-  { "__aarch64_" #B #N "_relax", \
-    "__aarch64_" #B #N "_acq", \
-    "__aarch64_" #B #N "_rel", \
-    "__aarch64_" #B #N "_acq_rel" }
-
-#define DEF4(B)  DEF0(B, 1), DEF0(B, 2), DEF0(B, 4), DEF0(B, 8), \
-		 { NULL, NULL, NULL, NULL }
-#define DEF5(B)  DEF0(B, 1), DEF0(B, 2), DEF0(B, 4), DEF0(B, 8), DEF0(B, 16)
-
-static const atomic_ool_names aarch64_ool_cas_names = { { DEF5(cas) } };
-const atomic_ool_names aarch64_ool_swp_names = { { DEF4(swp) } };
-const atomic_ool_names aarch64_ool_ldadd_names = { { DEF4(ldadd) } };
-const atomic_ool_names aarch64_ool_ldset_names = { { DEF4(ldset) } };
-const atomic_ool_names aarch64_ool_ldclr_names = { { DEF4(ldclr) } };
-const atomic_ool_names aarch64_ool_ldeor_names = { { DEF4(ldeor) } };
-
-#undef DEF0
-#undef DEF4
-#undef DEF5
-
 /* Expand a compare and swap pattern.  */
 
 void
@@ -18272,17 +18196,6 @@ aarch64_expand_compare_and_swap (rtx ope
 						   newval, mod_s));
       cc_reg = aarch64_gen_compare_reg_maybe_ze (NE, rval, oldval, mode);
     }
-  else if (TARGET_OUTLINE_ATOMICS)
-    {
-      /* Oldval must satisfy compare afterward.  */
-      if (!aarch64_plus_operand (oldval, mode))
-	oldval = force_reg (mode, oldval);
-      rtx func = aarch64_atomic_ool_func (mode, mod_s, &aarch64_ool_cas_names);
-      rval = emit_library_call_value (func, NULL_RTX, LCT_NORMAL, r_mode,
-				      oldval, mode, newval, mode,
-				      XEXP (mem, 0), Pmode);
-      cc_reg = aarch64_gen_compare_reg_maybe_ze (NE, rval, oldval, mode);
-    }
   else
     {
       /* The oldval predicate varies by mode.  Test it and force to reg.  */
diff -Nurp a/gcc/config/aarch64/aarch64.opt b/gcc/config/aarch64/aarch64.opt
--- a/gcc/config/aarch64/aarch64.opt	2021-03-11 17:12:30.380000000 +0800
+++ b/gcc/config/aarch64/aarch64.opt	2021-03-11 17:13:29.992000000 +0800
@@ -272,6 +272,3 @@ user-land code.
 TargetVariable
 long aarch64_stack_protector_guard_offset = 0
 
-moutline-atomics
-Target Report Mask(OUTLINE_ATOMICS) Save
-Generate local calls to out-of-line atomic operations.
diff -Nurp a/gcc/config/aarch64/atomics.md b/gcc/config/aarch64/atomics.md
--- a/gcc/config/aarch64/atomics.md	2021-03-11 17:12:30.380000000 +0800
+++ b/gcc/config/aarch64/atomics.md	2021-03-11 17:13:29.992000000 +0800
@@ -186,27 +186,16 @@
   (match_operand:SI 3 "const_int_operand")]
   ""
   {
+    rtx (*gen) (rtx, rtx, rtx, rtx);
+
     /* Use an atomic SWP when available.  */
     if (TARGET_LSE)
-      {
-	emit_insn (gen_aarch64_atomic_exchange<mode>_lse
-		   (operands[0], operands[1], operands[2], operands[3]));
-      }
-    else if (TARGET_OUTLINE_ATOMICS)
-      {
-	machine_mode mode = <MODE>mode;
-	rtx func = aarch64_atomic_ool_func (mode, operands[3],
-					    &aarch64_ool_swp_names);
-	rtx rval = emit_library_call_value (func, operands[0], LCT_NORMAL,
-					    mode, operands[2], mode,
-					    XEXP (operands[1], 0), Pmode);
-        emit_move_insn (operands[0], rval);
-      }
+      gen = gen_aarch64_atomic_exchange<mode>_lse;
     else
-      {
-	emit_insn (gen_aarch64_atomic_exchange<mode>
-		   (operands[0], operands[1], operands[2], operands[3]));
-      }
+      gen = gen_aarch64_atomic_exchange<mode>;
+
+    emit_insn (gen (operands[0], operands[1], operands[2], operands[3]));
+
     DONE;
   }
 )
@@ -291,39 +280,6 @@
 	  }
 	operands[1] = force_reg (<MODE>mode, operands[1]);
       }
-    else if (TARGET_OUTLINE_ATOMICS)
-      {
-        const atomic_ool_names *names;
-	switch (<CODE>)
-	  {
-	  case MINUS:
-	    operands[1] = expand_simple_unop (<MODE>mode, NEG, operands[1],
-					      NULL, 1);
-	    /* fallthru */
-	  case PLUS:
-	    names = &aarch64_ool_ldadd_names;
-	    break;
-	  case IOR:
-	    names = &aarch64_ool_ldset_names;
-	    break;
-	  case XOR:
-	    names = &aarch64_ool_ldeor_names;
-	    break;
-	  case AND:
-	    operands[1] = expand_simple_unop (<MODE>mode, NOT, operands[1],
-					      NULL, 1);
-	    names = &aarch64_ool_ldclr_names;
-	    break;
-	  default:
-	    gcc_unreachable ();
-	  }
-        machine_mode mode = <MODE>mode;
-	rtx func = aarch64_atomic_ool_func (mode, operands[2], names);
-	emit_library_call_value (func, NULL_RTX, LCT_NORMAL, mode,
-				 operands[1], mode,
-				 XEXP (operands[0], 0), Pmode);
-        DONE;
-      }
     else
       gen = gen_aarch64_atomic_<atomic_optab><mode>;
 
@@ -449,40 +405,6 @@
 	}
       operands[2] = force_reg (<MODE>mode, operands[2]);
     }
-  else if (TARGET_OUTLINE_ATOMICS)
-    {
-      const atomic_ool_names *names;
-      switch (<CODE>)
-	{
-	case MINUS:
-	  operands[2] = expand_simple_unop (<MODE>mode, NEG, operands[2],
-					    NULL, 1);
-	  /* fallthru */
-	case PLUS:
-	  names = &aarch64_ool_ldadd_names;
-	  break;
-	case IOR:
-	  names = &aarch64_ool_ldset_names;
-	  break;
-	case XOR:
-	  names = &aarch64_ool_ldeor_names;
-	  break;
-	case AND:
-	  operands[2] = expand_simple_unop (<MODE>mode, NOT, operands[2],
-					    NULL, 1);
-	  names = &aarch64_ool_ldclr_names;
-	  break;
-	default:
-	  gcc_unreachable ();
-	}
-      machine_mode mode = <MODE>mode;
-      rtx func = aarch64_atomic_ool_func (mode, operands[3], names);
-      rtx rval = emit_library_call_value (func, operands[0], LCT_NORMAL, mode,
-					  operands[2], mode,
-					  XEXP (operands[1], 0), Pmode);
-      emit_move_insn (operands[0], rval);
-      DONE;
-    }
   else
     gen = gen_aarch64_atomic_fetch_<atomic_optab><mode>;
 
@@ -572,7 +494,7 @@
 {
   /* Use an atomic load-operate instruction when possible.  In this case
      we will re-compute the result from the original mem value. */
-  if (TARGET_LSE || TARGET_OUTLINE_ATOMICS)
+  if (TARGET_LSE)
     {
       rtx tmp = gen_reg_rtx (<MODE>mode);
       operands[2] = force_reg (<MODE>mode, operands[2]);
diff -Nurp a/gcc/testsuite/gcc.target/aarch64/atomic_cmp_exchange_zero_reg_1.c b/gcc/testsuite/gcc.target/aarch64/atomic_cmp_exchange_zero_reg_1.c
--- a/gcc/testsuite/gcc.target/aarch64/atomic_cmp_exchange_zero_reg_1.c	2021-03-11 17:12:34.168000000 +0800
+++ b/gcc/testsuite/gcc.target/aarch64/atomic_cmp_exchange_zero_reg_1.c	2021-03-11 17:13:30.656000000 +0800
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O2 -march=armv8-a+nolse -mno-outline-atomics" } */
+/* { dg-options "-O2 -march=armv8-a+nolse" } */
 /* { dg-skip-if "" { *-*-* } { "-mcpu=*" } { "" } } */
 
 int
diff -Nurp a/gcc/testsuite/gcc.target/aarch64/atomic_cmp_exchange_zero_strong_1.c b/gcc/testsuite/gcc.target/aarch64/atomic_cmp_exchange_zero_strong_1.c
--- a/gcc/testsuite/gcc.target/aarch64/atomic_cmp_exchange_zero_strong_1.c	2021-03-11 17:12:34.168000000 +0800
+++ b/gcc/testsuite/gcc.target/aarch64/atomic_cmp_exchange_zero_strong_1.c	2021-03-11 17:13:30.656000000 +0800
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O2 -march=armv8-a+nolse -mno-outline-atomics" } */
+/* { dg-options "-O2 -march=armv8-a+nolse" } */
 /* { dg-skip-if "" { *-*-* } { "-mcpu=*" } { "" } } */
 
 int
diff -Nurp a/gcc/testsuite/gcc.target/aarch64/atomic-comp-swap-release-acquire.c b/gcc/testsuite/gcc.target/aarch64/atomic-comp-swap-release-acquire.c
--- a/gcc/testsuite/gcc.target/aarch64/atomic-comp-swap-release-acquire.c	2021-03-11 17:12:33.988000000 +0800
+++ b/gcc/testsuite/gcc.target/aarch64/atomic-comp-swap-release-acquire.c	2021-03-11 17:13:30.648000000 +0800
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=armv8-a+nolse -O2 -fno-ipa-icf -mno-outline-atomics" } */
+/* { dg-options "-march=armv8-a+nolse -O2 -fno-ipa-icf" } */
 
 #include "atomic-comp-swap-release-acquire.x"
 
diff -Nurp a/gcc/testsuite/gcc.target/aarch64/atomic-op-acq_rel.c b/gcc/testsuite/gcc.target/aarch64/atomic-op-acq_rel.c
--- a/gcc/testsuite/gcc.target/aarch64/atomic-op-acq_rel.c	2021-03-11 17:12:33.988000000 +0800
+++ b/gcc/testsuite/gcc.target/aarch64/atomic-op-acq_rel.c	2021-03-11 17:13:30.648000000 +0800
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=armv8-a+nolse -O2 -mno-outline-atomics" } */
+/* { dg-options "-march=armv8-a+nolse -O2" } */
 
 #include "atomic-op-acq_rel.x"
 
diff -Nurp a/gcc/testsuite/gcc.target/aarch64/atomic-op-acquire.c b/gcc/testsuite/gcc.target/aarch64/atomic-op-acquire.c
--- a/gcc/testsuite/gcc.target/aarch64/atomic-op-acquire.c	2021-03-11 17:12:33.988000000 +0800
+++ b/gcc/testsuite/gcc.target/aarch64/atomic-op-acquire.c	2021-03-11 17:13:30.648000000 +0800
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=armv8-a+nolse -O2 -mno-outline-atomics" } */
+/* { dg-options "-march=armv8-a+nolse -O2" } */
 
 #include "atomic-op-acquire.x"
 
diff -Nurp a/gcc/testsuite/gcc.target/aarch64/atomic-op-char.c b/gcc/testsuite/gcc.target/aarch64/atomic-op-char.c
--- a/gcc/testsuite/gcc.target/aarch64/atomic-op-char.c	2021-03-11 17:12:33.992000000 +0800
+++ b/gcc/testsuite/gcc.target/aarch64/atomic-op-char.c	2021-03-11 17:13:30.648000000 +0800
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=armv8-a+nolse -O2 -mno-outline-atomics" } */
+/* { dg-options "-march=armv8-a+nolse -O2" } */
 
 #include "atomic-op-char.x"
 
diff -Nurp a/gcc/testsuite/gcc.target/aarch64/atomic-op-consume.c b/gcc/testsuite/gcc.target/aarch64/atomic-op-consume.c
--- a/gcc/testsuite/gcc.target/aarch64/atomic-op-consume.c	2021-03-11 17:12:33.992000000 +0800
+++ b/gcc/testsuite/gcc.target/aarch64/atomic-op-consume.c	2021-03-11 17:13:30.648000000 +0800
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=armv8-a+nolse -O2 -mno-outline-atomics" } */
+/* { dg-options "-march=armv8-a+nolse -O2" } */
 
 #include "atomic-op-consume.x"
 
diff -Nurp a/gcc/testsuite/gcc.target/aarch64/atomic-op-imm.c b/gcc/testsuite/gcc.target/aarch64/atomic-op-imm.c
--- a/gcc/testsuite/gcc.target/aarch64/atomic-op-imm.c	2021-03-11 17:12:33.992000000 +0800
+++ b/gcc/testsuite/gcc.target/aarch64/atomic-op-imm.c	2021-03-11 17:13:30.648000000 +0800
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=armv8-a+nolse -O2 -mno-outline-atomics" } */
+/* { dg-options "-march=armv8-a+nolse -O2" } */
 
 int v = 0;
 
diff -Nurp a/gcc/testsuite/gcc.target/aarch64/atomic-op-int.c b/gcc/testsuite/gcc.target/aarch64/atomic-op-int.c
--- a/gcc/testsuite/gcc.target/aarch64/atomic-op-int.c	2021-03-11 17:12:33.992000000 +0800
+++ b/gcc/testsuite/gcc.target/aarch64/atomic-op-int.c	2021-03-11 17:13:30.648000000 +0800
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=armv8-a+nolse -O2 -mno-outline-atomics" } */
+/* { dg-options "-march=armv8-a+nolse -O2" } */
 
 #include "atomic-op-int.x"
 
diff -Nurp a/gcc/testsuite/gcc.target/aarch64/atomic-op-long.c b/gcc/testsuite/gcc.target/aarch64/atomic-op-long.c
--- a/gcc/testsuite/gcc.target/aarch64/atomic-op-long.c	2021-03-11 17:12:33.992000000 +0800
+++ b/gcc/testsuite/gcc.target/aarch64/atomic-op-long.c	2021-03-11 17:13:30.648000000 +0800
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=armv8-a+nolse -O2 -mno-outline-atomics" } */
+/* { dg-options "-march=armv8-a+nolse -O2" } */
 
 long v = 0;
 
diff -Nurp a/gcc/testsuite/gcc.target/aarch64/atomic-op-relaxed.c b/gcc/testsuite/gcc.target/aarch64/atomic-op-relaxed.c
--- a/gcc/testsuite/gcc.target/aarch64/atomic-op-relaxed.c	2021-03-11 17:12:33.992000000 +0800
+++ b/gcc/testsuite/gcc.target/aarch64/atomic-op-relaxed.c	2021-03-11 17:13:30.648000000 +0800
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=armv8-a+nolse -O2 -mno-outline-atomics" } */
+/* { dg-options "-march=armv8-a+nolse -O2" } */
 
 #include "atomic-op-relaxed.x"
 
diff -Nurp a/gcc/testsuite/gcc.target/aarch64/atomic-op-release.c b/gcc/testsuite/gcc.target/aarch64/atomic-op-release.c
--- a/gcc/testsuite/gcc.target/aarch64/atomic-op-release.c	2021-03-11 17:12:34.012000000 +0800
+++ b/gcc/testsuite/gcc.target/aarch64/atomic-op-release.c	2021-03-11 17:13:30.648000000 +0800
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=armv8-a+nolse -O2 -mno-outline-atomics" } */
+/* { dg-options "-march=armv8-a+nolse -O2" } */
 
 #include "atomic-op-release.x"
 
diff -Nurp a/gcc/testsuite/gcc.target/aarch64/atomic-op-seq_cst.c b/gcc/testsuite/gcc.target/aarch64/atomic-op-seq_cst.c
--- a/gcc/testsuite/gcc.target/aarch64/atomic-op-seq_cst.c	2021-03-11 17:12:34.012000000 +0800
+++ b/gcc/testsuite/gcc.target/aarch64/atomic-op-seq_cst.c	2021-03-11 17:13:30.648000000 +0800
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=armv8-a+nolse -O2 -mno-outline-atomics" } */
+/* { dg-options "-march=armv8-a+nolse -O2" } */
 
 #include "atomic-op-seq_cst.x"
 
diff -Nurp a/gcc/testsuite/gcc.target/aarch64/atomic-op-short.c b/gcc/testsuite/gcc.target/aarch64/atomic-op-short.c
--- a/gcc/testsuite/gcc.target/aarch64/atomic-op-short.c	2021-03-11 17:12:34.168000000 +0800
+++ b/gcc/testsuite/gcc.target/aarch64/atomic-op-short.c	2021-03-11 17:13:30.652000000 +0800
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=armv8-a+nolse -O2 -mno-outline-atomics" } */
+/* { dg-options "-march=armv8-a+nolse -O2" } */
 
 #include "atomic-op-short.x"
 
diff -Nurp a/gcc/testsuite/gcc.target/aarch64/sync-comp-swap.c b/gcc/testsuite/gcc.target/aarch64/sync-comp-swap.c
--- a/gcc/testsuite/gcc.target/aarch64/sync-comp-swap.c	2021-03-11 17:12:34.168000000 +0800
+++ b/gcc/testsuite/gcc.target/aarch64/sync-comp-swap.c	2021-03-11 17:13:30.656000000 +0800
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=armv8-a+nolse -O2 -fno-ipa-icf -mno-outline-atomics" } */
+/* { dg-options "-march=armv8-a+nolse -O2 -fno-ipa-icf" } */
 
 #include "sync-comp-swap.x"
 
diff -Nurp a/gcc/testsuite/gcc.target/aarch64/sync-op-acquire.c b/gcc/testsuite/gcc.target/aarch64/sync-op-acquire.c
--- a/gcc/testsuite/gcc.target/aarch64/sync-op-acquire.c	2021-03-11 17:12:34.168000000 +0800
+++ b/gcc/testsuite/gcc.target/aarch64/sync-op-acquire.c	2021-03-11 17:13:30.656000000 +0800
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=armv8-a+nolse -O2 -mno-outline-atomics" } */
+/* { dg-options "-march=armv8-a+nolse -O2" } */
 
 #include "sync-op-acquire.x"
 
diff -Nurp a/gcc/testsuite/gcc.target/aarch64/sync-op-full.c b/gcc/testsuite/gcc.target/aarch64/sync-op-full.c
--- a/gcc/testsuite/gcc.target/aarch64/sync-op-full.c	2021-03-11 17:12:34.168000000 +0800
+++ b/gcc/testsuite/gcc.target/aarch64/sync-op-full.c	2021-03-11 17:13:30.656000000 +0800
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=armv8-a+nolse -O2 -mno-outline-atomics" } */
+/* { dg-options "-march=armv8-a+nolse -O2" } */
 
 #include "sync-op-full.x"