35 lines
1.6 KiB
Diff
35 lines
1.6 KiB
Diff
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diff -Nurp a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
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--- a/gcc/config/aarch64/aarch64.c 2020-07-06 17:20:30.368000000 +0800
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+++ b/gcc/config/aarch64/aarch64.c 2020-07-06 20:02:39.480000000 +0800
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@@ -18860,8 +18860,12 @@ aarch64_simd_clone_compute_vecsize_and_s
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elt_bits = GET_MODE_BITSIZE (SCALAR_TYPE_MODE (base_type));
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if (clonei->simdlen == 0)
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{
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- count = 2;
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- vec_bits = (num == 0 ? 64 : 128);
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+ /* Currently mathlib or sleef hasn't provide function for V2SF mode
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+ simdclone of single precision functions. (e.g._ZCVnN2v_expf)
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+ Therefore this mode is disabled by default to avoid link error.
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+ Use -msimdmath-64 option to enable this mode. */
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+ count = flag_simdmath_64 ? 2 : 1;
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+ vec_bits = ((num == 0 && flag_simdmath_64) ? 64 : 128);
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clonei->simdlen = vec_bits / elt_bits;
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}
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else
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diff -Nurp a/gcc/config/aarch64/aarch64.opt b/gcc/config/aarch64/aarch64.opt
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--- a/gcc/config/aarch64/aarch64.opt 2020-07-06 17:20:30.364000000 +0800
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+++ b/gcc/config/aarch64/aarch64.opt 2020-07-06 20:02:39.480000000 +0800
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@@ -186,6 +186,12 @@ precision of square root results to abou
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single precision and to 32 bits for double precision.
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If enabled, it implies -mlow-precision-recip-sqrt.
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+msimdmath-64
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+Target Var(flag_simdmath_64) Optimization
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+Allow compiler to generate V2SF 64 bits simdclone of math functions,
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+which is not currently supported in mathlib or sleef.
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+Therefore this option is disabled by default.
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+
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mlow-precision-div
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Target Var(flag_mlow_precision_div) Optimization
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Enable the division approximation. Enabling this reduces
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