fftw/fftw-3.3.8-sw.patch
wzx 7fff300919 Add sw64 architecture
Signed-off-by: wzx <wuzx1226@qq.com>
2022-10-24 09:03:07 +08:00

54 lines
1.7 KiB
Diff
Executable File

diff -Naur fftw-3.3.8.org/kernel/cycle.h fftw-3.3.8.sw/kernel/cycle.h
--- fftw-3.3.8.org/kernel/cycle.h 2022-03-03 08:12:02.740000000 +0000
+++ fftw-3.3.8.sw/kernel/cycle.h 2022-03-03 08:14:34.660000000 +0000
@@ -385,6 +385,26 @@
#define HAVE_TICK_COUNTER
#endif
/*----------------------------------------------------------------*/
+#if defined(__GNUC__) && defined(__sw_64__) && !defined(HAVE_TICK_COUNTER)
+/*
+ * The 32-bit cycle counter on sw_64 overflows pretty quickly,
+ * unfortunately. A 1GHz machine overflows in 4 seconds.
+ */
+typedef unsigned int ticks;
+
+static __inline__ ticks getticks(void)
+{
+ unsigned long cc;
+ __asm__ __volatile__ ("rtc %0" : "=r"(cc));
+ return (cc & 0xFFFFFFFF);
+}
+
+INLINE_ELAPSED(__inline__)
+
+#define HAVE_TICK_COUNTER
+#endif
+
+/*----------------------------------------------------------------*/
#if defined(__GNUC__) && defined(__alpha__) && !defined(HAVE_TICK_COUNTER)
/*
* The 32-bit cycle counter on alpha overflows pretty quickly,
@@ -421,6 +441,22 @@
#endif
/*----------------------------------------------------------------*/
+#if (defined(__DECC) || defined(__DECCXX)) && defined(__sw_64) && defined(HAVE_C_ASM_H) && !defined(HAVE_TICK_COUNTER)
+# include <c_asm.h>
+typedef unsigned int ticks;
+
+static __inline ticks getticks(void)
+{
+ unsigned long cc;
+ cc = asm("rtc %v0");
+ return (cc & 0xFFFFFFFF);
+}
+
+INLINE_ELAPSED(__inline)
+
+#define HAVE_TICK_COUNTER
+#endif
+/*----------------------------------------------------------------*/
#if (defined(__DECC) || defined(__DECCXX)) && defined(__alpha) && defined(HAVE_C_ASM_H) && !defined(HAVE_TICK_COUNTER)
# include <c_asm.h>
typedef unsigned int ticks;