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dyninst/dyninst-support-clang-build.patch
lf14 ca0f9c5c98 support clang build
2023-09-23 11:39:59 +08:00

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From 6644c84edd08305f0305a1aaea20797cb01cb197 Mon Sep 17 00:00:00 2001
From: luofeng <luofeng13@huawei.com>
Date: Sat, 23 Sep 2023 10:17:45 +0800
Subject: [PATCH] support clang build
---
cmake/options.cmake | 3 ++-
.../src/AMDGPU/cdna2/InstructionDecoder-amdgpu-cdna2.C | 4 ++--
.../src/AMDGPU/cdna2/InstructionDecoder-amdgpu-cdna2.h | 2 +-
.../src/AMDGPU/gfx908/InstructionDecoder-amdgpu-gfx908.C | 2 +-
.../src/AMDGPU/gfx908/InstructionDecoder-amdgpu-gfx908.h | 2 +-
.../src/AMDGPU/vega/InstructionDecoder-amdgpu-vega.C | 4 ++--
6 files changed, 9 insertions(+), 8 deletions(-)
diff --git a/cmake/options.cmake b/cmake/options.cmake
index 7cbe66b..0481463 100644
--- a/cmake/options.cmake
+++ b/cmake/options.cmake
@@ -1,5 +1,6 @@
# Use OpenMP?
-option(USE_OpenMP "Use OpenMP for parallel parsing" ON)
+# option(USE_OpenMP "Use OpenMP for parallel parsing" ON)
+option(USE_OpenMP "Use OpenMP for parallel parsing" OFF)
# Use SymtabAPI or SymLite?
option(
diff --git a/instructionAPI/src/AMDGPU/cdna2/InstructionDecoder-amdgpu-cdna2.C b/instructionAPI/src/AMDGPU/cdna2/InstructionDecoder-amdgpu-cdna2.C
index daf7a4b..66b4a3a 100644
--- a/instructionAPI/src/AMDGPU/cdna2/InstructionDecoder-amdgpu-cdna2.C
+++ b/instructionAPI/src/AMDGPU/cdna2/InstructionDecoder-amdgpu-cdna2.C
@@ -162,7 +162,7 @@ namespace Dyninst {
Expression::Ptr InstructionDecoder_amdgpu_cdna2::decodeOPR_WAITCNT(uint64_t input){
return Immediate::makeImmediate(Result(s16, input));
}
- Expression::Ptr InstructionDecoder_amdgpu_cdna2::makeRegisterExpression(MachRegister registerID){
+ Expression::Ptr InstructionDecoder_amdgpu_cdna2::makeRegisterExpression(MachRegister registerID, uint32_t){
if(registerID == amdgpu_cdna2::src_literal){
return Immediate::makeImmediate(Result(u32,decodeOPR_LITERAL()));
}
@@ -235,7 +235,7 @@ namespace Dyninst {
mainDecode();
if(entryToCategory(insn_in_progress->getOperation().getID())==c_BranchInsn){
//cout << "Is Branch Instruction !! , name = " << insn_in_progress -> getOperation().mnemonic << endl;
- //std::mem_fn(decode_lookup_table[instr_family])(this);
+ //std::mem_fun(decode_lookup_table[instr_family])(this);
}
b.start += insn_in_progress->size();
return *insn_in_progress;
diff --git a/instructionAPI/src/AMDGPU/cdna2/InstructionDecoder-amdgpu-cdna2.h b/instructionAPI/src/AMDGPU/cdna2/InstructionDecoder-amdgpu-cdna2.h
index d35482f..f194ac4 100644
--- a/instructionAPI/src/AMDGPU/cdna2/InstructionDecoder-amdgpu-cdna2.h
+++ b/instructionAPI/src/AMDGPU/cdna2/InstructionDecoder-amdgpu-cdna2.h
@@ -306,7 +306,7 @@ namespace Dyninst {
Expression::Ptr decodeOPR_SIMM32(uint64_t input);
Expression::Ptr decodeOPR_WAITCNT(uint64_t input);
using InstructionDecoderImpl::makeRegisterExpression;
- Expression::Ptr makeRegisterExpression(MachRegister registerID);
+ Expression::Ptr makeRegisterExpression(MachRegister registerID, uint32_t num_elements = 1);
Expression::Ptr makeRegisterExpression(MachRegister registerID, uint32_t low , uint32_t high );
void specialHandle();
#include "amdgpu_cdna2_decoder_impl.h"
diff --git a/instructionAPI/src/AMDGPU/gfx908/InstructionDecoder-amdgpu-gfx908.C b/instructionAPI/src/AMDGPU/gfx908/InstructionDecoder-amdgpu-gfx908.C
index 70d9edc..a629b3c 100644
--- a/instructionAPI/src/AMDGPU/gfx908/InstructionDecoder-amdgpu-gfx908.C
+++ b/instructionAPI/src/AMDGPU/gfx908/InstructionDecoder-amdgpu-gfx908.C
@@ -178,7 +178,7 @@ namespace Dyninst {
Expression::Ptr InstructionDecoder_amdgpu_gfx908::decodeOPR_WAITCNT(uint64_t input){
return Immediate::makeImmediate(Result(s16, input));
}
- Expression::Ptr InstructionDecoder_amdgpu_gfx908::makeRegisterExpression(MachRegister registerID){
+ Expression::Ptr InstructionDecoder_amdgpu_gfx908::makeRegisterExpression(MachRegister registerID, uint32_t){
if(registerID == amdgpu_gfx908::src_literal){
return Immediate::makeImmediate(Result(u32,decodeOPR_LITERAL()));
}
diff --git a/instructionAPI/src/AMDGPU/gfx908/InstructionDecoder-amdgpu-gfx908.h b/instructionAPI/src/AMDGPU/gfx908/InstructionDecoder-amdgpu-gfx908.h
index 7826af0..b5420d8 100644
--- a/instructionAPI/src/AMDGPU/gfx908/InstructionDecoder-amdgpu-gfx908.h
+++ b/instructionAPI/src/AMDGPU/gfx908/InstructionDecoder-amdgpu-gfx908.h
@@ -299,7 +299,7 @@ namespace Dyninst {
Expression::Ptr decodeOPR_SIMM32(uint64_t input);
Expression::Ptr decodeOPR_WAITCNT(uint64_t input);
using InstructionDecoderImpl::makeRegisterExpression;
- Expression::Ptr makeRegisterExpression(MachRegister registerID);
+ Expression::Ptr makeRegisterExpression(MachRegister registerID, uint32_t num_elements = 1);
Expression::Ptr makeRegisterExpression(MachRegister registerID, uint32_t low , uint32_t high );
void specialHandle();
#include "amdgpu_gfx908_decoder_impl.h"
diff --git a/instructionAPI/src/AMDGPU/vega/InstructionDecoder-amdgpu-vega.C b/instructionAPI/src/AMDGPU/vega/InstructionDecoder-amdgpu-vega.C
index ed7cbed..3093ece 100644
--- a/instructionAPI/src/AMDGPU/vega/InstructionDecoder-amdgpu-vega.C
+++ b/instructionAPI/src/AMDGPU/vega/InstructionDecoder-amdgpu-vega.C
@@ -552,7 +552,7 @@ namespace Dyninst {
bool InstructionDecoder_amdgpu_vega::decodeOperands(const amdgpu_vega_insn_entry & insn_entry) {
if(insn_entry.operandCnt!=0){
for (std::size_t i =0 ; i < insn_entry.operandCnt; i++){
- std::mem_fn(insn_entry.operands[i])(this);
+ std::mem_fun(insn_entry.operands[i])(this);
}
}
return true;
@@ -721,7 +721,7 @@ namespace Dyninst {
setupInsnWord(b);
mainDecodeOpcode(b);
if(entryToCategory(insn_in_progress->getOperation().getID())==c_BranchInsn){
- std::mem_fn(decode_lookup_table[instr_family])(this);
+ std::mem_fun(decode_lookup_table[instr_family])(this);
}
b.start += insn_in_progress->size();
return *insn_in_progress;
--
2.19.1
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