1f34bd76e4
Sync some patches for hns3 about refactor mailbox, add new API for RSS, support power monitor and some bugfix, modifies are as follow: - app/testpmd: fix crash in multi -process forwarding - net/hns3: support power monitor - net/hns3: remove QinQ insert support for VF - net/hns3: fix reset level comparison - net/hns3: fix disable command with firmware - net/hns3: fix VF multiple count on one reset - net/hns3: refactor handle mailbox function - net/hns3: refactor send mailbox function - net/hns3: refactor PF mailbox message struct - net/hns3: refactor VF mailbox message struct - app/testpmd: set RSS hash algorithm - ethdev: get RSS hash algorithm by name - ring: add telemetry command for ring info - ring: add telemetry command to list rings - eal: introduce more macros for bit definition - dmadev: add tracepoints in data path API - dmadev: add telemetry capability for m2d auto free - maintainers: update for DMA device performance tool Signed-off-by: Dengdui Huang <huangdengdui@huawei.com>
103 lines
2.8 KiB
Diff
103 lines
2.8 KiB
Diff
From 8ff07d4203a07fadbae3b9cac3e0f6301d85b022 Mon Sep 17 00:00:00 2001
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From: Chengwen Feng <fengchengwen@huawei.com>
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Date: Fri, 26 Jan 2024 06:10:06 +0000
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Subject: [PATCH 16/30] eal: introduce more macros for bit definition
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[ upstream commit 1d8f2285ed3ffc3dfbf0857a960915c0e8ef6a8d ]
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Introduce macros:
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1. RTE_SHIFT_VAL64: get the uint64_t value which shifted by nr.
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2. RTE_SHIFT_VAL32: get the uint32_t value which shifted by nr.
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3. RTE_GENMASK64: generate a contiguous 64bit bitmask starting at bit
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position low and ending at position high.
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4. RTE_GENMASK32: generate a contiguous 32bit bitmask starting at bit
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position low and ending at position high.
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5. RTE_FIELD_GET64: extract a 64bit field element.
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6. RTE_FIELD_GET32: extract a 32bit field element.
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Signed-off-by: Chengwen Feng <fengchengwen@huawei.com>
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---
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lib/eal/include/rte_bitops.h | 66 ++++++++++++++++++++++++++++++++++++
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1 file changed, 66 insertions(+)
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diff --git a/lib/eal/include/rte_bitops.h b/lib/eal/include/rte_bitops.h
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index 6bd8bae..449565e 100644
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--- a/lib/eal/include/rte_bitops.h
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+++ b/lib/eal/include/rte_bitops.h
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@@ -39,6 +39,72 @@ extern "C" {
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*/
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#define RTE_BIT32(nr) (UINT32_C(1) << (nr))
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+/**
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+ * Get the uint32_t shifted value.
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+ *
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+ * @param val
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+ * The value to be shifted.
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+ * @param nr
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+ * The shift number in range of 0 to (32 - width of val).
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+ */
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+#define RTE_SHIFT_VAL32(val, nr) (UINT32_C(val) << (nr))
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+
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+/**
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+ * Get the uint64_t shifted value.
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+ *
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+ * @param val
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+ * The value to be shifted.
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+ * @param nr
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+ * The shift number in range of 0 to (64 - width of val).
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+ */
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+#define RTE_SHIFT_VAL64(val, nr) (UINT64_C(val) << (nr))
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+
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+/**
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+ * Generate a contiguous 32-bit mask
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+ * starting at bit position low and ending at position high.
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+ *
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+ * @param high
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+ * High bit position.
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+ * @param low
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+ * Low bit position.
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+ */
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+#define RTE_GENMASK32(high, low) \
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+ (((~UINT32_C(0)) << (low)) & (~UINT32_C(0) >> (31u - (high))))
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+
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+/**
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+ * Generate a contiguous 64-bit mask
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+ * starting at bit position low and ending at position high.
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+ *
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+ * @param high
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+ * High bit position.
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+ * @param low
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+ * Low bit position.
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+ */
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+#define RTE_GENMASK64(high, low) \
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+ (((~UINT64_C(0)) << (low)) & (~UINT64_C(0) >> (63u - (high))))
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+
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+/**
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+ * Extract a 32-bit field element.
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+ *
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+ * @param mask
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+ * Shifted mask.
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+ * @param reg
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+ * Value of entire bitfield.
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+ */
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+#define RTE_FIELD_GET32(mask, reg) \
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+ ((typeof(mask))(((reg) & (mask)) >> rte_ctz32(mask)))
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+
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+/**
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+ * Extract a 64-bit field element.
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+ *
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+ * @param mask
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+ * Shifted mask.
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+ * @param reg
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+ * Value of entire bitfield.
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+ */
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+#define RTE_FIELD_GET64(mask, reg) \
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+ ((typeof(mask))(((reg) & (mask)) >> rte_ctz64(mask)))
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+
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/*------------------------ 32-bit relaxed operations ------------------------*/
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/**
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--
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2.33.0
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