225 lines
8.1 KiB
Diff
225 lines
8.1 KiB
Diff
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From bc4b30bb7c3ce3310d98a43bb5364b327ecd5cf9 Mon Sep 17 00:00:00 2001
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From: Dongdong Liu <liudongdong3@huawei.com>
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Date: Fri, 21 Apr 2023 17:53:21 +0800
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Subject: net/hns3: simplify hardware checksum offloading
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[ upstream commit 7fd763a9dd18a3edd98e95c26e96349fd71cbb9b ]
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If the NIC support simple BD mode, the hardware will calculate
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the checksum from the start position of checksum and fill the
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checksum result to the offset position, which simple the
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HW operations of calculating the type and header length of
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L3/L4.
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Add this mode for hns3 PMD when the packet type is L4.
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Signed-off-by: Dongdong Liu <liudongdong3@huawei.com>
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---
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drivers/net/hns3/hns3_cmd.c | 3 ++
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drivers/net/hns3/hns3_cmd.h | 1 +
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drivers/net/hns3/hns3_dump.c | 1 +
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drivers/net/hns3/hns3_ethdev.h | 1 +
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drivers/net/hns3/hns3_rxtx.c | 52 +++++++++++++++++++++++++++++++++-
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drivers/net/hns3/hns3_rxtx.h | 12 +++++++-
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6 files changed, 68 insertions(+), 2 deletions(-)
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diff --git a/drivers/net/hns3/hns3_cmd.c b/drivers/net/hns3/hns3_cmd.c
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index bdfc85f934..d530650452 100644
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--- a/drivers/net/hns3/hns3_cmd.c
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+++ b/drivers/net/hns3/hns3_cmd.c
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@@ -419,6 +419,7 @@ hns3_get_caps_name(uint32_t caps_id)
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} dev_caps[] = {
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{ HNS3_CAPS_FD_QUEUE_REGION_B, "fd_queue_region" },
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{ HNS3_CAPS_PTP_B, "ptp" },
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+ { HNS3_CAPS_SIMPLE_BD_B, "simple_bd" },
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{ HNS3_CAPS_TX_PUSH_B, "tx_push" },
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{ HNS3_CAPS_PHY_IMP_B, "phy_imp" },
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{ HNS3_CAPS_TQP_TXRX_INDEP_B, "tqp_txrx_indep" },
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@@ -489,6 +490,8 @@ hns3_parse_capability(struct hns3_hw *hw,
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hns3_warn(hw, "ignore PTP capability due to lack of "
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"rxd advanced layout capability.");
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}
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+ if (hns3_get_bit(caps, HNS3_CAPS_SIMPLE_BD_B))
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+ hns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_SIMPLE_BD_B, 1);
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if (hns3_get_bit(caps, HNS3_CAPS_TX_PUSH_B))
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hns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_TX_PUSH_B, 1);
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if (hns3_get_bit(caps, HNS3_CAPS_PHY_IMP_B))
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diff --git a/drivers/net/hns3/hns3_cmd.h b/drivers/net/hns3/hns3_cmd.h
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index eb394c9dec..4abe0f1d13 100644
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--- a/drivers/net/hns3/hns3_cmd.h
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+++ b/drivers/net/hns3/hns3_cmd.h
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@@ -313,6 +313,7 @@ enum HNS3_CAPS_BITS {
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*/
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HNS3_CAPS_FD_QUEUE_REGION_B = 2,
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HNS3_CAPS_PTP_B,
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+ HNS3_CAPS_SIMPLE_BD_B = 5,
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HNS3_CAPS_TX_PUSH_B = 6,
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HNS3_CAPS_PHY_IMP_B = 7,
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HNS3_CAPS_TQP_TXRX_INDEP_B,
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diff --git a/drivers/net/hns3/hns3_dump.c b/drivers/net/hns3/hns3_dump.c
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index 8268506f6f..a793ba64ad 100644
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--- a/drivers/net/hns3/hns3_dump.c
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+++ b/drivers/net/hns3/hns3_dump.c
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@@ -96,6 +96,7 @@ hns3_get_dev_feature_capability(FILE *file, struct hns3_hw *hw)
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{HNS3_DEV_SUPPORT_TX_PUSH_B, "TX PUSH"},
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{HNS3_DEV_SUPPORT_INDEP_TXRX_B, "INDEP TXRX"},
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{HNS3_DEV_SUPPORT_STASH_B, "STASH"},
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+ {HNS3_DEV_SUPPORT_SIMPLE_BD_B, "SIMPLE BD"},
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{HNS3_DEV_SUPPORT_RXD_ADV_LAYOUT_B, "RXD Advanced Layout"},
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{HNS3_DEV_SUPPORT_OUTER_UDP_CKSUM_B, "OUTER UDP CKSUM"},
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{HNS3_DEV_SUPPORT_RAS_IMP_B, "RAS IMP"},
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diff --git a/drivers/net/hns3/hns3_ethdev.h b/drivers/net/hns3/hns3_ethdev.h
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index 9acc5a3d7e..ee4dd18d7b 100644
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--- a/drivers/net/hns3/hns3_ethdev.h
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+++ b/drivers/net/hns3/hns3_ethdev.h
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@@ -886,6 +886,7 @@ enum hns3_dev_cap {
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HNS3_DEV_SUPPORT_TX_PUSH_B,
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HNS3_DEV_SUPPORT_INDEP_TXRX_B,
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HNS3_DEV_SUPPORT_STASH_B,
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+ HNS3_DEV_SUPPORT_SIMPLE_BD_B,
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HNS3_DEV_SUPPORT_RXD_ADV_LAYOUT_B,
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HNS3_DEV_SUPPORT_OUTER_UDP_CKSUM_B,
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HNS3_DEV_SUPPORT_RAS_IMP_B,
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diff --git a/drivers/net/hns3/hns3_rxtx.c b/drivers/net/hns3/hns3_rxtx.c
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index 1f44c0345f..aaf0a06ca6 100644
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--- a/drivers/net/hns3/hns3_rxtx.c
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+++ b/drivers/net/hns3/hns3_rxtx.c
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@@ -3046,6 +3046,10 @@ hns3_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t nb_desc,
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HNS3_PORT_BASE_VLAN_ENABLE;
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else
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txq->pvid_sw_shift_en = false;
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+
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+ if (hns3_dev_get_support(hw, SIMPLE_BD))
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+ txq->simple_bd_enable = true;
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+
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txq->max_non_tso_bd_num = hw->max_non_tso_bd_num;
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txq->configured = true;
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txq->io_base = (void *)((char *)hw->io_base +
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@@ -3162,7 +3166,7 @@ hns3_set_tso(struct hns3_desc *desc, uint32_t paylen, struct rte_mbuf *rxm)
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return;
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desc->tx.type_cs_vlan_tso_len |= rte_cpu_to_le_32(BIT(HNS3_TXD_TSO_B));
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- desc->tx.mss = rte_cpu_to_le_16(rxm->tso_segsz);
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+ desc->tx.ckst_mss |= rte_cpu_to_le_16(rxm->tso_segsz);
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}
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static inline void
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@@ -3901,6 +3905,50 @@ hns3_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts,
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return i;
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}
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+static inline int
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+hns3_handle_simple_bd(struct hns3_tx_queue *txq, struct hns3_desc *desc,
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+ struct rte_mbuf *m)
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+{
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+#define HNS3_TCP_CSUM_OFFSET 16
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+#define HNS3_UDP_CSUM_OFFSET 6
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+
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+ /*
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+ * In HIP09, NIC HW support Tx simple BD mode that the HW will
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+ * calculate the checksum from the start position of checksum and fill
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+ * the checksum result to the offset position without packet type and
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+ * header length of L3/L4.
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+ * For non-tunneling packet:
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+ * - Tx simple BD support for TCP and UDP checksum.
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+ * For tunneling packet:
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+ * - Tx simple BD support for inner L4 checksum(except sctp checksum).
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+ * - Tx simple BD not support the outer checksum and the inner L3
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+ * checksum.
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+ * - Besides, Tx simple BD is not support for TSO.
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+ */
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+ if (txq->simple_bd_enable && !(m->ol_flags & RTE_MBUF_F_TX_IP_CKSUM) &&
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+ !(m->ol_flags & RTE_MBUF_F_TX_TCP_SEG) &&
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+ !(m->ol_flags & RTE_MBUF_F_TX_OUTER_IP_CKSUM) &&
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+ ((m->ol_flags & RTE_MBUF_F_TX_L4_MASK) == RTE_MBUF_F_TX_TCP_CKSUM ||
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+ (m->ol_flags & RTE_MBUF_F_TX_L4_MASK) == RTE_MBUF_F_TX_UDP_CKSUM)) {
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+ /* set checksum start and offset, defined in 2 Bytes */
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+ hns3_set_field(desc->tx.type_cs_vlan_tso_len,
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+ HNS3_TXD_L4_START_M, HNS3_TXD_L4_START_S,
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+ (m->l2_len + m->l3_len) >> HNS3_SIMPLE_BD_UNIT);
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+ hns3_set_field(desc->tx.ol_type_vlan_len_msec,
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+ HNS3_TXD_L4_CKS_OFFSET_M, HNS3_TXD_L4_CKS_OFFSET_S,
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+ (m->ol_flags & RTE_MBUF_F_TX_L4_MASK) ==
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+ RTE_MBUF_F_TX_TCP_CKSUM ?
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+ HNS3_TCP_CSUM_OFFSET >> HNS3_SIMPLE_BD_UNIT :
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+ HNS3_UDP_CSUM_OFFSET >> HNS3_SIMPLE_BD_UNIT);
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+
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+ hns3_set_bit(desc->tx.ckst_mss, HNS3_TXD_CKST_B, 1);
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+
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+ return 0;
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+ }
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+
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+ return -ENOTSUP;
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+}
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+
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static int
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hns3_parse_cksum(struct hns3_tx_queue *txq, uint16_t tx_desc_id,
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struct rte_mbuf *m)
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@@ -3910,6 +3958,8 @@ hns3_parse_cksum(struct hns3_tx_queue *txq, uint16_t tx_desc_id,
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/* Enable checksum offloading */
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if (m->ol_flags & HNS3_TX_CKSUM_OFFLOAD_MASK) {
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+ if (hns3_handle_simple_bd(txq, desc, m) == 0)
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+ return 0;
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/* Fill in tunneling parameters if necessary */
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if (hns3_parse_tunneling_params(txq, m, tx_desc_id)) {
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txq->dfx_stats.unsupported_tunnel_pkt_cnt++;
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diff --git a/drivers/net/hns3/hns3_rxtx.h b/drivers/net/hns3/hns3_rxtx.h
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index fa39f6481a..7685ac2ea3 100644
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--- a/drivers/net/hns3/hns3_rxtx.h
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+++ b/drivers/net/hns3/hns3_rxtx.h
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@@ -134,6 +134,9 @@
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#define HNS3_TXD_L4LEN_S 24
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#define HNS3_TXD_L4LEN_M (0xffUL << HNS3_TXD_L4LEN_S)
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+#define HNS3_TXD_L4_START_S 8
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+#define HNS3_TXD_L4_START_M (0xffff << HNS3_TXD_L4_START_S)
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+
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#define HNS3_TXD_OL3T_S 0
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#define HNS3_TXD_OL3T_M (0x3 << HNS3_TXD_OL3T_S)
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#define HNS3_TXD_OVLAN_B 2
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@@ -141,6 +144,9 @@
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#define HNS3_TXD_TUNTYPE_S 4
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#define HNS3_TXD_TUNTYPE_M (0xf << HNS3_TXD_TUNTYPE_S)
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+#define HNS3_TXD_L4_CKS_OFFSET_S 8
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+#define HNS3_TXD_L4_CKS_OFFSET_M (0xffff << HNS3_TXD_L4_CKS_OFFSET_S)
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+
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#define HNS3_TXD_BDTYPE_S 0
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#define HNS3_TXD_BDTYPE_M (0xf << HNS3_TXD_BDTYPE_S)
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#define HNS3_TXD_FE_B 4
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@@ -157,10 +163,13 @@
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#define HNS3_TXD_MSS_S 0
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#define HNS3_TXD_MSS_M (0x3fff << HNS3_TXD_MSS_S)
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+#define HNS3_TXD_CKST_B 14
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+
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#define HNS3_TXD_OL4CS_B 22
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#define HNS3_L2_LEN_UNIT 1UL
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#define HNS3_L3_LEN_UNIT 2UL
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#define HNS3_L4_LEN_UNIT 2UL
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+#define HNS3_SIMPLE_BD_UNIT 1UL
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#define HNS3_TXD_DEFAULT_BDTYPE 0
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#define HNS3_TXD_VLD_CMD (0x1 << HNS3_TXD_VLD_B)
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@@ -247,7 +256,7 @@ struct hns3_desc {
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uint32_t paylen_fd_dop_ol4cs;
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uint16_t tp_fe_sc_vld_ra_ri;
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- uint16_t mss;
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+ uint16_t ckst_mss;
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} tx;
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struct {
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@@ -488,6 +497,7 @@ struct hns3_tx_queue {
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*/
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uint16_t udp_cksum_mode:1;
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+ /* check whether the simple BD mode is supported */
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uint16_t simple_bd_enable:1;
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uint16_t tx_push_enable:1; /* check whether the tx push is enabled */
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/*
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--
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2.23.0
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