91 lines
2.8 KiB
Diff
91 lines
2.8 KiB
Diff
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From 1e64387af427ea8b610ea444715822ec7e2c874d Mon Sep 17 00:00:00 2001
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From: Jean Delvare <jdelvare@suse.de>
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Date: Fri, 26 May 2023 17:41:59 +0200
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Subject: [PATCH] dmidecode: Add support for Loongarch
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SMBIOS specification version 3.6.0 adds support for the Loongarch
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processor architecture.
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Signed-off-by: Jean Delvare <jdelvare@suse.de>
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---
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dmidecode.c | 28 ++++++++++++++++++++++++++++
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dmidecode.h | 1 +
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2 files changed, 29 insertions(+)
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diff --git a/dmidecode.c b/dmidecode.c
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index fbf9f9a..82d264c 100644
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--- a/dmidecode.c
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+++ b/dmidecode.c
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@@ -58,6 +58,8 @@
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* https://trustedcomputinggroup.org/pc-client-platform-tpm-profile-ptp-specification/
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* - "RedFish Host Interface Specification" (DMTF DSP0270)
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* https://www.dmtf.org/sites/default/files/DSP0270_1.0.1.pdf
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+ * - LoongArch Reference Manual, volume 1
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+ * https://loongson.github.io/LoongArch-Documentation/LoongArch-Vol1-EN.html#_cpucfg
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*/
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#include <fcntl.h>
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@@ -988,6 +990,24 @@ static const char *dmi_processor_family(const struct dmi_header *h, u16 ver)
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{ 0x200, "RV32" },
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{ 0x201, "RV64" },
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{ 0x202, "RV128" },
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+
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+ { 0x258, "LoongArch" },
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+ { 0x259, "Loongson 1" },
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+ { 0x25A, "Loongson 2" },
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+ { 0x25B, "Loongson 3" },
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+ { 0x25C, "Loongson 2K" },
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+ { 0x25D, "Loongson 3A" },
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+ { 0x25E, "Loongson 3B" },
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+ { 0x25F, "Loongson 3C" },
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+ { 0x260, "Loongson 3D" },
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+ { 0x261, "Loongson 3E" },
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+ { 0x262, "Dual-Core Loongson 2K 2xxx" },
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+ { 0x26C, "Quad-Core Loongson 3A 5xxx" },
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+ { 0x26D, "Multi-Core Loongson 3A 5xxx" },
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+ { 0x26E, "Quad-Core Loongson 3B 5xxx" },
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+ { 0x26F, "Multi-Core Loongson 3B 5xxx" },
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+ { 0x270, "Multi-Core Loongson 3C 5xxx" },
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+ { 0x271, "Multi-Core Loongson 3D 5xxx" },
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};
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/*
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* Note to developers: when adding entries to this list, check if
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@@ -1106,6 +1126,9 @@ static enum cpuid_type dmi_get_cpuid_type(const struct dmi_header *h)
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|| (type >= 0xB6 && type <= 0xB7) /* AMD */
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|| (type >= 0xE4 && type <= 0xEF)) /* AMD */
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return cpuid_x86_amd;
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+ else if ((type >= 0x258 && type <= 0x262) /* Loongarch */
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+ || (type >= 0x26C && type <= 0x271)) /* Loongarch */
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+ return cpuid_loongarch;
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/* neither X86 nor ARM */
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return cpuid_none;
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@@ -1203,6 +1226,11 @@ void dmi_print_cpuid(void (*print_cb)(const char *name, const char *format, ...)
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((eax >> 4) & 0xF) | (((eax >> 8) & 0xF) == 0xF ? (eax >> 12) & 0xF0 : 0),
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eax & 0xF);
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break;
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+
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+ case cpuid_loongarch: /* LoongArch Reference Manual, volume 1 */
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+ eax = DWORD(p);
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+ print_cb(label, "Processor Identity 0x%08x\n", eax);
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+ break;
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default:
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return;
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}
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diff --git a/dmidecode.h b/dmidecode.h
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index 318cdc6..04c9c93 100644
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--- a/dmidecode.h
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+++ b/dmidecode.h
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@@ -40,6 +40,7 @@ enum cpuid_type
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cpuid_arm_soc_id,
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cpuid_x86_intel,
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cpuid_x86_amd,
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+ cpuid_loongarch,
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};
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extern enum cpuid_type cpuid_type;
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--
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2.27.0
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