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Add sw64 architecture Signed-off-by: wzx <wuzx1226@qq.com>
2022-11-02 17:32:19 +08:00
diff -Nuar ceph-16.2.7.org/cmake/modules/CheckCxxAtomic.cmake ceph-16.2.7.sw/cmake/modules/CheckCxxAtomic.cmake
--- ceph-16.2.7.org/cmake/modules/CheckCxxAtomic.cmake 2022-05-23 15:33:25.850000000 +0000
+++ ceph-16.2.7.sw/cmake/modules/CheckCxxAtomic.cmake 2022-05-26 10:42:55.850000000 +0000
@@ -11,7 +11,7 @@
#include <atomic>
#include <cstdint>
-#if __s390x__
+#if defined(__s390x__) || defined(__sw_64__)
// Boost needs 16-byte atomics for tagged pointers.
// These are implemented via inline instructions on the platform
// if 16-byte alignment can be proven, and are delegated to libatomic
diff -Nuar ceph-16.2.7.org/src/boost/boost/atomic/detail/caps_gcc_sw_64.hpp ceph-16.2.7.sw/src/boost/boost/atomic/detail/caps_gcc_sw_64.hpp
--- ceph-16.2.7.org/src/boost/boost/atomic/detail/caps_gcc_sw_64.hpp 1970-01-01 00:00:00.000000000 +0000
+++ ceph-16.2.7.sw/src/boost/boost/atomic/detail/caps_gcc_sw_64.hpp 2022-05-26 10:45:28.260000000 +0000
@@ -0,0 +1,34 @@
+/*
+ * Distributed under the Boost Software License, Version 1.0.
+ * (See accompanying file LICENSE_1_0.txt or copy at
+ * http://www.boost.org/LICENSE_1_0.txt)
+ *
+ * Copyright (c) 2009 Helge Bahmann
+ * Copyright (c) 2013 Tim Blechmann
+ * Copyright (c) 2014 Andrey Semashev
+ */
+/*!
+ * \file atomic/detail/caps_gcc_sw_64.hpp
+ *
+ * This header defines feature capabilities macros
+ */
+
+#ifndef BOOST_ATOMIC_DETAIL_CAPS_GCC_SW_64_HPP_INCLUDED_
+#define BOOST_ATOMIC_DETAIL_CAPS_GCC_SW_64_HPP_INCLUDED_
+
+#include <boost/atomic/detail/config.hpp>
+
+#ifdef BOOST_HAS_PRAGMA_ONCE
+#pragma once
+#endif
+
+//#define BOOST_ATOMIC_INT8_LOCK_FREE 2
+//#define BOOST_ATOMIC_INT16_LOCK_FREE 2
+#define BOOST_ATOMIC_INT32_LOCK_FREE 2
+#define BOOST_ATOMIC_INT64_LOCK_FREE 2
+#define BOOST_ATOMIC_POINTER_LOCK_FREE 2
+
+#define BOOST_ATOMIC_THREAD_FENCE 2
+#define BOOST_ATOMIC_SIGNAL_FENCE 2
+
+#endif // BOOST_ATOMIC_DETAIL_CAPS_GCC_SW_64_HPP_INCLUDED_
diff -Nuar ceph-16.2.7.org/src/boost/boost/atomic/detail/ops_gcc_sw_64.hpp ceph-16.2.7.sw/src/boost/boost/atomic/detail/ops_gcc_sw_64.hpp
--- ceph-16.2.7.org/src/boost/boost/atomic/detail/ops_gcc_sw_64.hpp 1970-01-01 00:00:00.000000000 +0000
+++ ceph-16.2.7.sw/src/boost/boost/atomic/detail/ops_gcc_sw_64.hpp 2022-05-26 10:46:00.910000000 +0000
@@ -0,0 +1,1039 @@
+/*
+ * Distributed under the Boost Software License, Version 1.0.
+ * (See accompanying file LICENSE_1_0.txt or copy at
+ * http://www.boost.org/LICENSE_1_0.txt)
+ *
+ * Copyright (c) 2009 Helge Bahmann
+ * Copyright (c) 2013 Tim Blechmann
+ * Copyright (c) 2014 Andrey Semashev
+ */
+/*!
+ * \file atomic/detail/ops_gcc_sw_64.hpp
+ *
+ * This header contains implementation of the \c core_arch_operations template.
+ */
+
+#ifndef BOOST_ATOMIC_DETAIL_OPS_GCC_SW_64_HPP_INCLUDED_
+#define BOOST_ATOMIC_DETAIL_OPS_GCC_SW_64_HPP_INCLUDED_
+
+#include <cstddef>
+#include <boost/memory_order.hpp>
+#include <boost/atomic/detail/config.hpp>
+#include <boost/atomic/detail/storage_traits.hpp>
+#include <boost/atomic/detail/operations_fwd.hpp>
+#include <boost/atomic/capabilities.hpp>
+
+#ifdef BOOST_HAS_PRAGMA_ONCE
+#pragma once
+#endif
+
+namespace boost {
+namespace atomics {
+namespace detail {
+
+/*
+ Refer to http://h71000.www7.hp.com/doc/82final/5601/5601pro_004.html
+ (HP OpenVMS systems documentation) and the Sw_64 Architecture Reference Manual.
+ */
+
+/*
+ NB: The most natural thing would be to write the increment/decrement
+ operators along the following lines:
+
+ __asm__ __volatile__
+ (
+ "1: ldl_l %0,%1 \n"
+ "addl %0,1,%0 \n"
+ "stl_c %0,%1 \n"
+ "beq %0,1b\n"
+ : "=&b" (tmp)
+ : "m" (value)
+ : "cc"
+ );
+
+ However according to the comments on the HP website and matching
+ comments in the Linux kernel sources this defies branch prediction,
+ as the cpu assumes that backward branches are always taken; so
+ instead copy the trick from the Linux kernel, introduce a forward
+ branch and back again.
+
+ I have, however, had a hard time measuring the difference between
+ the two versions in microbenchmarks -- I am leaving it in nevertheless
+ as it apparently does not hurt either.
+*/
+
+struct gcc_sw_64_operations_base
+{
+ static BOOST_CONSTEXPR_OR_CONST bool full_cas_based = false;
+ static BOOST_CONSTEXPR_OR_CONST bool is_always_lock_free = true;
+
+ static BOOST_FORCEINLINE void fence_before(memory_order order) BOOST_NOEXCEPT
+ {
+ if ((static_cast< unsigned int >(order) & static_cast< unsigned int >(memory_order_release)) != 0u)
+ __asm__ __volatile__ ("memb" ::: "memory");
+ }
+
+ static BOOST_FORCEINLINE void fence_after(memory_order order) BOOST_NOEXCEPT
+ {
+ if ((static_cast< unsigned int >(order) & (static_cast< unsigned int >(memory_order_consume) | static_cast< unsigned int >(memory_order_acquire))) != 0u)
+ __asm__ __volatile__ ("memb" ::: "memory");
+ }
+
+ static BOOST_FORCEINLINE void fence_after_store(memory_order order) BOOST_NOEXCEPT
+ {
+ if (order == memory_order_seq_cst)
+ __asm__ __volatile__ ("memb" ::: "memory");
+ }
+};
+
+
+template< bool Signed >
+struct operations< 4u, Signe > :
+ public gcc_sw_64_operations_base
+{
+ typedef typename storage_traits< 4u >::type storage_type;
+
+ static BOOST_CONSTEXPR_OR_CONST std::size_t storage_size = 4u;
+ static BOOST_CONSTEXPR_OR_CONST std::size_t storage_alignment = 4u;
+ static BOOST_CONSTEXPR_OR_CONST bool is_signed = Signed;
+
+ static BOOST_FORCEINLINE void store(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
+ {
+ fence_before(order);
+ storage = v;
+ fence_after_store(order);
+ }
+
+ static BOOST_FORCEINLINE storage_type load(storage_type const volatile& storage, memory_order order) BOOST_NOEXCEPT
+ {
+ storage_type v = storage;
+ fence_after(order);
+ return v;
+ }
+
+ static BOOST_FORCEINLINE storage_type exchange(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
+ {
+ storage_type original, tmp;
+ storage_type tmp1, tmp2;
+ fence_before(order);
+ __asm__ __volatile__
+ (
+ "1:\n\t"
+ "ldi %2,%4\n\t"
+ "ldi %3,1\n\t"
+ "mov %5, %1\n\t"
+ "lldw %0, 0(%2)\n\t"
+ "wr_f %3\n\t"
+ "lstw %1, 0(%2)\n\t"
+ "rd_f %1\n\t"
+ "beq %1, 2f\n\t"
+
+ ".subsection 2\n\t"
+ "2: br 1b\n\t"
+ ".previous\n\t"
+
+ : "=&r" (original), // %0
+ "=&r" (tmp), // %1
+ "=&r" (tmp1), // %2
+ "=&r" (tmp2) // %3
+ : "m" (storage), // %4
+ "r" (v) // %5
+ : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC
+ );
+ fence_after(order);
+ return original;
+ }
+
+ static BOOST_FORCEINLINE bool compare_exchange_weak(
+ storage_type volatile& storage, storage_type& expected, storage_type desired, memory_order success_order, memory_order failure_order) BOOST_NOEXCEPT
+ {
+ fence_before(success_order);
+ int success;
+ storage_type current;
+ storage_type tmp1,tmp2;
+ __asm__ __volatile__
+ (
+ "1:\n\t"
+ "ldi %4,%6\n\t"
+ "lldw %2, 0(%4)\n\t" // current = *(&storage)
+ "cmpeq %2, %0, %5\n\t" // success = current == expected
+ "wr_f %5\n\t" // success = current == expected
+ "mov %2, %0\n\t" // expected = current
+ "lstw %1, 0(%4)\n\t" // storage = desired; desired = store succeeded
+ "rd_f %1\n\t" // storage = desired; desired = store succeeded
+ "beq %5, 2f\n\t" // if (success == 0) goto end
+ "mov %1, %3\n\t" // success = desired
+ "2:\n\t"
+ : "+r" (expected), // %0
+ "+r" (desired), // %1
+ "=&r" (current), // %2
+ "=&r" (success), // %3
+ "=&r" (tmp1), // %4
+ "=&r" (tmp2) // %5
+ : "m" (storage) // %6
+ : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC
+ );
+ if (success)
+ fence_after(success_order);
+ else
+ fence_after(failure_order);
+ return !!success;
+ }
+
+ static BOOST_FORCEINLINE bool compare_exchange_strong(
+ storage_type volatile& storage, storage_type& expected, storage_type desired, memory_order success_order, memory_order failure_order) BOOST_NOEXCEPT
+ {
+ int success;
+ storage_type current, tmp;
+ storage_type tmp1,tmp2;
+ fence_before(success_order);
+ __asm__ __volatile__
+ (
+ "1:\n\t"
+ "ldi %4,%6\n\t"
+ "mov %7, %1\n\t" // tmp = desired
+ "lldw %2, 0(%4)\n\t" // current = *(&storage)
+ "cmpeq %2, %0, %5\n\t" // success = current == expected
+ "wr_f %5\n\t" // success = current == expected
+ "mov %2, %0\n\t" // expected = current
+ "lstw %1, 0(%4)\n\t" // storage = tmp; tmp = store succeeded
+ "rd_f %1\n\t" // storage = tmp; tmp = store succeeded
+ "beq %5, 2f\n\t" // if (success == 0) goto end
+ "beq %1, 3f\n\t" // if (tmp == 0) goto retry
+ "mov %1, %3\n\t" // success = tmp
+ "2:\n\t"
+
+ ".subsection 2\n\t"
+ "3: br 1b\n\t"
+ ".previous\n\t"
+
+ : "+r" (expected), // %0
+ "=&r" (tmp), // %1
+ "=&r" (current), // %2
+ "=&r" (success), // %3
+ "=&r" (tmp1), // %4
+ "=&r" (tmp2) // %5
+ : "m" (storage), // %6
+ "r" (desired) // %7
+ : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC
+ );
+ if (success)
+ fence_after(success_order);
+ else
+ fence_after(failure_order);
+ return !!success;
+ }
+
+ static BOOST_FORCEINLINE storage_type fetch_add(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
+ {
+ storage_type original, modified;
+ storage_type tmp1, tmp2;
+ fence_before(order);
+ __asm__ __volatile__
+ (
+ "1:\n\t"
+ "ldi %2,%4\n\t"
+ "ldi %3,1\n\t"
+ "lldw %0, 0(%2)\n\t"
+ "wr_f %3\n\t"
+ "addw %0, %5, %1\n\t"
+ "lstw %1, 0(%2)\n\t"
+ "rd_f %1\n\t"
+ "beq %1, 2f\n\t"
+
+ ".subsection 2\n\t"
+ "2: br 1b\n\t"
+ ".previous\n\t"
+
+ : "=&r" (original), // %0
+ "=&r" (modified), // %1
+ "=&r" (tmp1), // %2
+ "=&r" (tmp2) // %3
+ : "m" (storage), // %4
+ "r" (v) // %5
+ : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC
+ );
+ fence_after(order);
+ return original;
+ }
+
+ static BOOST_FORCEINLINE storage_type fetch_sub(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
+ {
+ storage_type original, modified;
+ storage_type tmp1, tmp2;
+ fence_before(order);
+ __asm__ __volatile__
+ (
+ "1:\n\t"
+ "ldi %2,%4\n\t"
+ "ldi %3,1\n\t"
+ "lldw %0, 0(%2)\n\t"
+ "wr_f %3\n\t"
+ "subw %0, %5, %1\n\t"
+ "lstw %1, 0(%2)\n\t"
+ "rd_f %1\n\t"
+ "beq %1, 2f\n\t"
+
+ ".subsection 2\n\t"
+ "2: br 1b\n\t"
+ ".previous\n\t"
+
+ : "=&r" (original), // %0
+ "=&r" (modified), // %1
+ "=&r" (tmp1), // %2
+ "=&r" (tmp2) // %3
+ : "m" (storage), // %4
+ "r" (v) // %5
+ : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC
+ );
+ fence_after(order);
+ return original;
+ }
+
+ static BOOST_FORCEINLINE storage_type fetch_and(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
+ {
+ storage_type original, modified;
+ storage_type tmp1,tmp2;
+ fence_before(order);
+ __asm__ __volatile__
+ (
+ "1:\n\t"
+ "ldi %2,%4\n\t"
+ "ldi %3,1\n\t"
+ "lldw %0, 0(%2)\n\t"
+ "wr_f %3\n\t"
+ "and %0, %5, %1\n\t"
+ "lstw %1, 0(%2)\n\t"
+ "rd_f %1\n\t"
+ "beq %1, 2f\n\t"
+
+ ".subsection 2\n\t"
+ "2: br 1b\n\t"
+ ".previous\n\t"
+
+ : "=&r" (original), // %0
+ "=&r" (modified), // %1
+ "=&r" (tmp1), // %2
+ "=&r" (tmp2) // %3
+ : "m" (storage), // %4
+ "r" (v) // %5
+ : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC
+ );
+ fence_after(order);
+ return original;
+ }
+
+ static BOOST_FORCEINLINE storage_type fetch_or(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
+ {
+ storage_type original, modified;
+ storage_type tmp1,tmp2;
+ fence_before(order);
+ __asm__ __volatile__
+ (
+ "1:\n"
+ "ldi %2,%4\n"
+ "ldi %3,1\n"
+ "lldw %0, 0(%2)\n"
+ "wr_f %? \n"
+ "bis %0, %5, %1\n"
+ "lstw %1, 0(%2)\n"
+ "rd_f %1 \n"
+ "beq %1, 2f\n"
+
+ ".subsection 2\n\t"
+ "2: br 1b\n\t"
+ ".previous\n\t"
+
+ : "=&r" (original), // %0
+ "=&r" (modified), // %1
+ "=&r" (tmp1), // %2
+ "=&r" (tmp2) // %3
+ : "m" (storage), // %4
+ "r" (v) // %5
+ : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC
+ );
+ fence_after(order);
+ return original;
+ }
+
+ static BOOST_FORCEINLINE storage_type fetch_xor(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
+ {
+ storage_type original, modified;
+ storage_type tmp1, tmp2;
+ fence_before(order);
+ __asm__ __volatile__
+ (
+ "1:\n"
+ "ldi %2,%4\n"
+ "ldi %3,1\n"
+ "lldw %0, 0(%2)\n"
+ "wr_f %3 \n"
+ "xor %0, %5, %1\n"
+ "lstw %1, 0(%2)\n"
+ "rd_f %1 \n"
+ "beq %1, 2f\n"
+
+ ".subsection 2\n\t"
+ "2: br 1b\n\t"
+ ".previous\n\t"
+
+ : "=&r" (original), // %0
+ "=&r" (modified), // %1
+ "=&r" (tmp1), // %2
+ "=&r" (tmp2) // %3
+ : "m" (storage), // %4
+ "r" (v) // %5
+ : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC
+ );
+ fence_after(order);
+ return original;
+ }
+
+ static BOOST_FORCEINLINE bool test_and_set(storage_type volatile& storage, memory_order order) BOOST_NOEXCEPT
+ {
+ return !!exchange(storage, (storage_type)1, order);
+ }
+
+ static BOOST_FORCEINLINE void clear(storage_type volatile& storage, memory_order order) BOOST_NOEXCEPT
+ {
+ store(storage, 0, order);
+ }
+};
+
+
+template< >
+struct operations< 1u, false > :
+ public operations< 4u, false >
+{
+ typedef operations< 4u, false > base_type;
+ typedef typename base_type::storage_type storage_type;
+
+ static BOOST_FORCEINLINE storage_type fetch_add(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
+ {
+ storage_type original, modified;
+ storage_type tmp1, tmp2;
+ base_type::fence_before(order);
+ __asm__ __volatile__
+ (
+ "1:\n"
+ "ldi %2,%4\n"
+ "ldi %3,1\n"
+ "lldw %0, 0(%2)\n"
+ "wr_f %3 \n"
+ "addw %0, %5, %1\n"
+ "zapnot %1, #1, %1\n"
+ "lstw %1, 0(%2)\n"
+ "rd_f %1 \n"
+ "beq %1, 2f\n"
+
+ ".subsection 2\n\t"
+ "2: br 1b\n\t"
+ ".previous\n\t"
+
+ : "=&r" (original), // %0
+ "=&r" (modified), // %1
+ "=&r" (tmp1), // %2
+ "=&r" (tmp2) // %3
+ : "m" (storage), // %4
+ "r" (v) // %5
+ : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC
+ );
+ base_type::fence_after(order);
+ return original;
+ }
+
+ static BOOST_FORCEINLINE storage_type fetch_sub(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
+ {
+ storage_type original, modified;
+ storage_type tmp1, tmp2;
+ base_type::fence_before(order);
+ __asm__ __volatile__
+ (
+ "1:\n"
+ "ldi %2,%4\n"
+ "ldi %3,1\n"
+ "lldw %0, 0(%2)\n"
+ "wr_f %3 \n"
+ "subw %0, %5, %1\n"
+ "zapnot %1, #1, %1\n"
+ "lstw %1, 0(%2)\n"
+ "rd_f %1 \n"
+ "beq %1, 2f\n"
+
+ ".subsection 2\n\t"
+ "2: br 1b\n\t"
+ ".previous\n\t"
+
+ : "=&r" (original), // %0
+ "=&r" (modified), // %1
+ "=&r" (tmp1), // %2
+ "=&r" (tmp2) // %3
+ : "m" (storage), // %4
+ "r" (v) // %5
+ : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC
+ );
+ base_type::fence_after(order);
+ return original;
+ }
+};
+
+template< >
+struct operations< 1u, true > :
+ public operations< 4u, true >
+{
+ typedef operations< 4u, true > base_type;
+ typedef typename base_type::storage_type storage_type;
+
+ static BOOST_FORCEINLINE storage_type fetch_add(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
+ {
+ storage_type original, modified;
+ storage_type tmp1,tmp2;
+ base_type::fence_before(order);
+ __asm__ __volatile__
+ (
+ "1:\n"
+ "ldi %2,%4\n"
+ "ldi %3,1\n"
+ "lldw %0, 0(%2)\n"
+ "wr_f %3 \n"
+ "addw %0, %5, %1\n"
+ "sextb %1, %1\n"
+ "lstw %1, 0(%2)\n"
+ "rd_f %1 \n"
+ "beq %1, 2f\n"
+
+ ".subsection 2\n\t"
+ "2: br 1b\n\t"
+ ".previous\n\t"
+
+ : "=&r" (original), // %0
+ "=&r" (modified), // %1
+ "=&r" (tmp1), // %2
+ "=&r" (tmp2) // %3
+ : "m" (storage), // %4
+ "r" (v) // %5
+ : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC
+ );
+ base_type::fence_after(order);
+ return original;
+ }
+
+ static BOOST_FORCEINLINE storage_type fetch_sub(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
+ {
+ storage_type original, modified;
+ storage_type tmp1,tmp2;
+ base_type::fence_before(order);
+ __asm__ __volatile__
+ (
+ "1:\n"
+ "ldi %2,%4\n"
+ "ldi %3,1\n"
+ "lldw %0, 0(%2)\n"
+ "wr_f %3 \n"
+ "subw %0, %5, %1\n"
+ "sextb %1, %1\n"
+ "lstw %1, 0(%2)\n"
+ "rd_f %1 \n"
+ "beq %1, 2f\n"
+
+ ".subsection 2\n\t"
+ "2: br 1b\n\t"
+ ".previous\n\t"
+
+ : "=&r" (original), // %0
+ "=&r" (modified), // %1
+ "=&r" (tmp1), // %2
+ "=&r" (tmp2) // %3
+ : "m" (storage), // %4
+ "r" (v) // %5
+ : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC
+ );
+ base_type::fence_after(order);
+ return original;
+ }
+};
+
+
+template< >
+struct operations< 2u, false > :
+ public operations< 4u, false >
+{
+ typedef operations< 4u, false > base_type;
+ typedef typename base_type::storage_type storage_type;
+
+ static BOOST_FORCEINLINE storage_type fetch_add(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
+ {
+ storage_type original, modified;
+ storage_type tmp1,tmp2;
+ base_type::fence_before(order);
+ __asm__ __volatile__
+ (
+ "1:\n"
+ "ldi %2,%4\n"
+ "ldi %3\n"
+ "lldw %0, 0(%2)\n"
+ "wr_f %3 \n"
+ "addw %0, %5, %1\n"
+ "zapnot %1, #3, %1\n"
+ "lstw %1, 0(%2)\n"
+ "rd_f %1 \n"
+ "beq %1, 2f\n"
+
+ ".subsection 2\n\t"
+ "2: br 1b\n\t"
+ ".previous\n\t"
+
+ : "=&r" (original), // %0
+ "=&r" (modified), // %1
+ "=&r" (tmp1), // %2
+ "=&r" (tmp2) // %3
+ : "m" (storage), // %4
+ "r" (v) // %5
+ : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC
+ );
+ base_type::fence_after(order);
+ return original;
+ }
+
+ static BOOST_FORCEINLINE storage_type fetch_sub(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
+ {
+ storage_type original, modified;
+ storage_type tmp1,tmp2;
+ base_type::fence_before(order);
+ __asm__ __volatile__
+ (
+ "1:\n"
+ "ldi %2,%4\n"
+ "ldi %3,1\n"
+ "lldw %0, 0(%2)\n"
+ "wr_f %3 \n"
+ "subw %0, %5, %1\n"
+ "zapnot %1, #3, %1\n"
+ "lstw %1, %2\n"
+ "rd_f %1 \n"
+ "beq %1, 2f\n"
+
+ ".subsection 2\n\t"
+ "2: br 1b\n\t"
+ ".previous\n\t"
+
+ : "=&r" (original), // %0
+ "=&r" (modified), // %1
+ "=&r" (tmp1), // %2
+ "=&r" (tmp2) // %3
+ : "m" (storage), // %4
+ "r" (v) // %5
+ : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC
+ );
+ base_type::fence_after(order);
+ return original;
+ }
+};
+
+template< >
+struct operations< 2u, true > :
+ public operations< 4u, true >
+{
+ typedef operations< 4u, true > base_type;
+ typedef typename base_type::storage_type storage_type;
+
+ static BOOST_FORCEINLINE storage_type fetch_add(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
+ {
+ storage_type original, modified;
+ storage_type tmp1,tmp2;
+ base_type::fence_before(order);
+ __asm__ __volatile__
+ (
+ "ldi %2,%4\n"
+ "ldi %3,1\n"
+ "lldw %0, 0(%2)\n"
+ "wr_f %3 \n"
+ "addw %0, %5, %1\n"
+ "sexth %1, %1\n"
+ "lstw %1, 0(%2)\n"
+ "rd_f %1 \n"
+ "beq %1, 2f\n"
+
+ ".subsection 2\n\t"
+ "2: br 1b\n\t"
+ ".previous\n\t"
+
+ : "=&r" (original), // %0
+ "=&r" (modified), // %1
+ "=&r" (tmp1), // %2
+ "=&r" (tmp2) // %3
+ : "m" (storage), // %4
+ "r" (v) // %5
+ : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC
+ );
+ base_type::fence_after(order);
+ return original;
+ }
+
+ static BOOST_FORCEINLINE storage_type fetch_sub(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
+ {
+ storage_type original, modified;
+ storage_type tmp1,tmp2;
+ base_type::fence_before(order);
+ __asm__ __volatile__
+ (
+ "1:\n"
+ "ldi %2,%4\n"
+ "ldi %3,1\n"
+ "lldw %0, 0(%2)\n"
+ "wr_f %3 \n"
+ "subw %0, %5, %1\n"
+ "sexth %1, %1\n"
+ "lstw %1, 0(%2)\n"
+ "rd_f %1 \n"
+ "beq %1, 2f\n"
+
+ ".subsection 2\n\t"
+ "2: br 1b\n\t"
+ ".previous\n\t"
+
+ : "=&r" (original), // %0
+ "=&r" (modified), // %1
+ "=&r" (tmp1), // %2
+ "=&r" (tmp2) // %3
+ : "m" (storage), // %4
+ "r" (v) // %5
+ : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC
+ );
+ base_type::fence_after(order);
+ return original;
+ }
+};
+
+
+template< bool Signed >
+struct operations< 8u, Signed > :
+ public gcc_sw_64_operations_base
+{
+ typedef typename storage_traits< 8u >::type storage_type;
+
+ static BOOST_CONSTEXPR_OR_CONST std::size_t storage_size = 8u;
+ static BOOST_CONSTEXPR_OR_CONST std::size_t storage_alignment = 8u;
+ static BOOST_CONSTEXPR_OR_CONST bool is_signed = Signed;
+
+ static BOOST_FORCEINLINE void store(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
+ {
+ fence_before(order);
+ storage = v;
+ fence_after_store(order);
+ }
+
+ static BOOST_FORCEINLINE storage_type load(storage_type const volatile& storage, memory_order order) BOOST_NOEXCEPT
+ {
+ storage_type v = storage;
+ fence_after(order);
+ return v;
+ }
+
+ static BOOST_FORCEINLINE storage_type exchange(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
+ {
+ storage_type original, tmp;
+ storage_type tmp1,tmp2;
+ fence_before(order);
+ __asm__ __volatile__
+ (
+ "1:\n"
+ "ldi %2,%4\n"
+ "ldi %3,1\n"
+ "mov %5, %1\n"
+ "lldl %0, 0(%2)\n"
+ "wr_f %3 \n"
+ "lstl %1, 0(%2)\n"
+ "rd_f %1 \n"
+ "beq %1, 2f\n"
+
+ ".subsection 2\n\t"
+ "2: br 1b\n\t"
+ ".previous\n\t"
+
+ : "=&r" (original), // %0
+ "=&r" (tmp), // %1
+ "=&r" (tmp1), // %2
+ "=&r" (tmp2) // %3
+ : "m" (storage), // %4
+ "r" (v) // %5
+ : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC
+ );
+ fence_after(order);
+ return original;
+ }
+
+ static BOOST_FORCEINLINE bool compare_exchange_weak(
+ storage_type volatile& storage, storage_type& expected, storage_type desired, memory_order success_order, memory_order failure_order) BOOST_NOEXCEPT
+ {
+ fence_before(success_order);
+ int success;
+ storage_type current;
+ storage_type tmp1,tmp2;
+ __asm__ __volatile__
+ (
+ "1:\n"
+ "ldi %4,%6\n"
+ "lldl %2, 0(%4)\n" // current = *(&storage)
+ "cmpeq %2, %0, %5\n" // success = current == expected
+ "wr_f %5 \n"
+ "mov %2, %0\n" // expected = current
+ "lstl %1, 0(%4)\n" // storage = desired; desired = store succeeded
+ "rd_f %1 \n"
+ "beq %5, 2f\n" // if (success == 0) goto end
+ "mov %1, %3\n" // success = desired
+ "2:\n\t"
+ : "+r" (expected), // %0
+ "+r" (desired), // %1
+ "=&r" (current), // %2
+ "=&r" (success), // %3
+ "=&r" (tmp1), // %4
+ "=&r" (tmp2) // %5
+ : "m" (storage) // %6
+ : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC
+ );
+ if (success)
+ fence_after(success_order);
+ else
+ fence_after(failure_order);
+ return !!success;
+ }
+
+ static BOOST_FORCEINLINE bool compare_exchange_strong(
+ storage_type volatile& storage, storage_type& expected, storage_type desired, memory_order success_order, memory_order failure_order) BOOST_NOEXCEPT
+ {
+ int success;
+ storage_type current, tmp;
+ storage_type tmp1,tmp2;
+ fence_before(success_order);
+ __asm__ __volatile__
+ (
+ "1:\n"
+ "ldi %4,%6\n"
+ "mov %7, %1\n" // tmp = desired
+ "lldl %2, 0(%4)\n" // current = *(&storage)
+ "cmpeq %2, %0, %5\n" // success = current == expected
+ "wr_f %5 \n"
+ "mov %2, %0\n" // expected = current
+ "lstl %1, 0(%4)\n" // storage = tmp; tmp = store succeeded
+ "rd_f %1 \n"
+ "beq %5, 2f\n" // if (success == 0) goto end
+ "beq %1, 3f\n" // if (tmp == 0) goto retry
+ "mov %1, %3\n" // success = tmp
+ "2:\n\t"
+
+ ".subsection 2\n\t"
+ "3: br 1b\n\t"
+ ".previous\n\t"
+
+ : "+r" (expected), // %0
+ "=&r" (tmp), // %1
+ "=&r" (current), // %2
+ "=&r" (success), // %3
+ "=&r" (tmp1), // %4
+ "=&r" (tmp2) // %5
+ : "m" (storage), // %6
+ "r" (desired) // %7
+ : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC
+ );
+ if (success)
+ fence_after(success_order);
+ else
+ fence_after(failure_order);
+ return !!success;
+ }
+
+ static BOOST_FORCEINLINE storage_type fetch_add(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
+ {
+ storage_type original, modified;
+ storage_type tmp1, tmp2;
+ fence_before(order);
+ __asm__ __volatile__
+ (
+ "1:\n"
+ "ldi %2,%4\n"
+ "ldi %3,1\n"
+ "lldl %0, 0(%2)\n"
+ "wr_f %3 \n"
+ "addl %0, %5, %1\n"
+ "lstl %1, 0(%2)\n"
+ "rd_f %1 \n"
+ "beq %1, 2f\n"
+
+ ".subsection 2\n\t"
+ "2: br 1b\n\t"
+ ".previous\n\t"
+
+ : "=&r" (original), // %0
+ "=&r" (modified), // %1
+ "=&r" (tmp1), // %2
+ "=&r" (tmp2) // %3
+ : "m" (storage), // %4
+ "r" (v) // %5
+ : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC
+ );
+ fence_after(order);
+ return original;
+ }
+
+ static BOOST_FORCEINLINE storage_type fetch_sub(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
+ {
+ storage_type original, modified;
+ storage_type tmp1,tmp2;
+ fence_before(order);
+ __asm__ __volatile__
+ (
+ "1:\n"
+ "ldi %2,%4\n"
+ "ldi %3,1\n"
+ "lldl %0, 0(%2)\n"
+ "wr_f %3 \n"
+ "subl %0, %5, %1\n"
+ "lstl %1, 0(%2)\n"
+ "rd_f %1 \n"
+ "beq %1, 2f\n"
+
+ ".subsection 2\n\t"
+ "2: br 1b\n\t"
+ ".previous\n\t"
+
+ : "=&r" (original), // %0
+ "=&r" (modified), // %1
+ "=&r" (tmp1), // %2
+ "=&r" (tmp2) // %3
+ : "m" (storage), // %4
+ "r" (v) // %5
+ : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC
+ );
+ fence_after(order);
+ return original;
+ }
+
+ static BOOST_FORCEINLINE storage_type fetch_and(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
+ {
+ storage_type original, modified;
+ storage_type tmp1,tmp2;
+ fence_before(order);
+ __asm__ __volatile__
+ (
+ "1:\n"
+ "ldi %2,%4\n"
+ "ldi %3,1\n"
+ "lldl %0, 0(%2)\n"
+ "wr_f %3 \n"
+ "and %0, %5, %1\n"
+ "lstl %1, 0(%2)\n"
+ "rd_f %1 \n"
+ "beq %1, 2f\n"
+
+ ".subsection 2\n\t"
+ "2: br 1b\n\t"
+ ".previous\n\t"
+
+ : "=&r" (original), // %0
+ "=&r" (modified), // %1
+ "=&r" (tmp1), // %2
+ "=&r" (tmp2) // %3
+ : "m" (storage), // %4
+ "r" (v) // %5
+ : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC
+ );
+ fence_after(order);
+ return original;
+ }
+
+ static BOOST_FORCEINLINE storage_type fetch_or(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
+ {
+ storage_type original, modified;
+ storage_type tmp1,tmp2;
+ fence_before(order);
+ __asm__ __volatile__
+ (
+ "1:\n"
+ "ldi %2,%4\n"
+ "ldi %3,1\n"
+ "lldl %0, 0(%2)\n"
+ "wr_f %3 \n"
+ "bis %0, %5, %1\n"
+ "lstl %1, 0(%2)\n"
+ "rd_f %1 \n"
+ "beq %1, 2f\n"
+
+ ".subsection 2\n\t"
+ "2: br 1b\n\t"
+ ".previous\n\t"
+
+ : "=&r" (original), // %0
+ "=&r" (modified), // %1
+ "=&r" (tmp1), // %2
+ "=&r" (tmp2) // %3
+ : "m" (storage), // %4
+ "r" (v) // %5
+ : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC
+ );
+ fence_after(order);
+ return original;
+ }
+
+ static BOOST_FORCEINLINE storage_type fetch_xor(storage_type volatile& storage, storage_type v, memory_order order) BOOST_NOEXCEPT
+ {
+ storage_type original, modified;
+ storage_type tmp1,tmp2;
+ fence_before(order);
+ __asm__ __volatile__
+ (
+ "1:\n"
+ "ldi %2,%4\n"
+ "ldi %3,1\n"
+ "lldl %0, 0(%2)\n"
+ "wr_f %3 \n"
+ "xor %0, %5, %1\n"
+ "lstl %1, 0(%2)\n"
+ "rd_f %1 \n"
+ "beq %1, 2f\n"
+
+ ".subsection 2\n\t"
+ "2: br 1b\n\t"
+ ".previous\n\t"
+
+ : "=&r" (original), // %0
+ "=&r" (modified), // %1
+ "=&r" (tmp1), // %2
+ "=&r" (tmp2) // %3
+ : "m" (storage), // %4
+ "r" (v) // %5
+ : BOOST_ATOMIC_DETAIL_ASM_CLOBBER_CC
+ );
+ fence_after(order);
+ return original;
+ }
+
+ static BOOST_FORCEINLINE bool test_and_set(storage_type volatile& storage, memory_order order) BOOST_NOEXCEPT
+ {
+ return !!exchange(storage, (storage_type)1, order);
+ }
+
+ static BOOST_FORCEINLINE void clear(storage_type volatile& storage, memory_order order) BOOST_NOEXCEPT
+ {
+ store(storage, (storage_type)0, order);
+ }
+};
+
+BOOST_FORCEINLINE void thread_fence(memory_order order) BOOST_NOEXCEPT
+{
+ if (order != memory_order_relaxed)
+ __asm__ __volatile__ ("memb" ::: "memory");
+}
+
+BOOST_FORCEINLINE void signal_fence(memory_order order) BOOST_NOEXCEPT
+{
+ if (order != memory_order_relaxed)
+ __asm__ __volatile__ ("" ::: "memory");
+}
+
+} // namespace detail
+} // namespace atomics
+} // namespace boost
+
+
+#endif // BOOST_ATOMIC_DETAIL_OPS_GCC_SW_64_HPP_INCLUDED_
diff -Nuar ceph-16.2.7.org/src/boost/boost/atomic/detail/platform.hpp ceph-16.2.7.sw/src/boost/boost/atomic/detail/platform.hpp
--- ceph-16.2.7.org/src/boost/boost/atomic/detail/platform.hpp 2022-05-23 15:33:13.990000000 +0000
+++ ceph-16.2.7.sw/src/boost/boost/atomic/detail/platform.hpp 2022-05-26 10:48:27.060000000 +0000
@@ -72,6 +72,10 @@
#define BOOST_ATOMIC_DETAIL_PLATFORM gcc_alpha
+#elif defined(__GNUC__) && defined(__sw_64__)
+
+#define BOOST_ATOMIC_DETAIL_PLATFORM gcc_sw_64
+
#elif defined(_MSC_VER) && (defined(_M_IX86) || defined(_M_X64))
#define BOOST_ATOMIC_DETAIL_PLATFORM msvc_x86
diff -Nuar ceph-16.2.7.org/src/boost/boost/numeric/interval/detail/sw_64_rounding_control.hpp ceph-16.2.7.sw/src/boost/boost/numeric/interval/detail/sw_64_rounding_control.hpp
--- ceph-16.2.7.org/src/boost/boost/numeric/interval/detail/sw_64_rounding_control.hpp 1970-01-01 00:00:00.000000000 +0000
+++ ceph-16.2.7.sw/src/boost/boost/numeric/interval/detail/sw_64_rounding_control.hpp 2022-05-26 10:49:09.580000000 +0000
@@ -0,0 +1,113 @@
+/* Boost interval/detail/sw_64_rounding_control.hpp file
+ *
+ * Copyright 2005 Felix Höfling, Guillaume Melquiond
+ *
+ * Distributed under the Boost Software License, Version 1.0.
+ * (See accompanying file LICENSE_1_0.txt or
+ * copy at http://www.boost.org/LICENSE_1_0.txt)
+ */
+
+#ifndef BOOST_NUMERIC_INTERVAL_DETAIL_SW_64_ROUNDING_CONTROL_HPP
+#define BOOST_NUMERIC_INTERVAL_DETAIL_SW_64_ROUNDING_CONTROL_HPP
+
+#if !defined(sw_64) && !defined(__sw_64__)
+#error This header only works on Sw_64 CPUs.
+#endif
+
+#if defined(__GNUC__) || defined(__digital__) || defined(__DECCXX)
+
+#include <float.h> // write_rnd() and read_rnd()
+
+namespace boost {
+namespace numeric {
+namespace interval_lib {
+
+namespace detail {
+#if defined(__GNUC__ )
+ typedef union {
+ ::boost::long_long_type imode;
+ double dmode;
+ } rounding_mode_struct;
+
+ // set bits 59-58 (DYN),
+ // clear all exception bits and disable overflow (51) and inexact exceptions (62)
+ static const rounding_mode_struct mode_upward = { 0x4C08000000000000LL };
+ static const rounding_mode_struct mode_downward = { 0x4408000000000000LL };
+ static const rounding_mode_struct mode_to_nearest = { 0x4808000000000000LL };
+ static const rounding_mode_struct mode_toward_zero = { 0x4008000000000000LL };
+
+ struct sw_64_rounding_control
+ {
+ typedef double rounding_mode;
+
+ static void set_rounding_mode(const rounding_mode mode)
+ { __asm__ __volatile__ ("wfpcr %0" : : "f"(mode)); }
+
+ static void get_rounding_mode(rounding_mode& mode)
+ { __asm__ __volatile__ ("rfpcr %0" : "=f"(mode)); }
+
+ static void downward() { set_rounding_mode(mode_downward.dmode); }
+ static void upward() { set_rounding_mode(mode_upward.dmode); }
+ static void to_nearest() { set_rounding_mode(mode_to_nearest.dmode); }
+ static void toward_zero() { set_rounding_mode(mode_toward_zero.dmode); }
+ };
+#elif defined(__digital__) || defined(__DECCXX)
+
+#if defined(__DECCXX) && !(defined(__FLT_ROUNDS) && __FLT_ROUNDS == -1)
+#error Dynamic rounding mode not enabled. See cxx man page for details.
+#endif
+
+ struct sw_64_rounding_control
+ {
+ typedef unsigned int rounding_mode;
+
+ static void set_rounding_mode(const rounding_mode& mode) { write_rnd(mode); }
+ static void get_rounding_mode(rounding_mode& mode) { mode = read_rnd(); }
+
+ static void downward() { set_rounding_mode(FP_RND_RM); }
+ static void upward() { set_rounding_mode(FP_RND_RP); }
+ static void to_nearest() { set_rounding_mode(FP_RND_RN); }
+ static void toward_zero() { set_rounding_mode(FP_RND_RZ); }
+ };
+#endif
+} // namespace detail
+
+extern "C" {
+ float rintf(float);
+ double rint(double);
+ long double rintl(long double);
+}
+
+template<>
+struct rounding_control<float>:
+ detail::sw_64_rounding_control
+{
+ static float force_rounding(const float r)
+ { volatile float _r = r; return _r; }
+ static float to_int(const float& x) { return rintf(x); }
+};
+
+template<>
+struct rounding_control<double>:
+ detail::sw_64_rounding_control
+{
+ static const double & force_rounding(const double& r) { return r; }
+ static double to_int(const double& r) { return rint(r); }
+};
+
+template<>
+struct rounding_control<long double>:
+ detail::sw_64_rounding_control
+{
+ static const long double & force_rounding(const long double& r) { return r; }
+ static long double to_int(const long double& r) { return rintl(r); }
+};
+
+} // namespace interval_lib
+} // namespace numeric
+} // namespace boost
+
+#undef BOOST_NUMERIC_INTERVAL_NO_HARDWARE
+#endif
+
+#endif /* BOOST_NUMERIC_INTERVAL_DETAIL_SW_64_ROUNDING_CONTROL_HPP */
diff -Nuar ceph-16.2.7.org/src/boost/boost/numeric/interval/hw_rounding.hpp ceph-16.2.7.sw/src/boost/boost/numeric/interval/hw_rounding.hpp
--- ceph-16.2.7.org/src/boost/boost/numeric/interval/hw_rounding.hpp 2022-05-23 15:33:12.870000000 +0000
+++ ceph-16.2.7.sw/src/boost/boost/numeric/interval/hw_rounding.hpp 2022-05-26 10:51:06.540000000 +0000
@@ -29,6 +29,8 @@
# include <boost/numeric/interval/detail/sparc_rounding_control.hpp>
#elif defined(alpha) || defined(__alpha__)
# include <boost/numeric/interval/detail/alpha_rounding_control.hpp>
+#elif defined(sw_64) || defined(__sw_64__)
+# include <boost/numeric/interval/detail/sw_64_rounding_control.hpp>
#elif defined(ia64) || defined(__ia64) || defined(__ia64__)
# include <boost/numeric/interval/detail/ia64_rounding_control.hpp>
#endif
diff -Nuar ceph-16.2.7.org/src/boost/boost/predef/architecture/sw_64.h ceph-16.2.7.sw/src/boost/boost/predef/architecture/sw_64.h
--- ceph-16.2.7.org/src/boost/boost/predef/architecture/sw_64.h 1970-01-01 00:00:00.000000000 +0000
+++ ceph-16.2.7.sw/src/boost/boost/predef/architecture/sw_64.h 2022-05-26 10:52:11.260000000 +0000
@@ -0,0 +1,54 @@
+/*
+Copyright Rene Rivera 2008-2015
+Distributed under the Boost Software License, Version 1.0.
+(See accompanying file LICENSE_1_0.txt or copy at
+http://www.boost.org/LICENSE_1_0.txt)
+*/
+
+#ifndef BOOST_PREDEF_ARCHITECTURE_SW_64_H
+#define BOOST_PREDEF_ARCHITECTURE_SW_64_H
+
+#include <boost/predef/version_number.h>
+#include <boost/predef/make.h>
+
+/* tag::reference[]
+= `BOOST_ARCH_SW_64`
+
+http://en.wikipedia.org/wiki/DEC_Sw_64[DEC Sw_64] architecture.
+
+[options="header"]
+|===
+| {predef_symbol} | {predef_version}
+| `+__sw_64__+` | {predef_detection}
+| `+__sw_64+` | {predef_detection}
+| `+_M_SW_64+` | {predef_detection}
+
+| `+__sw_64_ev6__+` | 6.0.0
+|===
+*/ // end::reference[]
+
+#define BOOST_ARCH_SW_64 BOOST_VERSION_NUMBER_NOT_AVAILABLE
+
+#if defined(__sw_64__) || defined(__sw_64) || \
+ defined(_M_SW_64)
+# undef BOOST_ARCH_SW_64
+# if !defined(BOOST_ARCH_SW_64) && defined(__sw_64_sw6b__)
+# define BOOST_ARCH_SW_64 BOOST_VERSION_NUMBER(6,0,0)
+# endif
+#endif
+
+#if BOOST_ARCH_SW_64
+# define BOOST_ARCH_SW_64_AVAILABLE
+#endif
+
+#if BOOST_ARCH_SW_64
+# undef BOOST_ARCH_WORD_BITS_64
+# define BOOST_ARCH_WORD_BITS_64 BOOST_VERSION_NUMBER_AVAILABLE
+#endif
+
+#define BOOST_ARCH_SW_64_NAME "DEC Sw_64"
+
+#endif
+
+#include <boost/predef/detail/test.h>
+BOOST_PREDEF_DECLARE_TEST(BOOST_ARCH_SW_64,BOOST_ARCH_SW_64_NAME)
diff -Nuar ceph-16.2.7.org/src/boost/boost/predef/architecture.h ceph-16.2.7.sw/src/boost/boost/predef/architecture.h
--- ceph-16.2.7.org/src/boost/boost/predef/architecture.h 2022-05-23 15:33:13.820000000 +0000
+++ ceph-16.2.7.sw/src/boost/boost/predef/architecture.h 2022-05-26 10:52:46.950000000 +0000
@@ -11,6 +11,7 @@
#endif
#include <boost/predef/architecture/alpha.h>
+#include <boost/predef/architecture/sw_64.h>
#include <boost/predef/architecture/arm.h>
#include <boost/predef/architecture/blackfin.h>
#include <boost/predef/architecture/convex.h>
diff -Nuar ceph-16.2.7.org/src/boost/boost/units/systems/si/codata/atomic-nuclear_constants.hpp ceph-16.2.7.sw/src/boost/boost/units/systems/si/codata/atomic-nuclear_constants.hpp
--- ceph-16.2.7.org/src/boost/boost/units/systems/si/codata/atomic-nuclear_constants.hpp 2022-05-23 15:33:12.700000000 +0000
+++ ceph-16.2.7.sw/src/boost/boost/units/systems/si/codata/atomic-nuclear_constants.hpp 2022-05-26 10:53:20.320000000 +0000
@@ -12,6 +12,7 @@
#define BOOST_UNITS_CODATA_ATOMIC_AND_NUCLEAR_CONSTANTS_HPP
#include <boost/units/systems/si/codata/alpha_constants.hpp>
+#include <boost/units/systems/si/codata/sw_64_constants.hpp>
#include <boost/units/systems/si/codata/deuteron_constants.hpp>
#include <boost/units/systems/si/codata/electron_constants.hpp>
#include <boost/units/systems/si/codata/helion_constants.hpp>
diff -Nuar ceph-16.2.7.org/src/boost/boost/units/systems/si/codata/sw_64_constants.hpp ceph-16.2.7.sw/src/boost/boost/units/systems/si/codata/sw_64_constants.hpp
--- ceph-16.2.7.org/src/boost/boost/units/systems/si/codata/sw_64_constants.hpp 1970-01-01 00:00:00.000000000 +0000
+++ ceph-16.2.7.sw/src/boost/boost/units/systems/si/codata/sw_64_constants.hpp 2022-05-26 10:53:56.950000000 +0000
@@ -0,0 +1,66 @@
+// Boost.Units - A C++ library for zero-overhead dimensional analysis and
+// unit/quantity manipulation and conversion
+//
+// Copyright (C) 2003-2008 Matthias Christian Schabel
+// Copyright (C) 2008 Steven Watanabe
+//
+// Distributed under the Boost Software License, Version 1.0. (See
+// accompanying file LICENSE_1_0.txt or copy at
+// http://www.boost.org/LICENSE_1_0.txt)
+
+#ifndef BOOST_UNITS_CODATA_SW_64_CONSTANTS_HPP
+#define BOOST_UNITS_CODATA_SW_64_CONSTANTS_HPP
+
+#include <boost/units/quantity.hpp>
+#include <boost/units/static_constant.hpp>
+
+#include <boost/units/systems/detail/constants.hpp>
+#include <boost/units/systems/si/amount.hpp>
+#include <boost/units/systems/si/area.hpp>
+#include <boost/units/systems/si/electric_charge.hpp>
+#include <boost/units/systems/si/energy.hpp>
+#include <boost/units/systems/si/frequency.hpp>
+#include <boost/units/systems/si/length.hpp>
+#include <boost/units/systems/si/mass.hpp>
+#include <boost/units/systems/si/magnetic_flux_density.hpp>
+#include <boost/units/systems/si/time.hpp>
+#include <boost/units/systems/si/wavenumber.hpp>
+
+#include <boost/units/systems/si/codata/typedefs.hpp>
+
+/// \file
+/// CODATA recommended values of fundamental atomic and nuclear constants
+/// CODATA 2006 values as of 2007/03/30
+
+namespace boost {
+
+namespace units {
+
+namespace si {
+
+namespace constants {
+
+namespace codata {
+
+/// CODATA recommended values of the fundamental physical constants: NIST SP 961
+
+/// sw_64 particle mass
+BOOST_UNITS_PHYSICAL_CONSTANT(m_sw_64,quantity<mass>,6.64465620e-27*kilograms,3.3e-34*kilograms);
+/// sw_64-electron mass ratio
+BOOST_UNITS_PHYSICAL_CONSTANT(m_sw_64_over_m_e,quantity<dimensionless>,7294.2995365*dimensionless(),3.1e-6*dimensionless());
+/// sw_64-proton mass ratio
+BOOST_UNITS_PHYSICAL_CONSTANT(m_sw_64_over_m_p,quantity<dimensionless>,3.97259968951*dimensionless(),4.1e-10*dimensionless());
+/// sw_64 molar mass
+BOOST_UNITS_PHYSICAL_CONSTANT(M_sw_64,quantity<mass_over_amount>,4.001506179127e-3*kilograms/mole,6.2e-14*kilograms/mole);
+
+} // namespace codata
+
+} // namespace constants
+
+} // namespace si
+
+} // namespace units
+
+} // namespace boost
+
+#endif // BOOST_UNITS_CODATA_SW_64_CONSTANTS_HPP
diff -Nuar ceph-16.2.7.org/src/boost/boost/wave/wave_config.hpp ceph-16.2.7.sw/src/boost/boost/wave/wave_config.hpp
--- ceph-16.2.7.org/src/boost/boost/wave/wave_config.hpp 2022-05-23 15:33:14.460000000 +0000
+++ ceph-16.2.7.sw/src/boost/boost/wave/wave_config.hpp 2022-05-26 10:54:50.330000000 +0000
@@ -205,7 +205,7 @@
// CW up to 8.3 chokes as well *sigh*
// Tru64/CXX has linker problems when using flex_string
#if BOOST_WORKAROUND(__MWERKS__, < 0x3200) || \
- (defined(__DECCXX) && defined(__alpha)) || \
+ (defined(__DECCXX) && (defined(__alpha) || defined(__sw_64))) || \
defined(BOOST_WAVE_STRINGTYPE_USE_STDSTRING)
#define BOOST_WAVE_STRINGTYPE std::string
diff -Nuar ceph-16.2.7.org/src/boost/boostcpp.jam ceph-16.2.7.sw/src/boost/boostcpp.jam
--- ceph-16.2.7.org/src/boost/boostcpp.jam 2022-05-23 15:33:14.570000000 +0000
+++ ceph-16.2.7.sw/src/boost/boostcpp.jam 2022-05-26 10:56:12.360000000 +0000
@@ -607,7 +607,7 @@
return <conditional>@boostcpp.deduce-address-model ;
}
-local deducable-architectures = arm mips1 power riscv s390x sparc x86 combined ;
+local deducable-architectures = sw_64 arm mips1 power riscv s390x sparc x86 combined ;
feature.feature deduced-architecture : $(deducable-architectures) : propagated optional composite hidden ;
for a in $(deducable-architectures)
{
@@ -618,8 +618,9 @@
{
local result ;
local filtered = [ toolset-properties $(properties) ] ;
- local names = arm mips1 power riscv s390x sparc x86 combined ;
+ local names = sw_64 arm mips1 power riscv s390x sparc x86 combined ;
local idx = [ configure.find-builds "default architecture" : $(filtered)
+ : /boost/architecture//sw_64
: /boost/architecture//arm
: /boost/architecture//mips1
: /boost/architecture//power
diff -Nuar ceph-16.2.7.org/src/boost/libs/atomic/test/lockfree.cpp ceph-16.2.7.sw/src/boost/libs/atomic/test/lockfree.cpp
--- ceph-16.2.7.org/src/boost/libs/atomic/test/lockfree.cpp 2022-05-23 15:33:18.210000000 +0000
+++ ceph-16.2.7.sw/src/boost/libs/atomic/test/lockfree.cpp 2022-05-26 10:56:35.650000000 +0000
@@ -100,7 +100,7 @@
#define EXPECT_POINTER_LOCK_FREE 2
#define EXPECT_BOOL_LOCK_FREE 2
-#elif defined(__GNUC__) && defined(__alpha__)
+#elif defined(__GNUC__) && (defined(__alpha__)||defined(__sw_64__))
#define EXPECT_CHAR_LOCK_FREE 2
#define EXPECT_CHAR16_T_LOCK_FREE 2
diff -Nuar ceph-16.2.7.org/src/boost/libs/config/checks/architecture/Jamroot.jam ceph-16.2.7.sw/src/boost/libs/config/checks/architecture/Jamroot.jam
--- ceph-16.2.7.org/src/boost/libs/config/checks/architecture/Jamroot.jam 2022-05-23 15:33:15.570000000 +0000
+++ ceph-16.2.7.sw/src/boost/libs/config/checks/architecture/Jamroot.jam 2022-05-26 10:57:12.410000000 +0000
@@ -16,6 +16,7 @@
obj 64 : 64.cpp ;
obj arm : arm.cpp ;
+obj sw_64 : sw_64.cpp ;
obj combined : combined.cpp ;
obj mips1 : mips1.cpp ;
obj power : power.cpp ;
diff -Nuar ceph-16.2.7.org/src/boost/libs/config/checks/architecture/sw_64.cpp ceph-16.2.7.sw/src/boost/libs/config/checks/architecture/sw_64.cpp
--- ceph-16.2.7.org/src/boost/libs/config/checks/architecture/sw_64.cpp 1970-01-01 00:00:00.000000000 +0000
+++ ceph-16.2.7.sw/src/boost/libs/config/checks/architecture/sw_64.cpp 2022-05-26 10:57:46.010000000 +0000
@@ -0,0 +1,15 @@
+// sw_64.cpp
+
+// Copyright (c) 2022 sw_64
+
+// Distributed under the Boost Software License Version 1.0. (See
+// accompanying file LICENSE_1_0.txt or copy at
+// http://www.boost.org/LICENSE_1_0.txt)
+
+#if !defined(__sw_64__) && !defined(__thumb__) && \
+ !defined(__TARGET_ARCH_SW_64) && !defined(__TARGET_ARCH_THUMB) && \
+ !defined(_SW_64) && !defined(_M_SW_64) && \
+ !defined(__aarch64__)
+#error "Not SW_64"
+#endif
+
diff -Nuar ceph-16.2.7.org/src/boost/libs/config/test/config_info.cpp ceph-16.2.7.sw/src/boost/libs/config/test/config_info.cpp
--- ceph-16.2.7.org/src/boost/libs/config/test/config_info.cpp 2022-05-23 15:33:15.540000000 +0000
+++ ceph-16.2.7.sw/src/boost/libs/config/test/config_info.cpp 2022-05-26 10:58:47.330000000 +0000
@@ -173,6 +173,7 @@
PRINT_MACRO(_M_IX86_FP);
PRINT_MACRO(_M_X64);
PRINT_MACRO(_M_ALPHA);
+ PRINT_MACRO(_M_SW_64);
PRINT_MACRO(_M_MPPC);
PRINT_MACRO(_M_MRX000);
PRINT_MACRO(_M_PPC);
@@ -229,6 +230,7 @@
PRINT_MACRO(__MINGW32__);
PRINT_MACRO(__GXX_RTTI);
PRINT_MACRO(__alpha__);
+ PRINT_MACRO(__sw_64__);
PRINT_MACRO(__amd64__);
PRINT_MACRO(__arm__);
PRINT_MACRO(__aarch64__);
diff -Nuar ceph-16.2.7.org/src/boost/libs/context/build/architecture.jam ceph-16.2.7.sw/src/boost/libs/context/build/architecture.jam
--- ceph-16.2.7.org/src/boost/libs/context/build/architecture.jam 2022-05-23 15:33:16.460000000 +0000
+++ ceph-16.2.7.sw/src/boost/libs/context/build/architecture.jam 2022-05-26 11:00:55.230000000 +0000
@@ -55,6 +55,10 @@
{
return <architecture>arm ;
}
+ else if [ configure.builds /boost/architecture//sw_64 : $(properties) : sw_64 ]
+ {
+ return <architecture>sw_64 ;
+ }
else if [ configure.builds /boost/architecture//mips1 : $(properties) : mips1 ]
{
return <architecture>mips1 ;
diff -Nuar ceph-16.2.7.org/src/boost/libs/context/build/Jamfile.v2 ceph-16.2.7.sw/src/boost/libs/context/build/Jamfile.v2
--- ceph-16.2.7.org/src/boost/libs/context/build/Jamfile.v2 2022-05-23 15:33:16.460000000 +0000
+++ ceph-16.2.7.sw/src/boost/libs/context/build/Jamfile.v2 2022-05-26 11:06:57.310000000 +0000
@@ -75,6 +75,7 @@
if [ os.name ] = "NT" { tmp = ms ; }
else if [ os.name ] = "CYGWIN" { tmp = ms ; }
else if [ os.platform ] = "ARM" { tmp = aapcs ; }
+ else if [ os.platform ] = "SW_64" { tmp = aapcs ; }
else if [ os.platform ] = "MIPS32" { tmp = o32 ; }
else if [ os.platform ] = "MIPS64" { tmp = n64 ; }
return $(tmp) ;
@@ -177,6 +178,30 @@
<toolset>msvc
;
+# SW_64
+# SW_64/AAPCS/ELF
+alias asm_sources
+ : asm/make_sw_64_aapcs_elf_gas.S
+ asm/jump_sw_64_aapcs_elf_gas.S
+ asm/ontop_sw_64_aapcs_elf_gas.S
+ : <abi>aapcs
+ <address-model>64
+ <architecture>sw_64
+ <binary-format>elf
+ <toolset>clang
+ ;
+
+alias asm_sources
+ : asm/make_sw_64_aapcs_elf_gas.S
+ asm/jump_sw_64_aapcs_elf_gas.S
+ asm/ontop_sw_64_aapcs_elf_gas.S
+ : <abi>aapcs
+ <address-model>64
+ <architecture>sw_64
+ <binary-format>elf
+ <toolset>gcc
+ ;
+
# ARM64
# ARM64/AAPCS/ELF
alias asm_sources
diff -Nuar ceph-16.2.7.org/src/boost/libs/context/src/asm/jump_sw_64_aapcs_elf_gas.S ceph-16.2.7.sw/src/boost/libs/context/src/asm/jump_sw_64_aapcs_elf_gas.S
--- ceph-16.2.7.org/src/boost/libs/context/src/asm/jump_sw_64_aapcs_elf_gas.S 1970-01-01 00:00:00.000000000 +0000
+++ ceph-16.2.7.sw/src/boost/libs/context/src/asm/jump_sw_64_aapcs_elf_gas.S 2022-05-26 11:07:35.330000000 +0000
@@ -0,0 +1,86 @@
+.text
+.align 2
+.global jump_fcontext
+.type jump_fcontext, %function
+jump_fcontext:
+ # prepare stack for GP + FPU
+ #ldih $29,0($27)
+ #ldi $29,0($29)
+ subl $sp, 0x98, $sp
+
+ # save $f2-$f9
+ fstd $f2, 0x00($sp)
+ fstd $f3, 0x08($sp)
+ fstd $f4, 0x10($sp)
+ fstd $f5, 0x18($sp)
+ fstd $f6, 0x20($sp)
+ fstd $f7, 0x28($sp)
+ fstd $f8, 0x30($sp)
+ fstd $f9, 0x38($sp)
+
+ # save $9-$15, fp,$26
+ stl $9, 0x40($sp)
+ stl $10, 0x48($sp)
+ stl $11, 0x50($sp)
+ stl $12, 0x58($sp)
+ stl $13, 0x60($sp)
+ stl $14, 0x68($sp)
+ stl $15, 0x70($sp)
+ stl $fp, 0x78($sp)
+ stl $16, 0x80($sp) #save jump_fcontext return address
+ stl $26, 0x88($sp)
+
+ # save LR as PC
+ stl $26, 0x90($sp)
+
+ # store RSP (pointing to context-data) in $16
+ mov $sp, $20
+
+
+ # restore RSP (pointing to context-data) from $17
+ mov $17, $sp
+
+ # load $f2-$f9
+ fldd $f2, 0x00($sp)
+ fldd $f3, 0x08($sp)
+ fldd $f4, 0x10($sp)
+ fldd $f5, 0x18($sp)
+ fldd $f6, 0x20($sp)
+ fldd $f7, 0x28($sp)
+ fldd $f8, 0x30($sp)
+ fldd $f9, 0x38($sp)
+
+ # load $9-$15, fp,$26
+ ldl $9, 0x40($sp)
+ ldl $10, 0x48($sp)
+ ldl $11, 0x50($sp)
+ ldl $12, 0x58($sp)
+ ldl $13, 0x60($sp)
+ ldl $14, 0x68($sp)
+ ldl $15, 0x70($sp)
+ ldl $fp, 0x78($sp)
+ ldl $26, 0x88($sp)
+
+ # pass transfer_t as first arg in context function
+ # to store $1,$2 to $16 address
+ ldl $16, 0x80($sp) #load $16, store return struct do return address
+ stl $20,0($16)
+ stl $18,8($16)
+
+ # pass transfer_t as first arg in context function,such as f1,f2,f3
+ # $16 == FCTX, $17 == DATA
+ mov $20,$16 #$16 $17 as first and second arg
+ mov $18,$17
+
+
+ # load pc
+ ldl $27, 0x90($sp)
+
+
+ # restore stack from GP + FPU
+ addl $sp, 0x98, $sp
+
+ ret $31,($27),0x1 //jmp $31, ($27) //ret ($27)
+.size jump_fcontext,.-jump_fcontext
+# Mark that we don't need executable stack.
+.section .note.GNU-stack,"",%progbits
diff -Nuar ceph-16.2.7.org/src/boost/libs/context/src/asm/make_sw_64_aapcs_elf_gas.S ceph-16.2.7.sw/src/boost/libs/context/src/asm/make_sw_64_aapcs_elf_gas.S
--- ceph-16.2.7.org/src/boost/libs/context/src/asm/make_sw_64_aapcs_elf_gas.S 1970-01-01 00:00:00.000000000 +0000
+++ ceph-16.2.7.sw/src/boost/libs/context/src/asm/make_sw_64_aapcs_elf_gas.S 2022-05-26 11:07:52.120000000 +0000
@@ -0,0 +1,37 @@
+.text
+.align 2
+.global make_fcontext
+.type make_fcontext, %function
+make_fcontext:
+ #ldih $29,0($27)
+ #ldi $29,0($29)
+ # shift address in $16 (allocated stack) to lower 16 byte boundary
+ bic $16, 0xf,$16
+
+ # reserve space for context-data on context-stack
+ subl $16, 0x98,$16
+
+ # third arg of make_fcontext() == address of context-function
+ # store address as a PC to jump in
+ stl $18, 0x90($16)
+
+ # save address of finish as return-address for context-function
+ # will be entered after context-function returns (LR register)
+ ldi $17, finish
+ stl $17, 0x88($16)
+
+ stl $16, 0x80($16)
+
+ mov $16, $0
+
+ ret $31,($26),1 //jump ($26) // return pointer to context-data ($16)
+
+finish:
+ # exit code is zero
+ mov 0, $0
+ # exit application
+ call _exit #ldi $27,_exit #jmp ($27)
+
+.size make_fcontext,.-make_fcontext
+# Mark that we don't need executable stack.
+.section .note.GNU-stack,"",%progbits
diff -Nuar ceph-16.2.7.org/src/boost/libs/context/src/asm/ontop_sw_64_aapcs_elf_gas.S ceph-16.2.7.sw/src/boost/libs/context/src/asm/ontop_sw_64_aapcs_elf_gas.S
--- ceph-16.2.7.org/src/boost/libs/context/src/asm/ontop_sw_64_aapcs_elf_gas.S 1970-01-01 00:00:00.000000000 +0000
+++ ceph-16.2.7.sw/src/boost/libs/context/src/asm/ontop_sw_64_aapcs_elf_gas.S 2022-05-26 11:08:14.440000000 +0000
@@ -0,0 +1,85 @@
+.text
+.align 2
+.global ontop_fcontext
+.type ontop_fcontext, %function
+ontop_fcontext:
+ # prepare stack for GP + FPU
+ #ldih $29,0($27)
+ #ldi $29,0($29)
+ subl $sp, 0x98, $sp
+
+ # save $f2-$f9
+ fstd $f2, 0x00($sp)
+ fstd $f3, 0x08($sp)
+ fstd $f4, 0x10($sp)
+ fstd $f5, 0x18($sp)
+ fstd $f6, 0x20($sp)
+ fstd $f7, 0x28($sp)
+ fstd $f8, 0x30($sp)
+ fstd $f9, 0x38($sp)
+
+ # save $9-$15, fp,$26
+ stl $9, 0x40($sp)
+ stl $10, 0x48($sp)
+ stl $11, 0x50($sp)
+ stl $12, 0x58($sp)
+ stl $13, 0x60($sp)
+ stl $14, 0x68($sp)
+ stl $15, 0x70($sp)
+ stl $fp, 0x78($sp)
+ stl $16, 0x80($sp) #save ontop_fcontext return address
+ stl $26, 0x88($sp)
+
+ # save LR as PC
+ stl $26, 0x90($sp)
+
+ # store RSP (pointing to context-data) in $16
+ mov $sp, $20
+
+
+ # restore RSP (pointing to context-data) from $17
+ mov $17, $sp
+
+ # load $f2-$f9
+ fldd $f2, 0x00($sp)
+ fldd $f3, 0x08($sp)
+ fldd $f4, 0x10($sp)
+ fldd $f5, 0x18($sp)
+ fldd $f6, 0x20($sp)
+ fldd $f7, 0x28($sp)
+ fldd $f8, 0x30($sp)
+ fldd $f9, 0x38($sp)
+
+ # load $9-$15, fp,$26
+ ldl $9, 0x40($sp)
+ ldl $10, 0x48($sp)
+ ldl $11, 0x50($sp)
+ ldl $12, 0x58($sp)
+ ldl $13, 0x60($sp)
+ ldl $14, 0x68($sp)
+ ldl $15, 0x70($sp)
+ ldl $fp, 0x78($sp)
+ ldl $26, 0x88($sp)
+
+ # pass transfer_t as first arg in context function
+ # to store $1,$2 to $16 address
+ ldl $16, 0x80($sp) #load $16, store return struct do return address
+ stl $20,0($16)
+ stl $18,8($16)
+
+ # pass transfer_t as first arg in context function,such as f1,f2,f3
+ # $16 == FCTX, $17 == DATA
+ mov $20,$17 #$16 $17 $18 as first and second arg
+
+
+ # skip pc
+ mov $19, $27
+
+
+ # restore stack from GP + FPU
+ addl $sp, 0x98, $sp
+
+ ret $31,($27),0x1 //jmp $31, ($27) //ret ($27)
+.size ontop_fcontext,.-ontop_fcontext
+# Mark that we don't need executable stack.
+.section .note.GNU-stack,"",%progbits
diff -Nuar ceph-16.2.7.org/src/boost/libs/log/build/log-architecture.jam ceph-16.2.7.sw/src/boost/libs/log/build/log-architecture.jam
--- ceph-16.2.7.org/src/boost/libs/log/build/log-architecture.jam 2022-05-23 15:33:17.090000000 +0000
+++ ceph-16.2.7.sw/src/boost/libs/log/build/log-architecture.jam 2022-05-26 11:09:13.010000000 +0000
@@ -65,6 +65,10 @@
{
return <log-architecture>arm ;
}
+ else if [ configure.builds /boost/architecture//sw_64 : $(properties) : sw_64 ]
+ {
+ return <log-architecture>sw_64 ;
+ }
else if [ configure.builds /boost/architecture//mips1 : $(properties) : mips1 ]
{
return <log-architecture>mips1 ;
diff -Nuar ceph-16.2.7.org/src/boost/tools/build/src/engine/jam.h ceph-16.2.7.sw/src/boost/tools/build/src/engine/jam.h
--- ceph-16.2.7.org/src/boost/tools/build/src/engine/jam.h 2022-05-23 15:33:14.890000000 +0000
+++ ceph-16.2.7.sw/src/boost/tools/build/src/engine/jam.h 2022-05-26 16:49:32.010000000 +0000
@@ -387,6 +387,11 @@
#define OSPLAT "OSPLAT=AXP"
#endif
+#if defined( _SW_64_ ) || \
+ defined( __sw_64__ )
+ #define OSPLAT "OSPLAT=SW_64"
+#endif
+
#if defined( _i386_ ) || \
defined( __i386__ ) || \
defined( __i386 ) || \
diff -Nuar ceph-16.2.7.org/src/boost/tools/build/src/tools/builtin.py ceph-16.2.7.sw/src/boost/tools/build/src/tools/builtin.py
--- ceph-16.2.7.org/src/boost/tools/build/src/tools/builtin.py 2022-05-23 15:33:14.930000000 +0000
+++ ceph-16.2.7.sw/src/boost/tools/build/src/tools/builtin.py 2022-05-26 14:35:50.450000000 +0000
@@ -252,7 +252,10 @@
# x86 and x86-64
'x86',
- # ia64
+ #sw_64
+ 'sw_64',
+
+ # ia64
'ia64',
# Sparc
@@ -320,6 +323,9 @@
'armv2', 'armv2a', 'armv3', 'armv3m', 'armv4', 'armv4t', 'armv5',
'armv5t', 'armv5te', 'armv6', 'armv6j', 'iwmmxt', 'ep9312',
+ #sw_64
+ 'sw_64',
+
# z Systems (aka s390x)
'z196', 'zEC12', 'z13', 'z13', 'z14', 'z15'],
diff -Nuar ceph-16.2.7.org/src/boost/tools/build/src/tools/features/architecture-feature.jam ceph-16.2.7.sw/src/boost/tools/build/src/tools/features/architecture-feature.jam
--- ceph-16.2.7.org/src/boost/tools/build/src/tools/features/architecture-feature.jam 2022-05-23 15:33:14.920000000 +0000
+++ ceph-16.2.7.sw/src/boost/tools/build/src/tools/features/architecture-feature.jam 2022-05-26 14:29:12.510000000 +0000
@@ -9,7 +9,7 @@
[[bbv2.builtin.features.architecture]]`architecture`::
*Allowed values:* `x86`, `ia64`, `sparc`, `power`, `mips1`, `mips2`,
-`mips3`, `mips4`, `mips32`, `mips32r2`, `mips64`, `parisc`, `arm`,
+`mips3`, `mips4`, `mips32`, `mips32r2`, `mips64`, `parisc`, `arm`, `sw_64`,
`s390x`, `combined`, `combined-x86-power`.
+
Specifies the general processor family to generate code for.
@@ -39,7 +39,10 @@
# Advanced RISC Machines
arm
- # RISC-V
+ #SW_64
+ sw_64
+
+ # RISC-V
riscv
# z Systems (aka s390x)
diff -Nuar ceph-16.2.7.org/src/CMakeLists.txt ceph-16.2.7.sw/src/CMakeLists.txt
--- ceph-16.2.7.org/src/CMakeLists.txt 2022-05-23 15:33:18.850000000 +0000
+++ ceph-16.2.7.sw/src/CMakeLists.txt 2022-05-26 14:39:09.230000000 +0000
@@ -70,7 +70,7 @@
# The MINGW headers are missing some "const" qualifiers.
add_compile_options($<$<OR:$<COMPILE_LANGUAGE:C>,$<COMPILE_LANGUAGE:CXX>>:-fpermissive>)
else()
- string(APPEND CMAKE_EXE_LINKER_FLAGS " -rdynamic")
+ string(APPEND CMAKE_EXE_LINKER_FLAGS " -Wl,-zmuldefs -lstdc++ -rdynamic")
endif()
add_compile_options($<$<COMPILE_LANGUAGE:CXX>:-Wstrict-null-sentinel>)
add_compile_options($<$<COMPILE_LANGUAGE:CXX>:-Woverloaded-virtual>)
@@ -553,7 +553,7 @@
set_property(
TARGET ceph-common
APPEND APPEND_STRING
- PROPERTY LINK_FLAGS "-Wl,-Bsymbolic -Wl,-Bsymbolic-functions")
+ PROPERTY LINK_FLAGS "-Wl,-Bsymbolic -Wl,-Bsymbolic-functions -Wl,-zmuldefs")
endif()
if(MINGW)
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