174 lines
6.0 KiB
Diff
174 lines
6.0 KiB
Diff
From be2f8fcd9df7d50fd17125eccecf7fc0bad6b2c8 Mon Sep 17 00:00:00 2001
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From: Jan Beulich <jbeulich@suse.com>
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Date: Thu, 22 Jul 2021 13:02:08 +0200
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Subject: [PATCH] x86: correct VCVT{,U}SI2SD rounding mode handling
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With EVEX.W clear the instruction doesn't ignore the rounding mode, but
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(like for other insns without rounding semantics) EVEX.b set causes #UD.
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Hence the handling of EVEX.W needs to be done when processing
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evex_rounding_64_mode, not at the decode stages.
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Derive a new 64-bit testcase from the 32-bit one to cover the different
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EVEX.W treatment in both cases.
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diff --git a/gas/testsuite/gas/i386/evex.d b/gas/testsuite/gas/i386/evex.d
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index 2fbe295b86b..b02bca39098 100644
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--- a/gas/testsuite/gas/i386/evex.d
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+++ b/gas/testsuite/gas/i386/evex.d
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@@ -1,5 +1,5 @@
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#objdump: -dw -Msuffix
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-#name: i386 EVX insns
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+#name: i386 EVEX insns
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.*: +file format .*
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@@ -8,9 +8,12 @@ Disassembly of section .text:
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0+ <_start>:
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+[a-f0-9]+: 62 f1 d6 38 2a f0 vcvtsi2ssl %eax,\{rd-sae\},%xmm5,%xmm6
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+ +[a-f0-9]+: 62 f1 57 38 2a f0 vcvtsi2sdl %eax,\(bad\),%xmm5,%xmm6
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+[a-f0-9]+: 62 f1 d7 38 2a f0 vcvtsi2sdl %eax,\(bad\),%xmm5,%xmm6
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+[a-f0-9]+: 62 f1 d6 08 7b f0 vcvtusi2ssl %eax,%xmm5,%xmm6
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+ +[a-f0-9]+: 62 f1 57 08 7b f0 vcvtusi2sdl %eax,%xmm5,%xmm6
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+[a-f0-9]+: 62 f1 d7 08 7b f0 vcvtusi2sdl %eax,%xmm5,%xmm6
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+[a-f0-9]+: 62 f1 d6 38 7b f0 vcvtusi2ssl %eax,\{rd-sae\},%xmm5,%xmm6
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+ +[a-f0-9]+: 62 f1 57 38 7b f0 vcvtusi2sdl %eax,\(bad\),%xmm5,%xmm6
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+[a-f0-9]+: 62 f1 d7 38 7b f0 vcvtusi2sdl %eax,\(bad\),%xmm5,%xmm6
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#pass
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diff --git a/gas/testsuite/gas/i386/evex.s b/gas/testsuite/gas/i386/evex.s
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index a64cc573dcd..90c635a27b6 100644
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--- a/gas/testsuite/gas/i386/evex.s
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+++ b/gas/testsuite/gas/i386/evex.s
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@@ -4,8 +4,11 @@
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.text
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_start:
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.byte 0x62, 0xf1, 0xd6, 0x38, 0x2a, 0xf0
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+ .byte 0x62, 0xf1, 0x57, 0x38, 0x2a, 0xf0
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.byte 0x62, 0xf1, 0xd7, 0x38, 0x2a, 0xf0
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.byte 0x62, 0xf1, 0xd6, 0x08, 0x7b, 0xf0
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+ .byte 0x62, 0xf1, 0x57, 0x08, 0x7b, 0xf0
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.byte 0x62, 0xf1, 0xd7, 0x08, 0x7b, 0xf0
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.byte 0x62, 0xf1, 0xd6, 0x38, 0x7b, 0xf0
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+ .byte 0x62, 0xf1, 0x57, 0x38, 0x7b, 0xf0
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.byte 0x62, 0xf1, 0xd7, 0x38, 0x7b, 0xf0
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diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp
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index 1e0a363a803..6f9543eec3a 100644
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--- a/gas/testsuite/gas/i386/i386.exp
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+++ b/gas/testsuite/gas/i386/i386.exp
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@@ -929,6 +929,7 @@ if [gas_64_check] then {
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run_dump_test "x86-64-avx512er-intel"
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run_dump_test "x86-64-avx512pf"
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run_dump_test "x86-64-avx512pf-intel"
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+ run_dump_test "x86-64-evex"
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run_dump_test "x86-64-evex-lig256"
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run_dump_test "x86-64-evex-lig512"
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run_dump_test "x86-64-evex-lig256-intel"
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diff --git a/gas/testsuite/gas/i386/x86-64-evex.d b/gas/testsuite/gas/i386/x86-64-evex.d
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new file mode 100644
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index 00000000000..b360aa74a17
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--- /dev/null
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+++ b/gas/testsuite/gas/i386/x86-64-evex.d
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@@ -0,0 +1,20 @@
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+#objdump: -dw
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+#name: x86-64 EVEX insns
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+#source: evex.s
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+
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+.*: +file format .*
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+
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+
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+Disassembly of section .text:
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+
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+0+ <_start>:
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+ +[a-f0-9]+: 62 f1 d6 38 2a f0 vcvtsi2ss %rax,\{rd-sae\},%xmm5,%xmm6
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+ +[a-f0-9]+: 62 f1 57 38 2a f0 vcvtsi2sd %eax,\(bad\),%xmm5,%xmm6
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+ +[a-f0-9]+: 62 f1 d7 38 2a f0 vcvtsi2sd %rax,\{rd-sae\},%xmm5,%xmm6
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+ +[a-f0-9]+: 62 f1 d6 08 7b f0 vcvtusi2ss %rax,%xmm5,%xmm6
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+ +[a-f0-9]+: 62 f1 57 08 7b f0 vcvtusi2sd %eax,%xmm5,%xmm6
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+ +[a-f0-9]+: 62 f1 d7 08 7b f0 vcvtusi2sd %rax,%xmm5,%xmm6
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+ +[a-f0-9]+: 62 f1 d6 38 7b f0 vcvtusi2ss %rax,\{rd-sae\},%xmm5,%xmm6
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+ +[a-f0-9]+: 62 f1 57 38 7b f0 vcvtusi2sd %eax,\(bad\),%xmm5,%xmm6
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+ +[a-f0-9]+: 62 f1 d7 38 7b f0 vcvtusi2sd %rax,\{rd-sae\},%xmm5,%xmm6
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+#pass
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diff --git a/opcodes/i386-dis-evex-prefix.h b/opcodes/i386-dis-evex-prefix.h
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index 2ed8f6730c5..9ad9372a221 100644
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--- a/opcodes/i386-dis-evex-prefix.h
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+++ b/opcodes/i386-dis-evex-prefix.h
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@@ -30,7 +30,7 @@
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{ Bad_Opcode },
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{ "vcvtsi2ss{%LQ|}", { XMScalar, VexScalar, EXxEVexR, Edq }, 0 },
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{ Bad_Opcode },
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- { VEX_W_TABLE (EVEX_W_0F2A_P_3) },
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+ { "vcvtsi2sd{%LQ|}", { XMScalar, VexScalar, EXxEVexR64, Edq }, 0 },
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},
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/* PREFIX_EVEX_0F51 */
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{
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@@ -134,7 +134,7 @@
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{ Bad_Opcode },
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{ "vcvtusi2ss{%LQ|}", { XMScalar, VexScalar, EXxEVexR, Edq }, 0 },
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{ VEX_W_TABLE (EVEX_W_0F7B_P_2) },
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- { VEX_W_TABLE (EVEX_W_0F7B_P_3) },
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+ { "vcvtusi2sd{%LQ|}", { XMScalar, VexScalar, EXxEVexR64, Edq }, 0 },
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},
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/* PREFIX_EVEX_0F7E */
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{
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diff --git a/opcodes/i386-dis-evex-w.h b/opcodes/i386-dis-evex-w.h
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index 2c7d9bc2e34..8af4695a004 100644
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--- a/opcodes/i386-dis-evex-w.h
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+++ b/opcodes/i386-dis-evex-w.h
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@@ -37,11 +37,6 @@
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{
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{ "vmovshdup", { XM, EXx }, 0 },
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},
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- /* EVEX_W_0F2A_P_3 */
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- {
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- { "vcvtsi2sd{%LQ|}", { XMScalar, VexScalar, Ed }, 0 },
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- { "vcvtsi2sd{%LQ|}", { XMScalar, VexScalar, EXxEVexR64, Edq }, 0 },
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- },
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/* EVEX_W_0F51_P_1 */
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{
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{ "vsqrtss", { XMScalar, VexScalar, EXxmm_md, EXxEVexR }, 0 },
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@@ -243,11 +238,6 @@
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{ "vcvtps2qq", { XM, EXEvexHalfBcstXmmq, EXxEVexR }, 0 },
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{ "vcvtpd2qq", { XM, EXx, EXxEVexR }, 0 },
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},
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- /* EVEX_W_0F7B_P_3 */
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- {
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- { "vcvtusi2sd{%LQ|}", { XMScalar, VexScalar, Ed }, 0 },
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- { "vcvtusi2sd{%LQ|}", { XMScalar, VexScalar, EXxEVexR64, Edq }, 0 },
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- },
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/* EVEX_W_0F7E_P_1 */
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{
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{ Bad_Opcode },
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diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c
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index f88276ced6b..ccc49ff023f 100644
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--- a/opcodes/i386-dis.c
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+++ b/opcodes/i386-dis.c
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@@ -1476,7 +1476,6 @@ enum
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EVEX_W_0F12_P_3,
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EVEX_W_0F16_P_0_M_1,
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EVEX_W_0F16_P_1,
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- EVEX_W_0F2A_P_3,
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EVEX_W_0F51_P_1,
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EVEX_W_0F51_P_3,
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EVEX_W_0F58_P_1,
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@@ -1521,7 +1520,6 @@ enum
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EVEX_W_0F7A_P_2,
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EVEX_W_0F7A_P_3,
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EVEX_W_0F7B_P_2,
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- EVEX_W_0F7B_P_3,
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EVEX_W_0F7E_P_1,
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EVEX_W_0F7F_P_1,
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EVEX_W_0F7F_P_2,
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@@ -13724,7 +13722,7 @@ OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
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switch (bytemode)
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{
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case evex_rounding_64_mode:
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- if (address_mode != mode_64bit)
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+ if (address_mode != mode_64bit || !vex.w)
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{
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oappend ("(bad)");
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break;
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--
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2.33.0
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