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backport patch to fix memory leak and overflow

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openeuler-basic 2020-01-20 22:30:55 +08:00
parent 8a262dc580
commit 85758061ad
4 changed files with 809 additions and 13 deletions
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382
More-signed-overflow-fixes.patch Normal file
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@ -0,0 +1,382 @@
From 2480b6fa946bb2d2dc993b1c4a83a8e1258a75e8 Mon Sep 17 00:00:00 2001
From: Alan Modra <amodra@gmail.com>
Date: Wed, 18 Dec 2019 15:37:44 +1030
Subject: [PATCH] More signed overflow fixes
The arc fix in create_map avoiding signed overflow by casting an
unsigned char to unsigned int before shifting, shows one of the
dangers of blinding doing that. The problem in this case was that the
variable storing the value, newAuxRegister->address, was a long.
Using the unsigned cast meant that the 32-bit value was zero extended
when long is 64 bits. Previously we had a sign extension. Net result
was that comparisons in arcExtMap_auxRegName didn't match. Of course,
I could have cast the 32-bit unsigned value back to signed before
storing in a long, but it's neater to just use an unsigned int for the
address.
opcodes/
* alpha-opc.c (OP): Avoid signed overflow.
* arm-dis.c (print_insn): Likewise.
* mcore-dis.c (print_insn_mcore): Likewise.
* pj-dis.c (get_int): Likewise.
* ppc-opc.c (EBD15, EBD15BI): Likewise.
* score7-dis.c (s7_print_insn): Likewise.
* tic30-dis.c (print_insn_tic30): Likewise.
* v850-opc.c (insert_SELID): Likewise.
* vax-dis.c (print_insn_vax): Likewise.
* arc-ext.c (create_map): Likewise.
(struct ExtAuxRegister): Make "address" field unsigned int.
(arcExtMap_auxRegName): Pass unsigned address.
(dump_ARC_extmap): Adjust.
* arc-ext.h (arcExtMap_auxRegName): Update prototype.
---
opcodes/alpha-opc.c | 2 +-
opcodes/arc-ext.c | 10 ++++----
opcodes/arc-ext.h | 2 +-
opcodes/arm-dis.c | 6 ++---
opcodes/mcore-dis.c | 57 ++++++++++++++++++++------------------------
opcodes/pj-dis.c | 8 +++----
opcodes/ppc-opc.c | 4 ++--
opcodes/score7-dis.c | 6 ++---
opcodes/tic30-dis.c | 6 +++--
opcodes/v850-opc.c | 8 ++-----
opcodes/vax-dis.c | 3 ++-
11 files changed, 53 insertions(+), 59 deletions(-)
diff --git a/opcodes/alpha-opc.c b/opcodes/alpha-opc.c
index 3123a1c..f813e6e 100644
--- a/opcodes/alpha-opc.c
+++ b/opcodes/alpha-opc.c
@@ -332,7 +332,7 @@ const unsigned alpha_num_operands = sizeof(alpha_operands)/sizeof(*alpha_operand
/* Macros used to form opcodes. */
/* The main opcode. */
-#define OP(x) (((x) & 0x3F) << 26)
+#define OP(x) (((x) & 0x3Fu) << 26)
#define OP_MASK 0xFC000000
/* Branch format instructions. */
diff --git a/opcodes/arc-ext.c b/opcodes/arc-ext.c
index d792079..687993d 100644
--- a/opcodes/arc-ext.c
+++ b/opcodes/arc-ext.c
@@ -53,7 +53,7 @@
struct ExtAuxRegister
{
- long address;
+ unsigned address;
char * name;
struct ExtAuxRegister * next;
};
@@ -191,8 +191,8 @@ create_map (unsigned char *block,
char *aux_name = xstrdup ((char *) (p + 6));
newAuxRegister->name = aux_name;
- newAuxRegister->address = (p[2] << 24) | (p[3] << 16)
- | (p[4] << 8) | p[5];
+ newAuxRegister->address = (((unsigned) p[2] << 24) | (p[3] << 16)
+ | (p[4] << 8) | p[5]);
newAuxRegister->next = arc_extension_map.auxRegisters;
arc_extension_map.auxRegisters = newAuxRegister;
break;
@@ -406,7 +406,7 @@ arcExtMap_condCodeName (int code)
/* Get the name of an extension auxiliary register. */
const char *
-arcExtMap_auxRegName (long address)
+arcExtMap_auxRegName (unsigned address)
{
/* Walk the list of auxiliary register names and find the name. */
struct ExtAuxRegister *r;
@@ -463,7 +463,7 @@ dump_ARC_extmap (void)
while (r)
{
- printf ("AUX : %s %ld\n", r->name, r->address);
+ printf ("AUX : %s %u\n", r->name, r->address);
r = r->next;
}
diff --git a/opcodes/arc-ext.h b/opcodes/arc-ext.h
index 50b2ecb..077891c 100644
--- a/opcodes/arc-ext.h
+++ b/opcodes/arc-ext.h
@@ -125,7 +125,7 @@ extern void build_ARC_extmap (bfd *);
/* Accessor functions. */
extern enum ExtReadWrite arcExtMap_coreReadWrite (int);
extern const char * arcExtMap_coreRegName (int);
-extern const char * arcExtMap_auxRegName (long);
+extern const char * arcExtMap_auxRegName (unsigned);
extern const char * arcExtMap_condCodeName (int);
extern const extInstruction_t *arcExtMap_insn (int, unsigned long long);
extern struct arc_opcode *arcExtMap_genOpcode (const extInstruction_t *,
diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c
index b6cccc5..fde0c96 100644
--- a/opcodes/arm-dis.c
+++ b/opcodes/arm-dis.c
@@ -6444,7 +6444,7 @@ static int
print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little)
{
unsigned char b[4];
- long given;
+ unsigned long given;
int status;
int is_thumb = FALSE;
int is_data = FALSE;
@@ -6732,9 +6732,9 @@ print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little)
status = info->read_memory_func (pc, (bfd_byte *) b, 4, info);
if (little_code)
- given = (b[0]) | (b[1] << 8) | (b[2] << 16) | (b[3] << 24);
+ given = (b[0]) | (b[1] << 8) | (b[2] << 16) | ((unsigned) b[3] << 24);
else
- given = (b[3]) | (b[2] << 8) | (b[1] << 16) | (b[0] << 24);
+ given = (b[3]) | (b[2] << 8) | (b[1] << 16) | ((unsigned) b[0] << 24);
}
else
{
diff --git a/opcodes/mcore-dis.c b/opcodes/mcore-dis.c
index c56ee83..5f48783 100644
--- a/opcodes/mcore-dis.c
+++ b/opcodes/mcore-dis.c
@@ -196,18 +196,14 @@ print_insn_mcore (bfd_vma memaddr,
case BR:
{
- long val = inst & 0x3FF;
+ uint32_t val = ((inst & 0x3FF) ^ 0x400) - 0x400;
- if (inst & 0x400)
- val |= 0xFFFFFC00;
-
- (*print_func) (stream, "\t0x%lx", (long)(memaddr + 2 + (val << 1)));
+ val = memaddr + 2 + (val << 1);
+ (*print_func) (stream, "\t0x%x", val);
if (strcmp (mcore_table[i].name, "bsr") == 0)
{
/* For bsr, we'll try to get a symbol for the target. */
- val = memaddr + 2 + (val << 1);
-
if (info->print_address_func && val != 0)
{
(*print_func) (stream, "\t// ");
@@ -219,19 +215,18 @@ print_insn_mcore (bfd_vma memaddr,
case BL:
{
- long val;
- val = (inst & 0x000F);
- (*print_func) (stream, "\t%s, 0x%lx",
+ uint32_t val = inst & 0x000F;
+ (*print_func) (stream, "\t%s, 0x%x",
grname[(inst >> 4) & 0xF],
- (long) (memaddr - (val << 1)));
+ (uint32_t) (memaddr - (val << 1)));
}
break;
case LR:
{
- unsigned long val;
+ uint32_t val;
- val = (memaddr + 2 + ((inst & 0xFF) << 2)) & 0xFFFFFFFC;
+ val = (memaddr + 2 + ((inst & 0xFF) << 2)) & ~3;
/* We are not reading an instruction, so allow
reads to extend beyond the next symbol. */
@@ -244,27 +239,27 @@ print_insn_mcore (bfd_vma memaddr,
}
if (info->endian == BFD_ENDIAN_LITTLE)
- val = (ibytes[3] << 24) | (ibytes[2] << 16)
- | (ibytes[1] << 8) | (ibytes[0]);
+ val = (((unsigned) ibytes[3] << 24) | (ibytes[2] << 16)
+ | (ibytes[1] << 8) | (ibytes[0]));
else
- val = (ibytes[0] << 24) | (ibytes[1] << 16)
- | (ibytes[2] << 8) | (ibytes[3]);
+ val = (((unsigned) ibytes[0] << 24) | (ibytes[1] << 16)
+ | (ibytes[2] << 8) | (ibytes[3]));
/* Removed [] around literal value to match ABI syntax 12/95. */
- (*print_func) (stream, "\t%s, 0x%lX", grname[(inst >> 8) & 0xF], val);
+ (*print_func) (stream, "\t%s, 0x%X", grname[(inst >> 8) & 0xF], val);
if (val == 0)
- (*print_func) (stream, "\t// from address pool at 0x%lx",
- (long) (memaddr + 2
- + ((inst & 0xFF) << 2)) & 0xFFFFFFFC);
+ (*print_func) (stream, "\t// from address pool at 0x%x",
+ (uint32_t) (memaddr + 2
+ + ((inst & 0xFF) << 2)) & ~3);
}
break;
case LJ:
{
- unsigned long val;
+ uint32_t val;
- val = (memaddr + 2 + ((inst & 0xFF) << 2)) & 0xFFFFFFFC;
+ val = (memaddr + 2 + ((inst & 0xFF) << 2)) & ~3;
/* We are not reading an instruction, so allow
reads to extend beyond the next symbol. */
@@ -277,14 +272,14 @@ print_insn_mcore (bfd_vma memaddr,
}
if (info->endian == BFD_ENDIAN_LITTLE)
- val = (ibytes[3] << 24) | (ibytes[2] << 16)
- | (ibytes[1] << 8) | (ibytes[0]);
+ val = (((unsigned) ibytes[3] << 24) | (ibytes[2] << 16)
+ | (ibytes[1] << 8) | (ibytes[0]));
else
- val = (ibytes[0] << 24) | (ibytes[1] << 16)
- | (ibytes[2] << 8) | (ibytes[3]);
+ val = (((unsigned) ibytes[0] << 24) | (ibytes[1] << 16)
+ | (ibytes[2] << 8) | (ibytes[3]));
/* Removed [] around literal value to match ABI syntax 12/95. */
- (*print_func) (stream, "\t0x%lX", val);
+ (*print_func) (stream, "\t0x%X", val);
/* For jmpi/jsri, we'll try to get a symbol for the target. */
if (info->print_address_func && val != 0)
{
@@ -293,9 +288,9 @@ print_insn_mcore (bfd_vma memaddr,
}
else
{
- (*print_func) (stream, "\t// from address pool at 0x%lx",
- (long) (memaddr + 2
- + ((inst & 0xFF) << 2)) & 0xFFFFFFFC);
+ (*print_func) (stream, "\t// from address pool at 0x%x",
+ (uint32_t) (memaddr + 2
+ + ((inst & 0xFF) << 2)) & ~3);
}
}
break;
diff --git a/opcodes/pj-dis.c b/opcodes/pj-dis.c
index 9c959f1..66a7e7f 100644
--- a/opcodes/pj-dis.c
+++ b/opcodes/pj-dis.c
@@ -32,10 +32,10 @@ get_int (bfd_vma memaddr, int *iptr, struct disassemble_info *info)
unsigned char ival[4];
int status = info->read_memory_func (memaddr, ival, 4, info);
- *iptr = (ival[0] << 24)
- | (ival[1] << 16)
- | (ival[2] << 8)
- | (ival[3] << 0);
+ *iptr = (((unsigned) ival[0] << 24)
+ | (ival[1] << 16)
+ | (ival[2] << 8)
+ | (ival[3] << 0));
return status;
}
diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c
index 4a0fca5..ed6cb78 100644
--- a/opcodes/ppc-opc.c
+++ b/opcodes/ppc-opc.c
@@ -2720,7 +2720,7 @@ const unsigned int num_powerpc_operands = (sizeof (powerpc_operands)
/* A BD15 form instruction for extended conditional branch mnemonics. */
#define EBD15(op, aa, bo, lk) \
- (((op) & 0x3f) << 26) \
+ (((op) & 0x3fu) << 26) \
| (((aa) & 0xf) << 22) \
| (((bo) & 0x3) << 20) \
| ((lk) & 1)
@@ -2729,7 +2729,7 @@ const unsigned int num_powerpc_operands = (sizeof (powerpc_operands)
/* A BD15 form instruction for extended conditional branch mnemonics
with BI. */
#define EBD15BI(op, aa, bo, bi, lk) \
- ((((op) & 0x3f) << 26) \
+ ((((op) & 0x3fu) << 26) \
| (((aa) & 0xf) << 22) \
| (((bo) & 0x3) << 20) \
| (((bi) & 0x3) << 16) \
diff --git a/opcodes/score7-dis.c b/opcodes/score7-dis.c
index 9d21ef8..53d18ea 100644
--- a/opcodes/score7-dis.c
+++ b/opcodes/score7-dis.c
@@ -871,7 +871,7 @@ int
s7_print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little)
{
unsigned char b[4];
- long given;
+ unsigned long given;
long ridparity;
int status;
bfd_boolean insn_pce_p = FALSE;
@@ -907,11 +907,11 @@ s7_print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little)
if (little)
{
- given = (b[0]) | (b[1] << 8) | (b[2] << 16) | (b[3] << 24);
+ given = (b[0]) | (b[1] << 8) | (b[2] << 16) | ((unsigned) b[3] << 24);
}
else
{
- given = (b[0] << 24) | (b[1] << 16) | (b[2] << 8) | (b[3]);
+ given = ((unsigned) b[0] << 24) | (b[1] << 16) | (b[2] << 8) | (b[3]);
}
if ((given & 0x80008000) == 0x80008000)
diff --git a/opcodes/tic30-dis.c b/opcodes/tic30-dis.c
index 3f07450..8b93ca6 100644
--- a/opcodes/tic30-dis.c
+++ b/opcodes/tic30-dis.c
@@ -696,8 +696,10 @@ print_insn_tic30 (bfd_vma pc, disassemble_info *info)
bfd_vma bufaddr = pc - info->buffer_vma;
/* Obtain the current instruction word from the buffer. */
- insn_word = (*(info->buffer + bufaddr) << 24) | (*(info->buffer + bufaddr + 1) << 16) |
- (*(info->buffer + bufaddr + 2) << 8) | *(info->buffer + bufaddr + 3);
+ insn_word = (((unsigned) *(info->buffer + bufaddr) << 24)
+ | (*(info->buffer + bufaddr + 1) << 16)
+ | (*(info->buffer + bufaddr + 2) << 8)
+ | *(info->buffer + bufaddr + 3));
_pc = pc / 4;
/* Get the instruction refered to by the current instruction word
and print it out based on its type. */
diff --git a/opcodes/v850-opc.c b/opcodes/v850-opc.c
index 57f2051..17d1871 100644
--- a/opcodes/v850-opc.c
+++ b/opcodes/v850-opc.c
@@ -693,14 +693,10 @@ extract_WIDTH_L (unsigned long insn, int * invalid)
static unsigned long
insert_SELID (unsigned long insn, long selid, const char ** errmsg)
{
- unsigned long ret;
-
- if (selid > 0x1f || selid < 0)
+ if ((unsigned long) selid > 0x1f)
* errmsg = _(selid_out_of_range);
- ret = (insn | ((selid & 0x1f) << 27));
-
- return ret;
+ return insn | ((selid & 0x1fUL) << 27);
}
static unsigned long
diff --git a/opcodes/vax-dis.c b/opcodes/vax-dis.c
index 5e5a625..36868d5 100644
--- a/opcodes/vax-dis.c
+++ b/opcodes/vax-dis.c
@@ -440,7 +440,8 @@ print_insn_vax (bfd_vma memaddr, disassemble_info *info)
int offset;
FETCH_DATA (info, buffer + 4);
- offset = buffer[3] << 24 | buffer[2] << 16 | buffer[1] << 8 | buffer[0];
+ offset = ((unsigned) buffer[3] << 24 | buffer[2] << 16
+ | buffer[1] << 8 | buffer[0]);
(*info->fprintf_func) (info->stream, ".long 0x%08x", offset);
return 4;
--
2.19.1

120
PR24960-Memory-leak-from-disassembler.patch Normal file
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@ -0,0 +1,120 @@
From 20135676fc4c3912297c313b3e0d3cbd6cc402e3 Mon Sep 17 00:00:00 2001
From: Alan Modra <amodra@gmail.com>
Date: Mon, 9 Dec 2019 20:34:49 +1030
Subject: [PATCH 1/1] PR24960, Memory leak from disassembler
PR 24960
include/
* dis-asm.h (disassemble_free_target): Declare.
opcodes/
* disassemble.c (disassemble_free_target): New function.
binutils/
* objdump.c (disassemble_data): Call disassemble_free_target.
---
binutils/objdump.c | 1 +
include/dis-asm.h | 5 ++++-
opcodes/disassemble.c | 59 +++++++++++++++++++++++++++++++++++++++++++++++++++
6 files changed, 79 insertions(+), 1 deletion(-)
diff --git a/binutils/objdump.c b/binutils/objdump.c
index d48a73a..c10136e 100644
--- a/binutils/objdump.c
+++ b/binutils/objdump.c
@@ -2730,6 +2730,7 @@ disassemble_data (bfd *abfd)
if (aux.dynrelbuf != NULL)
free (aux.dynrelbuf);
free (sorted_syms);
+ disassemble_free_target (&disasm_info);
}
static bfd_boolean
diff --git a/include/dis-asm.h b/include/dis-asm.h
index c174650..82bf4dc 100644
--- a/include/dis-asm.h
+++ b/include/dis-asm.h
@@ -325,7 +325,10 @@ extern disassembler_ftype disassembler (enum bfd_architecture arc,
/* Amend the disassemble_info structure as necessary for the target architecture.
Should only be called after initialising the info->arch field. */
-extern void disassemble_init_for_target (struct disassemble_info * dinfo);
+extern void disassemble_init_for_target (struct disassemble_info *);
+
+/* Tidy any memory allocated by targets, such as info->private_data. */
+extern void disassemble_free_target (struct disassemble_info *);
/* Document any target specific options available from the disassembler. */
extern void disassembler_usage (FILE *);
diff --git a/opcodes/disassemble.c b/opcodes/disassemble.c
index f131ee8..7c91997 100644
--- a/opcodes/disassemble.c
+++ b/opcodes/disassemble.c
@@ -716,6 +716,65 @@ disassemble_init_for_target (struct disassemble_info * info)
}
}
+void
+disassemble_free_target (struct disassemble_info *info)
+{
+ if (info == NULL)
+ return;
+
+ switch (info->arch)
+ {
+ default:
+ return;
+
+#ifdef ARCH_bpf
+ case bfd_arch_bpf:
+#endif
+#ifdef ARCH_m32c
+ case bfd_arch_m32c:
+#endif
+#if defined ARCH_bpf || defined ARCH_m32c
+ if (info->private_data)
+ {
+ CGEN_BITSET *mask = info->private_data;
+ free (mask->bits);
+ }
+ break;
+#endif
+
+#ifdef ARCH_arc
+ case bfd_arch_arc:
+ break;
+#endif
+#ifdef ARCH_cris
+ case bfd_arch_cris:
+ break;
+#endif
+#ifdef ARCH_mmix
+ case bfd_arch_mmix:
+ break;
+#endif
+#ifdef ARCH_nfp
+ case bfd_arch_nfp:
+ break;
+#endif
+#ifdef ARCH_powerpc
+ case bfd_arch_powerpc:
+ break;
+#endif
+#ifdef ARCH_riscv
+ case bfd_arch_riscv:
+ break;
+#endif
+#ifdef ARCH_rs6000
+ case bfd_arch_rs6000:
+ break;
+#endif
+ }
+
+ free (info->private_data);
+}
+
/* Remove whitespace and consecutive commas from OPTIONS. */
char *
--
2.9.3

280
Use-disassemble_info-private_data-in-place-of-insn_sets.patch Normal file
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@ -0,0 +1,280 @@
From 103ebbc35cc1975442e1e6233207d8d7b2016556 Mon Sep 17 00:00:00 2001
From: Alan Modra <amodra@gmail.com>
Date: Mon, 9 Dec 2019 22:46:26 +1030
Subject: [PATCH] Use disassemble_info.private_data in place of insn_sets
No cgen target uses private_data. This patch removes a
disassemble_info field that is only used by cgen, and instead uses
private_data. It also removes a macro that is no longer used.
include/
* dis-asm.h (struct disassemble_info): Delete insn_sets.
(INIT_DISASSEMBLE_INFO_NO_ARCH): Don't define.
opcodes/
* cgen-dis.in (print_insn_@arch@): Replace insn_sets with private_data.
* disassemble.c (disassemble_init_for_target): Likewise.
* bpf-dis.c: Regenerate.
* epiphany-dis.c: Regenerate.
* fr30-dis.c: Regenerate.
* frv-dis.c: Regenerate.
* ip2k-dis.c: Regenerate.
* iq2000-dis.c: Regenerate.
* lm32-dis.c: Regenerate.
* m32c-dis.c: Regenerate.
* m32r-dis.c: Regenerate.
* mep-dis.c: Regenerate.
* mt-dis.c: Regenerate.
* or1k-dis.c: Regenerate.
* xc16x-dis.c: Regenerate.
* xstormy16-dis.c: Regenerate.
---
include/dis-asm.h | 8 --------
opcodes/cgen-dis.in | 2 +-
opcodes/disassemble.c | 8 ++++----
opcodes/epiphany-dis.c | 2 +-
opcodes/fr30-dis.c | 2 +-
opcodes/frv-dis.c | 2 +-
opcodes/ip2k-dis.c | 2 +-
opcodes/iq2000-dis.c | 2 +-
opcodes/lm32-dis.c | 2 +-
opcodes/m32c-dis.c | 2 +-
opcodes/m32r-dis.c | 2 +-
opcodes/mep-dis.c | 2 +-
opcodes/mt-dis.c | 2 +-
opcodes/or1k-dis.c | 2 +-
opcodes/xc16x-dis.c | 2 +-
opcodes/xstormy16-dis.c | 2 +-
16 files changed, 18 insertions(+), 26 deletions(-)
diff --git a/include/dis-asm.h b/include/dis-asm.h
index ee9c1e2..6a57564 100644
--- a/include/dis-asm.h
+++ b/include/dis-asm.h
@@ -77,11 +77,6 @@ typedef struct disassemble_info
enum bfd_endian endian;
/* Endianness of code, for mixed-endian situations such as ARM BE8. */
enum bfd_endian endian_code;
- /* An arch/mach-specific bitmask of selected instruction subsets, mainly
- for processors with run-time-switchable instruction sets. The default,
- zero, means that there is no constraint. CGEN-based opcodes ports
- may use ISA_foo masks. */
- void *insn_sets;
/* Some targets need information about the current section to accurately
display insns. If this is NULL, the target disassembler function
@@ -343,9 +338,6 @@ extern void init_disassemble_info (struct disassemble_info *dinfo, void *stream,
/* For compatibility with existing code. */
#define INIT_DISASSEMBLE_INFO(INFO, STREAM, FPRINTF_FUNC) \
init_disassemble_info (&(INFO), (STREAM), (fprintf_ftype) (FPRINTF_FUNC))
-#define INIT_DISASSEMBLE_INFO_NO_ARCH(INFO, STREAM, FPRINTF_FUNC) \
- init_disassemble_info (&(INFO), (STREAM), (fprintf_ftype) (FPRINTF_FUNC))
-
#ifdef __cplusplus
}
diff --git a/opcodes/cgen-dis.in b/opcodes/cgen-dis.in
index bf6d951..073548f 100644
--- a/opcodes/cgen-dis.in
+++ b/opcodes/cgen-dis.in
@@ -388,7 +388,7 @@ print_insn_@arch@ (bfd_vma pc, disassemble_info *info)
cgen_bitset_add (isa, CGEN_COMPUTE_ISA (info));
}
#else
- isa = info->insn_sets;
+ isa = info->private_data;
#endif
/* If we've switched cpu's, try to find a handle we've used before */
diff --git a/opcodes/disassemble.c b/opcodes/disassemble.c
index c8fda59..bff4dd9 100644
--- a/opcodes/disassemble.c
+++ b/opcodes/disassemble.c
@@ -616,13 +616,13 @@ disassemble_init_for_target (struct disassemble_info * info)
/* This processor in fact is little endian. The value set here
reflects the way opcodes are written in the cgen description. */
info->endian = BFD_ENDIAN_BIG;
- if (! info->insn_sets)
+ if (! info->private_data)
{
- info->insn_sets = cgen_bitset_create (ISA_MAX);
+ info->private_data = cgen_bitset_create (ISA_MAX);
if (info->mach == bfd_mach_m16c)
- cgen_bitset_set (info->insn_sets, ISA_M16C);
+ cgen_bitset_set (info->private_data, ISA_M16C);
else
- cgen_bitset_set (info->insn_sets, ISA_M32C);
+ cgen_bitset_set (info->private_data, ISA_M32C);
}
break;
#endif
diff --git a/opcodes/epiphany-dis.c b/opcodes/epiphany-dis.c
index d4ad501..af9c9e2 100644
--- a/opcodes/epiphany-dis.c
+++ b/opcodes/epiphany-dis.c
@@ -629,7 +629,7 @@ print_insn_epiphany (bfd_vma pc, disassemble_info *info)
cgen_bitset_add (isa, CGEN_COMPUTE_ISA (info));
}
#else
- isa = info->insn_sets;
+ isa = info->private_data;
#endif
/* If we've switched cpu's, try to find a handle we've used before */
diff --git a/opcodes/fr30-dis.c b/opcodes/fr30-dis.c
index 6a60eef..eca91c3 100644
--- a/opcodes/fr30-dis.c
+++ b/opcodes/fr30-dis.c
@@ -650,7 +650,7 @@ print_insn_fr30 (bfd_vma pc, disassemble_info *info)
cgen_bitset_add (isa, CGEN_COMPUTE_ISA (info));
}
#else
- isa = info->insn_sets;
+ isa = info->private_data;
#endif
/* If we've switched cpu's, try to find a handle we've used before */
diff --git a/opcodes/frv-dis.c b/opcodes/frv-dis.c
index af844f7..71a5c78 100644
--- a/opcodes/frv-dis.c
+++ b/opcodes/frv-dis.c
@@ -747,7 +747,7 @@ print_insn_frv (bfd_vma pc, disassemble_info *info)
cgen_bitset_add (isa, CGEN_COMPUTE_ISA (info));
}
#else
- isa = info->insn_sets;
+ isa = info->private_data;
#endif
/* If we've switched cpu's, try to find a handle we've used before */
diff --git a/opcodes/ip2k-dis.c b/opcodes/ip2k-dis.c
index 5e32903..8bf3fb3 100644
--- a/opcodes/ip2k-dis.c
+++ b/opcodes/ip2k-dis.c
@@ -639,7 +639,7 @@ print_insn_ip2k (bfd_vma pc, disassemble_info *info)
cgen_bitset_add (isa, CGEN_COMPUTE_ISA (info));
}
#else
- isa = info->insn_sets;
+ isa = info->private_data;
#endif
/* If we've switched cpu's, try to find a handle we've used before */
diff --git a/opcodes/iq2000-dis.c b/opcodes/iq2000-dis.c
index d173333..b9b3aa6 100644
--- a/opcodes/iq2000-dis.c
+++ b/opcodes/iq2000-dis.c
@@ -540,7 +540,7 @@ print_insn_iq2000 (bfd_vma pc, disassemble_info *info)
cgen_bitset_add (isa, CGEN_COMPUTE_ISA (info));
}
#else
- isa = info->insn_sets;
+ isa = info->private_data;
#endif
/* If we've switched cpu's, try to find a handle we've used before */
diff --git a/opcodes/lm32-dis.c b/opcodes/lm32-dis.c
index 90e67c7..d8fea64 100644
--- a/opcodes/lm32-dis.c
+++ b/opcodes/lm32-dis.c
@@ -498,7 +498,7 @@ print_insn_lm32 (bfd_vma pc, disassemble_info *info)
cgen_bitset_add (isa, CGEN_COMPUTE_ISA (info));
}
#else
- isa = info->insn_sets;
+ isa = info->private_data;
#endif
/* If we've switched cpu's, try to find a handle we've used before */
diff --git a/opcodes/m32c-dis.c b/opcodes/m32c-dis.c
index fc8ee0b..f980abc 100644
--- a/opcodes/m32c-dis.c
+++ b/opcodes/m32c-dis.c
@@ -1242,7 +1242,7 @@ print_insn_m32c (bfd_vma pc, disassemble_info *info)
cgen_bitset_add (isa, CGEN_COMPUTE_ISA (info));
}
#else
- isa = info->insn_sets;
+ isa = info->private_data;
#endif
/* If we've switched cpu's, try to find a handle we've used before */
diff --git a/opcodes/m32r-dis.c b/opcodes/m32r-dis.c
index cd3349c..9034665 100644
--- a/opcodes/m32r-dis.c
+++ b/opcodes/m32r-dis.c
@@ -630,7 +630,7 @@ print_insn_m32r (bfd_vma pc, disassemble_info *info)
cgen_bitset_add (isa, CGEN_COMPUTE_ISA (info));
}
#else
- isa = info->insn_sets;
+ isa = info->private_data;
#endif
/* If we've switched cpu's, try to find a handle we've used before */
diff --git a/opcodes/mep-dis.c b/opcodes/mep-dis.c
index e52db1e..e054821 100644
--- a/opcodes/mep-dis.c
+++ b/opcodes/mep-dis.c
@@ -1538,7 +1538,7 @@ print_insn_mep (bfd_vma pc, disassemble_info *info)
cgen_bitset_add (isa, CGEN_COMPUTE_ISA (info));
}
#else
- isa = info->insn_sets;
+ isa = info->private_data;
#endif
/* If we've switched cpu's, try to find a handle we've used before */
diff --git a/opcodes/mt-dis.c b/opcodes/mt-dis.c
index 9b6df6a..35ec998 100644
--- a/opcodes/mt-dis.c
+++ b/opcodes/mt-dis.c
@@ -641,7 +641,7 @@ print_insn_mt (bfd_vma pc, disassemble_info *info)
cgen_bitset_add (isa, CGEN_COMPUTE_ISA (info));
}
#else
- isa = info->insn_sets;
+ isa = info->private_data;
#endif
/* If we've switched cpu's, try to find a handle we've used before */
diff --git a/opcodes/or1k-dis.c b/opcodes/or1k-dis.c
index f54b6b4..8444f02 100644
--- a/opcodes/or1k-dis.c
+++ b/opcodes/or1k-dis.c
@@ -492,7 +492,7 @@ print_insn_or1k (bfd_vma pc, disassemble_info *info)
cgen_bitset_add (isa, CGEN_COMPUTE_ISA (info));
}
#else
- isa = info->insn_sets;
+ isa = info->private_data;
#endif
/* If we've switched cpu's, try to find a handle we've used before */
diff --git a/opcodes/xc16x-dis.c b/opcodes/xc16x-dis.c
index d634572..9bdc905 100644
--- a/opcodes/xc16x-dis.c
+++ b/opcodes/xc16x-dis.c
@@ -771,7 +771,7 @@ print_insn_xc16x (bfd_vma pc, disassemble_info *info)
cgen_bitset_add (isa, CGEN_COMPUTE_ISA (info));
}
#else
- isa = info->insn_sets;
+ isa = info->private_data;
#endif
/* If we've switched cpu's, try to find a handle we've used before */
diff --git a/opcodes/xstormy16-dis.c b/opcodes/xstormy16-dis.c
index 0c8d204..a372932 100644
--- a/opcodes/xstormy16-dis.c
+++ b/opcodes/xstormy16-dis.c
@@ -519,7 +519,7 @@ print_insn_xstormy16 (bfd_vma pc, disassemble_info *info)
cgen_bitset_add (isa, CGEN_COMPUTE_ISA (info));
}
#else
- isa = info->insn_sets;
+ isa = info->private_data;
#endif
/* If we've switched cpu's, try to find a handle we've used before */
--
2.19.1

40
binutils.spec
View File

@ -1,7 +1,7 @@
Summary: Binary utilities
Name: binutils
Version: 2.33.1
Release: 3
Release: 4
License: GPLv3+
URL: https://sourceware.org/binutils
@ -18,19 +18,23 @@ Patch05: binutils-2.27-aarch64-ifunc.patch
Patch06: binutils-gold-ignore-discarded-note-relocs.patch
#PATCH-CVE-UPSTREAM
Patch6009: CVE-2019-1010204.patch
Patch6022: CVE-2019-17450.patch
Patch6023: CVE-2019-17451.patch
Patch7: CVE-2019-1010204.patch
Patch8: CVE-2019-17450.patch
Patch9: CVE-2019-17451.patch
Patch6027: Fix-array-overrun-when-disassembling-corrupt-TIC30-binaries.patch
Patch6029: Fix-potential-array-overruns-when-disassembling-corrupt-v850.patch
Patch6030: Prevent-a-left-shift-by-a-negative-value-when-disassembling.patch
Patch6031: Stop-potential-illegal-memory-access-in-the-NS32K.patch
Patch6032: Fix-buffer-overrun-in-TIC30-disassembler.patch
Patch6033: ubsan-ia64-left-shift-of-negative-value.patch
Patch6035: Remove-more-shifts-for-sign-zero-extension.patch
Patch6036: left-shift-of-cannot-be-represented-in-type-int.patch
Patch6038: ubsan-cr16-left-shift-cannot-be-represented-in-type-int.patch
Patch10: Fix-array-overrun-when-disassembling-corrupt-TIC30-binaries.patch
Patch11: Fix-potential-array-overruns-when-disassembling-corrupt-v850.patch
Patch12: Prevent-a-left-shift-by-a-negative-value-when-disassembling.patch
Patch13: Stop-potential-illegal-memory-access-in-the-NS32K.patch
Patch14: Fix-buffer-overrun-in-TIC30-disassembler.patch
Patch15: ubsan-ia64-left-shift-of-negative-value.patch
Patch16: Remove-more-shifts-for-sign-zero-extension.patch
Patch17: left-shift-of-cannot-be-represented-in-type-int.patch
Patch18: ubsan-cr16-left-shift-cannot-be-represented-in-type-int.patch
Patch19: More-signed-overflow-fixes.patch
Patch20: Use-disassemble_info-private_data-in-place-of-insn_sets.patch
Patch21: PR24960-Memory-leak-from-disassembler.patch
Provides: bundled(libiberty)
@ -295,6 +299,9 @@ fi
%{_bindir}/ld.*
%ghost %{_bindir}/ld
%{_libdir}/lib*.so
%attr(750,root,root) %{_bindir}/ld.*
%attr(750,root,root) %{_bindir}/objdump
%attr(750,root,root) %{_bindir}/readelf
%exclude %{_libdir}/libbfd.so
%exclude %{_libdir}/libopcodes.so
@ -315,6 +322,13 @@ fi
%{_infodir}/bfd*info*
%changelog
* Mon Jan 20 2020 openEuler Buildteam <buildteam@openeuler.org> - 2.33.1-4
- Type:bugfix
- ID:CVE
- SUG:NA
- DESC:fix the issue that the permission changes due to the upgrade and
backport patch to fix memory leak and overflow
* Wed Jan 15 2020 openEuler Buildteam <buildteam@openeuler.org> - 2.33.1-3
- Type:bugfix
- ID:CVE