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!9 openEuler-binutils

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Merge pull request !9 from Liquor/next
This commit is contained in:
openeuler-ci-bot 2020-04-02 17:43:38 +08:00 committed by Gitee
commit 2a0eb0b8c9
2 changed files with 323 additions and 281 deletions
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84
Use-disassemble_info-private_data-in-place-of-insn_sets.patch
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@ -29,8 +29,9 @@ opcodes/
* xstormy16-dis.c: Regenerate.
---
include/dis-asm.h | 8 --------
opcodes/bpf-dis.c | 2 +-
opcodes/cgen-dis.in | 2 +-
opcodes/disassemble.c | 8 ++++----
opcodes/disassemble.c | 24 ++++++++++++------------
opcodes/epiphany-dis.c | 2 +-
opcodes/fr30-dis.c | 2 +-
opcodes/frv-dis.c | 2 +-
@ -44,13 +45,13 @@ opcodes/
opcodes/or1k-dis.c | 2 +-
opcodes/xc16x-dis.c | 2 +-
opcodes/xstormy16-dis.c | 2 +-
16 files changed, 18 insertions(+), 26 deletions(-)
17 files changed, 27 insertions(+), 35 deletions(-)
diff --git a/include/dis-asm.h b/include/dis-asm.h
index ee9c1e2..6a57564 100644
index b4d5025..c174650 100644
--- a/include/dis-asm.h
+++ b/include/dis-asm.h
@@ -77,11 +77,6 @@ typedef struct disassemble_info
@@ -78,11 +78,6 @@ typedef struct disassemble_info
enum bfd_endian endian;
/* Endianness of code, for mixed-endian situations such as ARM BE8. */
enum bfd_endian endian_code;
@ -62,7 +63,7 @@ index ee9c1e2..6a57564 100644
/* Some targets need information about the current section to accurately
display insns. If this is NULL, the target disassembler function
@@ -343,9 +338,6 @@ extern void init_disassemble_info (struct disassemble_info *dinfo, void *stream,
@@ -394,9 +389,6 @@ extern void init_disassemble_info (struct disassemble_info *dinfo, void *stream,
/* For compatibility with existing code. */
#define INIT_DISASSEMBLE_INFO(INFO, STREAM, FPRINTF_FUNC) \
init_disassemble_info (&(INFO), (STREAM), (fprintf_ftype) (FPRINTF_FUNC))
@ -72,8 +73,21 @@ index ee9c1e2..6a57564 100644
#ifdef __cplusplus
}
diff --git a/opcodes/bpf-dis.c b/opcodes/bpf-dis.c
index c48bce8..99a292a 100644
--- a/opcodes/bpf-dis.c
+++ b/opcodes/bpf-dis.c
@@ -553,7 +553,7 @@ print_insn_bpf (bfd_vma pc, disassemble_info *info)
cgen_bitset_add (isa, CGEN_COMPUTE_ISA (info));
}
#else
- isa = info->insn_sets;
+ isa = info->private_data;
#endif
/* If we've switched cpu's, try to find a handle we've used before */
diff --git a/opcodes/cgen-dis.in b/opcodes/cgen-dis.in
index bf6d951..073548f 100644
index d1e06bf..cf3e872 100644
--- a/opcodes/cgen-dis.in
+++ b/opcodes/cgen-dis.in
@@ -388,7 +388,7 @@ print_insn_@arch@ (bfd_vma pc, disassemble_info *info)
@ -86,15 +100,15 @@ index bf6d951..073548f 100644
/* If we've switched cpu's, try to find a handle we've used before */
diff --git a/opcodes/disassemble.c b/opcodes/disassemble.c
index c8fda59..bff4dd9 100644
index aef2fd8..f131ee8 100644
--- a/opcodes/disassemble.c
+++ b/opcodes/disassemble.c
@@ -616,13 +616,13 @@ disassemble_init_for_target (struct disassemble_info * info)
@@ -654,26 +654,26 @@ disassemble_init_for_target (struct disassemble_info * info)
/* This processor in fact is little endian. The value set here
reflects the way opcodes are written in the cgen description. */
info->endian = BFD_ENDIAN_BIG;
- if (! info->insn_sets)
+ if (! info->private_data)
+ if (!info->private_data)
{
- info->insn_sets = cgen_bitset_create (ISA_MAX);
+ info->private_data = cgen_bitset_create (ISA_MAX);
@ -107,8 +121,29 @@ index c8fda59..bff4dd9 100644
}
break;
#endif
#ifdef ARCH_bpf
case bfd_arch_bpf:
- if (!info->insn_sets)
- {
- info->insn_sets = cgen_bitset_create (ISA_EBPFMAX);
- if (info->endian == BFD_ENDIAN_BIG)
- cgen_bitset_set (info->insn_sets, ISA_EBPFBE);
- else
- cgen_bitset_set (info->insn_sets, ISA_EBPFLE);
- }
+ if (!info->private_data)
+ {
+ info->private_data = cgen_bitset_create (ISA_EBPFMAX);
+ if (info->endian == BFD_ENDIAN_BIG)
+ cgen_bitset_set (info->private_data, ISA_EBPFBE);
+ else
+ cgen_bitset_set (info->private_data, ISA_EBPFLE);
+ }
break;
#endif
#ifdef ARCH_pru
diff --git a/opcodes/epiphany-dis.c b/opcodes/epiphany-dis.c
index d4ad501..af9c9e2 100644
index 376d678..3c79031 100644
--- a/opcodes/epiphany-dis.c
+++ b/opcodes/epiphany-dis.c
@@ -629,7 +629,7 @@ print_insn_epiphany (bfd_vma pc, disassemble_info *info)
@ -121,7 +156,7 @@ index d4ad501..af9c9e2 100644
/* If we've switched cpu's, try to find a handle we've used before */
diff --git a/opcodes/fr30-dis.c b/opcodes/fr30-dis.c
index 6a60eef..eca91c3 100644
index b83051b..2d1de96 100644
--- a/opcodes/fr30-dis.c
+++ b/opcodes/fr30-dis.c
@@ -650,7 +650,7 @@ print_insn_fr30 (bfd_vma pc, disassemble_info *info)
@ -134,7 +169,7 @@ index 6a60eef..eca91c3 100644
/* If we've switched cpu's, try to find a handle we've used before */
diff --git a/opcodes/frv-dis.c b/opcodes/frv-dis.c
index af844f7..71a5c78 100644
index 9df0dd5..bf9d4f7 100644
--- a/opcodes/frv-dis.c
+++ b/opcodes/frv-dis.c
@@ -747,7 +747,7 @@ print_insn_frv (bfd_vma pc, disassemble_info *info)
@ -147,7 +182,7 @@ index af844f7..71a5c78 100644
/* If we've switched cpu's, try to find a handle we've used before */
diff --git a/opcodes/ip2k-dis.c b/opcodes/ip2k-dis.c
index 5e32903..8bf3fb3 100644
index 3d3e8be..bc758a6 100644
--- a/opcodes/ip2k-dis.c
+++ b/opcodes/ip2k-dis.c
@@ -639,7 +639,7 @@ print_insn_ip2k (bfd_vma pc, disassemble_info *info)
@ -160,7 +195,7 @@ index 5e32903..8bf3fb3 100644
/* If we've switched cpu's, try to find a handle we've used before */
diff --git a/opcodes/iq2000-dis.c b/opcodes/iq2000-dis.c
index d173333..b9b3aa6 100644
index 422665e..2762b64 100644
--- a/opcodes/iq2000-dis.c
+++ b/opcodes/iq2000-dis.c
@@ -540,7 +540,7 @@ print_insn_iq2000 (bfd_vma pc, disassemble_info *info)
@ -173,7 +208,7 @@ index d173333..b9b3aa6 100644
/* If we've switched cpu's, try to find a handle we've used before */
diff --git a/opcodes/lm32-dis.c b/opcodes/lm32-dis.c
index 90e67c7..d8fea64 100644
index b18fb3d..274b63f 100644
--- a/opcodes/lm32-dis.c
+++ b/opcodes/lm32-dis.c
@@ -498,7 +498,7 @@ print_insn_lm32 (bfd_vma pc, disassemble_info *info)
@ -186,7 +221,7 @@ index 90e67c7..d8fea64 100644
/* If we've switched cpu's, try to find a handle we've used before */
diff --git a/opcodes/m32c-dis.c b/opcodes/m32c-dis.c
index fc8ee0b..f980abc 100644
index 92b87f2..b368685 100644
--- a/opcodes/m32c-dis.c
+++ b/opcodes/m32c-dis.c
@@ -1242,7 +1242,7 @@ print_insn_m32c (bfd_vma pc, disassemble_info *info)
@ -199,7 +234,7 @@ index fc8ee0b..f980abc 100644
/* If we've switched cpu's, try to find a handle we've used before */
diff --git a/opcodes/m32r-dis.c b/opcodes/m32r-dis.c
index cd3349c..9034665 100644
index 8722d6b..c778b88 100644
--- a/opcodes/m32r-dis.c
+++ b/opcodes/m32r-dis.c
@@ -630,7 +630,7 @@ print_insn_m32r (bfd_vma pc, disassemble_info *info)
@ -212,7 +247,7 @@ index cd3349c..9034665 100644
/* If we've switched cpu's, try to find a handle we've used before */
diff --git a/opcodes/mep-dis.c b/opcodes/mep-dis.c
index e52db1e..e054821 100644
index 13bcb47..79bd776 100644
--- a/opcodes/mep-dis.c
+++ b/opcodes/mep-dis.c
@@ -1538,7 +1538,7 @@ print_insn_mep (bfd_vma pc, disassemble_info *info)
@ -225,7 +260,7 @@ index e52db1e..e054821 100644
/* If we've switched cpu's, try to find a handle we've used before */
diff --git a/opcodes/mt-dis.c b/opcodes/mt-dis.c
index 9b6df6a..35ec998 100644
index 44e6720..00b3d06 100644
--- a/opcodes/mt-dis.c
+++ b/opcodes/mt-dis.c
@@ -641,7 +641,7 @@ print_insn_mt (bfd_vma pc, disassemble_info *info)
@ -238,10 +273,10 @@ index 9b6df6a..35ec998 100644
/* If we've switched cpu's, try to find a handle we've used before */
diff --git a/opcodes/or1k-dis.c b/opcodes/or1k-dis.c
index f54b6b4..8444f02 100644
index 74bf38f..dce00b3 100644
--- a/opcodes/or1k-dis.c
+++ b/opcodes/or1k-dis.c
@@ -492,7 +492,7 @@ print_insn_or1k (bfd_vma pc, disassemble_info *info)
@@ -534,7 +534,7 @@ print_insn_or1k (bfd_vma pc, disassemble_info *info)
cgen_bitset_add (isa, CGEN_COMPUTE_ISA (info));
}
#else
@ -251,7 +286,7 @@ index f54b6b4..8444f02 100644
/* If we've switched cpu's, try to find a handle we've used before */
diff --git a/opcodes/xc16x-dis.c b/opcodes/xc16x-dis.c
index d634572..9bdc905 100644
index 2c61e81..3081083 100644
--- a/opcodes/xc16x-dis.c
+++ b/opcodes/xc16x-dis.c
@@ -771,7 +771,7 @@ print_insn_xc16x (bfd_vma pc, disassemble_info *info)
@ -264,7 +299,7 @@ index d634572..9bdc905 100644
/* If we've switched cpu's, try to find a handle we've used before */
diff --git a/opcodes/xstormy16-dis.c b/opcodes/xstormy16-dis.c
index 0c8d204..a372932 100644
index 2382d08..7da09f3 100644
--- a/opcodes/xstormy16-dis.c
+++ b/opcodes/xstormy16-dis.c
@@ -519,7 +519,7 @@ print_insn_xstormy16 (bfd_vma pc, disassemble_info *info)
@ -277,4 +312,5 @@ index 0c8d204..a372932 100644
/* If we've switched cpu's, try to find a handle we've used before */
--
2.19.1
1.8.3.1

8
binutils.spec
View File

@ -1,7 +1,7 @@
Summary: Binary utilities
Name: binutils
Version: 2.33.1
Release: 5
Release: 6
License: GPLv3+
URL: https://sourceware.org/binutils
@ -319,6 +319,12 @@ fi
%{_infodir}/bfd*info*
%changelog
* Thu Apr 02 2020 openEuler Buildteam <buildteam@openeuler.org> - 2.33.1-6
- Type:bugfix
- ID:NA
- SUG:NA
- DESC:Use disassemble_info.private_date in place of insn_sets
* Wed Jan 22 2020 openEuler Buildteam <buildteam@openeuler.org> - 2.33.1-5
- Type:bugfix
- ID:CVE